2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_kern_tls.h"
36 #include "opt_ratelimit.h"
38 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/socket.h>
42 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
49 #include <sys/sglist.h>
50 #include <sys/sysctl.h>
52 #include <sys/socketvar.h>
53 #include <sys/counter.h>
55 #include <net/ethernet.h>
57 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/ip6.h>
61 #include <netinet/tcp.h>
62 #include <netinet/udp.h>
63 #include <machine/in_cksum.h>
64 #include <machine/md_var.h>
68 #include <machine/bus.h>
69 #include <sys/selinfo.h>
70 #include <net/if_var.h>
71 #include <net/netmap.h>
72 #include <dev/netmap/netmap_kern.h>
75 #include "common/common.h"
76 #include "common/t4_regs.h"
77 #include "common/t4_regs_values.h"
78 #include "common/t4_msg.h"
80 #include "t4_mp_ring.h"
82 #ifdef T4_PKT_TIMESTAMP
83 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
85 #define RX_COPY_THRESHOLD MINCLSIZE
88 /* Internal mbuf flags stored in PH_loc.eight[1]. */
90 #define MC_RAW_WR 0x02
94 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
95 * 0-7 are valid values.
97 static int fl_pktshift = 0;
98 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
99 "payload DMA offset in rx buffer (bytes)");
102 * Pad ethernet payload up to this boundary.
103 * -1: driver should figure out a good value.
104 * 0: disable padding.
105 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
109 "payload pad boundary (bytes)");
112 * Status page length.
113 * -1: driver should figure out a good value.
114 * 64 or 128 are the only other valid values.
116 static int spg_len = -1;
117 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
118 "status page size (bytes)");
122 * -1: no congestion feedback (not recommended).
123 * 0: backpressure the channel instead of dropping packets right away.
124 * 1: no backpressure, drop packets for the congested queue immediately.
126 static int cong_drop = 0;
127 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
128 "Congestion control for RX queues (0 = backpressure, 1 = drop");
131 * Deliver multiple frames in the same free list buffer if they fit.
132 * -1: let the driver decide whether to enable buffer packing or not.
133 * 0: disable buffer packing.
134 * 1: enable buffer packing.
136 static int buffer_packing = -1;
137 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
138 0, "Enable buffer packing");
141 * Start next frame in a packed buffer at this boundary.
142 * -1: driver should figure out a good value.
143 * T4: driver will ignore this and use the same value as fl_pad above.
144 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
146 static int fl_pack = -1;
147 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
148 "payload pack boundary (bytes)");
151 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
152 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
153 * 1: ok to create mbuf(s) within a cluster if there is room.
155 static int allow_mbufs_in_cluster = 1;
156 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN,
157 &allow_mbufs_in_cluster, 0,
158 "Allow driver to create mbufs within a rx cluster");
161 * Largest rx cluster size that the driver is allowed to allocate.
163 static int largest_rx_cluster = MJUM16BYTES;
164 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
165 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
168 * Size of cluster allocation that's most likely to succeed. The driver will
169 * fall back to this size if it fails to allocate clusters larger than this.
171 static int safest_rx_cluster = PAGE_SIZE;
172 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
173 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
177 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
178 * for rewriting. -1 and 0-3 are all valid values.
179 * -1: hardware should leave the TCP timestamps alone.
185 static int tsclk = -1;
186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
187 "Control TCP timestamp rewriting when using pacing");
189 static int eo_max_backlog = 1024 * 1024;
190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
191 0, "Maximum backlog of ratelimited data per flow");
195 * The interrupt holdoff timers are multiplied by this value on T6+.
196 * 1 and 3-17 (both inclusive) are legal values.
198 static int tscale = 1;
199 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
200 "Interrupt holdoff timer scale on T6+");
203 * Number of LRO entries in the lro_ctrl structure per rx queue.
205 static int lro_entries = TCP_LRO_ENTRIES;
206 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
207 "Number of LRO entries per RX queue");
210 * This enables presorting of frames before they're fed into tcp_lro_rx.
212 static int lro_mbufs = 0;
213 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
214 "Enable presorting of LRO frames");
217 u_int wr_type; /* type 0 or type 1 */
218 u_int npkt; /* # of packets in this work request */
219 u_int plen; /* total payload (sum of all packets) */
220 u_int len16; /* # of 16B pieces used by this work request */
223 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
226 struct sglist_seg seg[TX_SGL_SEGS];
229 static int service_iq(struct sge_iq *, int);
230 static int service_iq_fl(struct sge_iq *, int);
231 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
232 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
233 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
234 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
235 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
237 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
238 bus_addr_t *, void **);
239 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
241 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
243 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
244 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
246 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
247 struct sysctl_oid *, struct sge_fl *);
248 static int alloc_fwq(struct adapter *);
249 static int free_fwq(struct adapter *);
250 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int,
251 struct sysctl_oid *);
252 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
253 struct sysctl_oid *);
254 static int free_rxq(struct vi_info *, struct sge_rxq *);
256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
257 struct sysctl_oid *);
258 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
261 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
262 struct sysctl_oid *);
263 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
264 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
265 struct sysctl_oid *);
266 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
268 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
269 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
270 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
271 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
273 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
274 static int free_eq(struct adapter *, struct sge_eq *);
275 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
276 struct sysctl_oid *);
277 static int free_wrq(struct adapter *, struct sge_wrq *);
278 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
279 struct sysctl_oid *);
280 static int free_txq(struct vi_info *, struct sge_txq *);
281 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
282 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
283 static int refill_fl(struct adapter *, struct sge_fl *, int);
284 static void refill_sfl(void *);
285 static int alloc_fl_sdesc(struct sge_fl *);
286 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
287 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
288 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
289 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
291 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
292 static inline u_int txpkt_len16(u_int, u_int);
293 static inline u_int txpkt_vm_len16(u_int, u_int);
294 static inline u_int txpkts0_len16(u_int);
295 static inline u_int txpkts1_len16(void);
296 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
297 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *,
298 struct fw_eth_tx_pkt_wr *, struct mbuf *, u_int);
299 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
300 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
301 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
302 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
303 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *,
304 struct fw_eth_tx_pkts_wr *, struct mbuf *, const struct txpkts *, u_int);
305 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
306 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
307 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
308 static inline uint16_t read_hw_cidx(struct sge_eq *);
309 static inline u_int reclaimable_tx_desc(struct sge_eq *);
310 static inline u_int total_available_tx_desc(struct sge_eq *);
311 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
312 static void tx_reclaim(void *, int);
313 static __be64 get_flit(struct sglist_seg *, int, int);
314 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
316 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
318 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
319 static void wrq_tx_drain(void *, int);
320 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
322 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
323 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
325 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
326 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
330 static counter_u64_t extfree_refs;
331 static counter_u64_t extfree_rels;
333 an_handler_t t4_an_handler;
334 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
335 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
336 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
337 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
338 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
339 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
340 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
343 t4_register_an_handler(an_handler_t h)
347 MPASS(h == NULL || t4_an_handler == NULL);
349 loc = (uintptr_t *)&t4_an_handler;
350 atomic_store_rel_ptr(loc, (uintptr_t)h);
354 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
358 MPASS(type < nitems(t4_fw_msg_handler));
359 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
361 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
362 * handler dispatch table. Reject any attempt to install a handler for
365 MPASS(type != FW_TYPE_RSSCPL);
366 MPASS(type != FW6_TYPE_RSSCPL);
368 loc = (uintptr_t *)&t4_fw_msg_handler[type];
369 atomic_store_rel_ptr(loc, (uintptr_t)h);
373 t4_register_cpl_handler(int opcode, cpl_handler_t h)
377 MPASS(opcode < nitems(t4_cpl_handler));
378 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
380 loc = (uintptr_t *)&t4_cpl_handler[opcode];
381 atomic_store_rel_ptr(loc, (uintptr_t)h);
385 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
388 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
395 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
397 * The return code for filter-write is put in the CPL cookie so
398 * we have to rely on the hardware tid (is_ftid) to determine
399 * that this is a response to a filter.
401 cookie = CPL_COOKIE_FILTER;
403 cookie = G_COOKIE(cpl->cookie);
405 MPASS(cookie > CPL_COOKIE_RESERVED);
406 MPASS(cookie < nitems(set_tcb_rpl_handlers));
408 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
412 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
415 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
420 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
421 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
425 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
428 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
429 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
432 MPASS(cookie != CPL_COOKIE_RESERVED);
434 return (act_open_rpl_handlers[cookie](iq, rss, m));
438 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
441 struct adapter *sc = iq->adapter;
445 if (is_hashfilter(sc))
446 cookie = CPL_COOKIE_HASHFILTER;
448 cookie = CPL_COOKIE_TOM;
450 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
454 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
456 struct adapter *sc = iq->adapter;
457 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
458 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
462 if (is_etid(sc, tid))
463 cookie = CPL_COOKIE_ETHOFLD;
465 cookie = CPL_COOKIE_TOM;
467 return (fw4_ack_handlers[cookie](iq, rss, m));
471 t4_init_shared_cpl_handlers(void)
474 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
475 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
476 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
477 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
478 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
482 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
486 MPASS(opcode < nitems(t4_cpl_handler));
487 MPASS(cookie > CPL_COOKIE_RESERVED);
488 MPASS(cookie < NUM_CPL_COOKIES);
489 MPASS(t4_cpl_handler[opcode] != NULL);
492 case CPL_SET_TCB_RPL:
493 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
495 case CPL_L2T_WRITE_RPL:
496 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
498 case CPL_ACT_OPEN_RPL:
499 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
501 case CPL_ABORT_RPL_RSS:
502 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
505 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
511 MPASS(h == NULL || *loc == (uintptr_t)NULL);
512 atomic_store_rel_ptr(loc, (uintptr_t)h);
516 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
522 if (fl_pktshift < 0 || fl_pktshift > 7) {
523 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
524 " using 0 instead.\n", fl_pktshift);
528 if (spg_len != 64 && spg_len != 128) {
531 #if defined(__i386__) || defined(__amd64__)
532 len = cpu_clflush_line_size > 64 ? 128 : 64;
537 printf("Invalid hw.cxgbe.spg_len value (%d),"
538 " using %d instead.\n", spg_len, len);
543 if (cong_drop < -1 || cong_drop > 1) {
544 printf("Invalid hw.cxgbe.cong_drop value (%d),"
545 " using 0 instead.\n", cong_drop);
549 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
550 printf("Invalid hw.cxgbe.tscale value (%d),"
551 " using 1 instead.\n", tscale);
555 extfree_refs = counter_u64_alloc(M_WAITOK);
556 extfree_rels = counter_u64_alloc(M_WAITOK);
557 counter_u64_zero(extfree_refs);
558 counter_u64_zero(extfree_rels);
560 t4_init_shared_cpl_handlers();
561 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
562 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
563 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
564 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
566 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
569 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
570 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
574 t4_sge_modunload(void)
577 counter_u64_free(extfree_refs);
578 counter_u64_free(extfree_rels);
582 t4_sge_extfree_refs(void)
586 rels = counter_u64_fetch(extfree_rels);
587 refs = counter_u64_fetch(extfree_refs);
589 return (refs - rels);
593 #define MAX_PACK_BOUNDARY 512
596 setup_pad_and_pack_boundaries(struct adapter *sc)
599 int pad, pack, pad_shift;
601 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
602 X_INGPADBOUNDARY_SHIFT;
604 if (fl_pad < (1 << pad_shift) ||
605 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
608 * If there is any chance that we might use buffer packing and
609 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
610 * it to the minimum allowed in all other cases.
612 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
615 * For fl_pad = 0 we'll still write a reasonable value to the
616 * register but all the freelists will opt out of padding.
617 * We'll complain here only if the user tried to set it to a
618 * value greater than 0 that was invalid.
621 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
622 " (%d), using %d instead.\n", fl_pad, pad);
625 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
626 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
627 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
630 if (fl_pack != -1 && fl_pack != pad) {
631 /* Complain but carry on. */
632 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
633 " using %d instead.\n", fl_pack, pad);
639 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
640 !powerof2(fl_pack)) {
641 if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
642 pack = MAX_PACK_BOUNDARY;
644 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
645 MPASS(powerof2(pack));
653 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
654 " (%d), using %d instead.\n", fl_pack, pack);
657 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
659 v = V_INGPACKBOUNDARY(0);
661 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
663 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
664 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
668 * adap->params.vpd.cclk must be set up before this is called.
671 t4_tweak_chip_settings(struct adapter *sc)
675 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
676 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
677 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
678 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
679 static int sge_flbuf_sizes[] = {
681 #if MJUMPAGESIZE != MCLBYTES
683 MJUMPAGESIZE - CL_METADATA_SIZE,
684 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
688 MCLBYTES - MSIZE - CL_METADATA_SIZE,
689 MJUM9BYTES - CL_METADATA_SIZE,
690 MJUM16BYTES - CL_METADATA_SIZE,
693 KASSERT(sc->flags & MASTER_PF,
694 ("%s: trying to change chip settings when not master.", __func__));
696 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
697 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
698 V_EGRSTATUSPAGESIZE(spg_len == 128);
699 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
701 setup_pad_and_pack_boundaries(sc);
703 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
704 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
705 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
706 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
707 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
708 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
709 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
710 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
711 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
713 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
714 ("%s: hw buffer size table too big", __func__));
715 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
716 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
717 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
718 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i),
722 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
723 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
724 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
726 KASSERT(intr_timer[0] <= timer_max,
727 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
729 for (i = 1; i < nitems(intr_timer); i++) {
730 KASSERT(intr_timer[i] >= intr_timer[i - 1],
731 ("%s: timers not listed in increasing order (%d)",
734 while (intr_timer[i] > timer_max) {
735 if (i == nitems(intr_timer) - 1) {
736 intr_timer[i] = timer_max;
739 intr_timer[i] += intr_timer[i - 1];
744 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
745 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
746 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
747 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
748 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
749 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
750 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
751 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
752 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
754 if (chip_id(sc) >= CHELSIO_T6) {
755 m = V_TSCALE(M_TSCALE);
759 v = V_TSCALE(tscale - 2);
760 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
762 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
763 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
764 V_WRTHRTHRESH(M_WRTHRTHRESH);
765 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
767 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
769 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
773 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
774 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
775 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
778 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
779 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
780 * may have to deal with is MAXPHYS + 1 page.
782 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
783 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
785 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
786 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
787 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
789 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
791 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
792 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
796 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
797 * padding is in use, the buffer's start and end need to be aligned to the pad
798 * boundary as well. We'll just make sure that the size is a multiple of the
799 * boundary here, it is up to the buffer allocation code to make sure the start
800 * of the buffer is aligned as well.
803 hwsz_ok(struct adapter *sc, int hwsz)
805 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
807 return (hwsz >= 64 && (hwsz & mask) == 0);
811 * XXX: driver really should be able to deal with unexpected settings.
814 t4_read_chip_settings(struct adapter *sc)
816 struct sge *s = &sc->sge;
817 struct sge_params *sp = &sc->params.sge;
820 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
821 static int sw_buf_sizes[] = { /* Sorted by size */
823 #if MJUMPAGESIZE != MCLBYTES
829 struct sw_zone_info *swz, *safe_swz;
830 struct hw_buf_info *hwb;
834 r = sc->params.sge.sge_control;
836 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
841 * If this changes then every single use of PAGE_SHIFT in the driver
842 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
844 if (sp->page_shift != PAGE_SHIFT) {
845 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
849 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
850 hwb = &s->hw_buf_info[0];
851 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
852 r = sc->params.sge.sge_fl_buffer_size[i];
854 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
859 * Create a sorted list in decreasing order of hw buffer sizes (and so
860 * increasing order of spare area) for each software zone.
862 * If padding is enabled then the start and end of the buffer must align
863 * to the pad boundary; if packing is enabled then they must align with
864 * the pack boundary as well. Allocations from the cluster zones are
865 * aligned to min(size, 4K), so the buffer starts at that alignment and
866 * ends at hwb->size alignment. If mbuf inlining is allowed the
867 * starting alignment will be reduced to MSIZE and the driver will
868 * exercise appropriate caution when deciding on the best buffer layout
871 n = 0; /* no usable buffer size to begin with */
872 swz = &s->sw_zone_info[0];
874 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
875 int8_t head = -1, tail = -1;
877 swz->size = sw_buf_sizes[i];
878 swz->zone = m_getzone(swz->size);
879 swz->type = m_gettype(swz->size);
881 if (swz->size < PAGE_SIZE) {
882 MPASS(powerof2(swz->size));
883 if (fl_pad && (swz->size % sp->pad_boundary != 0))
887 if (swz->size == safest_rx_cluster)
890 hwb = &s->hw_buf_info[0];
891 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
892 if (hwb->zidx != -1 || hwb->size > swz->size)
896 MPASS(hwb->size % sp->pad_boundary == 0);
901 else if (hwb->size < s->hw_buf_info[tail].size) {
902 s->hw_buf_info[tail].next = j;
906 struct hw_buf_info *t;
908 for (cur = &head; *cur != -1; cur = &t->next) {
909 t = &s->hw_buf_info[*cur];
910 if (hwb->size == t->size) {
914 if (hwb->size > t->size) {
922 swz->head_hwidx = head;
923 swz->tail_hwidx = tail;
927 if (swz->size - s->hw_buf_info[tail].size >=
929 sc->flags |= BUF_PACKING_OK;
933 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
939 if (safe_swz != NULL) {
940 s->safe_hwidx1 = safe_swz->head_hwidx;
941 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
944 hwb = &s->hw_buf_info[i];
947 MPASS(hwb->size % sp->pad_boundary == 0);
949 spare = safe_swz->size - hwb->size;
950 if (spare >= CL_METADATA_SIZE) {
957 if (sc->flags & IS_VF)
960 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
961 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
963 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
967 m = v = F_TDDPTAGTCB;
968 r = t4_read_reg(sc, A_ULP_RX_CTL);
970 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
974 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
976 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
977 r = t4_read_reg(sc, A_TP_PARA_REG5);
979 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
983 t4_init_tp_params(sc, 1);
985 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
986 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
992 t4_create_dma_tag(struct adapter *sc)
996 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
997 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
998 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
1001 device_printf(sc->dev,
1002 "failed to create main DMA tag: %d\n", rc);
1009 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
1010 struct sysctl_oid_list *children)
1012 struct sge_params *sp = &sc->params.sge;
1014 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
1015 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
1016 "freelist buffer sizes");
1018 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
1019 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1021 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1022 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1024 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1025 NULL, sp->spg_len, "status page size (bytes)");
1027 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1028 NULL, cong_drop, "congestion drop setting");
1030 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1031 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1035 t4_destroy_dma_tag(struct adapter *sc)
1038 bus_dma_tag_destroy(sc->dmat);
1044 * Allocate and initialize the firmware event queue, control queues, and special
1045 * purpose rx queues owned by the adapter.
1047 * Returns errno on failure. Resources allocated up to that point may still be
1048 * allocated. Caller is responsible for cleanup in case this function fails.
1051 t4_setup_adapter_queues(struct adapter *sc)
1053 struct sysctl_oid *oid;
1054 struct sysctl_oid_list *children;
1057 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1059 sysctl_ctx_init(&sc->ctx);
1060 sc->flags |= ADAP_SYSCTL_CTX;
1063 * Firmware event queue
1070 * That's all for the VF driver.
1072 if (sc->flags & IS_VF)
1075 oid = device_get_sysctl_tree(sc->dev);
1076 children = SYSCTL_CHILDREN(oid);
1079 * XXX: General purpose rx queues, one per port.
1083 * Control queues, one per port.
1085 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq",
1086 CTLFLAG_RD, NULL, "control queues");
1087 for_each_port(sc, i) {
1088 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i];
1090 rc = alloc_ctrlq(sc, ctrlq, i, oid);
1102 t4_teardown_adapter_queues(struct adapter *sc)
1106 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1108 /* Do this before freeing the queue */
1109 if (sc->flags & ADAP_SYSCTL_CTX) {
1110 sysctl_ctx_free(&sc->ctx);
1111 sc->flags &= ~ADAP_SYSCTL_CTX;
1114 if (!(sc->flags & IS_VF)) {
1115 for_each_port(sc, i)
1116 free_wrq(sc, &sc->sge.ctrlq[i]);
1123 /* Maximum payload that can be delivered with a single iq descriptor */
1125 mtu_to_max_payload(struct adapter *sc, int mtu)
1128 /* large enough even when hw VLAN extraction is disabled */
1129 return (sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1130 ETHER_VLAN_ENCAP_LEN + mtu);
1134 t4_setup_vi_queues(struct vi_info *vi)
1136 int rc = 0, i, intr_idx, iqidx;
1137 struct sge_rxq *rxq;
1138 struct sge_txq *txq;
1140 struct sge_ofld_rxq *ofld_rxq;
1142 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1143 struct sge_wrq *ofld_txq;
1147 struct sge_nm_rxq *nm_rxq;
1148 struct sge_nm_txq *nm_txq;
1151 struct port_info *pi = vi->pi;
1152 struct adapter *sc = pi->adapter;
1153 struct ifnet *ifp = vi->ifp;
1154 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1155 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1156 int maxp, mtu = ifp->if_mtu;
1158 /* Interrupt vector to start from (when using multiple vectors) */
1159 intr_idx = vi->first_intr;
1162 saved_idx = intr_idx;
1163 if (ifp->if_capabilities & IFCAP_NETMAP) {
1165 /* netmap is supported with direct interrupts only. */
1166 MPASS(!forwarding_intr_to_fwq(sc));
1169 * We don't have buffers to back the netmap rx queues
1170 * right now so we create the queues in a way that
1171 * doesn't set off any congestion signal in the chip.
1173 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1174 CTLFLAG_RD, NULL, "rx queues");
1175 for_each_nm_rxq(vi, i, nm_rxq) {
1176 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1182 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1183 CTLFLAG_RD, NULL, "tx queues");
1184 for_each_nm_txq(vi, i, nm_txq) {
1185 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1186 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1192 /* Normal rx queues and netmap rx queues share the same interrupts. */
1193 intr_idx = saved_idx;
1197 * Allocate rx queues first because a default iqid is required when
1198 * creating a tx queue.
1200 maxp = mtu_to_max_payload(sc, mtu);
1201 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1202 CTLFLAG_RD, NULL, "rx queues");
1203 for_each_rxq(vi, i, rxq) {
1205 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1207 snprintf(name, sizeof(name), "%s rxq%d-fl",
1208 device_get_nameunit(vi->dev), i);
1209 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1211 rc = alloc_rxq(vi, rxq,
1212 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1218 if (ifp->if_capabilities & IFCAP_NETMAP)
1219 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1222 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1223 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections");
1224 for_each_ofld_rxq(vi, i, ofld_rxq) {
1226 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1229 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1230 device_get_nameunit(vi->dev), i);
1231 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1233 rc = alloc_ofld_rxq(vi, ofld_rxq,
1234 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1242 * Now the tx queues.
1244 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1246 for_each_txq(vi, i, txq) {
1247 iqidx = vi->first_rxq + (i % vi->nrxq);
1248 snprintf(name, sizeof(name), "%s txq%d",
1249 device_get_nameunit(vi->dev), i);
1250 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1251 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1253 rc = alloc_txq(vi, txq, i, oid);
1257 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1258 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1259 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD");
1260 for_each_ofld_txq(vi, i, ofld_txq) {
1261 struct sysctl_oid *oid2;
1263 snprintf(name, sizeof(name), "%s ofld_txq%d",
1264 device_get_nameunit(vi->dev), i);
1265 if (vi->nofldrxq > 0) {
1266 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1267 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1268 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id,
1271 iqidx = vi->first_rxq + (i % vi->nrxq);
1272 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1273 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name);
1276 snprintf(name, sizeof(name), "%d", i);
1277 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1278 name, CTLFLAG_RD, NULL, "offload tx queue");
1280 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1287 t4_teardown_vi_queues(vi);
1296 t4_teardown_vi_queues(struct vi_info *vi)
1299 struct sge_rxq *rxq;
1300 struct sge_txq *txq;
1301 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1302 struct port_info *pi = vi->pi;
1303 struct adapter *sc = pi->adapter;
1304 struct sge_wrq *ofld_txq;
1307 struct sge_ofld_rxq *ofld_rxq;
1310 struct sge_nm_rxq *nm_rxq;
1311 struct sge_nm_txq *nm_txq;
1314 /* Do this before freeing the queues */
1315 if (vi->flags & VI_SYSCTL_CTX) {
1316 sysctl_ctx_free(&vi->ctx);
1317 vi->flags &= ~VI_SYSCTL_CTX;
1321 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1322 for_each_nm_txq(vi, i, nm_txq) {
1323 free_nm_txq(vi, nm_txq);
1326 for_each_nm_rxq(vi, i, nm_rxq) {
1327 free_nm_rxq(vi, nm_rxq);
1333 * Take down all the tx queues first, as they reference the rx queues
1334 * (for egress updates, etc.).
1337 for_each_txq(vi, i, txq) {
1340 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1341 for_each_ofld_txq(vi, i, ofld_txq) {
1342 free_wrq(sc, ofld_txq);
1347 * Then take down the rx queues.
1350 for_each_rxq(vi, i, rxq) {
1354 for_each_ofld_rxq(vi, i, ofld_rxq) {
1355 free_ofld_rxq(vi, ofld_rxq);
1363 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1366 * a) Deals with errors, if any.
1367 * b) Services firmware event queue, which is taking interrupts for all other
1371 t4_intr_all(void *arg)
1373 struct adapter *sc = arg;
1374 struct sge_iq *fwq = &sc->sge.fwq;
1376 MPASS(sc->intr_count == 1);
1378 if (sc->intr_type == INTR_INTX)
1379 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1386 * Interrupt handler for errors (installed directly when multiple interrupts are
1387 * being used, or called by t4_intr_all).
1390 t4_intr_err(void *arg)
1392 struct adapter *sc = arg;
1394 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1396 if (sc->flags & ADAP_ERR)
1399 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1402 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1405 t4_slow_intr_handler(sc, verbose);
1409 * Interrupt handler for iq-only queues. The firmware event queue is the only
1410 * such queue right now.
1413 t4_intr_evt(void *arg)
1415 struct sge_iq *iq = arg;
1417 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1419 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1424 * Interrupt handler for iq+fl queues.
1429 struct sge_iq *iq = arg;
1431 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1432 service_iq_fl(iq, 0);
1433 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1439 * Interrupt handler for netmap rx queues.
1442 t4_nm_intr(void *arg)
1444 struct sge_nm_rxq *nm_rxq = arg;
1446 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1447 service_nm_rxq(nm_rxq);
1448 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1453 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1456 t4_vi_intr(void *arg)
1458 struct irq *irq = arg;
1460 MPASS(irq->nm_rxq != NULL);
1461 t4_nm_intr(irq->nm_rxq);
1463 MPASS(irq->rxq != NULL);
1469 * Deals with interrupts on an iq-only (no freelist) queue.
1472 service_iq(struct sge_iq *iq, int budget)
1475 struct adapter *sc = iq->adapter;
1476 struct iq_desc *d = &iq->desc[iq->cidx];
1477 int ndescs = 0, limit;
1480 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1482 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1483 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1484 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1486 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1487 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1489 limit = budget ? budget : iq->qsize / 16;
1492 * We always come back and check the descriptor ring for new indirect
1493 * interrupts and other responses after running a single handler.
1496 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1500 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1501 lq = be32toh(d->rsp.pldbuflen_qid);
1504 case X_RSPD_TYPE_FLBUF:
1505 panic("%s: data for an iq (%p) with no freelist",
1510 case X_RSPD_TYPE_CPL:
1511 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1512 ("%s: bad opcode %02x.", __func__,
1514 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1517 case X_RSPD_TYPE_INTR:
1519 * There are 1K interrupt-capable queues (qids 0
1520 * through 1023). A response type indicating a
1521 * forwarded interrupt with a qid >= 1K is an
1522 * iWARP async notification.
1524 if (__predict_true(lq >= 1024)) {
1525 t4_an_handler(iq, &d->rsp);
1529 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1531 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1533 if (service_iq_fl(q, q->qsize / 16) == 0) {
1534 (void) atomic_cmpset_int(&q->state,
1535 IQS_BUSY, IQS_IDLE);
1537 STAILQ_INSERT_TAIL(&iql, q,
1545 ("%s: illegal response type %d on iq %p",
1546 __func__, rsp_type, iq));
1548 "%s: illegal response type %d on iq %p",
1549 device_get_nameunit(sc->dev), rsp_type, iq);
1554 if (__predict_false(++iq->cidx == iq->sidx)) {
1556 iq->gen ^= F_RSPD_GEN;
1559 if (__predict_false(++ndescs == limit)) {
1560 t4_write_reg(sc, sc->sge_gts_reg,
1562 V_INGRESSQID(iq->cntxt_id) |
1563 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1567 return (EINPROGRESS);
1572 if (STAILQ_EMPTY(&iql))
1576 * Process the head only, and send it to the back of the list if
1577 * it's still not done.
1579 q = STAILQ_FIRST(&iql);
1580 STAILQ_REMOVE_HEAD(&iql, link);
1581 if (service_iq_fl(q, q->qsize / 8) == 0)
1582 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1584 STAILQ_INSERT_TAIL(&iql, q, link);
1587 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1588 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1594 sort_before_lro(struct lro_ctrl *lro)
1597 return (lro->lro_mbuf_max != 0);
1600 static inline uint64_t
1601 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1603 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */
1605 if (n > UINT64_MAX / 1000000)
1606 return (n / sc->params.vpd.cclk * 1000000);
1608 return (n * 1000000 / sc->params.vpd.cclk);
1612 * Deals with interrupts on an iq+fl queue.
1615 service_iq_fl(struct sge_iq *iq, int budget)
1617 struct sge_rxq *rxq = iq_to_rxq(iq);
1619 struct adapter *sc = iq->adapter;
1620 struct iq_desc *d = &iq->desc[iq->cidx];
1621 int ndescs = 0, limit;
1622 int rsp_type, refill, starved;
1624 uint16_t fl_hw_cidx;
1626 #if defined(INET) || defined(INET6)
1627 const struct timeval lro_timeout = {0, sc->lro_timeout};
1628 struct lro_ctrl *lro = &rxq->lro;
1631 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1632 MPASS(iq->flags & IQ_HAS_FL);
1634 limit = budget ? budget : iq->qsize / 16;
1636 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1638 #if defined(INET) || defined(INET6)
1639 if (iq->flags & IQ_ADJ_CREDIT) {
1640 MPASS(sort_before_lro(lro));
1641 iq->flags &= ~IQ_ADJ_CREDIT;
1642 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1643 tcp_lro_flush_all(lro);
1644 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1645 V_INGRESSQID((u32)iq->cntxt_id) |
1646 V_SEINTARM(iq->intr_params));
1652 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1655 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1661 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1662 lq = be32toh(d->rsp.pldbuflen_qid);
1665 case X_RSPD_TYPE_FLBUF:
1667 m0 = get_fl_payload(sc, fl, lq);
1668 if (__predict_false(m0 == NULL))
1670 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1672 if (iq->flags & IQ_RX_TIMESTAMP) {
1674 * Fill up rcv_tstmp but do not set M_TSTMP.
1675 * rcv_tstmp is not in the format that the
1676 * kernel expects and we don't want to mislead
1677 * it. For now this is only for custom code
1678 * that knows how to interpret cxgbe's stamp.
1680 m0->m_pkthdr.rcv_tstmp =
1681 last_flit_to_ns(sc, d->rsp.u.last_flit);
1683 m0->m_flags |= M_TSTMP;
1689 case X_RSPD_TYPE_CPL:
1690 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1691 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1692 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1695 case X_RSPD_TYPE_INTR:
1698 * There are 1K interrupt-capable queues (qids 0
1699 * through 1023). A response type indicating a
1700 * forwarded interrupt with a qid >= 1K is an
1701 * iWARP async notification. That is the only
1702 * acceptable indirect interrupt on this queue.
1704 if (__predict_false(lq < 1024)) {
1705 panic("%s: indirect interrupt on iq_fl %p "
1706 "with qid %u", __func__, iq, lq);
1709 t4_an_handler(iq, &d->rsp);
1713 KASSERT(0, ("%s: illegal response type %d on iq %p",
1714 __func__, rsp_type, iq));
1715 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1716 device_get_nameunit(sc->dev), rsp_type, iq);
1721 if (__predict_false(++iq->cidx == iq->sidx)) {
1723 iq->gen ^= F_RSPD_GEN;
1726 if (__predict_false(++ndescs == limit)) {
1727 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1728 V_INGRESSQID(iq->cntxt_id) |
1729 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1732 #if defined(INET) || defined(INET6)
1733 if (iq->flags & IQ_LRO_ENABLED &&
1734 !sort_before_lro(lro) &&
1735 sc->lro_timeout != 0) {
1736 tcp_lro_flush_inactive(lro, &lro_timeout);
1741 refill_fl(sc, fl, 32);
1744 return (EINPROGRESS);
1749 refill_fl(sc, fl, 32);
1751 fl_hw_cidx = fl->hw_cidx;
1755 #if defined(INET) || defined(INET6)
1756 if (iq->flags & IQ_LRO_ENABLED) {
1757 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1758 MPASS(sort_before_lro(lro));
1759 /* hold back one credit and don't flush LRO state */
1760 iq->flags |= IQ_ADJ_CREDIT;
1763 tcp_lro_flush_all(lro);
1768 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1769 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1772 starved = refill_fl(sc, fl, 64);
1774 if (__predict_false(starved != 0))
1775 add_fl_to_sfl(sc, fl);
1781 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1783 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1786 MPASS(cll->region3 >= CL_METADATA_SIZE);
1791 static inline struct cluster_metadata *
1792 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1796 if (cl_has_metadata(fl, cll)) {
1797 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1799 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1805 rxb_free(struct mbuf *m)
1807 struct cluster_metadata *clm = m->m_ext.ext_arg1;
1809 uma_zfree(clm->zone, clm->cl);
1810 counter_u64_add(extfree_rels, 1);
1814 * The mbuf returned by this function could be allocated from zone_mbuf or
1815 * constructed in spare room in the cluster.
1817 * The mbuf carries the payload in one of these ways
1818 * a) frame inside the mbuf (mbuf from zone_mbuf)
1819 * b) m_cljset (for clusters without metadata) zone_mbuf
1820 * c) m_extaddref (cluster with metadata) inline mbuf
1821 * d) m_extaddref (cluster with metadata) zone_mbuf
1823 static struct mbuf *
1824 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1828 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1829 struct cluster_layout *cll = &sd->cll;
1830 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1831 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1832 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1836 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1837 len = min(remaining, blen);
1838 payload = sd->cl + cll->region1 + fl->rx_offset;
1839 if (fl->flags & FL_BUF_PACKING) {
1840 const u_int l = fr_offset + len;
1841 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1843 if (fl->rx_offset + len + pad < hwb->size)
1845 MPASS(fl->rx_offset + blen <= hwb->size);
1847 MPASS(fl->rx_offset == 0); /* not packing */
1851 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1854 * Copy payload into a freshly allocated mbuf.
1857 m = fr_offset == 0 ?
1858 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1861 fl->mbuf_allocated++;
1863 /* copy data to mbuf */
1864 bcopy(payload, mtod(m, caddr_t), len);
1866 } else if (sd->nmbuf * MSIZE < cll->region1) {
1869 * There's spare room in the cluster for an mbuf. Create one
1870 * and associate it with the payload that's in the cluster.
1874 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1875 /* No bzero required */
1876 if (m_init(m, M_NOWAIT, MT_DATA,
1877 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1880 if (sd->nmbuf++ == 0) {
1882 clm->zone = swz->zone;
1884 counter_u64_add(extfree_refs, 1);
1886 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1891 * Grab an mbuf from zone_mbuf and associate it with the
1892 * payload in the cluster.
1895 m = fr_offset == 0 ?
1896 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1899 fl->mbuf_allocated++;
1901 if (sd->nmbuf++ == 0) {
1903 clm->zone = swz->zone;
1905 counter_u64_add(extfree_refs, 1);
1907 m_extaddref(m, payload, blen, &clm->refcount,
1908 rxb_free, clm, NULL);
1910 m_cljset(m, sd->cl, swz->type);
1911 sd->cl = NULL; /* consumed, not a recycle candidate */
1915 m->m_pkthdr.len = remaining;
1918 if (fl->flags & FL_BUF_PACKING) {
1919 fl->rx_offset += blen;
1920 MPASS(fl->rx_offset <= hwb->size);
1921 if (fl->rx_offset < hwb->size)
1922 return (m); /* without advancing the cidx */
1925 if (__predict_false(++fl->cidx % 8 == 0)) {
1926 uint16_t cidx = fl->cidx / 8;
1928 if (__predict_false(cidx == fl->sidx))
1929 fl->cidx = cidx = 0;
1937 static struct mbuf *
1938 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1940 struct mbuf *m0, *m, **pnext;
1942 const u_int total = G_RSPD_LEN(len_newbuf);
1944 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1945 M_ASSERTPKTHDR(fl->m0);
1946 MPASS(fl->m0->m_pkthdr.len == total);
1947 MPASS(fl->remaining < total);
1951 remaining = fl->remaining;
1952 fl->flags &= ~FL_BUF_RESUME;
1956 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1958 if (__predict_false(++fl->cidx % 8 == 0)) {
1959 uint16_t cidx = fl->cidx / 8;
1961 if (__predict_false(cidx == fl->sidx))
1962 fl->cidx = cidx = 0;
1968 * Payload starts at rx_offset in the current hw buffer. Its length is
1969 * 'len' and it may span multiple hw buffers.
1972 m0 = get_scatter_segment(sc, fl, 0, total);
1975 remaining = total - m0->m_len;
1976 pnext = &m0->m_next;
1977 while (remaining > 0) {
1979 MPASS(fl->rx_offset == 0);
1980 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1981 if (__predict_false(m == NULL)) {
1984 fl->remaining = remaining;
1985 fl->flags |= FL_BUF_RESUME;
1990 remaining -= m->m_len;
1999 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
2001 struct sge_rxq *rxq = iq_to_rxq(iq);
2002 struct ifnet *ifp = rxq->ifp;
2003 struct adapter *sc = iq->adapter;
2004 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
2005 #if defined(INET) || defined(INET6)
2006 struct lro_ctrl *lro = &rxq->lro;
2008 static const int sw_hashtype[4][2] = {
2009 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
2010 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
2011 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
2012 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
2015 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
2018 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
2019 m0->m_len -= sc->params.sge.fl_pktshift;
2020 m0->m_data += sc->params.sge.fl_pktshift;
2022 m0->m_pkthdr.rcvif = ifp;
2023 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
2024 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
2026 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
2027 if (ifp->if_capenable & IFCAP_RXCSUM &&
2028 cpl->l2info & htobe32(F_RXF_IP)) {
2029 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
2030 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
2032 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
2033 cpl->l2info & htobe32(F_RXF_IP6)) {
2034 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
2039 if (__predict_false(cpl->ip_frag))
2040 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2042 m0->m_pkthdr.csum_data = 0xffff;
2046 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2047 m0->m_flags |= M_VLANTAG;
2048 rxq->vlan_extraction++;
2052 m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2054 #if defined(INET) || defined(INET6)
2055 if (iq->flags & IQ_LRO_ENABLED &&
2056 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2057 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2058 if (sort_before_lro(lro)) {
2059 tcp_lro_queue_mbuf(lro, m0);
2060 return (0); /* queued for sort, then LRO */
2062 if (tcp_lro_rx(lro, m0, 0) == 0)
2063 return (0); /* queued for LRO */
2066 ifp->if_input(ifp, m0);
2072 * Must drain the wrq or make sure that someone else will.
2075 wrq_tx_drain(void *arg, int n)
2077 struct sge_wrq *wrq = arg;
2078 struct sge_eq *eq = &wrq->eq;
2081 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2082 drain_wrq_wr_list(wrq->adapter, wrq);
2087 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2089 struct sge_eq *eq = &wrq->eq;
2090 u_int available, dbdiff; /* # of hardware descriptors */
2093 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2095 EQ_LOCK_ASSERT_OWNED(eq);
2096 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2097 wr = STAILQ_FIRST(&wrq->wr_list);
2098 MPASS(wr != NULL); /* Must be called with something useful to do */
2099 MPASS(eq->pidx == eq->dbidx);
2103 eq->cidx = read_hw_cidx(eq);
2104 if (eq->pidx == eq->cidx)
2105 available = eq->sidx - 1;
2107 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2109 MPASS(wr->wrq == wrq);
2110 n = howmany(wr->wr_len, EQ_ESIZE);
2114 dst = (void *)&eq->desc[eq->pidx];
2115 if (__predict_true(eq->sidx - eq->pidx > n)) {
2116 /* Won't wrap, won't end exactly at the status page. */
2117 bcopy(&wr->wr[0], dst, wr->wr_len);
2120 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2122 bcopy(&wr->wr[0], dst, first_portion);
2123 if (wr->wr_len > first_portion) {
2124 bcopy(&wr->wr[first_portion], &eq->desc[0],
2125 wr->wr_len - first_portion);
2127 eq->pidx = n - (eq->sidx - eq->pidx);
2129 wrq->tx_wrs_copied++;
2131 if (available < eq->sidx / 4 &&
2132 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2134 * XXX: This is not 100% reliable with some
2135 * types of WRs. But this is a very unusual
2136 * situation for an ofld/ctrl queue anyway.
2138 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2144 ring_eq_db(sc, eq, dbdiff);
2148 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2150 MPASS(wrq->nwr_pending > 0);
2152 MPASS(wrq->ndesc_needed >= n);
2153 wrq->ndesc_needed -= n;
2154 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2157 ring_eq_db(sc, eq, dbdiff);
2161 * Doesn't fail. Holds on to work requests it can't send right away.
2164 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2167 struct sge_eq *eq = &wrq->eq;
2170 EQ_LOCK_ASSERT_OWNED(eq);
2172 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2173 MPASS((wr->wr_len & 0x7) == 0);
2175 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2177 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2179 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2180 return; /* commit_wrq_wr will drain wr_list as well. */
2182 drain_wrq_wr_list(sc, wrq);
2184 /* Doorbell must have caught up to the pidx. */
2185 MPASS(eq->pidx == eq->dbidx);
2189 t4_update_fl_bufsize(struct ifnet *ifp)
2191 struct vi_info *vi = ifp->if_softc;
2192 struct adapter *sc = vi->pi->adapter;
2193 struct sge_rxq *rxq;
2195 struct sge_ofld_rxq *ofld_rxq;
2198 int i, maxp, mtu = ifp->if_mtu;
2200 maxp = mtu_to_max_payload(sc, mtu);
2201 for_each_rxq(vi, i, rxq) {
2205 find_best_refill_source(sc, fl, maxp);
2209 for_each_ofld_rxq(vi, i, ofld_rxq) {
2213 find_best_refill_source(sc, fl, maxp);
2220 mbuf_nsegs(struct mbuf *m)
2224 KASSERT(m->m_pkthdr.l5hlen > 0,
2225 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2227 return (m->m_pkthdr.l5hlen);
2231 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2235 m->m_pkthdr.l5hlen = nsegs;
2239 mbuf_cflags(struct mbuf *m)
2243 return (m->m_pkthdr.PH_loc.eight[4]);
2247 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2251 m->m_pkthdr.PH_loc.eight[4] = flags;
2255 mbuf_len16(struct mbuf *m)
2260 n = m->m_pkthdr.PH_loc.eight[0];
2261 if (!(mbuf_cflags(m) & MC_TLS))
2262 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2268 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2272 m->m_pkthdr.PH_loc.eight[0] = len16;
2277 mbuf_eo_nsegs(struct mbuf *m)
2281 return (m->m_pkthdr.PH_loc.eight[1]);
2285 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2289 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2293 mbuf_eo_len16(struct mbuf *m)
2298 n = m->m_pkthdr.PH_loc.eight[2];
2299 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2305 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2309 m->m_pkthdr.PH_loc.eight[2] = len16;
2313 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2317 return (m->m_pkthdr.PH_loc.eight[3]);
2321 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2325 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2329 needs_eo(struct cxgbe_snd_tag *cst)
2332 return (cst != NULL && cst->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2337 * Try to allocate an mbuf to contain a raw work request. To make it
2338 * easy to construct the work request, don't allocate a chain but a
2342 alloc_wr_mbuf(int len, int how)
2347 m = m_gethdr(how, MT_DATA);
2348 else if (len <= MCLBYTES)
2349 m = m_getcl(how, MT_DATA, M_PKTHDR);
2354 m->m_pkthdr.len = len;
2356 set_mbuf_cflags(m, MC_RAW_WR);
2357 set_mbuf_len16(m, howmany(len, 16));
2362 needs_hwcsum(struct mbuf *m)
2367 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP |
2368 CSUM_TSO | CSUM_UDP_IPV6 | CSUM_TCP_IPV6));
2372 needs_tso(struct mbuf *m)
2377 return (m->m_pkthdr.csum_flags & CSUM_TSO);
2381 needs_l3_csum(struct mbuf *m)
2386 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO));
2390 needs_tcp_csum(struct mbuf *m)
2394 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO));
2399 needs_l4_csum(struct mbuf *m)
2404 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2405 CSUM_TCP_IPV6 | CSUM_TSO));
2409 needs_udp_csum(struct mbuf *m)
2413 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6));
2418 needs_vlan_insertion(struct mbuf *m)
2423 return (m->m_flags & M_VLANTAG);
2427 m_advance(struct mbuf **pm, int *poffset, int len)
2429 struct mbuf *m = *pm;
2430 int offset = *poffset;
2436 if (offset + len < m->m_len) {
2438 p = mtod(m, uintptr_t) + offset;
2441 len -= m->m_len - offset;
2452 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2454 struct mbuf_ext_pgs *ext_pgs;
2456 int i, len, off, pglen, pgoff, seglen, segoff;
2459 MBUF_EXT_PGS_ASSERT(m);
2460 ext_pgs = m->m_ext.ext_pgs;
2461 off = mtod(m, vm_offset_t);
2466 if (ext_pgs->hdr_len != 0) {
2467 if (off >= ext_pgs->hdr_len) {
2468 off -= ext_pgs->hdr_len;
2470 seglen = ext_pgs->hdr_len - off;
2472 seglen = min(seglen, len);
2475 paddr = pmap_kextract(
2476 (vm_offset_t)&ext_pgs->hdr[segoff]);
2477 if (*nextaddr != paddr)
2479 *nextaddr = paddr + seglen;
2482 pgoff = ext_pgs->first_pg_off;
2483 for (i = 0; i < ext_pgs->npgs && len > 0; i++) {
2484 pglen = mbuf_ext_pg_len(ext_pgs, i, pgoff);
2490 seglen = pglen - off;
2491 segoff = pgoff + off;
2493 seglen = min(seglen, len);
2495 paddr = ext_pgs->pa[i] + segoff;
2496 if (*nextaddr != paddr)
2498 *nextaddr = paddr + seglen;
2502 seglen = min(len, ext_pgs->trail_len - off);
2504 paddr = pmap_kextract((vm_offset_t)&ext_pgs->trail[off]);
2505 if (*nextaddr != paddr)
2507 *nextaddr = paddr + seglen;
2515 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2516 * must have at least one mbuf that's not empty. It is possible for this
2517 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2520 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2522 vm_paddr_t nextaddr, paddr;
2527 MPASS(m->m_pkthdr.len > 0);
2528 MPASS(m->m_pkthdr.len >= skip);
2532 for (; m; m = m->m_next) {
2534 if (__predict_false(len == 0))
2540 if ((m->m_flags & M_NOMAP) != 0) {
2541 *cflags |= MC_NOMAP;
2542 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2546 va = mtod(m, vm_offset_t) + skip;
2549 paddr = pmap_kextract(va);
2550 nsegs += sglist_count((void *)(uintptr_t)va, len);
2551 if (paddr == nextaddr)
2553 nextaddr = pmap_kextract(va + len - 1) + 1;
2560 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2561 * a) caller can assume it's been freed if this function returns with an error.
2562 * b) it may get defragged up if the gather list is too long for the hardware.
2565 parse_pkt(struct adapter *sc, struct mbuf **mp)
2567 struct mbuf *m0 = *mp, *m;
2568 int rc, nsegs, defragged = 0, offset;
2569 struct ether_header *eh;
2571 #if defined(INET) || defined(INET6)
2574 #if defined(KERN_TLS) || defined(RATELIMIT)
2575 struct cxgbe_snd_tag *cst;
2582 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2591 * First count the number of gather list segments in the payload.
2592 * Defrag the mbuf if nsegs exceeds the hardware limit.
2595 MPASS(m0->m_pkthdr.len > 0);
2596 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2597 #if defined(KERN_TLS) || defined(RATELIMIT)
2598 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2599 cst = mst_to_cst(m0->m_pkthdr.snd_tag);
2604 if (cst != NULL && cst->type == IF_SND_TAG_TYPE_TLS) {
2608 set_mbuf_cflags(m0, cflags);
2609 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16);
2612 set_mbuf_nsegs(m0, nsegs);
2613 set_mbuf_len16(m0, len16);
2617 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2618 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2622 *mp = m0 = m; /* update caller's copy after defrag */
2626 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2627 !(cflags & MC_NOMAP))) {
2628 m0 = m_pullup(m0, m0->m_pkthdr.len);
2630 /* Should have left well enough alone. */
2634 *mp = m0; /* update caller's copy after pullup */
2637 set_mbuf_nsegs(m0, nsegs);
2638 set_mbuf_cflags(m0, cflags);
2639 if (sc->flags & IS_VF)
2640 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2642 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2646 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2647 * checksumming is enabled. needs_l4_csum happens to check for all the
2650 if (__predict_false(needs_eo(cst) && !needs_l4_csum(m0))) {
2651 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2652 m0->m_pkthdr.snd_tag = NULL;
2653 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2658 if (!needs_hwcsum(m0)
2666 eh = mtod(m, struct ether_header *);
2667 eh_type = ntohs(eh->ether_type);
2668 if (eh_type == ETHERTYPE_VLAN) {
2669 struct ether_vlan_header *evh = (void *)eh;
2671 eh_type = ntohs(evh->evl_proto);
2672 m0->m_pkthdr.l2hlen = sizeof(*evh);
2674 m0->m_pkthdr.l2hlen = sizeof(*eh);
2677 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2681 case ETHERTYPE_IPV6:
2683 struct ip6_hdr *ip6 = l3hdr;
2685 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2687 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2694 struct ip *ip = l3hdr;
2696 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2701 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2702 " with the same INET/INET6 options as the kernel.",
2706 #if defined(INET) || defined(INET6)
2707 if (needs_tcp_csum(m0)) {
2708 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2709 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2711 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2712 set_mbuf_eo_tsclk_tsoff(m0,
2713 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2714 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2716 set_mbuf_eo_tsclk_tsoff(m0, 0);
2717 } else if (needs_udp_csum(m0)) {
2718 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2722 if (needs_eo(cst)) {
2725 /* EO WRs have the headers in the WR and not the GL. */
2726 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2727 m0->m_pkthdr.l4hlen;
2729 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2730 MPASS(cflags == mbuf_cflags(m0));
2731 set_mbuf_eo_nsegs(m0, nsegs);
2732 set_mbuf_eo_len16(m0,
2733 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2742 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2744 struct sge_eq *eq = &wrq->eq;
2745 struct adapter *sc = wrq->adapter;
2746 int ndesc, available;
2751 ndesc = howmany(len16, EQ_ESIZE / 16);
2752 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2756 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2757 drain_wrq_wr_list(sc, wrq);
2759 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2762 wr = alloc_wrqe(len16 * 16, wrq);
2763 if (__predict_false(wr == NULL))
2766 cookie->ndesc = ndesc;
2770 eq->cidx = read_hw_cidx(eq);
2771 if (eq->pidx == eq->cidx)
2772 available = eq->sidx - 1;
2774 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2775 if (available < ndesc)
2778 cookie->pidx = eq->pidx;
2779 cookie->ndesc = ndesc;
2780 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2782 w = &eq->desc[eq->pidx];
2783 IDXINCR(eq->pidx, ndesc, eq->sidx);
2784 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2786 wrq->ss_pidx = cookie->pidx;
2787 wrq->ss_len = len16 * 16;
2796 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2798 struct sge_eq *eq = &wrq->eq;
2799 struct adapter *sc = wrq->adapter;
2801 struct wrq_cookie *prev, *next;
2803 if (cookie->pidx == -1) {
2804 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2810 if (__predict_false(w == &wrq->ss[0])) {
2811 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2813 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2814 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2815 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2818 wrq->tx_wrs_direct++;
2821 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2822 pidx = cookie->pidx;
2823 MPASS(pidx >= 0 && pidx < eq->sidx);
2824 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2825 next = TAILQ_NEXT(cookie, link);
2827 MPASS(pidx == eq->dbidx);
2828 if (next == NULL || ndesc >= 16) {
2830 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2833 * Note that the WR via which we'll request tx updates
2834 * is at pidx and not eq->pidx, which has moved on
2837 dst = (void *)&eq->desc[pidx];
2838 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2839 if (available < eq->sidx / 4 &&
2840 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2842 * XXX: This is not 100% reliable with some
2843 * types of WRs. But this is a very unusual
2844 * situation for an ofld/ctrl queue anyway.
2846 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2850 ring_eq_db(wrq->adapter, eq, ndesc);
2852 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2854 next->ndesc += ndesc;
2857 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2858 prev->ndesc += ndesc;
2860 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2862 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2863 drain_wrq_wr_list(sc, wrq);
2866 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2867 /* Doorbell must have caught up to the pidx. */
2868 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2875 can_resume_eth_tx(struct mp_ring *r)
2877 struct sge_eq *eq = r->cookie;
2879 return (total_available_tx_desc(eq) > eq->sidx / 8);
2883 cannot_use_txpkts(struct mbuf *m)
2885 /* maybe put a GL limit too, to avoid silliness? */
2887 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
2891 discard_tx(struct sge_eq *eq)
2894 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2898 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr)
2901 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
2903 case FW_ETH_TX_PKT_WR:
2904 case FW_ETH_TX_PKTS_WR:
2905 case FW_ETH_TX_PKTS2_WR:
2906 case FW_ETH_TX_PKT_VM_WR:
2914 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2915 * be consumed. Return the actual number consumed. 0 indicates a stall.
2918 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2920 struct sge_txq *txq = r->cookie;
2921 struct sge_eq *eq = &txq->eq;
2922 struct ifnet *ifp = txq->ifp;
2923 struct vi_info *vi = ifp->if_softc;
2924 struct port_info *pi = vi->pi;
2925 struct adapter *sc = pi->adapter;
2926 u_int total, remaining; /* # of packets */
2927 u_int available, dbdiff; /* # of hardware descriptors */
2929 struct mbuf *m0, *tail;
2931 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2933 remaining = IDXDIFF(pidx, cidx, r->size);
2934 MPASS(remaining > 0); /* Must not be called without work to do. */
2938 if (__predict_false(discard_tx(eq))) {
2939 while (cidx != pidx) {
2940 m0 = r->items[cidx];
2942 if (++cidx == r->size)
2945 reclaim_tx_descs(txq, 2048);
2950 /* How many hardware descriptors do we have readily available. */
2951 if (eq->pidx == eq->cidx)
2952 available = eq->sidx - 1;
2954 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2955 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2957 while (remaining > 0) {
2959 m0 = r->items[cidx];
2961 MPASS(m0->m_nextpkt == NULL);
2963 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16)) {
2964 MPASS(howmany(mbuf_len16(m0), EQ_ESIZE / 16) <= 64);
2965 available += reclaim_tx_descs(txq, 64);
2966 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2967 break; /* out of descriptors */
2970 next_cidx = cidx + 1;
2971 if (__predict_false(next_cidx == r->size))
2974 wr = (void *)&eq->desc[eq->pidx];
2975 if (mbuf_cflags(m0) & MC_RAW_WR) {
2978 n = write_raw_wr(txq, (void *)wr, m0, available);
2980 } else if (mbuf_cflags(m0) & MC_TLS) {
2983 ETHER_BPF_MTAP(ifp, m0);
2984 n = t6_ktls_write_wr(txq,(void *)wr, m0,
2985 mbuf_nsegs(m0), available);
2987 } else if (sc->flags & IS_VF) {
2990 ETHER_BPF_MTAP(ifp, m0);
2991 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2993 } else if (remaining > 1 &&
2994 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2996 /* pkts at cidx, next_cidx should both be in txp. */
2997 MPASS(txp.npkt == 2);
2998 tail = r->items[next_cidx];
2999 MPASS(tail->m_nextpkt == NULL);
3000 ETHER_BPF_MTAP(ifp, m0);
3001 ETHER_BPF_MTAP(ifp, tail);
3002 m0->m_nextpkt = tail;
3004 if (__predict_false(++next_cidx == r->size))
3007 while (next_cidx != pidx) {
3008 if (add_to_txpkts(r->items[next_cidx], &txp,
3011 tail->m_nextpkt = r->items[next_cidx];
3012 tail = tail->m_nextpkt;
3013 ETHER_BPF_MTAP(ifp, tail);
3014 if (__predict_false(++next_cidx == r->size))
3018 n = write_txpkts_wr(sc, txq, wr, m0, &txp, available);
3020 remaining -= txp.npkt;
3024 ETHER_BPF_MTAP(ifp, m0);
3025 n = write_txpkt_wr(sc, txq, (void *)wr, m0, available);
3027 MPASS(n >= 1 && n <= available);
3028 if (!(mbuf_cflags(m0) & MC_TLS))
3029 MPASS(n <= SGE_MAX_WR_NDESC);
3033 IDXINCR(eq->pidx, n, eq->sidx);
3035 if (wr_can_update_eq(wr)) {
3036 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
3037 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3038 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3040 eq->equeqidx = eq->pidx;
3041 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >=
3043 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3044 eq->equeqidx = eq->pidx;
3048 if (dbdiff >= 16 && remaining >= 4) {
3049 ring_eq_db(sc, eq, dbdiff);
3050 available += reclaim_tx_descs(txq, 4 * dbdiff);
3057 ring_eq_db(sc, eq, dbdiff);
3058 reclaim_tx_descs(txq, 32);
3067 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3071 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3072 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3073 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3074 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3078 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3079 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3080 if (pktc_idx >= 0) {
3081 iq->intr_params |= F_QINTR_CNT_EN;
3082 iq->intr_pktc_idx = pktc_idx;
3084 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3085 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3089 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3093 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3094 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3095 if (sc->flags & BUF_PACKING_OK &&
3096 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3097 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3098 fl->flags |= FL_BUF_PACKING;
3099 find_best_refill_source(sc, fl, maxp);
3100 find_safe_refill_source(sc, fl);
3104 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3105 uint8_t tx_chan, uint16_t iqid, char *name)
3107 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
3109 eq->flags = eqtype & EQ_TYPEMASK;
3110 eq->tx_chan = tx_chan;
3112 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3113 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3117 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3118 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3122 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3123 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3125 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
3129 rc = bus_dmamem_alloc(*tag, va,
3130 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3132 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
3136 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3138 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
3143 free_ring(sc, *tag, *map, *pa, *va);
3149 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3150 bus_addr_t pa, void *va)
3153 bus_dmamap_unload(tag, map);
3155 bus_dmamem_free(tag, va, map);
3157 bus_dma_tag_destroy(tag);
3163 * Allocates the ring for an ingress queue and an optional freelist. If the
3164 * freelist is specified it will be allocated and then associated with the
3167 * Returns errno on failure. Resources allocated up to that point may still be
3168 * allocated. Caller is responsible for cleanup in case this function fails.
3170 * If the ingress queue will take interrupts directly then the intr_idx
3171 * specifies the vector, starting from 0. -1 means the interrupts for this
3172 * queue should be forwarded to the fwq.
3175 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3176 int intr_idx, int cong)
3178 int rc, i, cntxt_id;
3181 struct port_info *pi = vi->pi;
3182 struct adapter *sc = iq->adapter;
3183 struct sge_params *sp = &sc->params.sge;
3186 len = iq->qsize * IQ_ESIZE;
3187 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3188 (void **)&iq->desc);
3192 bzero(&c, sizeof(c));
3193 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3194 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3195 V_FW_IQ_CMD_VFN(0));
3197 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3200 /* Special handling for firmware event queue */
3201 if (iq == &sc->sge.fwq)
3202 v |= F_FW_IQ_CMD_IQASYNCH;
3205 /* Forwarded interrupts, all headed to fwq */
3206 v |= F_FW_IQ_CMD_IQANDST;
3207 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3209 KASSERT(intr_idx < sc->intr_count,
3210 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
3211 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
3214 c.type_to_iqandstindex = htobe32(v |
3215 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3216 V_FW_IQ_CMD_VIID(vi->viid) |
3217 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3218 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3219 F_FW_IQ_CMD_IQGTSMODE |
3220 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3221 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3222 c.iqsize = htobe16(iq->qsize);
3223 c.iqaddr = htobe64(iq->ba);
3225 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3228 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3230 len = fl->qsize * EQ_ESIZE;
3231 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3232 &fl->ba, (void **)&fl->desc);
3236 /* Allocate space for one software descriptor per buffer. */
3237 rc = alloc_fl_sdesc(fl);
3239 device_printf(sc->dev,
3240 "failed to setup fl software descriptors: %d\n",
3245 if (fl->flags & FL_BUF_PACKING) {
3246 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3247 fl->buf_boundary = sp->pack_boundary;
3249 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3250 fl->buf_boundary = 16;
3252 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3253 fl->buf_boundary = sp->pad_boundary;
3255 c.iqns_to_fl0congen |=
3256 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3257 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3258 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3259 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3262 c.iqns_to_fl0congen |=
3263 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
3264 F_FW_IQ_CMD_FL0CONGCIF |
3265 F_FW_IQ_CMD_FL0CONGEN);
3267 c.fl0dcaen_to_fl0cidxfthresh =
3268 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3269 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3270 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3271 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3272 c.fl0size = htobe16(fl->qsize);
3273 c.fl0addr = htobe64(fl->ba);
3276 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3278 device_printf(sc->dev,
3279 "failed to create ingress queue: %d\n", rc);
3284 iq->gen = F_RSPD_GEN;
3285 iq->intr_next = iq->intr_params;
3286 iq->cntxt_id = be16toh(c.iqid);
3287 iq->abs_id = be16toh(c.physiqid);
3288 iq->flags |= IQ_ALLOCATED;
3290 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3291 if (cntxt_id >= sc->sge.niq) {
3292 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3293 cntxt_id, sc->sge.niq - 1);
3295 sc->sge.iqmap[cntxt_id] = iq;
3300 iq->flags |= IQ_HAS_FL;
3301 fl->cntxt_id = be16toh(c.fl0id);
3302 fl->pidx = fl->cidx = 0;
3304 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3305 if (cntxt_id >= sc->sge.neq) {
3306 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3307 __func__, cntxt_id, sc->sge.neq - 1);
3309 sc->sge.eqmap[cntxt_id] = (void *)fl;
3312 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3313 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3314 uint32_t mask = (1 << s_qpp) - 1;
3315 volatile uint8_t *udb;
3317 udb = sc->udbs_base + UDBS_DB_OFFSET;
3318 udb += (qid >> s_qpp) << PAGE_SHIFT;
3320 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3321 udb += qid << UDBS_SEG_SHIFT;
3324 fl->udb = (volatile void *)udb;
3326 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3329 /* Enough to make sure the SGE doesn't think it's starved */
3330 refill_fl(sc, fl, fl->lowat);
3334 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
3335 uint32_t param, val;
3337 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3338 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3339 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3344 for (i = 0; i < 4; i++) {
3345 if (cong & (1 << i))
3346 val |= 1 << (i << 2);
3350 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3352 /* report error but carry on */
3353 device_printf(sc->dev,
3354 "failed to set congestion manager context for "
3355 "ingress queue %d: %d\n", iq->cntxt_id, rc);
3359 /* Enable IQ interrupts */
3360 atomic_store_rel_int(&iq->state, IQS_IDLE);
3361 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3362 V_INGRESSQID(iq->cntxt_id));
3368 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3371 struct adapter *sc = iq->adapter;
3375 return (0); /* nothing to do */
3377 dev = vi ? vi->dev : sc->dev;
3379 if (iq->flags & IQ_ALLOCATED) {
3380 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
3381 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
3382 fl ? fl->cntxt_id : 0xffff, 0xffff);
3385 "failed to free queue %p: %d\n", iq, rc);
3388 iq->flags &= ~IQ_ALLOCATED;
3391 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3393 bzero(iq, sizeof(*iq));
3396 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
3400 free_fl_sdesc(sc, fl);
3402 if (mtx_initialized(&fl->fl_lock))
3403 mtx_destroy(&fl->fl_lock);
3405 bzero(fl, sizeof(*fl));
3412 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3415 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3417 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3418 "bus address of descriptor ring");
3419 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3420 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3421 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3422 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I",
3423 "absolute id of the queue");
3424 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3425 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I",
3426 "SGE context id of the queue");
3427 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3428 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I",
3433 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3434 struct sysctl_oid *oid, struct sge_fl *fl)
3436 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3438 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3440 children = SYSCTL_CHILDREN(oid);
3442 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3443 &fl->ba, "bus address of descriptor ring");
3444 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3445 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3446 "desc ring size in bytes");
3447 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3448 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
3449 "SGE context id of the freelist");
3450 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3451 fl_pad ? 1 : 0, "padding enabled");
3452 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3453 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3454 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3455 0, "consumer index");
3456 if (fl->flags & FL_BUF_PACKING) {
3457 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3458 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3460 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3461 0, "producer index");
3462 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
3463 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
3464 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
3465 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
3466 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3467 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3468 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3469 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3470 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3471 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3475 alloc_fwq(struct adapter *sc)
3478 struct sge_iq *fwq = &sc->sge.fwq;
3479 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3480 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3482 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3483 if (sc->flags & IS_VF)
3486 intr_idx = sc->intr_count > 1 ? 1 : 0;
3487 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3489 device_printf(sc->dev,
3490 "failed to create firmware event queue: %d\n", rc);
3494 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
3495 NULL, "firmware event queue");
3496 add_iq_sysctls(&sc->ctx, oid, fwq);
3502 free_fwq(struct adapter *sc)
3504 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3508 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx,
3509 struct sysctl_oid *oid)
3513 struct sysctl_oid_list *children;
3515 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev),
3517 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan,
3518 sc->sge.fwq.cntxt_id, name);
3520 children = SYSCTL_CHILDREN(oid);
3521 snprintf(name, sizeof(name), "%d", idx);
3522 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3523 NULL, "ctrl queue");
3524 rc = alloc_wrq(sc, NULL, ctrlq, oid);
3530 tnl_cong(struct port_info *pi, int drop)
3538 return (pi->rx_e_chan_map);
3542 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3543 struct sysctl_oid *oid)
3546 struct adapter *sc = vi->pi->adapter;
3547 struct sysctl_oid_list *children;
3550 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3551 tnl_cong(vi->pi, cong_drop));
3556 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3558 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3559 ("iq_base mismatch"));
3560 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3561 ("PF with non-zero iq_base"));
3564 * The freelist is just barely above the starvation threshold right now,
3565 * fill it up a bit more.
3568 refill_fl(sc, &rxq->fl, 128);
3569 FL_UNLOCK(&rxq->fl);
3571 #if defined(INET) || defined(INET6)
3572 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3575 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3577 if (vi->ifp->if_capenable & IFCAP_LRO)
3578 rxq->iq.flags |= IQ_LRO_ENABLED;
3580 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP)
3581 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3584 children = SYSCTL_CHILDREN(oid);
3586 snprintf(name, sizeof(name), "%d", idx);
3587 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3589 children = SYSCTL_CHILDREN(oid);
3591 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3592 #if defined(INET) || defined(INET6)
3593 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3594 &rxq->lro.lro_queued, 0, NULL);
3595 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3596 &rxq->lro.lro_flushed, 0, NULL);
3598 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3599 &rxq->rxcsum, "# of times hardware assisted with checksum");
3600 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3601 CTLFLAG_RD, &rxq->vlan_extraction,
3602 "# of times hardware extracted 802.1Q tag");
3604 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3610 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3614 #if defined(INET) || defined(INET6)
3616 tcp_lro_free(&rxq->lro);
3617 rxq->lro.ifp = NULL;
3621 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3623 bzero(rxq, sizeof(*rxq));
3630 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3631 int intr_idx, int idx, struct sysctl_oid *oid)
3633 struct port_info *pi = vi->pi;
3635 struct sysctl_oid_list *children;
3638 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3642 children = SYSCTL_CHILDREN(oid);
3644 snprintf(name, sizeof(name), "%d", idx);
3645 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3647 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3648 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3654 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3658 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3660 bzero(ofld_rxq, sizeof(*ofld_rxq));
3668 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3669 int idx, struct sysctl_oid *oid)
3672 struct sysctl_oid_list *children;
3673 struct sysctl_ctx_list *ctx;
3676 struct adapter *sc = vi->pi->adapter;
3677 struct netmap_adapter *na = NA(vi->ifp);
3681 len = vi->qsize_rxq * IQ_ESIZE;
3682 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3683 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3687 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3688 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3689 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3695 nm_rxq->iq_cidx = 0;
3696 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3697 nm_rxq->iq_gen = F_RSPD_GEN;
3698 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3699 nm_rxq->fl_sidx = na->num_rx_desc;
3700 nm_rxq->intr_idx = intr_idx;
3701 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3704 children = SYSCTL_CHILDREN(oid);
3706 snprintf(name, sizeof(name), "%d", idx);
3707 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3709 children = SYSCTL_CHILDREN(oid);
3711 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3712 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3713 "I", "absolute id of the queue");
3714 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3715 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3716 "I", "SGE context id of the queue");
3717 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3718 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3721 children = SYSCTL_CHILDREN(oid);
3722 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3724 children = SYSCTL_CHILDREN(oid);
3726 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3727 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3728 "I", "SGE context id of the freelist");
3729 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3730 &nm_rxq->fl_cidx, 0, "consumer index");
3731 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3732 &nm_rxq->fl_pidx, 0, "producer index");
3739 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3741 struct adapter *sc = vi->pi->adapter;
3743 if (vi->flags & VI_INIT_DONE)
3744 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3746 MPASS(nm_rxq->iq_cntxt_id == 0);
3748 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3750 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3757 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3758 struct sysctl_oid *oid)
3762 struct port_info *pi = vi->pi;
3763 struct adapter *sc = pi->adapter;
3764 struct netmap_adapter *na = NA(vi->ifp);
3766 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3768 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3769 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3770 &nm_txq->ba, (void **)&nm_txq->desc);
3774 nm_txq->pidx = nm_txq->cidx = 0;
3775 nm_txq->sidx = na->num_tx_desc;
3777 nm_txq->iqidx = iqidx;
3778 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3779 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
3780 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
3781 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0))
3782 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
3784 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
3785 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3787 snprintf(name, sizeof(name), "%d", idx);
3788 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3789 NULL, "netmap tx queue");
3790 children = SYSCTL_CHILDREN(oid);
3792 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3793 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3794 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3795 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3797 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3798 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3805 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3807 struct adapter *sc = vi->pi->adapter;
3809 if (vi->flags & VI_INIT_DONE)
3810 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3812 MPASS(nm_txq->cntxt_id == 0);
3814 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3822 * Returns a reasonable automatic cidx flush threshold for a given queue size.
3825 qsize_to_fthresh(int qsize)
3829 while (!powerof2(qsize))
3831 fthresh = ilog2(qsize);
3832 if (fthresh > X_CIDXFLUSHTHRESH_128)
3833 fthresh = X_CIDXFLUSHTHRESH_128;
3839 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3842 struct fw_eq_ctrl_cmd c;
3843 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3845 bzero(&c, sizeof(c));
3847 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3848 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3849 V_FW_EQ_CTRL_CMD_VFN(0));
3850 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3851 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3852 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3853 c.physeqid_pkd = htobe32(0);
3854 c.fetchszm_to_iqid =
3855 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3856 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3857 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3859 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3860 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
3861 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3862 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3863 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3864 c.eqaddr = htobe64(eq->ba);
3866 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3868 device_printf(sc->dev,
3869 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3872 eq->flags |= EQ_ALLOCATED;
3874 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3875 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3876 if (cntxt_id >= sc->sge.neq)
3877 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3878 cntxt_id, sc->sge.neq - 1);
3879 sc->sge.eqmap[cntxt_id] = eq;
3885 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3888 struct fw_eq_eth_cmd c;
3889 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3891 bzero(&c, sizeof(c));
3893 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3894 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3895 V_FW_EQ_ETH_CMD_VFN(0));
3896 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3897 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3898 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3899 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3900 c.fetchszm_to_iqid =
3901 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3902 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3903 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3905 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3906 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
3907 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3908 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3909 c.eqaddr = htobe64(eq->ba);
3911 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3913 device_printf(vi->dev,
3914 "failed to create Ethernet egress queue: %d\n", rc);
3917 eq->flags |= EQ_ALLOCATED;
3919 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3920 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3921 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3922 if (cntxt_id >= sc->sge.neq)
3923 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3924 cntxt_id, sc->sge.neq - 1);
3925 sc->sge.eqmap[cntxt_id] = eq;
3930 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3932 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3935 struct fw_eq_ofld_cmd c;
3936 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3938 bzero(&c, sizeof(c));
3940 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3941 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3942 V_FW_EQ_OFLD_CMD_VFN(0));
3943 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3944 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3945 c.fetchszm_to_iqid =
3946 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3947 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3948 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3950 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3951 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
3952 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3953 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3954 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3955 c.eqaddr = htobe64(eq->ba);
3957 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3959 device_printf(vi->dev,
3960 "failed to create egress queue for TCP offload: %d\n", rc);
3963 eq->flags |= EQ_ALLOCATED;
3965 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3966 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3967 if (cntxt_id >= sc->sge.neq)
3968 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3969 cntxt_id, sc->sge.neq - 1);
3970 sc->sge.eqmap[cntxt_id] = eq;
3977 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3982 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3984 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3985 len = qsize * EQ_ESIZE;
3986 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3987 &eq->ba, (void **)&eq->desc);
3991 eq->pidx = eq->cidx = eq->dbidx = 0;
3992 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
3994 eq->doorbells = sc->doorbells;
3996 switch (eq->flags & EQ_TYPEMASK) {
3998 rc = ctrl_eq_alloc(sc, eq);
4002 rc = eth_eq_alloc(sc, vi, eq);
4005 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4007 rc = ofld_eq_alloc(sc, vi, eq);
4012 panic("%s: invalid eq type %d.", __func__,
4013 eq->flags & EQ_TYPEMASK);
4016 device_printf(sc->dev,
4017 "failed to allocate egress queue(%d): %d\n",
4018 eq->flags & EQ_TYPEMASK, rc);
4021 if (isset(&eq->doorbells, DOORBELL_UDB) ||
4022 isset(&eq->doorbells, DOORBELL_UDBWC) ||
4023 isset(&eq->doorbells, DOORBELL_WCWR)) {
4024 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4025 uint32_t mask = (1 << s_qpp) - 1;
4026 volatile uint8_t *udb;
4028 udb = sc->udbs_base + UDBS_DB_OFFSET;
4029 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
4030 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
4031 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4032 clrbit(&eq->doorbells, DOORBELL_WCWR);
4034 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
4037 eq->udb = (volatile void *)udb;
4044 free_eq(struct adapter *sc, struct sge_eq *eq)
4048 if (eq->flags & EQ_ALLOCATED) {
4049 switch (eq->flags & EQ_TYPEMASK) {
4051 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
4056 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
4060 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4062 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
4068 panic("%s: invalid eq type %d.", __func__,
4069 eq->flags & EQ_TYPEMASK);
4072 device_printf(sc->dev,
4073 "failed to free egress queue (%d): %d\n",
4074 eq->flags & EQ_TYPEMASK, rc);
4077 eq->flags &= ~EQ_ALLOCATED;
4080 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4082 if (mtx_initialized(&eq->eq_lock))
4083 mtx_destroy(&eq->eq_lock);
4085 bzero(eq, sizeof(*eq));
4090 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4091 struct sysctl_oid *oid)
4094 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
4095 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4097 rc = alloc_eq(sc, vi, &wrq->eq);
4102 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4103 TAILQ_INIT(&wrq->incomplete_wrs);
4104 STAILQ_INIT(&wrq->wr_list);
4105 wrq->nwr_pending = 0;
4106 wrq->ndesc_needed = 0;
4108 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4109 &wrq->eq.ba, "bus address of descriptor ring");
4110 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4111 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
4112 "desc ring size in bytes");
4113 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4114 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
4115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
4116 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
4118 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
4119 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
4121 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4122 wrq->eq.sidx, "status page index");
4123 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4124 &wrq->tx_wrs_direct, "# of work requests (direct)");
4125 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4126 &wrq->tx_wrs_copied, "# of work requests (copied)");
4127 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4128 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4134 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4138 rc = free_eq(sc, &wrq->eq);
4142 bzero(wrq, sizeof(*wrq));
4147 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
4148 struct sysctl_oid *oid)
4151 struct port_info *pi = vi->pi;
4152 struct adapter *sc = pi->adapter;
4153 struct sge_eq *eq = &txq->eq;
4155 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4157 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
4160 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
4164 rc = alloc_eq(sc, vi, eq);
4166 mp_ring_free(txq->r);
4171 /* Can't fail after this point. */
4174 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4176 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4177 ("eq_base mismatch"));
4178 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4179 ("PF with non-zero eq_base"));
4181 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4183 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4184 if (sc->flags & IS_VF)
4185 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4186 V_TXPKT_INTF(pi->tx_chan));
4188 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4189 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4190 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4192 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4195 snprintf(name, sizeof(name), "%d", idx);
4196 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
4198 children = SYSCTL_CHILDREN(oid);
4200 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4201 &eq->ba, "bus address of descriptor ring");
4202 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4203 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4204 "desc ring size in bytes");
4205 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4206 &eq->abs_id, 0, "absolute id of the queue");
4207 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4208 &eq->cntxt_id, 0, "SGE context id of the queue");
4209 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
4210 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
4212 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
4213 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
4215 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4216 eq->sidx, "status page index");
4218 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
4219 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
4220 "traffic class (-1 means none)");
4222 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4223 &txq->txcsum, "# of times hardware assisted with checksum");
4224 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
4225 CTLFLAG_RD, &txq->vlan_insertion,
4226 "# of times hardware inserted 802.1Q tag");
4227 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4228 &txq->tso_wrs, "# of TSO work requests");
4229 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4230 &txq->imm_wrs, "# of work requests with immediate data");
4231 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4232 &txq->sgl_wrs, "# of work requests with direct SGL");
4233 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4234 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4235 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
4236 CTLFLAG_RD, &txq->txpkts0_wrs,
4237 "# of txpkts (type 0) work requests");
4238 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
4239 CTLFLAG_RD, &txq->txpkts1_wrs,
4240 "# of txpkts (type 1) work requests");
4241 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
4242 CTLFLAG_RD, &txq->txpkts0_pkts,
4243 "# of frames tx'd using type0 txpkts work requests");
4244 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
4245 CTLFLAG_RD, &txq->txpkts1_pkts,
4246 "# of frames tx'd using type1 txpkts work requests");
4247 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4248 &txq->raw_wrs, "# of raw work requests (non-packets)");
4249 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tls_wrs", CTLFLAG_RD,
4250 &txq->tls_wrs, "# of TLS work requests (TLS records)");
4253 if (sc->flags & KERN_TLS_OK) {
4254 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4255 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records,
4256 "# of NIC TLS records transmitted");
4257 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4258 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short,
4259 "# of short NIC TLS records transmitted");
4260 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4261 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial,
4262 "# of partial NIC TLS records transmitted");
4263 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4264 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full,
4265 "# of full NIC TLS records transmitted");
4266 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4267 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets,
4268 "# of payload octets in transmitted NIC TLS records");
4269 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4270 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste,
4271 "# of octets DMAd but not transmitted in NIC TLS records");
4272 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4273 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options,
4274 "# of NIC TLS options-only packets transmitted");
4275 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4276 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header,
4277 "# of NIC TLS header-only packets transmitted");
4278 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4279 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin,
4280 "# of NIC TLS FIN-only packets transmitted");
4281 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4282 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short,
4283 "# of NIC TLS padded FIN packets on short TLS records");
4284 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4285 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc,
4286 "# of NIC TLS sessions using AES-CBC");
4287 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4288 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm,
4289 "# of NIC TLS sessions using AES-GCM");
4293 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
4294 CTLFLAG_RD, &txq->r->enqueues,
4295 "# of enqueues to the mp_ring for this queue");
4296 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
4297 CTLFLAG_RD, &txq->r->drops,
4298 "# of drops in the mp_ring for this queue");
4299 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
4300 CTLFLAG_RD, &txq->r->starts,
4301 "# of normal consumer starts in the mp_ring for this queue");
4302 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
4303 CTLFLAG_RD, &txq->r->stalls,
4304 "# of consumer stalls in the mp_ring for this queue");
4305 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
4306 CTLFLAG_RD, &txq->r->restarts,
4307 "# of consumer restarts in the mp_ring for this queue");
4308 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
4309 CTLFLAG_RD, &txq->r->abdications,
4310 "# of consumer abdications in the mp_ring for this queue");
4316 free_txq(struct vi_info *vi, struct sge_txq *txq)
4319 struct adapter *sc = vi->pi->adapter;
4320 struct sge_eq *eq = &txq->eq;
4322 rc = free_eq(sc, eq);
4326 sglist_free(txq->gl);
4327 free(txq->sdesc, M_CXGBE);
4328 mp_ring_free(txq->r);
4330 bzero(txq, sizeof(*txq));
4335 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4337 bus_addr_t *ba = arg;
4340 ("%s meant for single segment mappings only.", __func__));
4342 *ba = error ? 0 : segs->ds_addr;
4346 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4350 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
4354 v = fl->dbval | V_PIDX(n);
4356 *fl->udb = htole32(v);
4358 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4359 IDXINCR(fl->dbidx, n, fl->sidx);
4363 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4364 * recycled do not count towards this allocation budget.
4366 * Returns non-zero to indicate that this freelist should be added to the list
4367 * of starving freelists.
4370 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4373 struct fl_sdesc *sd;
4376 struct cluster_layout *cll;
4377 struct sw_zone_info *swz;
4378 struct cluster_metadata *clm;
4380 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4382 FL_LOCK_ASSERT_OWNED(fl);
4385 * We always stop at the beginning of the hardware descriptor that's just
4386 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4387 * which would mean an empty freelist to the chip.
4389 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4390 if (fl->pidx == max_pidx * 8)
4393 d = &fl->desc[fl->pidx];
4394 sd = &fl->sdesc[fl->pidx];
4395 cll = &fl->cll_def; /* default layout */
4396 swz = &sc->sge.sw_zone_info[cll->zidx];
4400 if (sd->cl != NULL) {
4402 if (sd->nmbuf == 0) {
4404 * Fast recycle without involving any atomics on
4405 * the cluster's metadata (if the cluster has
4406 * metadata). This happens when all frames
4407 * received in the cluster were small enough to
4408 * fit within a single mbuf each.
4410 fl->cl_fast_recycled++;
4412 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4414 MPASS(clm->refcount == 1);
4420 * Cluster is guaranteed to have metadata. Clusters
4421 * without metadata always take the fast recycle path
4422 * when they're recycled.
4424 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4427 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4429 counter_u64_add(extfree_rels, 1);
4432 sd->cl = NULL; /* gave up my reference */
4434 MPASS(sd->cl == NULL);
4436 cl = uma_zalloc(swz->zone, M_NOWAIT);
4437 if (__predict_false(cl == NULL)) {
4438 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
4439 fl->cll_def.zidx == fl->cll_alt.zidx)
4442 /* fall back to the safe zone */
4444 swz = &sc->sge.sw_zone_info[cll->zidx];
4450 pa = pmap_kextract((vm_offset_t)cl);
4454 *d = htobe64(pa | cll->hwidx);
4459 if (__predict_false(++fl->pidx % 8 == 0)) {
4460 uint16_t pidx = fl->pidx / 8;
4462 if (__predict_false(pidx == fl->sidx)) {
4468 if (pidx == max_pidx)
4471 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4476 if (fl->pidx / 8 != fl->dbidx)
4479 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4483 * Attempt to refill all starving freelists.
4486 refill_sfl(void *arg)
4488 struct adapter *sc = arg;
4489 struct sge_fl *fl, *fl_temp;
4491 mtx_assert(&sc->sfl_lock, MA_OWNED);
4492 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4494 refill_fl(sc, fl, 64);
4495 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4496 TAILQ_REMOVE(&sc->sfl, fl, link);
4497 fl->flags &= ~FL_STARVING;
4502 if (!TAILQ_EMPTY(&sc->sfl))
4503 callout_schedule(&sc->sfl_callout, hz / 5);
4507 alloc_fl_sdesc(struct sge_fl *fl)
4510 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4517 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4519 struct fl_sdesc *sd;
4520 struct cluster_metadata *clm;
4521 struct cluster_layout *cll;
4525 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4530 clm = cl_metadata(sc, fl, cll, sd->cl);
4532 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4533 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4534 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4535 counter_u64_add(extfree_rels, 1);
4540 free(fl->sdesc, M_CXGBE);
4545 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4552 rc = sglist_append_mbuf(gl, m);
4553 if (__predict_false(rc != 0)) {
4554 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4555 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4558 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4559 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4560 mbuf_nsegs(m), gl->sg_nseg));
4561 KASSERT(gl->sg_nseg > 0 &&
4562 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4563 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4564 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4568 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4571 txpkt_len16(u_int nsegs, u_int tso)
4577 nsegs--; /* first segment is part of ulptx_sgl */
4578 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4579 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4581 n += sizeof(struct cpl_tx_pkt_lso_core);
4583 return (howmany(n, 16));
4587 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4591 txpkt_vm_len16(u_int nsegs, u_int tso)
4597 nsegs--; /* first segment is part of ulptx_sgl */
4598 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4599 sizeof(struct cpl_tx_pkt_core) +
4600 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4602 n += sizeof(struct cpl_tx_pkt_lso_core);
4604 return (howmany(n, 16));
4608 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4612 txpkts0_len16(u_int nsegs)
4618 nsegs--; /* first segment is part of ulptx_sgl */
4619 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4620 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4621 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4623 return (howmany(n, 16));
4627 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4635 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4637 return (howmany(n, 16));
4641 imm_payload(u_int ndesc)
4645 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4646 sizeof(struct cpl_tx_pkt_core);
4651 static inline uint64_t
4652 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
4659 if (needs_hwcsum(m) == 0)
4660 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
4663 if (needs_l3_csum(m) == 0)
4664 ctrl |= F_TXPKT_IPCSUM_DIS;
4665 switch (m->m_pkthdr.csum_flags &
4666 (CSUM_IP_TCP | CSUM_IP_UDP | CSUM_IP6_TCP | CSUM_IP6_UDP)) {
4668 csum_type = TX_CSUM_TCPIP;
4671 csum_type = TX_CSUM_UDPIP;
4674 csum_type = TX_CSUM_TCPIP6;
4677 csum_type = TX_CSUM_UDPIP6;
4680 /* needs_hwcsum told us that at least some hwcsum is needed. */
4682 MPASS(m->m_pkthdr.csum_flags & CSUM_IP);
4683 ctrl |= F_TXPKT_L4CSUM_DIS;
4684 csum_type = TX_CSUM_IP;
4688 MPASS(m->m_pkthdr.l2hlen > 0);
4689 MPASS(m->m_pkthdr.l3hlen > 0);
4690 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) |
4691 V_TXPKT_IPHDR_LEN(m->m_pkthdr.l3hlen);
4692 if (chip_id(sc) <= CHELSIO_T5)
4693 ctrl |= V_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN);
4695 ctrl |= V_T6_TXPKT_ETHHDR_LEN(m->m_pkthdr.l2hlen - ETHER_HDR_LEN);
4701 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4702 * software descriptor, and advance the pidx. It is guaranteed that enough
4703 * descriptors are available.
4705 * The return value is the # of hardware descriptors used.
4708 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4709 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4711 struct sge_eq *eq = &txq->eq;
4712 struct tx_sdesc *txsd;
4713 struct cpl_tx_pkt_core *cpl;
4714 uint32_t ctrl; /* used in many unrelated places */
4716 int len16, ndesc, pktlen, nsegs;
4719 TXQ_LOCK_ASSERT_OWNED(txq);
4721 MPASS(available > 0 && available < eq->sidx);
4723 len16 = mbuf_len16(m0);
4724 nsegs = mbuf_nsegs(m0);
4725 pktlen = m0->m_pkthdr.len;
4726 ctrl = sizeof(struct cpl_tx_pkt_core);
4728 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4729 ndesc = howmany(len16, EQ_ESIZE / 16);
4730 MPASS(ndesc <= available);
4732 /* Firmware work request header */
4733 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4734 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4735 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4737 ctrl = V_FW_WR_LEN16(len16);
4738 wr->equiq_to_len16 = htobe32(ctrl);
4743 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4744 * vlantci is ignored unless the ethtype is 0x8100, so it's
4745 * simpler to always copy it rather than making it
4746 * conditional. Also, it seems that we do not have to set
4747 * vlantci or fake the ethtype when doing VLAN tag insertion.
4749 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4751 if (needs_tso(m0)) {
4752 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4754 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4755 m0->m_pkthdr.l4hlen > 0,
4756 ("%s: mbuf %p needs TSO but missing header lengths",
4759 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4760 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
4761 ETHER_HDR_LEN) >> 2) |
4762 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
4763 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4764 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4767 lso->lso_ctrl = htobe32(ctrl);
4768 lso->ipid_ofst = htobe16(0);
4769 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4770 lso->seqno_offset = htobe32(0);
4771 lso->len = htobe32(pktlen);
4773 cpl = (void *)(lso + 1);
4777 cpl = (void *)(wr + 1);
4779 /* Checksum offload */
4780 ctrl1 = csum_to_ctrl(sc, m0);
4781 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
4782 txq->txcsum++; /* some hardware assistance provided */
4784 /* VLAN tag insertion */
4785 if (needs_vlan_insertion(m0)) {
4786 ctrl1 |= F_TXPKT_VLAN_VLD |
4787 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4788 txq->vlan_insertion++;
4792 cpl->ctrl0 = txq->cpl_ctrl0;
4794 cpl->len = htobe16(pktlen);
4795 cpl->ctrl1 = htobe64(ctrl1);
4798 dst = (void *)(cpl + 1);
4801 * A packet using TSO will use up an entire descriptor for the
4802 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4803 * If this descriptor is the last descriptor in the ring, wrap
4804 * around to the front of the ring explicitly for the start of
4807 if (dst == (void *)&eq->desc[eq->sidx]) {
4808 dst = (void *)&eq->desc[0];
4809 write_gl_to_txd(txq, m0, &dst, 0);
4811 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4816 txsd = &txq->sdesc[eq->pidx];
4818 txsd->desc_used = ndesc;
4824 * Write a raw WR to the hardware descriptors, update the software
4825 * descriptor, and advance the pidx. It is guaranteed that enough
4826 * descriptors are available.
4828 * The return value is the # of hardware descriptors used.
4831 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
4833 struct sge_eq *eq = &txq->eq;
4834 struct tx_sdesc *txsd;
4839 len16 = mbuf_len16(m0);
4840 ndesc = howmany(len16, EQ_ESIZE / 16);
4841 MPASS(ndesc <= available);
4844 for (m = m0; m != NULL; m = m->m_next)
4845 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4849 txsd = &txq->sdesc[eq->pidx];
4851 txsd->desc_used = ndesc;
4857 * Write a txpkt WR for this packet to the hardware descriptors, update the
4858 * software descriptor, and advance the pidx. It is guaranteed that enough
4859 * descriptors are available.
4861 * The return value is the # of hardware descriptors used.
4864 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq,
4865 struct fw_eth_tx_pkt_wr *wr, struct mbuf *m0, u_int available)
4867 struct sge_eq *eq = &txq->eq;
4868 struct tx_sdesc *txsd;
4869 struct cpl_tx_pkt_core *cpl;
4870 uint32_t ctrl; /* used in many unrelated places */
4872 int len16, ndesc, pktlen, nsegs;
4875 TXQ_LOCK_ASSERT_OWNED(txq);
4877 MPASS(available > 0 && available < eq->sidx);
4879 len16 = mbuf_len16(m0);
4880 nsegs = mbuf_nsegs(m0);
4881 pktlen = m0->m_pkthdr.len;
4882 ctrl = sizeof(struct cpl_tx_pkt_core);
4884 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4885 else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
4887 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4889 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4890 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4893 ndesc = howmany(len16, EQ_ESIZE / 16);
4894 MPASS(ndesc <= available);
4896 /* Firmware work request header */
4897 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4898 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4899 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4901 ctrl = V_FW_WR_LEN16(len16);
4902 wr->equiq_to_len16 = htobe32(ctrl);
4905 if (needs_tso(m0)) {
4906 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4908 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4909 m0->m_pkthdr.l4hlen > 0,
4910 ("%s: mbuf %p needs TSO but missing header lengths",
4913 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4914 F_LSO_LAST_SLICE | V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
4915 ETHER_HDR_LEN) >> 2) |
4916 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
4917 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4918 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4921 lso->lso_ctrl = htobe32(ctrl);
4922 lso->ipid_ofst = htobe16(0);
4923 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4924 lso->seqno_offset = htobe32(0);
4925 lso->len = htobe32(pktlen);
4927 cpl = (void *)(lso + 1);
4931 cpl = (void *)(wr + 1);
4933 /* Checksum offload */
4934 ctrl1 = csum_to_ctrl(sc, m0);
4935 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
4936 txq->txcsum++; /* some hardware assistance provided */
4938 /* VLAN tag insertion */
4939 if (needs_vlan_insertion(m0)) {
4940 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4941 txq->vlan_insertion++;
4945 cpl->ctrl0 = txq->cpl_ctrl0;
4947 cpl->len = htobe16(pktlen);
4948 cpl->ctrl1 = htobe64(ctrl1);
4951 dst = (void *)(cpl + 1);
4954 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4959 for (m = m0; m != NULL; m = m->m_next) {
4960 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4966 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4973 txsd = &txq->sdesc[eq->pidx];
4975 txsd->desc_used = ndesc;
4981 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4983 u_int needed, nsegs1, nsegs2, l1, l2;
4985 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4988 nsegs1 = mbuf_nsegs(m);
4989 nsegs2 = mbuf_nsegs(n);
4990 if (nsegs1 + nsegs2 == 2) {
4992 l1 = l2 = txpkts1_len16();
4995 l1 = txpkts0_len16(nsegs1);
4996 l2 = txpkts0_len16(nsegs2);
4998 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4999 needed = howmany(txp->len16, EQ_ESIZE / 16);
5000 if (needed > SGE_MAX_WR_NDESC || needed > available)
5003 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
5004 if (txp->plen > 65535)
5008 set_mbuf_len16(m, l1);
5009 set_mbuf_len16(n, l2);
5015 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
5017 u_int plen, len16, needed, nsegs;
5019 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5021 if (cannot_use_txpkts(m))
5024 nsegs = mbuf_nsegs(m);
5025 if (txp->wr_type == 1 && nsegs != 1)
5028 plen = txp->plen + m->m_pkthdr.len;
5032 if (txp->wr_type == 0)
5033 len16 = txpkts0_len16(nsegs);
5035 len16 = txpkts1_len16();
5036 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
5037 if (needed > SGE_MAX_WR_NDESC || needed > available)
5042 txp->len16 += len16;
5043 set_mbuf_len16(m, len16);
5049 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5050 * the software descriptor, and advance the pidx. It is guaranteed that enough
5051 * descriptors are available.
5053 * The return value is the # of hardware descriptors used.
5056 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq,
5057 struct fw_eth_tx_pkts_wr *wr, struct mbuf *m0, const struct txpkts *txp,
5060 struct sge_eq *eq = &txq->eq;
5061 struct tx_sdesc *txsd;
5062 struct cpl_tx_pkt_core *cpl;
5065 int ndesc, checkwrap;
5069 TXQ_LOCK_ASSERT_OWNED(txq);
5070 MPASS(txp->npkt > 0);
5071 MPASS(txp->plen < 65536);
5073 MPASS(m0->m_nextpkt != NULL);
5074 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5075 MPASS(available > 0 && available < eq->sidx);
5077 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
5078 MPASS(ndesc <= available);
5080 MPASS(wr == (void *)&eq->desc[eq->pidx]);
5081 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5082 ctrl = V_FW_WR_LEN16(txp->len16);
5083 wr->equiq_to_len16 = htobe32(ctrl);
5084 wr->plen = htobe16(txp->plen);
5085 wr->npkt = txp->npkt;
5087 wr->type = txp->wr_type;
5091 * At this point we are 16B into a hardware descriptor. If checkwrap is
5092 * set then we know the WR is going to wrap around somewhere. We'll
5093 * check for that at appropriate points.
5095 checkwrap = eq->sidx - ndesc < eq->pidx;
5096 for (m = m0; m != NULL; m = m->m_nextpkt) {
5097 if (txp->wr_type == 0) {
5098 struct ulp_txpkt *ulpmc;
5099 struct ulptx_idata *ulpsc;
5101 /* ULP master command */
5103 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5104 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5105 ulpmc->len = htobe32(mbuf_len16(m));
5107 /* ULP subcommand */
5108 ulpsc = (void *)(ulpmc + 1);
5109 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5111 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5113 cpl = (void *)(ulpsc + 1);
5115 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5116 cpl = (void *)&eq->desc[0];
5121 /* Checksum offload */
5122 ctrl1 = csum_to_ctrl(sc, m);
5123 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5124 txq->txcsum++; /* some hardware assistance provided */
5126 /* VLAN tag insertion */
5127 if (needs_vlan_insertion(m)) {
5128 ctrl1 |= F_TXPKT_VLAN_VLD |
5129 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5130 txq->vlan_insertion++;
5134 cpl->ctrl0 = txq->cpl_ctrl0;
5136 cpl->len = htobe16(m->m_pkthdr.len);
5137 cpl->ctrl1 = htobe64(ctrl1);
5141 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5142 flitp = (void *)&eq->desc[0];
5144 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5148 if (txp->wr_type == 0) {
5149 txq->txpkts0_pkts += txp->npkt;
5152 txq->txpkts1_pkts += txp->npkt;
5156 txsd = &txq->sdesc[eq->pidx];
5158 txsd->desc_used = ndesc;
5164 * If the SGL ends on an address that is not 16 byte aligned, this function will
5165 * add a 0 filled flit at the end.
5168 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5170 struct sge_eq *eq = &txq->eq;
5171 struct sglist *gl = txq->gl;
5172 struct sglist_seg *seg;
5173 __be64 *flitp, *wrap;
5174 struct ulptx_sgl *usgl;
5175 int i, nflits, nsegs;
5177 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5178 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5179 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5180 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5183 nsegs = gl->sg_nseg;
5186 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5187 flitp = (__be64 *)(*to);
5188 wrap = (__be64 *)(&eq->desc[eq->sidx]);
5189 seg = &gl->sg_segs[0];
5190 usgl = (void *)flitp;
5193 * We start at a 16 byte boundary somewhere inside the tx descriptor
5194 * ring, so we're at least 16 bytes away from the status page. There is
5195 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5198 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5199 V_ULPTX_NSGE(nsegs));
5200 usgl->len0 = htobe32(seg->ss_len);
5201 usgl->addr0 = htobe64(seg->ss_paddr);
5204 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5206 /* Won't wrap around at all */
5208 for (i = 0; i < nsegs - 1; i++, seg++) {
5209 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5210 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5213 usgl->sge[i / 2].len[1] = htobe32(0);
5217 /* Will wrap somewhere in the rest of the SGL */
5219 /* 2 flits already written, write the rest flit by flit */
5220 flitp = (void *)(usgl + 1);
5221 for (i = 0; i < nflits - 2; i++) {
5223 flitp = (void *)eq->desc;
5224 *flitp++ = get_flit(seg, nsegs - 1, i);
5229 MPASS(((uintptr_t)flitp) & 0xf);
5233 MPASS((((uintptr_t)flitp) & 0xf) == 0);
5234 if (__predict_false(flitp == wrap))
5235 *to = (void *)eq->desc;
5237 *to = (void *)flitp;
5241 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
5244 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5245 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5247 if (__predict_true((uintptr_t)(*to) + len <=
5248 (uintptr_t)&eq->desc[eq->sidx])) {
5249 bcopy(from, *to, len);
5252 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
5254 bcopy(from, *to, portion);
5256 portion = len - portion; /* remaining */
5257 bcopy(from, (void *)eq->desc, portion);
5258 (*to) = (caddr_t)eq->desc + portion;
5263 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
5271 clrbit(&db, DOORBELL_WCWR);
5274 switch (ffs(db) - 1) {
5276 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5279 case DOORBELL_WCWR: {
5280 volatile uint64_t *dst, *src;
5284 * Queues whose 128B doorbell segment fits in the page do not
5285 * use relative qid (udb_qid is always 0). Only queues with
5286 * doorbell segments can do WCWR.
5288 KASSERT(eq->udb_qid == 0 && n == 1,
5289 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
5290 __func__, eq->doorbells, n, eq->dbidx, eq));
5292 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
5295 src = (void *)&eq->desc[i];
5296 while (src != (void *)&eq->desc[i + 1])
5302 case DOORBELL_UDBWC:
5303 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5308 t4_write_reg(sc, sc->sge_kdoorbell_reg,
5309 V_QID(eq->cntxt_id) | V_PIDX(n));
5313 IDXINCR(eq->dbidx, n, eq->sidx);
5317 reclaimable_tx_desc(struct sge_eq *eq)
5321 hw_cidx = read_hw_cidx(eq);
5322 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
5326 total_available_tx_desc(struct sge_eq *eq)
5328 uint16_t hw_cidx, pidx;
5330 hw_cidx = read_hw_cidx(eq);
5333 if (pidx == hw_cidx)
5334 return (eq->sidx - 1);
5336 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
5339 static inline uint16_t
5340 read_hw_cidx(struct sge_eq *eq)
5342 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5343 uint16_t cidx = spg->cidx; /* stable snapshot */
5345 return (be16toh(cidx));
5349 * Reclaim 'n' descriptors approximately.
5352 reclaim_tx_descs(struct sge_txq *txq, u_int n)
5354 struct tx_sdesc *txsd;
5355 struct sge_eq *eq = &txq->eq;
5356 u_int can_reclaim, reclaimed;
5358 TXQ_LOCK_ASSERT_OWNED(txq);
5362 can_reclaim = reclaimable_tx_desc(eq);
5363 while (can_reclaim && reclaimed < n) {
5365 struct mbuf *m, *nextpkt;
5367 txsd = &txq->sdesc[eq->cidx];
5368 ndesc = txsd->desc_used;
5370 /* Firmware doesn't return "partial" credits. */
5371 KASSERT(can_reclaim >= ndesc,
5372 ("%s: unexpected number of credits: %d, %d",
5373 __func__, can_reclaim, ndesc));
5375 ("%s: descriptor with no credits: cidx %d",
5376 __func__, eq->cidx));
5378 for (m = txsd->m; m != NULL; m = nextpkt) {
5379 nextpkt = m->m_nextpkt;
5380 m->m_nextpkt = NULL;
5384 can_reclaim -= ndesc;
5385 IDXINCR(eq->cidx, ndesc, eq->sidx);
5392 tx_reclaim(void *arg, int n)
5394 struct sge_txq *txq = arg;
5395 struct sge_eq *eq = &txq->eq;
5398 if (TXQ_TRYLOCK(txq) == 0)
5400 n = reclaim_tx_descs(txq, 32);
5401 if (eq->cidx == eq->pidx)
5402 eq->equeqidx = eq->pidx;
5408 get_flit(struct sglist_seg *segs, int nsegs, int idx)
5410 int i = (idx / 3) * 2;
5416 rc = (uint64_t)segs[i].ss_len << 32;
5418 rc |= (uint64_t)(segs[i + 1].ss_len);
5420 return (htobe64(rc));
5423 return (htobe64(segs[i].ss_paddr));
5425 return (htobe64(segs[i + 1].ss_paddr));
5432 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
5434 int8_t zidx, hwidx, idx;
5435 uint16_t region1, region3;
5436 int spare, spare_needed, n;
5437 struct sw_zone_info *swz;
5438 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
5441 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
5442 * large enough for the max payload and cluster metadata. Otherwise
5443 * settle for the largest bufsize that leaves enough room in the cluster
5446 * Without buffer packing: Look for the smallest zone which has a
5447 * bufsize large enough for the max payload. Settle for the largest
5448 * bufsize available if there's nothing big enough for max payload.
5450 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
5451 swz = &sc->sge.sw_zone_info[0];
5453 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
5454 if (swz->size > largest_rx_cluster) {
5455 if (__predict_true(hwidx != -1))
5459 * This is a misconfiguration. largest_rx_cluster is
5460 * preventing us from finding a refill source. See
5461 * dev.t5nex.<n>.buffer_sizes to figure out why.
5463 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
5464 " refill source for fl %p (dma %u). Ignored.\n",
5465 largest_rx_cluster, fl, maxp);
5467 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
5468 hwb = &hwb_list[idx];
5469 spare = swz->size - hwb->size;
5470 if (spare < spare_needed)
5473 hwidx = idx; /* best option so far */
5474 if (hwb->size >= maxp) {
5476 if ((fl->flags & FL_BUF_PACKING) == 0)
5477 goto done; /* stop looking (not packing) */
5479 if (swz->size >= safest_rx_cluster)
5480 goto done; /* stop looking (packing) */
5482 break; /* keep looking, next zone */
5486 /* A usable hwidx has been located. */
5488 hwb = &hwb_list[hwidx];
5490 swz = &sc->sge.sw_zone_info[zidx];
5492 region3 = swz->size - hwb->size;
5495 * Stay within this zone and see if there is a better match when mbuf
5496 * inlining is allowed. Remember that the hwidx's are sorted in
5497 * decreasing order of size (so in increasing order of spare area).
5499 for (idx = hwidx; idx != -1; idx = hwb->next) {
5500 hwb = &hwb_list[idx];
5501 spare = swz->size - hwb->size;
5503 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
5507 * Do not inline mbufs if doing so would violate the pad/pack
5508 * boundary alignment requirement.
5510 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
5512 if (fl->flags & FL_BUF_PACKING &&
5513 (MSIZE % sc->params.sge.pack_boundary) != 0)
5516 if (spare < CL_METADATA_SIZE + MSIZE)
5518 n = (spare - CL_METADATA_SIZE) / MSIZE;
5519 if (n > howmany(hwb->size, maxp))
5523 if (fl->flags & FL_BUF_PACKING) {
5524 region1 = n * MSIZE;
5525 region3 = spare - region1;
5528 region3 = spare - region1;
5533 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
5534 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
5535 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
5536 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
5537 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
5538 sc->sge.sw_zone_info[zidx].size,
5539 ("%s: bad buffer layout for fl %p, maxp %d. "
5540 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5541 sc->sge.sw_zone_info[zidx].size, region1,
5542 sc->sge.hw_buf_info[hwidx].size, region3));
5543 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
5544 KASSERT(region3 >= CL_METADATA_SIZE,
5545 ("%s: no room for metadata. fl %p, maxp %d; "
5546 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5547 sc->sge.sw_zone_info[zidx].size, region1,
5548 sc->sge.hw_buf_info[hwidx].size, region3));
5549 KASSERT(region1 % MSIZE == 0,
5550 ("%s: bad mbuf region for fl %p, maxp %d. "
5551 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5552 sc->sge.sw_zone_info[zidx].size, region1,
5553 sc->sge.hw_buf_info[hwidx].size, region3));
5556 fl->cll_def.zidx = zidx;
5557 fl->cll_def.hwidx = hwidx;
5558 fl->cll_def.region1 = region1;
5559 fl->cll_def.region3 = region3;
5563 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
5565 struct sge *s = &sc->sge;
5566 struct hw_buf_info *hwb;
5567 struct sw_zone_info *swz;
5571 if (fl->flags & FL_BUF_PACKING)
5572 hwidx = s->safe_hwidx2; /* with room for metadata */
5573 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
5574 hwidx = s->safe_hwidx2;
5575 hwb = &s->hw_buf_info[hwidx];
5576 swz = &s->sw_zone_info[hwb->zidx];
5577 spare = swz->size - hwb->size;
5579 /* no good if there isn't room for an mbuf as well */
5580 if (spare < CL_METADATA_SIZE + MSIZE)
5581 hwidx = s->safe_hwidx1;
5583 hwidx = s->safe_hwidx1;
5586 /* No fallback source */
5587 fl->cll_alt.hwidx = -1;
5588 fl->cll_alt.zidx = -1;
5593 hwb = &s->hw_buf_info[hwidx];
5594 swz = &s->sw_zone_info[hwb->zidx];
5595 spare = swz->size - hwb->size;
5596 fl->cll_alt.hwidx = hwidx;
5597 fl->cll_alt.zidx = hwb->zidx;
5598 if (allow_mbufs_in_cluster &&
5599 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5600 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5602 fl->cll_alt.region1 = 0;
5603 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5607 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5609 mtx_lock(&sc->sfl_lock);
5611 if ((fl->flags & FL_DOOMED) == 0) {
5612 fl->flags |= FL_STARVING;
5613 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5614 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5617 mtx_unlock(&sc->sfl_lock);
5621 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5623 struct sge_wrq *wrq = (void *)eq;
5625 atomic_readandclear_int(&eq->equiq);
5626 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5630 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5632 struct sge_txq *txq = (void *)eq;
5634 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5636 atomic_readandclear_int(&eq->equiq);
5637 mp_ring_check_drainage(txq->r, 0);
5638 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5642 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5645 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5646 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5647 struct adapter *sc = iq->adapter;
5648 struct sge *s = &sc->sge;
5650 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5651 &handle_wrq_egr_update, &handle_eth_egr_update,
5652 &handle_wrq_egr_update};
5654 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5657 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5658 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5663 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5664 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5665 offsetof(struct cpl_fw6_msg, data));
5668 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5670 struct adapter *sc = iq->adapter;
5671 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5673 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5676 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5677 const struct rss_header *rss2;
5679 rss2 = (const struct rss_header *)&cpl->data[0];
5680 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5683 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5687 * t4_handle_wrerr_rpl - process a FW work request error message
5688 * @adap: the adapter
5689 * @rpl: start of the FW message
5692 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5694 u8 opcode = *(const u8 *)rpl;
5695 const struct fw_error_cmd *e = (const void *)rpl;
5698 if (opcode != FW_ERROR_CMD) {
5700 "%s: Received WRERR_RPL message with opcode %#x\n",
5701 device_get_nameunit(adap->dev), opcode);
5704 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5705 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5707 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5708 case FW_ERROR_TYPE_EXCEPTION:
5709 log(LOG_ERR, "exception info:\n");
5710 for (i = 0; i < nitems(e->u.exception.info); i++)
5711 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5712 be32toh(e->u.exception.info[i]));
5715 case FW_ERROR_TYPE_HWMODULE:
5716 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5717 be32toh(e->u.hwmodule.regaddr),
5718 be32toh(e->u.hwmodule.regval));
5720 case FW_ERROR_TYPE_WR:
5721 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5722 be16toh(e->u.wr.cidx),
5723 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5724 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5725 be32toh(e->u.wr.eqid));
5726 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5727 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5731 case FW_ERROR_TYPE_ACL:
5732 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5733 be16toh(e->u.acl.cidx),
5734 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5735 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5736 be32toh(e->u.acl.eqid),
5737 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5739 for (i = 0; i < nitems(e->u.acl.val); i++)
5740 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5744 log(LOG_ERR, "type %#x\n",
5745 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5752 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5754 uint16_t *id = arg1;
5757 return sysctl_handle_int(oidp, &i, 0, req);
5761 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5763 struct sge *s = arg1;
5764 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5765 struct sw_zone_info *swz = &s->sw_zone_info[0];
5770 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5771 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5772 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5777 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5781 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5788 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5791 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
5797 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
5798 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
5799 if (__predict_false(nsegs == 0))
5802 nsegs--; /* first segment is part of ulptx_sgl */
5803 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5805 n += sizeof(struct cpl_tx_pkt_lso_core);
5808 return (howmany(n, 16));
5811 #define ETID_FLOWC_NPARAMS 6
5812 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
5813 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
5814 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
5817 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
5820 struct wrq_cookie cookie;
5821 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
5822 struct fw_flowc_wr *flowc;
5824 mtx_assert(&cst->lock, MA_OWNED);
5825 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
5828 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie);
5829 if (__predict_false(flowc == NULL))
5832 bzero(flowc, ETID_FLOWC_LEN);
5833 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5834 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
5835 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
5836 V_FW_WR_FLOWID(cst->etid));
5837 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
5838 flowc->mnemval[0].val = htobe32(pfvf);
5839 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
5840 flowc->mnemval[1].val = htobe32(pi->tx_chan);
5841 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
5842 flowc->mnemval[2].val = htobe32(pi->tx_chan);
5843 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
5844 flowc->mnemval[3].val = htobe32(cst->iqid);
5845 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
5846 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
5847 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
5848 flowc->mnemval[5].val = htobe32(cst->schedcl);
5850 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5852 cst->flags &= ~EO_FLOWC_PENDING;
5853 cst->flags |= EO_FLOWC_RPL_PENDING;
5854 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
5855 cst->tx_credits -= ETID_FLOWC_LEN16;
5860 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
5863 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
5865 struct fw_flowc_wr *flowc;
5866 struct wrq_cookie cookie;
5868 mtx_assert(&cst->lock, MA_OWNED);
5870 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie);
5871 if (__predict_false(flowc == NULL))
5872 CXGBE_UNIMPLEMENTED(__func__);
5874 bzero(flowc, ETID_FLUSH_LEN16 * 16);
5875 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5876 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
5877 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
5878 V_FW_WR_FLOWID(cst->etid));
5880 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5882 cst->flags |= EO_FLUSH_RPL_PENDING;
5883 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
5884 cst->tx_credits -= ETID_FLUSH_LEN16;
5889 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
5890 struct mbuf *m0, int compl)
5892 struct cpl_tx_pkt_core *cpl;
5894 uint32_t ctrl; /* used in many unrelated places */
5895 int len16, pktlen, nsegs, immhdrs;
5898 struct ulptx_sgl *usgl;
5900 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
5902 mtx_assert(&cst->lock, MA_OWNED);
5904 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5905 m0->m_pkthdr.l4hlen > 0,
5906 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
5908 len16 = mbuf_eo_len16(m0);
5909 nsegs = mbuf_eo_nsegs(m0);
5910 pktlen = m0->m_pkthdr.len;
5911 ctrl = sizeof(struct cpl_tx_pkt_core);
5913 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5914 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
5917 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
5918 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
5919 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
5920 V_FW_WR_FLOWID(cst->etid));
5922 if (needs_udp_csum(m0)) {
5923 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
5924 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
5925 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5926 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
5927 wr->u.udpseg.rtplen = 0;
5928 wr->u.udpseg.r4 = 0;
5929 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
5930 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
5931 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
5932 cpl = (void *)(wr + 1);
5934 MPASS(needs_tcp_csum(m0));
5935 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
5936 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
5937 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5938 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
5939 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
5940 wr->u.tcpseg.r4 = 0;
5941 wr->u.tcpseg.r5 = 0;
5942 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
5944 if (needs_tso(m0)) {
5945 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
5947 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
5949 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5950 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5951 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
5952 ETHER_HDR_LEN) >> 2) |
5953 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5954 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5955 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5957 lso->lso_ctrl = htobe32(ctrl);
5958 lso->ipid_ofst = htobe16(0);
5959 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5960 lso->seqno_offset = htobe32(0);
5961 lso->len = htobe32(pktlen);
5963 cpl = (void *)(lso + 1);
5965 wr->u.tcpseg.mss = htobe16(0xffff);
5966 cpl = (void *)(wr + 1);
5970 /* Checksum offload must be requested for ethofld. */
5971 MPASS(needs_l4_csum(m0));
5972 ctrl1 = csum_to_ctrl(cst->adapter, m0);
5974 /* VLAN tag insertion */
5975 if (needs_vlan_insertion(m0)) {
5976 ctrl1 |= F_TXPKT_VLAN_VLD |
5977 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5981 cpl->ctrl0 = cst->ctrl0;
5983 cpl->len = htobe16(pktlen);
5984 cpl->ctrl1 = htobe64(ctrl1);
5986 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
5987 p = (uintptr_t)(cpl + 1);
5988 m_copydata(m0, 0, immhdrs, (void *)p);
5991 dst = (void *)(cpl + 1);
5995 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
5997 pad = 16 - (immhdrs & 0xf);
5998 bzero((void *)p, pad);
6000 usgl = (void *)(p + pad);
6001 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6002 V_ULPTX_NSGE(nsegs));
6004 sglist_init(&sg, nitems(segs), segs);
6005 for (; m0 != NULL; m0 = m0->m_next) {
6006 if (__predict_false(m0->m_len == 0))
6008 if (immhdrs >= m0->m_len) {
6009 immhdrs -= m0->m_len;
6013 sglist_append(&sg, mtod(m0, char *) + immhdrs,
6014 m0->m_len - immhdrs);
6017 MPASS(sg.sg_nseg == nsegs);
6020 * Zero pad last 8B in case the WR doesn't end on a 16B
6023 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6025 usgl->len0 = htobe32(segs[0].ss_len);
6026 usgl->addr0 = htobe64(segs[0].ss_paddr);
6027 for (i = 0; i < nsegs - 1; i++) {
6028 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6029 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6032 usgl->sge[i / 2].len[1] = htobe32(0);
6038 ethofld_tx(struct cxgbe_rate_tag *cst)
6041 struct wrq_cookie cookie;
6042 int next_credits, compl;
6043 struct fw_eth_tx_eo_wr *wr;
6045 mtx_assert(&cst->lock, MA_OWNED);
6047 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6050 /* How many len16 credits do we need to send this mbuf. */
6051 next_credits = mbuf_eo_len16(m);
6052 MPASS(next_credits > 0);
6053 if (next_credits > cst->tx_credits) {
6055 * Tx will make progress eventually because there is at
6056 * least one outstanding fw4_ack that will return
6057 * credits and kick the tx.
6059 MPASS(cst->ncompl > 0);
6062 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie);
6063 if (__predict_false(wr == NULL)) {
6064 /* XXX: wishful thinking, not a real assertion. */
6065 MPASS(cst->ncompl > 0);
6068 cst->tx_credits -= next_credits;
6069 cst->tx_nocompl += next_credits;
6070 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6071 ETHER_BPF_MTAP(cst->com.com.ifp, m);
6072 write_ethofld_wr(cst, wr, m, compl);
6073 commit_wrq_wr(cst->eo_txq, wr, &cookie);
6076 cst->tx_nocompl = 0;
6078 (void) mbufq_dequeue(&cst->pending_tx);
6081 * Drop the mbuf's reference on the tag now rather
6082 * than waiting until m_freem(). This ensures that
6083 * cxgbe_rate_tag_free gets called when the inp drops
6084 * its reference on the tag and there are no more
6085 * mbufs in the pending_tx queue and can flush any
6086 * pending requests. Otherwise if the last mbuf
6087 * doesn't request a completion the etid will never be
6090 m->m_pkthdr.snd_tag = NULL;
6091 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6092 m_snd_tag_rele(&cst->com.com);
6094 mbufq_enqueue(&cst->pending_fwack, m);
6099 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
6101 struct cxgbe_rate_tag *cst;
6104 MPASS(m0->m_nextpkt == NULL);
6105 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6106 MPASS(m0->m_pkthdr.snd_tag != NULL);
6107 cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6109 mtx_lock(&cst->lock);
6110 MPASS(cst->flags & EO_SND_TAG_REF);
6112 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6113 struct vi_info *vi = ifp->if_softc;
6114 struct port_info *pi = vi->pi;
6115 struct adapter *sc = pi->adapter;
6116 const uint32_t rss_mask = vi->rss_size - 1;
6119 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6120 if (M_HASHTYPE_ISHASH(m0))
6121 rss_hash = m0->m_pkthdr.flowid;
6123 rss_hash = arc4random();
6124 /* We assume RSS hashing */
6125 cst->iqid = vi->rss[rss_hash & rss_mask];
6126 cst->eo_txq += rss_hash % vi->nofldtxq;
6127 rc = send_etid_flowc_wr(cst, pi, vi);
6132 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6137 mbufq_enqueue(&cst->pending_tx, m0);
6138 cst->plen += m0->m_pkthdr.len;
6141 * Hold an extra reference on the tag while generating work
6142 * requests to ensure that we don't try to free the tag during
6143 * ethofld_tx() in case we are sending the final mbuf after
6144 * the inp was freed.
6146 m_snd_tag_ref(&cst->com.com);
6148 mtx_unlock(&cst->lock);
6149 m_snd_tag_rele(&cst->com.com);
6153 mtx_unlock(&cst->lock);
6154 if (__predict_false(rc != 0))
6160 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6162 struct adapter *sc = iq->adapter;
6163 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6165 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6166 struct cxgbe_rate_tag *cst;
6167 uint8_t credits = cpl->credits;
6169 cst = lookup_etid(sc, etid);
6170 mtx_lock(&cst->lock);
6171 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6172 MPASS(credits >= ETID_FLOWC_LEN16);
6173 credits -= ETID_FLOWC_LEN16;
6174 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6177 KASSERT(cst->ncompl > 0,
6178 ("%s: etid %u (%p) wasn't expecting completion.",
6179 __func__, etid, cst));
6182 while (credits > 0) {
6183 m = mbufq_dequeue(&cst->pending_fwack);
6184 if (__predict_false(m == NULL)) {
6186 * The remaining credits are for the final flush that
6187 * was issued when the tag was freed by the kernel.
6190 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6191 EO_FLUSH_RPL_PENDING);
6192 MPASS(credits == ETID_FLUSH_LEN16);
6193 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6194 MPASS(cst->ncompl == 0);
6196 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6197 cst->tx_credits += cpl->credits;
6198 cxgbe_rate_tag_free_locked(cst);
6199 return (0); /* cst is gone. */
6202 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6204 KASSERT(credits >= mbuf_eo_len16(m),
6205 ("%s: too few credits (%u, %u, %u)", __func__,
6206 cpl->credits, credits, mbuf_eo_len16(m)));
6207 credits -= mbuf_eo_len16(m);
6208 cst->plen -= m->m_pkthdr.len;
6212 cst->tx_credits += cpl->credits;
6213 MPASS(cst->tx_credits <= cst->tx_total);
6215 if (cst->flags & EO_SND_TAG_REF) {
6217 * As with ethofld_transmit(), hold an extra reference
6218 * so that the tag is stable across ethold_tx().
6220 m_snd_tag_ref(&cst->com.com);
6221 m = mbufq_first(&cst->pending_tx);
6222 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6224 mtx_unlock(&cst->lock);
6225 m_snd_tag_rele(&cst->com.com);
6228 * There shouldn't be any pending packets if the tag
6229 * was freed by the kernel since any pending packet
6230 * should hold a reference to the tag.
6232 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6233 mtx_unlock(&cst->lock);