2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_ratelimit.h"
37 #include <sys/types.h>
38 #include <sys/eventhandler.h>
40 #include <sys/socket.h>
41 #include <sys/kernel.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
47 #include <sys/sglist.h>
48 #include <sys/sysctl.h>
50 #include <sys/counter.h>
52 #include <net/ethernet.h>
54 #include <net/if_vlan_var.h>
55 #include <netinet/in.h>
56 #include <netinet/ip.h>
57 #include <netinet/ip6.h>
58 #include <netinet/tcp.h>
59 #include <netinet/udp.h>
60 #include <machine/in_cksum.h>
61 #include <machine/md_var.h>
65 #include <machine/bus.h>
66 #include <sys/selinfo.h>
67 #include <net/if_var.h>
68 #include <net/netmap.h>
69 #include <dev/netmap/netmap_kern.h>
72 #include "common/common.h"
73 #include "common/t4_regs.h"
74 #include "common/t4_regs_values.h"
75 #include "common/t4_msg.h"
77 #include "t4_mp_ring.h"
79 #ifdef T4_PKT_TIMESTAMP
80 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
82 #define RX_COPY_THRESHOLD MINCLSIZE
85 /* Internal mbuf flags stored in PH_loc.eight[1]. */
87 #define MC_RAW_WR 0x02
90 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
91 * 0-7 are valid values.
93 static int fl_pktshift = 0;
94 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
95 "payload DMA offset in rx buffer (bytes)");
98 * Pad ethernet payload up to this boundary.
99 * -1: driver should figure out a good value.
100 * 0: disable padding.
101 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
104 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
105 "payload pad boundary (bytes)");
108 * Status page length.
109 * -1: driver should figure out a good value.
110 * 64 or 128 are the only other valid values.
112 static int spg_len = -1;
113 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
114 "status page size (bytes)");
118 * -1: no congestion feedback (not recommended).
119 * 0: backpressure the channel instead of dropping packets right away.
120 * 1: no backpressure, drop packets for the congested queue immediately.
122 static int cong_drop = 0;
123 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
124 "Congestion control for RX queues (0 = backpressure, 1 = drop");
127 * Deliver multiple frames in the same free list buffer if they fit.
128 * -1: let the driver decide whether to enable buffer packing or not.
129 * 0: disable buffer packing.
130 * 1: enable buffer packing.
132 static int buffer_packing = -1;
133 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
134 0, "Enable buffer packing");
137 * Start next frame in a packed buffer at this boundary.
138 * -1: driver should figure out a good value.
139 * T4: driver will ignore this and use the same value as fl_pad above.
140 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
142 static int fl_pack = -1;
143 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
144 "payload pack boundary (bytes)");
147 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
148 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
149 * 1: ok to create mbuf(s) within a cluster if there is room.
151 static int allow_mbufs_in_cluster = 1;
152 SYSCTL_INT(_hw_cxgbe, OID_AUTO, allow_mbufs_in_cluster, CTLFLAG_RDTUN,
153 &allow_mbufs_in_cluster, 0,
154 "Allow driver to create mbufs within a rx cluster");
157 * Largest rx cluster size that the driver is allowed to allocate.
159 static int largest_rx_cluster = MJUM16BYTES;
160 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
161 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
164 * Size of cluster allocation that's most likely to succeed. The driver will
165 * fall back to this size if it fails to allocate clusters larger than this.
167 static int safest_rx_cluster = PAGE_SIZE;
168 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
169 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
173 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
174 * for rewriting. -1 and 0-3 are all valid values.
175 * -1: hardware should leave the TCP timestamps alone.
181 static int tsclk = -1;
182 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
183 "Control TCP timestamp rewriting when using pacing");
185 static int eo_max_backlog = 1024 * 1024;
186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
187 0, "Maximum backlog of ratelimited data per flow");
191 * The interrupt holdoff timers are multiplied by this value on T6+.
192 * 1 and 3-17 (both inclusive) are legal values.
194 static int tscale = 1;
195 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
196 "Interrupt holdoff timer scale on T6+");
199 * Number of LRO entries in the lro_ctrl structure per rx queue.
201 static int lro_entries = TCP_LRO_ENTRIES;
202 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
203 "Number of LRO entries per RX queue");
206 * This enables presorting of frames before they're fed into tcp_lro_rx.
208 static int lro_mbufs = 0;
209 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
210 "Enable presorting of LRO frames");
213 u_int wr_type; /* type 0 or type 1 */
214 u_int npkt; /* # of packets in this work request */
215 u_int plen; /* total payload (sum of all packets) */
216 u_int len16; /* # of 16B pieces used by this work request */
219 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
222 struct sglist_seg seg[TX_SGL_SEGS];
225 static int service_iq(struct sge_iq *, int);
226 static int service_iq_fl(struct sge_iq *, int);
227 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
228 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
229 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
230 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
231 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
233 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
234 bus_addr_t *, void **);
235 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
237 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
239 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
240 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
242 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
243 struct sysctl_oid *, struct sge_fl *);
244 static int alloc_fwq(struct adapter *);
245 static int free_fwq(struct adapter *);
246 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int,
247 struct sysctl_oid *);
248 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
249 struct sysctl_oid *);
250 static int free_rxq(struct vi_info *, struct sge_rxq *);
252 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
253 struct sysctl_oid *);
254 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
257 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
258 struct sysctl_oid *);
259 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
260 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
261 struct sysctl_oid *);
262 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
264 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
265 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
266 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
267 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
269 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
270 static int free_eq(struct adapter *, struct sge_eq *);
271 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
272 struct sysctl_oid *);
273 static int free_wrq(struct adapter *, struct sge_wrq *);
274 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
275 struct sysctl_oid *);
276 static int free_txq(struct vi_info *, struct sge_txq *);
277 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
278 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
279 static int refill_fl(struct adapter *, struct sge_fl *, int);
280 static void refill_sfl(void *);
281 static int alloc_fl_sdesc(struct sge_fl *);
282 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
283 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
284 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
285 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
287 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
288 static inline u_int txpkt_len16(u_int, u_int);
289 static inline u_int txpkt_vm_len16(u_int, u_int);
290 static inline u_int txpkts0_len16(u_int);
291 static inline u_int txpkts1_len16(void);
292 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
293 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
294 struct mbuf *, u_int);
295 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
296 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
297 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
298 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
299 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
300 struct mbuf *, const struct txpkts *, u_int);
301 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
302 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
303 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
304 static inline uint16_t read_hw_cidx(struct sge_eq *);
305 static inline u_int reclaimable_tx_desc(struct sge_eq *);
306 static inline u_int total_available_tx_desc(struct sge_eq *);
307 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
308 static void tx_reclaim(void *, int);
309 static __be64 get_flit(struct sglist_seg *, int, int);
310 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
312 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
314 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
315 static void wrq_tx_drain(void *, int);
316 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
318 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
319 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
321 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
322 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
326 static counter_u64_t extfree_refs;
327 static counter_u64_t extfree_rels;
329 an_handler_t t4_an_handler;
330 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
331 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
332 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
333 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
334 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
335 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
336 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
339 t4_register_an_handler(an_handler_t h)
343 MPASS(h == NULL || t4_an_handler == NULL);
345 loc = (uintptr_t *)&t4_an_handler;
346 atomic_store_rel_ptr(loc, (uintptr_t)h);
350 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
354 MPASS(type < nitems(t4_fw_msg_handler));
355 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
357 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
358 * handler dispatch table. Reject any attempt to install a handler for
361 MPASS(type != FW_TYPE_RSSCPL);
362 MPASS(type != FW6_TYPE_RSSCPL);
364 loc = (uintptr_t *)&t4_fw_msg_handler[type];
365 atomic_store_rel_ptr(loc, (uintptr_t)h);
369 t4_register_cpl_handler(int opcode, cpl_handler_t h)
373 MPASS(opcode < nitems(t4_cpl_handler));
374 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
376 loc = (uintptr_t *)&t4_cpl_handler[opcode];
377 atomic_store_rel_ptr(loc, (uintptr_t)h);
381 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
384 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
391 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
393 * The return code for filter-write is put in the CPL cookie so
394 * we have to rely on the hardware tid (is_ftid) to determine
395 * that this is a response to a filter.
397 cookie = CPL_COOKIE_FILTER;
399 cookie = G_COOKIE(cpl->cookie);
401 MPASS(cookie > CPL_COOKIE_RESERVED);
402 MPASS(cookie < nitems(set_tcb_rpl_handlers));
404 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
408 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
411 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
416 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
417 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
421 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
424 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
425 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
428 MPASS(cookie != CPL_COOKIE_RESERVED);
430 return (act_open_rpl_handlers[cookie](iq, rss, m));
434 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
437 struct adapter *sc = iq->adapter;
441 if (is_hashfilter(sc))
442 cookie = CPL_COOKIE_HASHFILTER;
444 cookie = CPL_COOKIE_TOM;
446 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
450 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
452 struct adapter *sc = iq->adapter;
453 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
454 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
458 if (is_etid(sc, tid))
459 cookie = CPL_COOKIE_ETHOFLD;
461 cookie = CPL_COOKIE_TOM;
463 return (fw4_ack_handlers[cookie](iq, rss, m));
467 t4_init_shared_cpl_handlers(void)
470 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
471 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
472 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
473 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
474 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
478 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
482 MPASS(opcode < nitems(t4_cpl_handler));
483 MPASS(cookie > CPL_COOKIE_RESERVED);
484 MPASS(cookie < NUM_CPL_COOKIES);
485 MPASS(t4_cpl_handler[opcode] != NULL);
488 case CPL_SET_TCB_RPL:
489 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
491 case CPL_L2T_WRITE_RPL:
492 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
494 case CPL_ACT_OPEN_RPL:
495 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
497 case CPL_ABORT_RPL_RSS:
498 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
501 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
507 MPASS(h == NULL || *loc == (uintptr_t)NULL);
508 atomic_store_rel_ptr(loc, (uintptr_t)h);
512 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
518 if (fl_pktshift < 0 || fl_pktshift > 7) {
519 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
520 " using 0 instead.\n", fl_pktshift);
524 if (spg_len != 64 && spg_len != 128) {
527 #if defined(__i386__) || defined(__amd64__)
528 len = cpu_clflush_line_size > 64 ? 128 : 64;
533 printf("Invalid hw.cxgbe.spg_len value (%d),"
534 " using %d instead.\n", spg_len, len);
539 if (cong_drop < -1 || cong_drop > 1) {
540 printf("Invalid hw.cxgbe.cong_drop value (%d),"
541 " using 0 instead.\n", cong_drop);
545 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
546 printf("Invalid hw.cxgbe.tscale value (%d),"
547 " using 1 instead.\n", tscale);
551 extfree_refs = counter_u64_alloc(M_WAITOK);
552 extfree_rels = counter_u64_alloc(M_WAITOK);
553 counter_u64_zero(extfree_refs);
554 counter_u64_zero(extfree_rels);
556 t4_init_shared_cpl_handlers();
557 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
558 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
559 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
560 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
562 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
565 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
566 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
570 t4_sge_modunload(void)
573 counter_u64_free(extfree_refs);
574 counter_u64_free(extfree_rels);
578 t4_sge_extfree_refs(void)
582 rels = counter_u64_fetch(extfree_rels);
583 refs = counter_u64_fetch(extfree_refs);
585 return (refs - rels);
589 setup_pad_and_pack_boundaries(struct adapter *sc)
592 int pad, pack, pad_shift;
594 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
595 X_INGPADBOUNDARY_SHIFT;
597 if (fl_pad < (1 << pad_shift) ||
598 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
601 * If there is any chance that we might use buffer packing and
602 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
603 * it to the minimum allowed in all other cases.
605 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
608 * For fl_pad = 0 we'll still write a reasonable value to the
609 * register but all the freelists will opt out of padding.
610 * We'll complain here only if the user tried to set it to a
611 * value greater than 0 that was invalid.
614 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
615 " (%d), using %d instead.\n", fl_pad, pad);
618 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
619 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
620 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
623 if (fl_pack != -1 && fl_pack != pad) {
624 /* Complain but carry on. */
625 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
626 " using %d instead.\n", fl_pack, pad);
632 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
633 !powerof2(fl_pack)) {
634 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
635 MPASS(powerof2(pack));
643 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
644 " (%d), using %d instead.\n", fl_pack, pack);
647 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
649 v = V_INGPACKBOUNDARY(0);
651 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
653 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
654 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
658 * adap->params.vpd.cclk must be set up before this is called.
661 t4_tweak_chip_settings(struct adapter *sc)
665 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
666 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
667 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
668 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
669 static int sge_flbuf_sizes[] = {
671 #if MJUMPAGESIZE != MCLBYTES
673 MJUMPAGESIZE - CL_METADATA_SIZE,
674 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
678 MCLBYTES - MSIZE - CL_METADATA_SIZE,
679 MJUM9BYTES - CL_METADATA_SIZE,
680 MJUM16BYTES - CL_METADATA_SIZE,
683 KASSERT(sc->flags & MASTER_PF,
684 ("%s: trying to change chip settings when not master.", __func__));
686 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
687 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
688 V_EGRSTATUSPAGESIZE(spg_len == 128);
689 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
691 setup_pad_and_pack_boundaries(sc);
693 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
694 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
695 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
696 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
697 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
698 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
699 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
700 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
701 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
703 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
704 ("%s: hw buffer size table too big", __func__));
705 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
706 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
707 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
708 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE15 - (4 * i),
712 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
713 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
714 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
716 KASSERT(intr_timer[0] <= timer_max,
717 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
719 for (i = 1; i < nitems(intr_timer); i++) {
720 KASSERT(intr_timer[i] >= intr_timer[i - 1],
721 ("%s: timers not listed in increasing order (%d)",
724 while (intr_timer[i] > timer_max) {
725 if (i == nitems(intr_timer) - 1) {
726 intr_timer[i] = timer_max;
729 intr_timer[i] += intr_timer[i - 1];
734 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
735 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
736 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
737 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
738 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
739 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
740 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
741 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
742 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
744 if (chip_id(sc) >= CHELSIO_T6) {
745 m = V_TSCALE(M_TSCALE);
749 v = V_TSCALE(tscale - 2);
750 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
752 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
753 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
754 V_WRTHRTHRESH(M_WRTHRTHRESH);
755 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
757 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
759 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
763 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
764 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
765 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
768 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
769 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
770 * may have to deal with is MAXPHYS + 1 page.
772 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
773 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
775 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
776 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
777 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
779 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
781 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
782 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
786 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
787 * padding is in use, the buffer's start and end need to be aligned to the pad
788 * boundary as well. We'll just make sure that the size is a multiple of the
789 * boundary here, it is up to the buffer allocation code to make sure the start
790 * of the buffer is aligned as well.
793 hwsz_ok(struct adapter *sc, int hwsz)
795 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
797 return (hwsz >= 64 && (hwsz & mask) == 0);
801 * XXX: driver really should be able to deal with unexpected settings.
804 t4_read_chip_settings(struct adapter *sc)
806 struct sge *s = &sc->sge;
807 struct sge_params *sp = &sc->params.sge;
810 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
811 static int sw_buf_sizes[] = { /* Sorted by size */
813 #if MJUMPAGESIZE != MCLBYTES
819 struct sw_zone_info *swz, *safe_swz;
820 struct hw_buf_info *hwb;
824 r = sc->params.sge.sge_control;
826 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
831 * If this changes then every single use of PAGE_SHIFT in the driver
832 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
834 if (sp->page_shift != PAGE_SHIFT) {
835 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
839 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
840 hwb = &s->hw_buf_info[0];
841 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
842 r = sc->params.sge.sge_fl_buffer_size[i];
844 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
849 * Create a sorted list in decreasing order of hw buffer sizes (and so
850 * increasing order of spare area) for each software zone.
852 * If padding is enabled then the start and end of the buffer must align
853 * to the pad boundary; if packing is enabled then they must align with
854 * the pack boundary as well. Allocations from the cluster zones are
855 * aligned to min(size, 4K), so the buffer starts at that alignment and
856 * ends at hwb->size alignment. If mbuf inlining is allowed the
857 * starting alignment will be reduced to MSIZE and the driver will
858 * exercise appropriate caution when deciding on the best buffer layout
861 n = 0; /* no usable buffer size to begin with */
862 swz = &s->sw_zone_info[0];
864 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
865 int8_t head = -1, tail = -1;
867 swz->size = sw_buf_sizes[i];
868 swz->zone = m_getzone(swz->size);
869 swz->type = m_gettype(swz->size);
871 if (swz->size < PAGE_SIZE) {
872 MPASS(powerof2(swz->size));
873 if (fl_pad && (swz->size % sp->pad_boundary != 0))
877 if (swz->size == safest_rx_cluster)
880 hwb = &s->hw_buf_info[0];
881 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
882 if (hwb->zidx != -1 || hwb->size > swz->size)
886 MPASS(hwb->size % sp->pad_boundary == 0);
891 else if (hwb->size < s->hw_buf_info[tail].size) {
892 s->hw_buf_info[tail].next = j;
896 struct hw_buf_info *t;
898 for (cur = &head; *cur != -1; cur = &t->next) {
899 t = &s->hw_buf_info[*cur];
900 if (hwb->size == t->size) {
904 if (hwb->size > t->size) {
912 swz->head_hwidx = head;
913 swz->tail_hwidx = tail;
917 if (swz->size - s->hw_buf_info[tail].size >=
919 sc->flags |= BUF_PACKING_OK;
923 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
929 if (safe_swz != NULL) {
930 s->safe_hwidx1 = safe_swz->head_hwidx;
931 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
934 hwb = &s->hw_buf_info[i];
937 MPASS(hwb->size % sp->pad_boundary == 0);
939 spare = safe_swz->size - hwb->size;
940 if (spare >= CL_METADATA_SIZE) {
947 if (sc->flags & IS_VF)
950 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
951 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
953 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
957 m = v = F_TDDPTAGTCB;
958 r = t4_read_reg(sc, A_ULP_RX_CTL);
960 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
964 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
966 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
967 r = t4_read_reg(sc, A_TP_PARA_REG5);
969 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
973 t4_init_tp_params(sc, 1);
975 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
976 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
982 t4_create_dma_tag(struct adapter *sc)
986 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
988 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
991 device_printf(sc->dev,
992 "failed to create main DMA tag: %d\n", rc);
999 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
1000 struct sysctl_oid_list *children)
1002 struct sge_params *sp = &sc->params.sge;
1004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
1005 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
1006 "freelist buffer sizes");
1008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
1009 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1011 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1012 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1015 NULL, sp->spg_len, "status page size (bytes)");
1017 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1018 NULL, cong_drop, "congestion drop setting");
1020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1021 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1025 t4_destroy_dma_tag(struct adapter *sc)
1028 bus_dma_tag_destroy(sc->dmat);
1034 * Allocate and initialize the firmware event queue, control queues, and special
1035 * purpose rx queues owned by the adapter.
1037 * Returns errno on failure. Resources allocated up to that point may still be
1038 * allocated. Caller is responsible for cleanup in case this function fails.
1041 t4_setup_adapter_queues(struct adapter *sc)
1043 struct sysctl_oid *oid;
1044 struct sysctl_oid_list *children;
1047 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1049 sysctl_ctx_init(&sc->ctx);
1050 sc->flags |= ADAP_SYSCTL_CTX;
1053 * Firmware event queue
1060 * That's all for the VF driver.
1062 if (sc->flags & IS_VF)
1065 oid = device_get_sysctl_tree(sc->dev);
1066 children = SYSCTL_CHILDREN(oid);
1069 * XXX: General purpose rx queues, one per port.
1073 * Control queues, one per port.
1075 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq",
1076 CTLFLAG_RD, NULL, "control queues");
1077 for_each_port(sc, i) {
1078 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i];
1080 rc = alloc_ctrlq(sc, ctrlq, i, oid);
1092 t4_teardown_adapter_queues(struct adapter *sc)
1096 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1098 /* Do this before freeing the queue */
1099 if (sc->flags & ADAP_SYSCTL_CTX) {
1100 sysctl_ctx_free(&sc->ctx);
1101 sc->flags &= ~ADAP_SYSCTL_CTX;
1104 if (!(sc->flags & IS_VF)) {
1105 for_each_port(sc, i)
1106 free_wrq(sc, &sc->sge.ctrlq[i]);
1113 /* Maximum payload that can be delivered with a single iq descriptor */
1115 mtu_to_max_payload(struct adapter *sc, int mtu)
1118 /* large enough even when hw VLAN extraction is disabled */
1119 return (sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1120 ETHER_VLAN_ENCAP_LEN + mtu);
1124 t4_setup_vi_queues(struct vi_info *vi)
1126 int rc = 0, i, intr_idx, iqidx;
1127 struct sge_rxq *rxq;
1128 struct sge_txq *txq;
1130 struct sge_ofld_rxq *ofld_rxq;
1132 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1133 struct sge_wrq *ofld_txq;
1137 struct sge_nm_rxq *nm_rxq;
1138 struct sge_nm_txq *nm_txq;
1141 struct port_info *pi = vi->pi;
1142 struct adapter *sc = pi->adapter;
1143 struct ifnet *ifp = vi->ifp;
1144 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1145 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1146 int maxp, mtu = ifp->if_mtu;
1148 /* Interrupt vector to start from (when using multiple vectors) */
1149 intr_idx = vi->first_intr;
1152 saved_idx = intr_idx;
1153 if (ifp->if_capabilities & IFCAP_NETMAP) {
1155 /* netmap is supported with direct interrupts only. */
1156 MPASS(!forwarding_intr_to_fwq(sc));
1159 * We don't have buffers to back the netmap rx queues
1160 * right now so we create the queues in a way that
1161 * doesn't set off any congestion signal in the chip.
1163 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1164 CTLFLAG_RD, NULL, "rx queues");
1165 for_each_nm_rxq(vi, i, nm_rxq) {
1166 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1172 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1173 CTLFLAG_RD, NULL, "tx queues");
1174 for_each_nm_txq(vi, i, nm_txq) {
1175 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1176 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1182 /* Normal rx queues and netmap rx queues share the same interrupts. */
1183 intr_idx = saved_idx;
1187 * Allocate rx queues first because a default iqid is required when
1188 * creating a tx queue.
1190 maxp = mtu_to_max_payload(sc, mtu);
1191 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1192 CTLFLAG_RD, NULL, "rx queues");
1193 for_each_rxq(vi, i, rxq) {
1195 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1197 snprintf(name, sizeof(name), "%s rxq%d-fl",
1198 device_get_nameunit(vi->dev), i);
1199 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1201 rc = alloc_rxq(vi, rxq,
1202 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1208 if (ifp->if_capabilities & IFCAP_NETMAP)
1209 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1212 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1213 CTLFLAG_RD, NULL, "rx queues for offloaded TCP connections");
1214 for_each_ofld_rxq(vi, i, ofld_rxq) {
1216 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1219 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1220 device_get_nameunit(vi->dev), i);
1221 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1223 rc = alloc_ofld_rxq(vi, ofld_rxq,
1224 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1232 * Now the tx queues.
1234 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1236 for_each_txq(vi, i, txq) {
1237 iqidx = vi->first_rxq + (i % vi->nrxq);
1238 snprintf(name, sizeof(name), "%s txq%d",
1239 device_get_nameunit(vi->dev), i);
1240 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1241 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1243 rc = alloc_txq(vi, txq, i, oid);
1247 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1248 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1249 CTLFLAG_RD, NULL, "tx queues for TOE/ETHOFLD");
1250 for_each_ofld_txq(vi, i, ofld_txq) {
1251 struct sysctl_oid *oid2;
1253 snprintf(name, sizeof(name), "%s ofld_txq%d",
1254 device_get_nameunit(vi->dev), i);
1255 if (vi->nofldrxq > 0) {
1256 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1257 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1258 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id,
1261 iqidx = vi->first_rxq + (i % vi->nrxq);
1262 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1263 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name);
1266 snprintf(name, sizeof(name), "%d", i);
1267 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1268 name, CTLFLAG_RD, NULL, "offload tx queue");
1270 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1277 t4_teardown_vi_queues(vi);
1286 t4_teardown_vi_queues(struct vi_info *vi)
1289 struct sge_rxq *rxq;
1290 struct sge_txq *txq;
1291 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1292 struct port_info *pi = vi->pi;
1293 struct adapter *sc = pi->adapter;
1294 struct sge_wrq *ofld_txq;
1297 struct sge_ofld_rxq *ofld_rxq;
1300 struct sge_nm_rxq *nm_rxq;
1301 struct sge_nm_txq *nm_txq;
1304 /* Do this before freeing the queues */
1305 if (vi->flags & VI_SYSCTL_CTX) {
1306 sysctl_ctx_free(&vi->ctx);
1307 vi->flags &= ~VI_SYSCTL_CTX;
1311 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1312 for_each_nm_txq(vi, i, nm_txq) {
1313 free_nm_txq(vi, nm_txq);
1316 for_each_nm_rxq(vi, i, nm_rxq) {
1317 free_nm_rxq(vi, nm_rxq);
1323 * Take down all the tx queues first, as they reference the rx queues
1324 * (for egress updates, etc.).
1327 for_each_txq(vi, i, txq) {
1330 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1331 for_each_ofld_txq(vi, i, ofld_txq) {
1332 free_wrq(sc, ofld_txq);
1337 * Then take down the rx queues.
1340 for_each_rxq(vi, i, rxq) {
1344 for_each_ofld_rxq(vi, i, ofld_rxq) {
1345 free_ofld_rxq(vi, ofld_rxq);
1353 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1356 * a) Deals with errors, if any.
1357 * b) Services firmware event queue, which is taking interrupts for all other
1361 t4_intr_all(void *arg)
1363 struct adapter *sc = arg;
1364 struct sge_iq *fwq = &sc->sge.fwq;
1366 MPASS(sc->intr_count == 1);
1368 if (sc->intr_type == INTR_INTX)
1369 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1376 * Interrupt handler for errors (installed directly when multiple interrupts are
1377 * being used, or called by t4_intr_all).
1380 t4_intr_err(void *arg)
1382 struct adapter *sc = arg;
1384 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1386 if (sc->flags & ADAP_ERR)
1389 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1392 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1395 t4_slow_intr_handler(sc, verbose);
1399 * Interrupt handler for iq-only queues. The firmware event queue is the only
1400 * such queue right now.
1403 t4_intr_evt(void *arg)
1405 struct sge_iq *iq = arg;
1407 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1409 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1414 * Interrupt handler for iq+fl queues.
1419 struct sge_iq *iq = arg;
1421 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1422 service_iq_fl(iq, 0);
1423 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1429 * Interrupt handler for netmap rx queues.
1432 t4_nm_intr(void *arg)
1434 struct sge_nm_rxq *nm_rxq = arg;
1436 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1437 service_nm_rxq(nm_rxq);
1438 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1443 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1446 t4_vi_intr(void *arg)
1448 struct irq *irq = arg;
1450 MPASS(irq->nm_rxq != NULL);
1451 t4_nm_intr(irq->nm_rxq);
1453 MPASS(irq->rxq != NULL);
1459 * Deals with interrupts on an iq-only (no freelist) queue.
1462 service_iq(struct sge_iq *iq, int budget)
1465 struct adapter *sc = iq->adapter;
1466 struct iq_desc *d = &iq->desc[iq->cidx];
1467 int ndescs = 0, limit;
1470 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1472 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1473 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1474 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1476 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1477 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1479 limit = budget ? budget : iq->qsize / 16;
1482 * We always come back and check the descriptor ring for new indirect
1483 * interrupts and other responses after running a single handler.
1486 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1490 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1491 lq = be32toh(d->rsp.pldbuflen_qid);
1494 case X_RSPD_TYPE_FLBUF:
1495 panic("%s: data for an iq (%p) with no freelist",
1500 case X_RSPD_TYPE_CPL:
1501 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1502 ("%s: bad opcode %02x.", __func__,
1504 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1507 case X_RSPD_TYPE_INTR:
1509 * There are 1K interrupt-capable queues (qids 0
1510 * through 1023). A response type indicating a
1511 * forwarded interrupt with a qid >= 1K is an
1512 * iWARP async notification.
1514 if (__predict_true(lq >= 1024)) {
1515 t4_an_handler(iq, &d->rsp);
1519 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1521 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1523 if (service_iq_fl(q, q->qsize / 16) == 0) {
1524 (void) atomic_cmpset_int(&q->state,
1525 IQS_BUSY, IQS_IDLE);
1527 STAILQ_INSERT_TAIL(&iql, q,
1535 ("%s: illegal response type %d on iq %p",
1536 __func__, rsp_type, iq));
1538 "%s: illegal response type %d on iq %p",
1539 device_get_nameunit(sc->dev), rsp_type, iq);
1544 if (__predict_false(++iq->cidx == iq->sidx)) {
1546 iq->gen ^= F_RSPD_GEN;
1549 if (__predict_false(++ndescs == limit)) {
1550 t4_write_reg(sc, sc->sge_gts_reg,
1552 V_INGRESSQID(iq->cntxt_id) |
1553 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1557 return (EINPROGRESS);
1562 if (STAILQ_EMPTY(&iql))
1566 * Process the head only, and send it to the back of the list if
1567 * it's still not done.
1569 q = STAILQ_FIRST(&iql);
1570 STAILQ_REMOVE_HEAD(&iql, link);
1571 if (service_iq_fl(q, q->qsize / 8) == 0)
1572 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1574 STAILQ_INSERT_TAIL(&iql, q, link);
1577 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1578 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1584 sort_before_lro(struct lro_ctrl *lro)
1587 return (lro->lro_mbuf_max != 0);
1590 static inline uint64_t
1591 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1593 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */
1595 if (n > UINT64_MAX / 1000000)
1596 return (n / sc->params.vpd.cclk * 1000000);
1598 return (n * 1000000 / sc->params.vpd.cclk);
1602 * Deals with interrupts on an iq+fl queue.
1605 service_iq_fl(struct sge_iq *iq, int budget)
1607 struct sge_rxq *rxq = iq_to_rxq(iq);
1609 struct adapter *sc = iq->adapter;
1610 struct iq_desc *d = &iq->desc[iq->cidx];
1611 int ndescs = 0, limit;
1612 int rsp_type, refill, starved;
1614 uint16_t fl_hw_cidx;
1616 #if defined(INET) || defined(INET6)
1617 const struct timeval lro_timeout = {0, sc->lro_timeout};
1618 struct lro_ctrl *lro = &rxq->lro;
1621 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1622 MPASS(iq->flags & IQ_HAS_FL);
1624 limit = budget ? budget : iq->qsize / 16;
1626 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1628 #if defined(INET) || defined(INET6)
1629 if (iq->flags & IQ_ADJ_CREDIT) {
1630 MPASS(sort_before_lro(lro));
1631 iq->flags &= ~IQ_ADJ_CREDIT;
1632 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1633 tcp_lro_flush_all(lro);
1634 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1635 V_INGRESSQID((u32)iq->cntxt_id) |
1636 V_SEINTARM(iq->intr_params));
1642 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1645 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1651 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1652 lq = be32toh(d->rsp.pldbuflen_qid);
1655 case X_RSPD_TYPE_FLBUF:
1657 m0 = get_fl_payload(sc, fl, lq);
1658 if (__predict_false(m0 == NULL))
1660 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1662 if (iq->flags & IQ_RX_TIMESTAMP) {
1664 * Fill up rcv_tstmp but do not set M_TSTMP.
1665 * rcv_tstmp is not in the format that the
1666 * kernel expects and we don't want to mislead
1667 * it. For now this is only for custom code
1668 * that knows how to interpret cxgbe's stamp.
1670 m0->m_pkthdr.rcv_tstmp =
1671 last_flit_to_ns(sc, d->rsp.u.last_flit);
1673 m0->m_flags |= M_TSTMP;
1679 case X_RSPD_TYPE_CPL:
1680 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1681 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1682 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1685 case X_RSPD_TYPE_INTR:
1688 * There are 1K interrupt-capable queues (qids 0
1689 * through 1023). A response type indicating a
1690 * forwarded interrupt with a qid >= 1K is an
1691 * iWARP async notification. That is the only
1692 * acceptable indirect interrupt on this queue.
1694 if (__predict_false(lq < 1024)) {
1695 panic("%s: indirect interrupt on iq_fl %p "
1696 "with qid %u", __func__, iq, lq);
1699 t4_an_handler(iq, &d->rsp);
1703 KASSERT(0, ("%s: illegal response type %d on iq %p",
1704 __func__, rsp_type, iq));
1705 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1706 device_get_nameunit(sc->dev), rsp_type, iq);
1711 if (__predict_false(++iq->cidx == iq->sidx)) {
1713 iq->gen ^= F_RSPD_GEN;
1716 if (__predict_false(++ndescs == limit)) {
1717 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1718 V_INGRESSQID(iq->cntxt_id) |
1719 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1722 #if defined(INET) || defined(INET6)
1723 if (iq->flags & IQ_LRO_ENABLED &&
1724 !sort_before_lro(lro) &&
1725 sc->lro_timeout != 0) {
1726 tcp_lro_flush_inactive(lro, &lro_timeout);
1731 refill_fl(sc, fl, 32);
1734 return (EINPROGRESS);
1739 refill_fl(sc, fl, 32);
1741 fl_hw_cidx = fl->hw_cidx;
1745 #if defined(INET) || defined(INET6)
1746 if (iq->flags & IQ_LRO_ENABLED) {
1747 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1748 MPASS(sort_before_lro(lro));
1749 /* hold back one credit and don't flush LRO state */
1750 iq->flags |= IQ_ADJ_CREDIT;
1753 tcp_lro_flush_all(lro);
1758 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1759 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1762 starved = refill_fl(sc, fl, 64);
1764 if (__predict_false(starved != 0))
1765 add_fl_to_sfl(sc, fl);
1771 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1773 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1776 MPASS(cll->region3 >= CL_METADATA_SIZE);
1781 static inline struct cluster_metadata *
1782 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1786 if (cl_has_metadata(fl, cll)) {
1787 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1789 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1795 rxb_free(struct mbuf *m)
1797 uma_zone_t zone = m->m_ext.ext_arg1;
1798 void *cl = m->m_ext.ext_arg2;
1800 uma_zfree(zone, cl);
1801 counter_u64_add(extfree_rels, 1);
1805 * The mbuf returned by this function could be allocated from zone_mbuf or
1806 * constructed in spare room in the cluster.
1808 * The mbuf carries the payload in one of these ways
1809 * a) frame inside the mbuf (mbuf from zone_mbuf)
1810 * b) m_cljset (for clusters without metadata) zone_mbuf
1811 * c) m_extaddref (cluster with metadata) inline mbuf
1812 * d) m_extaddref (cluster with metadata) zone_mbuf
1814 static struct mbuf *
1815 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1819 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1820 struct cluster_layout *cll = &sd->cll;
1821 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1822 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1823 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1827 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1828 len = min(remaining, blen);
1829 payload = sd->cl + cll->region1 + fl->rx_offset;
1830 if (fl->flags & FL_BUF_PACKING) {
1831 const u_int l = fr_offset + len;
1832 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1834 if (fl->rx_offset + len + pad < hwb->size)
1836 MPASS(fl->rx_offset + blen <= hwb->size);
1838 MPASS(fl->rx_offset == 0); /* not packing */
1842 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1845 * Copy payload into a freshly allocated mbuf.
1848 m = fr_offset == 0 ?
1849 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1852 fl->mbuf_allocated++;
1854 /* copy data to mbuf */
1855 bcopy(payload, mtod(m, caddr_t), len);
1857 } else if (sd->nmbuf * MSIZE < cll->region1) {
1860 * There's spare room in the cluster for an mbuf. Create one
1861 * and associate it with the payload that's in the cluster.
1865 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1866 /* No bzero required */
1867 if (m_init(m, M_NOWAIT, MT_DATA,
1868 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1871 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1873 if (sd->nmbuf++ == 0)
1874 counter_u64_add(extfree_refs, 1);
1879 * Grab an mbuf from zone_mbuf and associate it with the
1880 * payload in the cluster.
1883 m = fr_offset == 0 ?
1884 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1887 fl->mbuf_allocated++;
1889 m_extaddref(m, payload, blen, &clm->refcount,
1890 rxb_free, swz->zone, sd->cl);
1891 if (sd->nmbuf++ == 0)
1892 counter_u64_add(extfree_refs, 1);
1894 m_cljset(m, sd->cl, swz->type);
1895 sd->cl = NULL; /* consumed, not a recycle candidate */
1899 m->m_pkthdr.len = remaining;
1902 if (fl->flags & FL_BUF_PACKING) {
1903 fl->rx_offset += blen;
1904 MPASS(fl->rx_offset <= hwb->size);
1905 if (fl->rx_offset < hwb->size)
1906 return (m); /* without advancing the cidx */
1909 if (__predict_false(++fl->cidx % 8 == 0)) {
1910 uint16_t cidx = fl->cidx / 8;
1912 if (__predict_false(cidx == fl->sidx))
1913 fl->cidx = cidx = 0;
1921 static struct mbuf *
1922 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1924 struct mbuf *m0, *m, **pnext;
1926 const u_int total = G_RSPD_LEN(len_newbuf);
1928 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1929 M_ASSERTPKTHDR(fl->m0);
1930 MPASS(fl->m0->m_pkthdr.len == total);
1931 MPASS(fl->remaining < total);
1935 remaining = fl->remaining;
1936 fl->flags &= ~FL_BUF_RESUME;
1940 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1942 if (__predict_false(++fl->cidx % 8 == 0)) {
1943 uint16_t cidx = fl->cidx / 8;
1945 if (__predict_false(cidx == fl->sidx))
1946 fl->cidx = cidx = 0;
1952 * Payload starts at rx_offset in the current hw buffer. Its length is
1953 * 'len' and it may span multiple hw buffers.
1956 m0 = get_scatter_segment(sc, fl, 0, total);
1959 remaining = total - m0->m_len;
1960 pnext = &m0->m_next;
1961 while (remaining > 0) {
1963 MPASS(fl->rx_offset == 0);
1964 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1965 if (__predict_false(m == NULL)) {
1968 fl->remaining = remaining;
1969 fl->flags |= FL_BUF_RESUME;
1974 remaining -= m->m_len;
1983 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1985 struct sge_rxq *rxq = iq_to_rxq(iq);
1986 struct ifnet *ifp = rxq->ifp;
1987 struct adapter *sc = iq->adapter;
1988 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1989 #if defined(INET) || defined(INET6)
1990 struct lro_ctrl *lro = &rxq->lro;
1992 static const int sw_hashtype[4][2] = {
1993 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1994 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1995 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1996 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1999 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
2002 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
2003 m0->m_len -= sc->params.sge.fl_pktshift;
2004 m0->m_data += sc->params.sge.fl_pktshift;
2006 m0->m_pkthdr.rcvif = ifp;
2007 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
2008 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
2010 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
2011 if (ifp->if_capenable & IFCAP_RXCSUM &&
2012 cpl->l2info & htobe32(F_RXF_IP)) {
2013 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
2014 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
2016 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
2017 cpl->l2info & htobe32(F_RXF_IP6)) {
2018 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
2023 if (__predict_false(cpl->ip_frag))
2024 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2026 m0->m_pkthdr.csum_data = 0xffff;
2030 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2031 m0->m_flags |= M_VLANTAG;
2032 rxq->vlan_extraction++;
2036 m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2038 #if defined(INET) || defined(INET6)
2039 if (iq->flags & IQ_LRO_ENABLED) {
2040 if (sort_before_lro(lro)) {
2041 tcp_lro_queue_mbuf(lro, m0);
2042 return (0); /* queued for sort, then LRO */
2044 if (tcp_lro_rx(lro, m0, 0) == 0)
2045 return (0); /* queued for LRO */
2048 ifp->if_input(ifp, m0);
2054 * Must drain the wrq or make sure that someone else will.
2057 wrq_tx_drain(void *arg, int n)
2059 struct sge_wrq *wrq = arg;
2060 struct sge_eq *eq = &wrq->eq;
2063 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2064 drain_wrq_wr_list(wrq->adapter, wrq);
2069 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2071 struct sge_eq *eq = &wrq->eq;
2072 u_int available, dbdiff; /* # of hardware descriptors */
2075 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2077 EQ_LOCK_ASSERT_OWNED(eq);
2078 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2079 wr = STAILQ_FIRST(&wrq->wr_list);
2080 MPASS(wr != NULL); /* Must be called with something useful to do */
2081 MPASS(eq->pidx == eq->dbidx);
2085 eq->cidx = read_hw_cidx(eq);
2086 if (eq->pidx == eq->cidx)
2087 available = eq->sidx - 1;
2089 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2091 MPASS(wr->wrq == wrq);
2092 n = howmany(wr->wr_len, EQ_ESIZE);
2096 dst = (void *)&eq->desc[eq->pidx];
2097 if (__predict_true(eq->sidx - eq->pidx > n)) {
2098 /* Won't wrap, won't end exactly at the status page. */
2099 bcopy(&wr->wr[0], dst, wr->wr_len);
2102 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2104 bcopy(&wr->wr[0], dst, first_portion);
2105 if (wr->wr_len > first_portion) {
2106 bcopy(&wr->wr[first_portion], &eq->desc[0],
2107 wr->wr_len - first_portion);
2109 eq->pidx = n - (eq->sidx - eq->pidx);
2111 wrq->tx_wrs_copied++;
2113 if (available < eq->sidx / 4 &&
2114 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2116 * XXX: This is not 100% reliable with some
2117 * types of WRs. But this is a very unusual
2118 * situation for an ofld/ctrl queue anyway.
2120 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2126 ring_eq_db(sc, eq, dbdiff);
2130 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2132 MPASS(wrq->nwr_pending > 0);
2134 MPASS(wrq->ndesc_needed >= n);
2135 wrq->ndesc_needed -= n;
2136 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2139 ring_eq_db(sc, eq, dbdiff);
2143 * Doesn't fail. Holds on to work requests it can't send right away.
2146 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2149 struct sge_eq *eq = &wrq->eq;
2152 EQ_LOCK_ASSERT_OWNED(eq);
2154 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2155 MPASS((wr->wr_len & 0x7) == 0);
2157 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2159 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2161 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2162 return; /* commit_wrq_wr will drain wr_list as well. */
2164 drain_wrq_wr_list(sc, wrq);
2166 /* Doorbell must have caught up to the pidx. */
2167 MPASS(eq->pidx == eq->dbidx);
2171 t4_update_fl_bufsize(struct ifnet *ifp)
2173 struct vi_info *vi = ifp->if_softc;
2174 struct adapter *sc = vi->pi->adapter;
2175 struct sge_rxq *rxq;
2177 struct sge_ofld_rxq *ofld_rxq;
2180 int i, maxp, mtu = ifp->if_mtu;
2182 maxp = mtu_to_max_payload(sc, mtu);
2183 for_each_rxq(vi, i, rxq) {
2187 find_best_refill_source(sc, fl, maxp);
2191 for_each_ofld_rxq(vi, i, ofld_rxq) {
2195 find_best_refill_source(sc, fl, maxp);
2202 mbuf_nsegs(struct mbuf *m)
2206 KASSERT(m->m_pkthdr.l5hlen > 0,
2207 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2209 return (m->m_pkthdr.l5hlen);
2213 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2217 m->m_pkthdr.l5hlen = nsegs;
2221 mbuf_cflags(struct mbuf *m)
2225 return (m->m_pkthdr.PH_loc.eight[4]);
2229 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2233 m->m_pkthdr.PH_loc.eight[4] = flags;
2237 mbuf_len16(struct mbuf *m)
2242 n = m->m_pkthdr.PH_loc.eight[0];
2243 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2249 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2253 m->m_pkthdr.PH_loc.eight[0] = len16;
2258 mbuf_eo_nsegs(struct mbuf *m)
2262 return (m->m_pkthdr.PH_loc.eight[1]);
2266 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2270 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2274 mbuf_eo_len16(struct mbuf *m)
2279 n = m->m_pkthdr.PH_loc.eight[2];
2280 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2286 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2290 m->m_pkthdr.PH_loc.eight[2] = len16;
2294 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2298 return (m->m_pkthdr.PH_loc.eight[3]);
2302 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2306 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2310 needs_eo(struct mbuf *m)
2313 return (m->m_pkthdr.csum_flags & CSUM_SND_TAG);
2318 * Try to allocate an mbuf to contain a raw work request. To make it
2319 * easy to construct the work request, don't allocate a chain but a
2323 alloc_wr_mbuf(int len, int how)
2328 m = m_gethdr(how, MT_DATA);
2329 else if (len <= MCLBYTES)
2330 m = m_getcl(how, MT_DATA, M_PKTHDR);
2335 m->m_pkthdr.len = len;
2337 set_mbuf_cflags(m, MC_RAW_WR);
2338 set_mbuf_len16(m, howmany(len, 16));
2343 needs_tso(struct mbuf *m)
2348 return (m->m_pkthdr.csum_flags & CSUM_TSO);
2352 needs_l3_csum(struct mbuf *m)
2357 return (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO));
2361 needs_l4_csum(struct mbuf *m)
2366 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2367 CSUM_TCP_IPV6 | CSUM_TSO));
2371 needs_tcp_csum(struct mbuf *m)
2375 return (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_TCP_IPV6 | CSUM_TSO));
2380 needs_udp_csum(struct mbuf *m)
2384 return (m->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_UDP_IPV6));
2389 needs_vlan_insertion(struct mbuf *m)
2394 return (m->m_flags & M_VLANTAG);
2398 m_advance(struct mbuf **pm, int *poffset, int len)
2400 struct mbuf *m = *pm;
2401 int offset = *poffset;
2407 if (offset + len < m->m_len) {
2409 p = mtod(m, uintptr_t) + offset;
2412 len -= m->m_len - offset;
2423 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2425 struct mbuf_ext_pgs *ext_pgs;
2427 int i, len, off, pglen, pgoff, seglen, segoff;
2430 MBUF_EXT_PGS_ASSERT(m);
2431 ext_pgs = m->m_ext.ext_pgs;
2432 off = mtod(m, vm_offset_t);
2437 if (ext_pgs->hdr_len != 0) {
2438 if (off >= ext_pgs->hdr_len) {
2439 off -= ext_pgs->hdr_len;
2441 seglen = ext_pgs->hdr_len - off;
2443 seglen = min(seglen, len);
2446 paddr = pmap_kextract(
2447 (vm_offset_t)&ext_pgs->hdr[segoff]);
2448 if (*nextaddr != paddr)
2450 *nextaddr = paddr + seglen;
2453 pgoff = ext_pgs->first_pg_off;
2454 for (i = 0; i < ext_pgs->npgs && len > 0; i++) {
2455 pglen = mbuf_ext_pg_len(ext_pgs, i, pgoff);
2461 seglen = pglen - off;
2462 segoff = pgoff + off;
2464 seglen = min(seglen, len);
2466 paddr = ext_pgs->pa[i] + segoff;
2467 if (*nextaddr != paddr)
2469 *nextaddr = paddr + seglen;
2473 seglen = min(len, ext_pgs->trail_len - off);
2475 paddr = pmap_kextract((vm_offset_t)&ext_pgs->trail[off]);
2476 if (*nextaddr != paddr)
2478 *nextaddr = paddr + seglen;
2486 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2487 * must have at least one mbuf that's not empty. It is possible for this
2488 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2491 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2493 vm_paddr_t nextaddr, paddr;
2498 MPASS(m->m_pkthdr.len > 0);
2499 MPASS(m->m_pkthdr.len >= skip);
2503 for (; m; m = m->m_next) {
2505 if (__predict_false(len == 0))
2511 if ((m->m_flags & M_NOMAP) != 0) {
2512 *cflags |= MC_NOMAP;
2513 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2517 va = mtod(m, vm_offset_t) + skip;
2520 paddr = pmap_kextract(va);
2521 nsegs += sglist_count((void *)(uintptr_t)va, len);
2522 if (paddr == nextaddr)
2524 nextaddr = pmap_kextract(va + len - 1) + 1;
2531 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2532 * a) caller can assume it's been freed if this function returns with an error.
2533 * b) it may get defragged up if the gather list is too long for the hardware.
2536 parse_pkt(struct adapter *sc, struct mbuf **mp)
2538 struct mbuf *m0 = *mp, *m;
2539 int rc, nsegs, defragged = 0, offset;
2540 struct ether_header *eh;
2542 #if defined(INET) || defined(INET6)
2550 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2559 * First count the number of gather list segments in the payload.
2560 * Defrag the mbuf if nsegs exceeds the hardware limit.
2563 MPASS(m0->m_pkthdr.len > 0);
2564 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2565 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2566 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2570 *mp = m0 = m; /* update caller's copy after defrag */
2574 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2575 !(cflags & MC_NOMAP))) {
2576 m0 = m_pullup(m0, m0->m_pkthdr.len);
2578 /* Should have left well enough alone. */
2582 *mp = m0; /* update caller's copy after pullup */
2585 set_mbuf_nsegs(m0, nsegs);
2586 set_mbuf_cflags(m0, cflags);
2587 if (sc->flags & IS_VF)
2588 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2590 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2594 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2595 * checksumming is enabled. needs_l4_csum happens to check for all the
2598 if (__predict_false(needs_eo(m0) && !needs_l4_csum(m0))) {
2599 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2600 m0->m_pkthdr.snd_tag = NULL;
2601 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2605 if (!needs_tso(m0) &&
2609 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2613 eh = mtod(m, struct ether_header *);
2614 eh_type = ntohs(eh->ether_type);
2615 if (eh_type == ETHERTYPE_VLAN) {
2616 struct ether_vlan_header *evh = (void *)eh;
2618 eh_type = ntohs(evh->evl_proto);
2619 m0->m_pkthdr.l2hlen = sizeof(*evh);
2621 m0->m_pkthdr.l2hlen = sizeof(*eh);
2624 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2628 case ETHERTYPE_IPV6:
2630 struct ip6_hdr *ip6 = l3hdr;
2632 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2634 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2641 struct ip *ip = l3hdr;
2643 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2648 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2649 " with the same INET/INET6 options as the kernel.",
2653 #if defined(INET) || defined(INET6)
2654 if (needs_tcp_csum(m0)) {
2655 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2656 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2658 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2659 set_mbuf_eo_tsclk_tsoff(m0,
2660 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2661 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2663 set_mbuf_eo_tsclk_tsoff(m0, 0);
2664 } else if (needs_udp_csum(m)) {
2665 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2672 /* EO WRs have the headers in the WR and not the GL. */
2673 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2674 m0->m_pkthdr.l4hlen;
2676 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2677 MPASS(cflags == mbuf_cflags(m0));
2678 set_mbuf_eo_nsegs(m0, nsegs);
2679 set_mbuf_eo_len16(m0,
2680 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2689 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2691 struct sge_eq *eq = &wrq->eq;
2692 struct adapter *sc = wrq->adapter;
2693 int ndesc, available;
2698 ndesc = howmany(len16, EQ_ESIZE / 16);
2699 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2703 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2704 drain_wrq_wr_list(sc, wrq);
2706 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2709 wr = alloc_wrqe(len16 * 16, wrq);
2710 if (__predict_false(wr == NULL))
2713 cookie->ndesc = ndesc;
2717 eq->cidx = read_hw_cidx(eq);
2718 if (eq->pidx == eq->cidx)
2719 available = eq->sidx - 1;
2721 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2722 if (available < ndesc)
2725 cookie->pidx = eq->pidx;
2726 cookie->ndesc = ndesc;
2727 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2729 w = &eq->desc[eq->pidx];
2730 IDXINCR(eq->pidx, ndesc, eq->sidx);
2731 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2733 wrq->ss_pidx = cookie->pidx;
2734 wrq->ss_len = len16 * 16;
2743 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2745 struct sge_eq *eq = &wrq->eq;
2746 struct adapter *sc = wrq->adapter;
2748 struct wrq_cookie *prev, *next;
2750 if (cookie->pidx == -1) {
2751 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2757 if (__predict_false(w == &wrq->ss[0])) {
2758 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2760 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2761 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2762 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2765 wrq->tx_wrs_direct++;
2768 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2769 pidx = cookie->pidx;
2770 MPASS(pidx >= 0 && pidx < eq->sidx);
2771 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2772 next = TAILQ_NEXT(cookie, link);
2774 MPASS(pidx == eq->dbidx);
2775 if (next == NULL || ndesc >= 16) {
2777 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2780 * Note that the WR via which we'll request tx updates
2781 * is at pidx and not eq->pidx, which has moved on
2784 dst = (void *)&eq->desc[pidx];
2785 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2786 if (available < eq->sidx / 4 &&
2787 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2789 * XXX: This is not 100% reliable with some
2790 * types of WRs. But this is a very unusual
2791 * situation for an ofld/ctrl queue anyway.
2793 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2797 ring_eq_db(wrq->adapter, eq, ndesc);
2799 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2801 next->ndesc += ndesc;
2804 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2805 prev->ndesc += ndesc;
2807 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2809 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2810 drain_wrq_wr_list(sc, wrq);
2813 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2814 /* Doorbell must have caught up to the pidx. */
2815 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2822 can_resume_eth_tx(struct mp_ring *r)
2824 struct sge_eq *eq = r->cookie;
2826 return (total_available_tx_desc(eq) > eq->sidx / 8);
2830 cannot_use_txpkts(struct mbuf *m)
2832 /* maybe put a GL limit too, to avoid silliness? */
2834 return (needs_tso(m) || (mbuf_cflags(m) & MC_RAW_WR) != 0);
2838 discard_tx(struct sge_eq *eq)
2841 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2845 wr_can_update_eq(struct fw_eth_tx_pkts_wr *wr)
2848 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
2850 case FW_ETH_TX_PKT_WR:
2851 case FW_ETH_TX_PKTS_WR:
2852 case FW_ETH_TX_PKT_VM_WR:
2860 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2861 * be consumed. Return the actual number consumed. 0 indicates a stall.
2864 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2866 struct sge_txq *txq = r->cookie;
2867 struct sge_eq *eq = &txq->eq;
2868 struct ifnet *ifp = txq->ifp;
2869 struct vi_info *vi = ifp->if_softc;
2870 struct port_info *pi = vi->pi;
2871 struct adapter *sc = pi->adapter;
2872 u_int total, remaining; /* # of packets */
2873 u_int available, dbdiff; /* # of hardware descriptors */
2875 struct mbuf *m0, *tail;
2877 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2879 remaining = IDXDIFF(pidx, cidx, r->size);
2880 MPASS(remaining > 0); /* Must not be called without work to do. */
2884 if (__predict_false(discard_tx(eq))) {
2885 while (cidx != pidx) {
2886 m0 = r->items[cidx];
2888 if (++cidx == r->size)
2891 reclaim_tx_descs(txq, 2048);
2896 /* How many hardware descriptors do we have readily available. */
2897 if (eq->pidx == eq->cidx)
2898 available = eq->sidx - 1;
2900 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2901 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2903 while (remaining > 0) {
2905 m0 = r->items[cidx];
2907 MPASS(m0->m_nextpkt == NULL);
2909 if (available < SGE_MAX_WR_NDESC) {
2910 available += reclaim_tx_descs(txq, 64);
2911 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2912 break; /* out of descriptors */
2915 next_cidx = cidx + 1;
2916 if (__predict_false(next_cidx == r->size))
2919 wr = (void *)&eq->desc[eq->pidx];
2920 if (sc->flags & IS_VF) {
2923 ETHER_BPF_MTAP(ifp, m0);
2924 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2926 } else if (remaining > 1 &&
2927 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2929 /* pkts at cidx, next_cidx should both be in txp. */
2930 MPASS(txp.npkt == 2);
2931 tail = r->items[next_cidx];
2932 MPASS(tail->m_nextpkt == NULL);
2933 ETHER_BPF_MTAP(ifp, m0);
2934 ETHER_BPF_MTAP(ifp, tail);
2935 m0->m_nextpkt = tail;
2937 if (__predict_false(++next_cidx == r->size))
2940 while (next_cidx != pidx) {
2941 if (add_to_txpkts(r->items[next_cidx], &txp,
2944 tail->m_nextpkt = r->items[next_cidx];
2945 tail = tail->m_nextpkt;
2946 ETHER_BPF_MTAP(ifp, tail);
2947 if (__predict_false(++next_cidx == r->size))
2951 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2953 remaining -= txp.npkt;
2954 } else if (mbuf_cflags(m0) & MC_RAW_WR) {
2957 n = write_raw_wr(txq, (void *)wr, m0, available);
2961 ETHER_BPF_MTAP(ifp, m0);
2962 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2964 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2968 IDXINCR(eq->pidx, n, eq->sidx);
2970 if (wr_can_update_eq(wr)) {
2971 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2972 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2973 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2975 eq->equeqidx = eq->pidx;
2976 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >=
2978 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2979 eq->equeqidx = eq->pidx;
2983 if (dbdiff >= 16 && remaining >= 4) {
2984 ring_eq_db(sc, eq, dbdiff);
2985 available += reclaim_tx_descs(txq, 4 * dbdiff);
2992 ring_eq_db(sc, eq, dbdiff);
2993 reclaim_tx_descs(txq, 32);
3002 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3006 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3007 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3008 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3009 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3013 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3014 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3015 if (pktc_idx >= 0) {
3016 iq->intr_params |= F_QINTR_CNT_EN;
3017 iq->intr_pktc_idx = pktc_idx;
3019 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3020 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3024 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3028 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3029 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3030 if (sc->flags & BUF_PACKING_OK &&
3031 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3032 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3033 fl->flags |= FL_BUF_PACKING;
3034 find_best_refill_source(sc, fl, maxp);
3035 find_safe_refill_source(sc, fl);
3039 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3040 uint8_t tx_chan, uint16_t iqid, char *name)
3042 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
3044 eq->flags = eqtype & EQ_TYPEMASK;
3045 eq->tx_chan = tx_chan;
3047 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3048 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3052 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3053 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3057 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3058 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3060 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
3064 rc = bus_dmamem_alloc(*tag, va,
3065 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3067 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
3071 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3073 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
3078 free_ring(sc, *tag, *map, *pa, *va);
3084 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3085 bus_addr_t pa, void *va)
3088 bus_dmamap_unload(tag, map);
3090 bus_dmamem_free(tag, va, map);
3092 bus_dma_tag_destroy(tag);
3098 * Allocates the ring for an ingress queue and an optional freelist. If the
3099 * freelist is specified it will be allocated and then associated with the
3102 * Returns errno on failure. Resources allocated up to that point may still be
3103 * allocated. Caller is responsible for cleanup in case this function fails.
3105 * If the ingress queue will take interrupts directly then the intr_idx
3106 * specifies the vector, starting from 0. -1 means the interrupts for this
3107 * queue should be forwarded to the fwq.
3110 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3111 int intr_idx, int cong)
3113 int rc, i, cntxt_id;
3116 struct port_info *pi = vi->pi;
3117 struct adapter *sc = iq->adapter;
3118 struct sge_params *sp = &sc->params.sge;
3121 len = iq->qsize * IQ_ESIZE;
3122 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3123 (void **)&iq->desc);
3127 bzero(&c, sizeof(c));
3128 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3129 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3130 V_FW_IQ_CMD_VFN(0));
3132 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3135 /* Special handling for firmware event queue */
3136 if (iq == &sc->sge.fwq)
3137 v |= F_FW_IQ_CMD_IQASYNCH;
3140 /* Forwarded interrupts, all headed to fwq */
3141 v |= F_FW_IQ_CMD_IQANDST;
3142 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3144 KASSERT(intr_idx < sc->intr_count,
3145 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
3146 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
3149 c.type_to_iqandstindex = htobe32(v |
3150 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3151 V_FW_IQ_CMD_VIID(vi->viid) |
3152 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3153 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3154 F_FW_IQ_CMD_IQGTSMODE |
3155 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3156 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3157 c.iqsize = htobe16(iq->qsize);
3158 c.iqaddr = htobe64(iq->ba);
3160 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3163 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3165 len = fl->qsize * EQ_ESIZE;
3166 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3167 &fl->ba, (void **)&fl->desc);
3171 /* Allocate space for one software descriptor per buffer. */
3172 rc = alloc_fl_sdesc(fl);
3174 device_printf(sc->dev,
3175 "failed to setup fl software descriptors: %d\n",
3180 if (fl->flags & FL_BUF_PACKING) {
3181 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3182 fl->buf_boundary = sp->pack_boundary;
3184 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3185 fl->buf_boundary = 16;
3187 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3188 fl->buf_boundary = sp->pad_boundary;
3190 c.iqns_to_fl0congen |=
3191 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3192 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3193 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3194 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3197 c.iqns_to_fl0congen |=
3198 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
3199 F_FW_IQ_CMD_FL0CONGCIF |
3200 F_FW_IQ_CMD_FL0CONGEN);
3202 c.fl0dcaen_to_fl0cidxfthresh =
3203 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3204 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
3205 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3206 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3207 c.fl0size = htobe16(fl->qsize);
3208 c.fl0addr = htobe64(fl->ba);
3211 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3213 device_printf(sc->dev,
3214 "failed to create ingress queue: %d\n", rc);
3219 iq->gen = F_RSPD_GEN;
3220 iq->intr_next = iq->intr_params;
3221 iq->cntxt_id = be16toh(c.iqid);
3222 iq->abs_id = be16toh(c.physiqid);
3223 iq->flags |= IQ_ALLOCATED;
3225 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3226 if (cntxt_id >= sc->sge.niq) {
3227 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3228 cntxt_id, sc->sge.niq - 1);
3230 sc->sge.iqmap[cntxt_id] = iq;
3235 iq->flags |= IQ_HAS_FL;
3236 fl->cntxt_id = be16toh(c.fl0id);
3237 fl->pidx = fl->cidx = 0;
3239 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3240 if (cntxt_id >= sc->sge.neq) {
3241 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3242 __func__, cntxt_id, sc->sge.neq - 1);
3244 sc->sge.eqmap[cntxt_id] = (void *)fl;
3247 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3248 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3249 uint32_t mask = (1 << s_qpp) - 1;
3250 volatile uint8_t *udb;
3252 udb = sc->udbs_base + UDBS_DB_OFFSET;
3253 udb += (qid >> s_qpp) << PAGE_SHIFT;
3255 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3256 udb += qid << UDBS_SEG_SHIFT;
3259 fl->udb = (volatile void *)udb;
3261 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3264 /* Enough to make sure the SGE doesn't think it's starved */
3265 refill_fl(sc, fl, fl->lowat);
3269 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
3270 uint32_t param, val;
3272 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3273 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3274 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3279 for (i = 0; i < 4; i++) {
3280 if (cong & (1 << i))
3281 val |= 1 << (i << 2);
3285 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3287 /* report error but carry on */
3288 device_printf(sc->dev,
3289 "failed to set congestion manager context for "
3290 "ingress queue %d: %d\n", iq->cntxt_id, rc);
3294 /* Enable IQ interrupts */
3295 atomic_store_rel_int(&iq->state, IQS_IDLE);
3296 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3297 V_INGRESSQID(iq->cntxt_id));
3303 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3306 struct adapter *sc = iq->adapter;
3310 return (0); /* nothing to do */
3312 dev = vi ? vi->dev : sc->dev;
3314 if (iq->flags & IQ_ALLOCATED) {
3315 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
3316 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
3317 fl ? fl->cntxt_id : 0xffff, 0xffff);
3320 "failed to free queue %p: %d\n", iq, rc);
3323 iq->flags &= ~IQ_ALLOCATED;
3326 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3328 bzero(iq, sizeof(*iq));
3331 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
3335 free_fl_sdesc(sc, fl);
3337 if (mtx_initialized(&fl->fl_lock))
3338 mtx_destroy(&fl->fl_lock);
3340 bzero(fl, sizeof(*fl));
3347 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3350 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3352 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3353 "bus address of descriptor ring");
3354 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3355 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3356 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3357 CTLTYPE_INT | CTLFLAG_RD, &iq->abs_id, 0, sysctl_uint16, "I",
3358 "absolute id of the queue");
3359 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3360 CTLTYPE_INT | CTLFLAG_RD, &iq->cntxt_id, 0, sysctl_uint16, "I",
3361 "SGE context id of the queue");
3362 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3363 CTLTYPE_INT | CTLFLAG_RD, &iq->cidx, 0, sysctl_uint16, "I",
3368 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3369 struct sysctl_oid *oid, struct sge_fl *fl)
3371 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3373 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3375 children = SYSCTL_CHILDREN(oid);
3377 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3378 &fl->ba, "bus address of descriptor ring");
3379 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3380 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3381 "desc ring size in bytes");
3382 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3383 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
3384 "SGE context id of the freelist");
3385 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3386 fl_pad ? 1 : 0, "padding enabled");
3387 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3388 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3389 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3390 0, "consumer index");
3391 if (fl->flags & FL_BUF_PACKING) {
3392 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3393 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3395 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3396 0, "producer index");
3397 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
3398 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
3399 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
3400 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
3401 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3402 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3403 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3404 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3405 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3406 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3410 alloc_fwq(struct adapter *sc)
3413 struct sge_iq *fwq = &sc->sge.fwq;
3414 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3415 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3417 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3418 if (sc->flags & IS_VF)
3421 intr_idx = sc->intr_count > 1 ? 1 : 0;
3422 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3424 device_printf(sc->dev,
3425 "failed to create firmware event queue: %d\n", rc);
3429 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
3430 NULL, "firmware event queue");
3431 add_iq_sysctls(&sc->ctx, oid, fwq);
3437 free_fwq(struct adapter *sc)
3439 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3443 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx,
3444 struct sysctl_oid *oid)
3448 struct sysctl_oid_list *children;
3450 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev),
3452 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan,
3453 sc->sge.fwq.cntxt_id, name);
3455 children = SYSCTL_CHILDREN(oid);
3456 snprintf(name, sizeof(name), "%d", idx);
3457 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3458 NULL, "ctrl queue");
3459 rc = alloc_wrq(sc, NULL, ctrlq, oid);
3465 tnl_cong(struct port_info *pi, int drop)
3473 return (pi->rx_e_chan_map);
3477 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3478 struct sysctl_oid *oid)
3481 struct adapter *sc = vi->pi->adapter;
3482 struct sysctl_oid_list *children;
3485 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3486 tnl_cong(vi->pi, cong_drop));
3491 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3493 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3494 ("iq_base mismatch"));
3495 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3496 ("PF with non-zero iq_base"));
3499 * The freelist is just barely above the starvation threshold right now,
3500 * fill it up a bit more.
3503 refill_fl(sc, &rxq->fl, 128);
3504 FL_UNLOCK(&rxq->fl);
3506 #if defined(INET) || defined(INET6)
3507 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3510 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3512 if (vi->ifp->if_capenable & IFCAP_LRO)
3513 rxq->iq.flags |= IQ_LRO_ENABLED;
3515 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP)
3516 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3519 children = SYSCTL_CHILDREN(oid);
3521 snprintf(name, sizeof(name), "%d", idx);
3522 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3524 children = SYSCTL_CHILDREN(oid);
3526 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3527 #if defined(INET) || defined(INET6)
3528 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3529 &rxq->lro.lro_queued, 0, NULL);
3530 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3531 &rxq->lro.lro_flushed, 0, NULL);
3533 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3534 &rxq->rxcsum, "# of times hardware assisted with checksum");
3535 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3536 CTLFLAG_RD, &rxq->vlan_extraction,
3537 "# of times hardware extracted 802.1Q tag");
3539 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3545 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3549 #if defined(INET) || defined(INET6)
3551 tcp_lro_free(&rxq->lro);
3552 rxq->lro.ifp = NULL;
3556 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3558 bzero(rxq, sizeof(*rxq));
3565 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3566 int intr_idx, int idx, struct sysctl_oid *oid)
3568 struct port_info *pi = vi->pi;
3570 struct sysctl_oid_list *children;
3573 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3577 children = SYSCTL_CHILDREN(oid);
3579 snprintf(name, sizeof(name), "%d", idx);
3580 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3582 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3583 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3589 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3593 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3595 bzero(ofld_rxq, sizeof(*ofld_rxq));
3603 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3604 int idx, struct sysctl_oid *oid)
3607 struct sysctl_oid_list *children;
3608 struct sysctl_ctx_list *ctx;
3611 struct adapter *sc = vi->pi->adapter;
3612 struct netmap_adapter *na = NA(vi->ifp);
3616 len = vi->qsize_rxq * IQ_ESIZE;
3617 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3618 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3622 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3623 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3624 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3630 nm_rxq->iq_cidx = 0;
3631 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3632 nm_rxq->iq_gen = F_RSPD_GEN;
3633 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3634 nm_rxq->fl_sidx = na->num_rx_desc;
3635 nm_rxq->intr_idx = intr_idx;
3636 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3639 children = SYSCTL_CHILDREN(oid);
3641 snprintf(name, sizeof(name), "%d", idx);
3642 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3644 children = SYSCTL_CHILDREN(oid);
3646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3647 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3648 "I", "absolute id of the queue");
3649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3650 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3651 "I", "SGE context id of the queue");
3652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3653 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3656 children = SYSCTL_CHILDREN(oid);
3657 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3659 children = SYSCTL_CHILDREN(oid);
3661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3662 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3663 "I", "SGE context id of the freelist");
3664 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3665 &nm_rxq->fl_cidx, 0, "consumer index");
3666 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3667 &nm_rxq->fl_pidx, 0, "producer index");
3674 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3676 struct adapter *sc = vi->pi->adapter;
3678 if (vi->flags & VI_INIT_DONE)
3679 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3681 MPASS(nm_rxq->iq_cntxt_id == 0);
3683 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3685 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3692 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3693 struct sysctl_oid *oid)
3697 struct port_info *pi = vi->pi;
3698 struct adapter *sc = pi->adapter;
3699 struct netmap_adapter *na = NA(vi->ifp);
3701 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3703 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3704 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3705 &nm_txq->ba, (void **)&nm_txq->desc);
3709 nm_txq->pidx = nm_txq->cidx = 0;
3710 nm_txq->sidx = na->num_tx_desc;
3712 nm_txq->iqidx = iqidx;
3713 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3714 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
3715 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
3716 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3718 snprintf(name, sizeof(name), "%d", idx);
3719 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3720 NULL, "netmap tx queue");
3721 children = SYSCTL_CHILDREN(oid);
3723 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3724 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3725 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3726 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3728 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3729 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3736 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3738 struct adapter *sc = vi->pi->adapter;
3740 if (vi->flags & VI_INIT_DONE)
3741 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3743 MPASS(nm_txq->cntxt_id == 0);
3745 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3753 * Returns a reasonable automatic cidx flush threshold for a given queue size.
3756 qsize_to_fthresh(int qsize)
3760 while (!powerof2(qsize))
3762 fthresh = ilog2(qsize);
3763 if (fthresh > X_CIDXFLUSHTHRESH_128)
3764 fthresh = X_CIDXFLUSHTHRESH_128;
3770 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3773 struct fw_eq_ctrl_cmd c;
3774 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3776 bzero(&c, sizeof(c));
3778 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3779 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3780 V_FW_EQ_CTRL_CMD_VFN(0));
3781 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3782 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3783 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3784 c.physeqid_pkd = htobe32(0);
3785 c.fetchszm_to_iqid =
3786 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3787 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3788 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3790 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3791 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3792 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3793 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3794 c.eqaddr = htobe64(eq->ba);
3796 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3798 device_printf(sc->dev,
3799 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3802 eq->flags |= EQ_ALLOCATED;
3804 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3805 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3806 if (cntxt_id >= sc->sge.neq)
3807 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3808 cntxt_id, sc->sge.neq - 1);
3809 sc->sge.eqmap[cntxt_id] = eq;
3815 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3818 struct fw_eq_eth_cmd c;
3819 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3821 bzero(&c, sizeof(c));
3823 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3824 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3825 V_FW_EQ_ETH_CMD_VFN(0));
3826 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3827 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3828 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3829 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3830 c.fetchszm_to_iqid =
3831 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3832 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3833 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3834 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3835 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3836 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3837 c.eqaddr = htobe64(eq->ba);
3839 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3841 device_printf(vi->dev,
3842 "failed to create Ethernet egress queue: %d\n", rc);
3845 eq->flags |= EQ_ALLOCATED;
3847 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3848 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3849 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3850 if (cntxt_id >= sc->sge.neq)
3851 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3852 cntxt_id, sc->sge.neq - 1);
3853 sc->sge.eqmap[cntxt_id] = eq;
3858 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3860 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3863 struct fw_eq_ofld_cmd c;
3864 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3866 bzero(&c, sizeof(c));
3868 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3869 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3870 V_FW_EQ_OFLD_CMD_VFN(0));
3871 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3872 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3873 c.fetchszm_to_iqid =
3874 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3875 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3876 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3878 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3879 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3880 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
3881 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3882 c.eqaddr = htobe64(eq->ba);
3884 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3886 device_printf(vi->dev,
3887 "failed to create egress queue for TCP offload: %d\n", rc);
3890 eq->flags |= EQ_ALLOCATED;
3892 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3893 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3894 if (cntxt_id >= sc->sge.neq)
3895 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3896 cntxt_id, sc->sge.neq - 1);
3897 sc->sge.eqmap[cntxt_id] = eq;
3904 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3909 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3911 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3912 len = qsize * EQ_ESIZE;
3913 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3914 &eq->ba, (void **)&eq->desc);
3918 eq->pidx = eq->cidx = eq->dbidx = 0;
3919 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
3921 eq->doorbells = sc->doorbells;
3923 switch (eq->flags & EQ_TYPEMASK) {
3925 rc = ctrl_eq_alloc(sc, eq);
3929 rc = eth_eq_alloc(sc, vi, eq);
3932 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3934 rc = ofld_eq_alloc(sc, vi, eq);
3939 panic("%s: invalid eq type %d.", __func__,
3940 eq->flags & EQ_TYPEMASK);
3943 device_printf(sc->dev,
3944 "failed to allocate egress queue(%d): %d\n",
3945 eq->flags & EQ_TYPEMASK, rc);
3948 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3949 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3950 isset(&eq->doorbells, DOORBELL_WCWR)) {
3951 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3952 uint32_t mask = (1 << s_qpp) - 1;
3953 volatile uint8_t *udb;
3955 udb = sc->udbs_base + UDBS_DB_OFFSET;
3956 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3957 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3958 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3959 clrbit(&eq->doorbells, DOORBELL_WCWR);
3961 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3964 eq->udb = (volatile void *)udb;
3971 free_eq(struct adapter *sc, struct sge_eq *eq)
3975 if (eq->flags & EQ_ALLOCATED) {
3976 switch (eq->flags & EQ_TYPEMASK) {
3978 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3983 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3987 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
3989 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3995 panic("%s: invalid eq type %d.", __func__,
3996 eq->flags & EQ_TYPEMASK);
3999 device_printf(sc->dev,
4000 "failed to free egress queue (%d): %d\n",
4001 eq->flags & EQ_TYPEMASK, rc);
4004 eq->flags &= ~EQ_ALLOCATED;
4007 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4009 if (mtx_initialized(&eq->eq_lock))
4010 mtx_destroy(&eq->eq_lock);
4012 bzero(eq, sizeof(*eq));
4017 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4018 struct sysctl_oid *oid)
4021 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
4022 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4024 rc = alloc_eq(sc, vi, &wrq->eq);
4029 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4030 TAILQ_INIT(&wrq->incomplete_wrs);
4031 STAILQ_INIT(&wrq->wr_list);
4032 wrq->nwr_pending = 0;
4033 wrq->ndesc_needed = 0;
4035 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4036 &wrq->eq.ba, "bus address of descriptor ring");
4037 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4038 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
4039 "desc ring size in bytes");
4040 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4041 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
4042 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
4043 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
4045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
4046 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
4048 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4049 wrq->eq.sidx, "status page index");
4050 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4051 &wrq->tx_wrs_direct, "# of work requests (direct)");
4052 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4053 &wrq->tx_wrs_copied, "# of work requests (copied)");
4054 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4055 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4061 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4065 rc = free_eq(sc, &wrq->eq);
4069 bzero(wrq, sizeof(*wrq));
4074 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
4075 struct sysctl_oid *oid)
4078 struct port_info *pi = vi->pi;
4079 struct adapter *sc = pi->adapter;
4080 struct sge_eq *eq = &txq->eq;
4082 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4084 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
4087 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
4091 rc = alloc_eq(sc, vi, eq);
4093 mp_ring_free(txq->r);
4098 /* Can't fail after this point. */
4101 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4103 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4104 ("eq_base mismatch"));
4105 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4106 ("PF with non-zero eq_base"));
4108 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4110 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4111 if (sc->flags & IS_VF)
4112 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4113 V_TXPKT_INTF(pi->tx_chan));
4115 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
4116 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4117 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4119 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4122 snprintf(name, sizeof(name), "%d", idx);
4123 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
4125 children = SYSCTL_CHILDREN(oid);
4127 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4128 &eq->ba, "bus address of descriptor ring");
4129 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4130 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4131 "desc ring size in bytes");
4132 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4133 &eq->abs_id, 0, "absolute id of the queue");
4134 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4135 &eq->cntxt_id, 0, "SGE context id of the queue");
4136 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
4137 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
4139 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
4140 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
4142 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4143 eq->sidx, "status page index");
4145 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
4146 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
4147 "traffic class (-1 means none)");
4149 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4150 &txq->txcsum, "# of times hardware assisted with checksum");
4151 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
4152 CTLFLAG_RD, &txq->vlan_insertion,
4153 "# of times hardware inserted 802.1Q tag");
4154 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4155 &txq->tso_wrs, "# of TSO work requests");
4156 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4157 &txq->imm_wrs, "# of work requests with immediate data");
4158 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4159 &txq->sgl_wrs, "# of work requests with direct SGL");
4160 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4161 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4162 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
4163 CTLFLAG_RD, &txq->txpkts0_wrs,
4164 "# of txpkts (type 0) work requests");
4165 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
4166 CTLFLAG_RD, &txq->txpkts1_wrs,
4167 "# of txpkts (type 1) work requests");
4168 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
4169 CTLFLAG_RD, &txq->txpkts0_pkts,
4170 "# of frames tx'd using type0 txpkts work requests");
4171 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
4172 CTLFLAG_RD, &txq->txpkts1_pkts,
4173 "# of frames tx'd using type1 txpkts work requests");
4174 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4175 &txq->raw_wrs, "# of raw work requests (non-packets)");
4177 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
4178 CTLFLAG_RD, &txq->r->enqueues,
4179 "# of enqueues to the mp_ring for this queue");
4180 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
4181 CTLFLAG_RD, &txq->r->drops,
4182 "# of drops in the mp_ring for this queue");
4183 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
4184 CTLFLAG_RD, &txq->r->starts,
4185 "# of normal consumer starts in the mp_ring for this queue");
4186 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
4187 CTLFLAG_RD, &txq->r->stalls,
4188 "# of consumer stalls in the mp_ring for this queue");
4189 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
4190 CTLFLAG_RD, &txq->r->restarts,
4191 "# of consumer restarts in the mp_ring for this queue");
4192 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
4193 CTLFLAG_RD, &txq->r->abdications,
4194 "# of consumer abdications in the mp_ring for this queue");
4200 free_txq(struct vi_info *vi, struct sge_txq *txq)
4203 struct adapter *sc = vi->pi->adapter;
4204 struct sge_eq *eq = &txq->eq;
4206 rc = free_eq(sc, eq);
4210 sglist_free(txq->gl);
4211 free(txq->sdesc, M_CXGBE);
4212 mp_ring_free(txq->r);
4214 bzero(txq, sizeof(*txq));
4219 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4221 bus_addr_t *ba = arg;
4224 ("%s meant for single segment mappings only.", __func__));
4226 *ba = error ? 0 : segs->ds_addr;
4230 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4234 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
4238 v = fl->dbval | V_PIDX(n);
4240 *fl->udb = htole32(v);
4242 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4243 IDXINCR(fl->dbidx, n, fl->sidx);
4247 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4248 * recycled do not count towards this allocation budget.
4250 * Returns non-zero to indicate that this freelist should be added to the list
4251 * of starving freelists.
4254 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4257 struct fl_sdesc *sd;
4260 struct cluster_layout *cll;
4261 struct sw_zone_info *swz;
4262 struct cluster_metadata *clm;
4264 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4266 FL_LOCK_ASSERT_OWNED(fl);
4269 * We always stop at the beginning of the hardware descriptor that's just
4270 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4271 * which would mean an empty freelist to the chip.
4273 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4274 if (fl->pidx == max_pidx * 8)
4277 d = &fl->desc[fl->pidx];
4278 sd = &fl->sdesc[fl->pidx];
4279 cll = &fl->cll_def; /* default layout */
4280 swz = &sc->sge.sw_zone_info[cll->zidx];
4284 if (sd->cl != NULL) {
4286 if (sd->nmbuf == 0) {
4288 * Fast recycle without involving any atomics on
4289 * the cluster's metadata (if the cluster has
4290 * metadata). This happens when all frames
4291 * received in the cluster were small enough to
4292 * fit within a single mbuf each.
4294 fl->cl_fast_recycled++;
4296 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4298 MPASS(clm->refcount == 1);
4304 * Cluster is guaranteed to have metadata. Clusters
4305 * without metadata always take the fast recycle path
4306 * when they're recycled.
4308 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
4311 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4313 counter_u64_add(extfree_rels, 1);
4316 sd->cl = NULL; /* gave up my reference */
4318 MPASS(sd->cl == NULL);
4320 cl = uma_zalloc(swz->zone, M_NOWAIT);
4321 if (__predict_false(cl == NULL)) {
4322 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
4323 fl->cll_def.zidx == fl->cll_alt.zidx)
4326 /* fall back to the safe zone */
4328 swz = &sc->sge.sw_zone_info[cll->zidx];
4334 pa = pmap_kextract((vm_offset_t)cl);
4338 *d = htobe64(pa | cll->hwidx);
4339 clm = cl_metadata(sc, fl, cll, cl);
4351 if (__predict_false(++fl->pidx % 8 == 0)) {
4352 uint16_t pidx = fl->pidx / 8;
4354 if (__predict_false(pidx == fl->sidx)) {
4360 if (pidx == max_pidx)
4363 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4368 if (fl->pidx / 8 != fl->dbidx)
4371 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4375 * Attempt to refill all starving freelists.
4378 refill_sfl(void *arg)
4380 struct adapter *sc = arg;
4381 struct sge_fl *fl, *fl_temp;
4383 mtx_assert(&sc->sfl_lock, MA_OWNED);
4384 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4386 refill_fl(sc, fl, 64);
4387 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4388 TAILQ_REMOVE(&sc->sfl, fl, link);
4389 fl->flags &= ~FL_STARVING;
4394 if (!TAILQ_EMPTY(&sc->sfl))
4395 callout_schedule(&sc->sfl_callout, hz / 5);
4399 alloc_fl_sdesc(struct sge_fl *fl)
4402 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4409 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4411 struct fl_sdesc *sd;
4412 struct cluster_metadata *clm;
4413 struct cluster_layout *cll;
4417 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4422 clm = cl_metadata(sc, fl, cll, sd->cl);
4424 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4425 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4426 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4427 counter_u64_add(extfree_rels, 1);
4432 free(fl->sdesc, M_CXGBE);
4437 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4444 rc = sglist_append_mbuf(gl, m);
4445 if (__predict_false(rc != 0)) {
4446 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4447 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4450 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4451 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4452 mbuf_nsegs(m), gl->sg_nseg));
4453 KASSERT(gl->sg_nseg > 0 &&
4454 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4455 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4456 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4460 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4463 txpkt_len16(u_int nsegs, u_int tso)
4469 nsegs--; /* first segment is part of ulptx_sgl */
4470 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4471 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4473 n += sizeof(struct cpl_tx_pkt_lso_core);
4475 return (howmany(n, 16));
4479 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4483 txpkt_vm_len16(u_int nsegs, u_int tso)
4489 nsegs--; /* first segment is part of ulptx_sgl */
4490 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4491 sizeof(struct cpl_tx_pkt_core) +
4492 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4494 n += sizeof(struct cpl_tx_pkt_lso_core);
4496 return (howmany(n, 16));
4500 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4504 txpkts0_len16(u_int nsegs)
4510 nsegs--; /* first segment is part of ulptx_sgl */
4511 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4512 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4513 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4515 return (howmany(n, 16));
4519 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4527 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4529 return (howmany(n, 16));
4533 imm_payload(u_int ndesc)
4537 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4538 sizeof(struct cpl_tx_pkt_core);
4544 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4545 * software descriptor, and advance the pidx. It is guaranteed that enough
4546 * descriptors are available.
4548 * The return value is the # of hardware descriptors used.
4551 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4552 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4554 struct sge_eq *eq = &txq->eq;
4555 struct tx_sdesc *txsd;
4556 struct cpl_tx_pkt_core *cpl;
4557 uint32_t ctrl; /* used in many unrelated places */
4559 int csum_type, len16, ndesc, pktlen, nsegs;
4562 TXQ_LOCK_ASSERT_OWNED(txq);
4564 MPASS(available > 0 && available < eq->sidx);
4566 len16 = mbuf_len16(m0);
4567 nsegs = mbuf_nsegs(m0);
4568 pktlen = m0->m_pkthdr.len;
4569 ctrl = sizeof(struct cpl_tx_pkt_core);
4571 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4572 ndesc = howmany(len16, EQ_ESIZE / 16);
4573 MPASS(ndesc <= available);
4575 /* Firmware work request header */
4576 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4577 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4578 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4580 ctrl = V_FW_WR_LEN16(len16);
4581 wr->equiq_to_len16 = htobe32(ctrl);
4586 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4587 * vlantci is ignored unless the ethtype is 0x8100, so it's
4588 * simpler to always copy it rather than making it
4589 * conditional. Also, it seems that we do not have to set
4590 * vlantci or fake the ethtype when doing VLAN tag insertion.
4592 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4595 if (needs_tso(m0)) {
4596 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4598 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4599 m0->m_pkthdr.l4hlen > 0,
4600 ("%s: mbuf %p needs TSO but missing header lengths",
4603 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4604 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4605 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4606 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4607 ctrl |= V_LSO_ETHHDR_LEN(1);
4608 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4611 lso->lso_ctrl = htobe32(ctrl);
4612 lso->ipid_ofst = htobe16(0);
4613 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4614 lso->seqno_offset = htobe32(0);
4615 lso->len = htobe32(pktlen);
4617 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4618 csum_type = TX_CSUM_TCPIP6;
4620 csum_type = TX_CSUM_TCPIP;
4622 cpl = (void *)(lso + 1);
4626 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4627 csum_type = TX_CSUM_TCPIP;
4628 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4629 csum_type = TX_CSUM_UDPIP;
4630 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4631 csum_type = TX_CSUM_TCPIP6;
4632 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4633 csum_type = TX_CSUM_UDPIP6;
4635 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4637 * XXX: The firmware appears to stomp on the
4638 * fragment/flags field of the IP header when
4639 * using TX_CSUM_IP. Fall back to doing
4640 * software checksums.
4648 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4649 offsetof(struct ip, ip_sum));
4650 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4651 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4652 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4656 cpl = (void *)(wr + 1);
4659 /* Checksum offload */
4661 if (needs_l3_csum(m0) == 0)
4662 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4663 if (csum_type >= 0) {
4664 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4665 ("%s: mbuf %p needs checksum offload but missing header lengths",
4668 if (chip_id(sc) <= CHELSIO_T5) {
4669 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4672 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4675 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4676 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4678 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4679 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4680 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4681 txq->txcsum++; /* some hardware assistance provided */
4683 /* VLAN tag insertion */
4684 if (needs_vlan_insertion(m0)) {
4685 ctrl1 |= F_TXPKT_VLAN_VLD |
4686 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4687 txq->vlan_insertion++;
4691 cpl->ctrl0 = txq->cpl_ctrl0;
4693 cpl->len = htobe16(pktlen);
4694 cpl->ctrl1 = htobe64(ctrl1);
4697 dst = (void *)(cpl + 1);
4700 * A packet using TSO will use up an entire descriptor for the
4701 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4702 * If this descriptor is the last descriptor in the ring, wrap
4703 * around to the front of the ring explicitly for the start of
4706 if (dst == (void *)&eq->desc[eq->sidx]) {
4707 dst = (void *)&eq->desc[0];
4708 write_gl_to_txd(txq, m0, &dst, 0);
4710 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4715 txsd = &txq->sdesc[eq->pidx];
4717 txsd->desc_used = ndesc;
4723 * Write a raw WR to the hardware descriptors, update the software
4724 * descriptor, and advance the pidx. It is guaranteed that enough
4725 * descriptors are available.
4727 * The return value is the # of hardware descriptors used.
4730 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
4732 struct sge_eq *eq = &txq->eq;
4733 struct tx_sdesc *txsd;
4738 len16 = mbuf_len16(m0);
4739 ndesc = howmany(len16, EQ_ESIZE / 16);
4740 MPASS(ndesc <= available);
4743 for (m = m0; m != NULL; m = m->m_next)
4744 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4748 txsd = &txq->sdesc[eq->pidx];
4750 txsd->desc_used = ndesc;
4756 * Write a txpkt WR for this packet to the hardware descriptors, update the
4757 * software descriptor, and advance the pidx. It is guaranteed that enough
4758 * descriptors are available.
4760 * The return value is the # of hardware descriptors used.
4763 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4764 struct mbuf *m0, u_int available)
4766 struct sge_eq *eq = &txq->eq;
4767 struct tx_sdesc *txsd;
4768 struct cpl_tx_pkt_core *cpl;
4769 uint32_t ctrl; /* used in many unrelated places */
4771 int len16, ndesc, pktlen, nsegs;
4774 TXQ_LOCK_ASSERT_OWNED(txq);
4776 MPASS(available > 0 && available < eq->sidx);
4778 len16 = mbuf_len16(m0);
4779 nsegs = mbuf_nsegs(m0);
4780 pktlen = m0->m_pkthdr.len;
4781 ctrl = sizeof(struct cpl_tx_pkt_core);
4783 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4784 else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
4786 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4788 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4789 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4792 ndesc = howmany(len16, EQ_ESIZE / 16);
4793 MPASS(ndesc <= available);
4795 /* Firmware work request header */
4796 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4797 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4798 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4800 ctrl = V_FW_WR_LEN16(len16);
4801 wr->equiq_to_len16 = htobe32(ctrl);
4804 if (needs_tso(m0)) {
4805 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4807 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4808 m0->m_pkthdr.l4hlen > 0,
4809 ("%s: mbuf %p needs TSO but missing header lengths",
4812 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4813 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4814 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4815 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4816 ctrl |= V_LSO_ETHHDR_LEN(1);
4817 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4820 lso->lso_ctrl = htobe32(ctrl);
4821 lso->ipid_ofst = htobe16(0);
4822 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4823 lso->seqno_offset = htobe32(0);
4824 lso->len = htobe32(pktlen);
4826 cpl = (void *)(lso + 1);
4830 cpl = (void *)(wr + 1);
4832 /* Checksum offload */
4834 if (needs_l3_csum(m0) == 0)
4835 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4836 if (needs_l4_csum(m0) == 0)
4837 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4838 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4839 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4840 txq->txcsum++; /* some hardware assistance provided */
4842 /* VLAN tag insertion */
4843 if (needs_vlan_insertion(m0)) {
4844 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4845 txq->vlan_insertion++;
4849 cpl->ctrl0 = txq->cpl_ctrl0;
4851 cpl->len = htobe16(pktlen);
4852 cpl->ctrl1 = htobe64(ctrl1);
4855 dst = (void *)(cpl + 1);
4858 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4863 for (m = m0; m != NULL; m = m->m_next) {
4864 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4870 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4877 txsd = &txq->sdesc[eq->pidx];
4879 txsd->desc_used = ndesc;
4885 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4887 u_int needed, nsegs1, nsegs2, l1, l2;
4889 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4892 nsegs1 = mbuf_nsegs(m);
4893 nsegs2 = mbuf_nsegs(n);
4894 if (nsegs1 + nsegs2 == 2) {
4896 l1 = l2 = txpkts1_len16();
4899 l1 = txpkts0_len16(nsegs1);
4900 l2 = txpkts0_len16(nsegs2);
4902 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4903 needed = howmany(txp->len16, EQ_ESIZE / 16);
4904 if (needed > SGE_MAX_WR_NDESC || needed > available)
4907 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4908 if (txp->plen > 65535)
4912 set_mbuf_len16(m, l1);
4913 set_mbuf_len16(n, l2);
4919 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4921 u_int plen, len16, needed, nsegs;
4923 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4925 if (cannot_use_txpkts(m))
4928 nsegs = mbuf_nsegs(m);
4929 if (txp->wr_type == 1 && nsegs != 1)
4932 plen = txp->plen + m->m_pkthdr.len;
4936 if (txp->wr_type == 0)
4937 len16 = txpkts0_len16(nsegs);
4939 len16 = txpkts1_len16();
4940 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4941 if (needed > SGE_MAX_WR_NDESC || needed > available)
4946 txp->len16 += len16;
4947 set_mbuf_len16(m, len16);
4953 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4954 * the software descriptor, and advance the pidx. It is guaranteed that enough
4955 * descriptors are available.
4957 * The return value is the # of hardware descriptors used.
4960 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4961 struct mbuf *m0, const struct txpkts *txp, u_int available)
4963 struct sge_eq *eq = &txq->eq;
4964 struct tx_sdesc *txsd;
4965 struct cpl_tx_pkt_core *cpl;
4968 int ndesc, checkwrap;
4972 TXQ_LOCK_ASSERT_OWNED(txq);
4973 MPASS(txp->npkt > 0);
4974 MPASS(txp->plen < 65536);
4976 MPASS(m0->m_nextpkt != NULL);
4977 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4978 MPASS(available > 0 && available < eq->sidx);
4980 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4981 MPASS(ndesc <= available);
4983 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4984 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4985 ctrl = V_FW_WR_LEN16(txp->len16);
4986 wr->equiq_to_len16 = htobe32(ctrl);
4987 wr->plen = htobe16(txp->plen);
4988 wr->npkt = txp->npkt;
4990 wr->type = txp->wr_type;
4994 * At this point we are 16B into a hardware descriptor. If checkwrap is
4995 * set then we know the WR is going to wrap around somewhere. We'll
4996 * check for that at appropriate points.
4998 checkwrap = eq->sidx - ndesc < eq->pidx;
4999 for (m = m0; m != NULL; m = m->m_nextpkt) {
5000 if (txp->wr_type == 0) {
5001 struct ulp_txpkt *ulpmc;
5002 struct ulptx_idata *ulpsc;
5004 /* ULP master command */
5006 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5007 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5008 ulpmc->len = htobe32(mbuf_len16(m));
5010 /* ULP subcommand */
5011 ulpsc = (void *)(ulpmc + 1);
5012 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5014 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5016 cpl = (void *)(ulpsc + 1);
5018 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5019 cpl = (void *)&eq->desc[0];
5024 /* Checksum offload */
5026 if (needs_l3_csum(m) == 0)
5027 ctrl1 |= F_TXPKT_IPCSUM_DIS;
5028 if (needs_l4_csum(m) == 0)
5029 ctrl1 |= F_TXPKT_L4CSUM_DIS;
5030 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
5031 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
5032 txq->txcsum++; /* some hardware assistance provided */
5034 /* VLAN tag insertion */
5035 if (needs_vlan_insertion(m)) {
5036 ctrl1 |= F_TXPKT_VLAN_VLD |
5037 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5038 txq->vlan_insertion++;
5042 cpl->ctrl0 = txq->cpl_ctrl0;
5044 cpl->len = htobe16(m->m_pkthdr.len);
5045 cpl->ctrl1 = htobe64(ctrl1);
5049 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5050 flitp = (void *)&eq->desc[0];
5052 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5056 if (txp->wr_type == 0) {
5057 txq->txpkts0_pkts += txp->npkt;
5060 txq->txpkts1_pkts += txp->npkt;
5064 txsd = &txq->sdesc[eq->pidx];
5066 txsd->desc_used = ndesc;
5072 * If the SGL ends on an address that is not 16 byte aligned, this function will
5073 * add a 0 filled flit at the end.
5076 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5078 struct sge_eq *eq = &txq->eq;
5079 struct sglist *gl = txq->gl;
5080 struct sglist_seg *seg;
5081 __be64 *flitp, *wrap;
5082 struct ulptx_sgl *usgl;
5083 int i, nflits, nsegs;
5085 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5086 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5087 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5088 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5091 nsegs = gl->sg_nseg;
5094 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5095 flitp = (__be64 *)(*to);
5096 wrap = (__be64 *)(&eq->desc[eq->sidx]);
5097 seg = &gl->sg_segs[0];
5098 usgl = (void *)flitp;
5101 * We start at a 16 byte boundary somewhere inside the tx descriptor
5102 * ring, so we're at least 16 bytes away from the status page. There is
5103 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5106 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5107 V_ULPTX_NSGE(nsegs));
5108 usgl->len0 = htobe32(seg->ss_len);
5109 usgl->addr0 = htobe64(seg->ss_paddr);
5112 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5114 /* Won't wrap around at all */
5116 for (i = 0; i < nsegs - 1; i++, seg++) {
5117 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5118 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5121 usgl->sge[i / 2].len[1] = htobe32(0);
5125 /* Will wrap somewhere in the rest of the SGL */
5127 /* 2 flits already written, write the rest flit by flit */
5128 flitp = (void *)(usgl + 1);
5129 for (i = 0; i < nflits - 2; i++) {
5131 flitp = (void *)eq->desc;
5132 *flitp++ = get_flit(seg, nsegs - 1, i);
5137 MPASS(((uintptr_t)flitp) & 0xf);
5141 MPASS((((uintptr_t)flitp) & 0xf) == 0);
5142 if (__predict_false(flitp == wrap))
5143 *to = (void *)eq->desc;
5145 *to = (void *)flitp;
5149 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
5152 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5153 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5155 if (__predict_true((uintptr_t)(*to) + len <=
5156 (uintptr_t)&eq->desc[eq->sidx])) {
5157 bcopy(from, *to, len);
5160 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
5162 bcopy(from, *to, portion);
5164 portion = len - portion; /* remaining */
5165 bcopy(from, (void *)eq->desc, portion);
5166 (*to) = (caddr_t)eq->desc + portion;
5171 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
5179 clrbit(&db, DOORBELL_WCWR);
5182 switch (ffs(db) - 1) {
5184 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5187 case DOORBELL_WCWR: {
5188 volatile uint64_t *dst, *src;
5192 * Queues whose 128B doorbell segment fits in the page do not
5193 * use relative qid (udb_qid is always 0). Only queues with
5194 * doorbell segments can do WCWR.
5196 KASSERT(eq->udb_qid == 0 && n == 1,
5197 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
5198 __func__, eq->doorbells, n, eq->dbidx, eq));
5200 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
5203 src = (void *)&eq->desc[i];
5204 while (src != (void *)&eq->desc[i + 1])
5210 case DOORBELL_UDBWC:
5211 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5216 t4_write_reg(sc, sc->sge_kdoorbell_reg,
5217 V_QID(eq->cntxt_id) | V_PIDX(n));
5221 IDXINCR(eq->dbidx, n, eq->sidx);
5225 reclaimable_tx_desc(struct sge_eq *eq)
5229 hw_cidx = read_hw_cidx(eq);
5230 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
5234 total_available_tx_desc(struct sge_eq *eq)
5236 uint16_t hw_cidx, pidx;
5238 hw_cidx = read_hw_cidx(eq);
5241 if (pidx == hw_cidx)
5242 return (eq->sidx - 1);
5244 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
5247 static inline uint16_t
5248 read_hw_cidx(struct sge_eq *eq)
5250 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5251 uint16_t cidx = spg->cidx; /* stable snapshot */
5253 return (be16toh(cidx));
5257 * Reclaim 'n' descriptors approximately.
5260 reclaim_tx_descs(struct sge_txq *txq, u_int n)
5262 struct tx_sdesc *txsd;
5263 struct sge_eq *eq = &txq->eq;
5264 u_int can_reclaim, reclaimed;
5266 TXQ_LOCK_ASSERT_OWNED(txq);
5270 can_reclaim = reclaimable_tx_desc(eq);
5271 while (can_reclaim && reclaimed < n) {
5273 struct mbuf *m, *nextpkt;
5275 txsd = &txq->sdesc[eq->cidx];
5276 ndesc = txsd->desc_used;
5278 /* Firmware doesn't return "partial" credits. */
5279 KASSERT(can_reclaim >= ndesc,
5280 ("%s: unexpected number of credits: %d, %d",
5281 __func__, can_reclaim, ndesc));
5283 ("%s: descriptor with no credits: cidx %d",
5284 __func__, eq->cidx));
5286 for (m = txsd->m; m != NULL; m = nextpkt) {
5287 nextpkt = m->m_nextpkt;
5288 m->m_nextpkt = NULL;
5292 can_reclaim -= ndesc;
5293 IDXINCR(eq->cidx, ndesc, eq->sidx);
5300 tx_reclaim(void *arg, int n)
5302 struct sge_txq *txq = arg;
5303 struct sge_eq *eq = &txq->eq;
5306 if (TXQ_TRYLOCK(txq) == 0)
5308 n = reclaim_tx_descs(txq, 32);
5309 if (eq->cidx == eq->pidx)
5310 eq->equeqidx = eq->pidx;
5316 get_flit(struct sglist_seg *segs, int nsegs, int idx)
5318 int i = (idx / 3) * 2;
5324 rc = (uint64_t)segs[i].ss_len << 32;
5326 rc |= (uint64_t)(segs[i + 1].ss_len);
5328 return (htobe64(rc));
5331 return (htobe64(segs[i].ss_paddr));
5333 return (htobe64(segs[i + 1].ss_paddr));
5340 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
5342 int8_t zidx, hwidx, idx;
5343 uint16_t region1, region3;
5344 int spare, spare_needed, n;
5345 struct sw_zone_info *swz;
5346 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
5349 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
5350 * large enough for the max payload and cluster metadata. Otherwise
5351 * settle for the largest bufsize that leaves enough room in the cluster
5354 * Without buffer packing: Look for the smallest zone which has a
5355 * bufsize large enough for the max payload. Settle for the largest
5356 * bufsize available if there's nothing big enough for max payload.
5358 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
5359 swz = &sc->sge.sw_zone_info[0];
5361 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
5362 if (swz->size > largest_rx_cluster) {
5363 if (__predict_true(hwidx != -1))
5367 * This is a misconfiguration. largest_rx_cluster is
5368 * preventing us from finding a refill source. See
5369 * dev.t5nex.<n>.buffer_sizes to figure out why.
5371 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
5372 " refill source for fl %p (dma %u). Ignored.\n",
5373 largest_rx_cluster, fl, maxp);
5375 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
5376 hwb = &hwb_list[idx];
5377 spare = swz->size - hwb->size;
5378 if (spare < spare_needed)
5381 hwidx = idx; /* best option so far */
5382 if (hwb->size >= maxp) {
5384 if ((fl->flags & FL_BUF_PACKING) == 0)
5385 goto done; /* stop looking (not packing) */
5387 if (swz->size >= safest_rx_cluster)
5388 goto done; /* stop looking (packing) */
5390 break; /* keep looking, next zone */
5394 /* A usable hwidx has been located. */
5396 hwb = &hwb_list[hwidx];
5398 swz = &sc->sge.sw_zone_info[zidx];
5400 region3 = swz->size - hwb->size;
5403 * Stay within this zone and see if there is a better match when mbuf
5404 * inlining is allowed. Remember that the hwidx's are sorted in
5405 * decreasing order of size (so in increasing order of spare area).
5407 for (idx = hwidx; idx != -1; idx = hwb->next) {
5408 hwb = &hwb_list[idx];
5409 spare = swz->size - hwb->size;
5411 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
5415 * Do not inline mbufs if doing so would violate the pad/pack
5416 * boundary alignment requirement.
5418 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
5420 if (fl->flags & FL_BUF_PACKING &&
5421 (MSIZE % sc->params.sge.pack_boundary) != 0)
5424 if (spare < CL_METADATA_SIZE + MSIZE)
5426 n = (spare - CL_METADATA_SIZE) / MSIZE;
5427 if (n > howmany(hwb->size, maxp))
5431 if (fl->flags & FL_BUF_PACKING) {
5432 region1 = n * MSIZE;
5433 region3 = spare - region1;
5436 region3 = spare - region1;
5441 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
5442 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
5443 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
5444 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
5445 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
5446 sc->sge.sw_zone_info[zidx].size,
5447 ("%s: bad buffer layout for fl %p, maxp %d. "
5448 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5449 sc->sge.sw_zone_info[zidx].size, region1,
5450 sc->sge.hw_buf_info[hwidx].size, region3));
5451 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
5452 KASSERT(region3 >= CL_METADATA_SIZE,
5453 ("%s: no room for metadata. fl %p, maxp %d; "
5454 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5455 sc->sge.sw_zone_info[zidx].size, region1,
5456 sc->sge.hw_buf_info[hwidx].size, region3));
5457 KASSERT(region1 % MSIZE == 0,
5458 ("%s: bad mbuf region for fl %p, maxp %d. "
5459 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5460 sc->sge.sw_zone_info[zidx].size, region1,
5461 sc->sge.hw_buf_info[hwidx].size, region3));
5464 fl->cll_def.zidx = zidx;
5465 fl->cll_def.hwidx = hwidx;
5466 fl->cll_def.region1 = region1;
5467 fl->cll_def.region3 = region3;
5471 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
5473 struct sge *s = &sc->sge;
5474 struct hw_buf_info *hwb;
5475 struct sw_zone_info *swz;
5479 if (fl->flags & FL_BUF_PACKING)
5480 hwidx = s->safe_hwidx2; /* with room for metadata */
5481 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
5482 hwidx = s->safe_hwidx2;
5483 hwb = &s->hw_buf_info[hwidx];
5484 swz = &s->sw_zone_info[hwb->zidx];
5485 spare = swz->size - hwb->size;
5487 /* no good if there isn't room for an mbuf as well */
5488 if (spare < CL_METADATA_SIZE + MSIZE)
5489 hwidx = s->safe_hwidx1;
5491 hwidx = s->safe_hwidx1;
5494 /* No fallback source */
5495 fl->cll_alt.hwidx = -1;
5496 fl->cll_alt.zidx = -1;
5501 hwb = &s->hw_buf_info[hwidx];
5502 swz = &s->sw_zone_info[hwb->zidx];
5503 spare = swz->size - hwb->size;
5504 fl->cll_alt.hwidx = hwidx;
5505 fl->cll_alt.zidx = hwb->zidx;
5506 if (allow_mbufs_in_cluster &&
5507 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5508 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5510 fl->cll_alt.region1 = 0;
5511 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5515 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5517 mtx_lock(&sc->sfl_lock);
5519 if ((fl->flags & FL_DOOMED) == 0) {
5520 fl->flags |= FL_STARVING;
5521 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5522 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5525 mtx_unlock(&sc->sfl_lock);
5529 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5531 struct sge_wrq *wrq = (void *)eq;
5533 atomic_readandclear_int(&eq->equiq);
5534 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5538 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5540 struct sge_txq *txq = (void *)eq;
5542 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5544 atomic_readandclear_int(&eq->equiq);
5545 mp_ring_check_drainage(txq->r, 0);
5546 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5550 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5553 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5554 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5555 struct adapter *sc = iq->adapter;
5556 struct sge *s = &sc->sge;
5558 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5559 &handle_wrq_egr_update, &handle_eth_egr_update,
5560 &handle_wrq_egr_update};
5562 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5565 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5566 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5571 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5572 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5573 offsetof(struct cpl_fw6_msg, data));
5576 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5578 struct adapter *sc = iq->adapter;
5579 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5581 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5584 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5585 const struct rss_header *rss2;
5587 rss2 = (const struct rss_header *)&cpl->data[0];
5588 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5591 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5595 * t4_handle_wrerr_rpl - process a FW work request error message
5596 * @adap: the adapter
5597 * @rpl: start of the FW message
5600 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5602 u8 opcode = *(const u8 *)rpl;
5603 const struct fw_error_cmd *e = (const void *)rpl;
5606 if (opcode != FW_ERROR_CMD) {
5608 "%s: Received WRERR_RPL message with opcode %#x\n",
5609 device_get_nameunit(adap->dev), opcode);
5612 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5613 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5615 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5616 case FW_ERROR_TYPE_EXCEPTION:
5617 log(LOG_ERR, "exception info:\n");
5618 for (i = 0; i < nitems(e->u.exception.info); i++)
5619 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5620 be32toh(e->u.exception.info[i]));
5623 case FW_ERROR_TYPE_HWMODULE:
5624 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5625 be32toh(e->u.hwmodule.regaddr),
5626 be32toh(e->u.hwmodule.regval));
5628 case FW_ERROR_TYPE_WR:
5629 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5630 be16toh(e->u.wr.cidx),
5631 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5632 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5633 be32toh(e->u.wr.eqid));
5634 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5635 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5639 case FW_ERROR_TYPE_ACL:
5640 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5641 be16toh(e->u.acl.cidx),
5642 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5643 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5644 be32toh(e->u.acl.eqid),
5645 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5647 for (i = 0; i < nitems(e->u.acl.val); i++)
5648 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5652 log(LOG_ERR, "type %#x\n",
5653 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5660 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5662 uint16_t *id = arg1;
5665 return sysctl_handle_int(oidp, &i, 0, req);
5669 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5671 struct sge *s = arg1;
5672 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5673 struct sw_zone_info *swz = &s->sw_zone_info[0];
5678 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5679 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5680 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5685 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5689 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5696 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5699 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
5705 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
5706 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
5707 if (__predict_false(nsegs == 0))
5710 nsegs--; /* first segment is part of ulptx_sgl */
5711 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5713 n += sizeof(struct cpl_tx_pkt_lso_core);
5716 return (howmany(n, 16));
5719 #define ETID_FLOWC_NPARAMS 6
5720 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
5721 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
5722 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
5725 send_etid_flowc_wr(struct cxgbe_snd_tag *cst, struct port_info *pi,
5728 struct wrq_cookie cookie;
5729 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
5730 struct fw_flowc_wr *flowc;
5732 mtx_assert(&cst->lock, MA_OWNED);
5733 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
5736 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie);
5737 if (__predict_false(flowc == NULL))
5740 bzero(flowc, ETID_FLOWC_LEN);
5741 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5742 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
5743 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
5744 V_FW_WR_FLOWID(cst->etid));
5745 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
5746 flowc->mnemval[0].val = htobe32(pfvf);
5747 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
5748 flowc->mnemval[1].val = htobe32(pi->tx_chan);
5749 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
5750 flowc->mnemval[2].val = htobe32(pi->tx_chan);
5751 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
5752 flowc->mnemval[3].val = htobe32(cst->iqid);
5753 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
5754 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
5755 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
5756 flowc->mnemval[5].val = htobe32(cst->schedcl);
5758 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5760 cst->flags &= ~EO_FLOWC_PENDING;
5761 cst->flags |= EO_FLOWC_RPL_PENDING;
5762 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
5763 cst->tx_credits -= ETID_FLOWC_LEN16;
5768 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
5771 send_etid_flush_wr(struct cxgbe_snd_tag *cst)
5773 struct fw_flowc_wr *flowc;
5774 struct wrq_cookie cookie;
5776 mtx_assert(&cst->lock, MA_OWNED);
5778 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie);
5779 if (__predict_false(flowc == NULL))
5780 CXGBE_UNIMPLEMENTED(__func__);
5782 bzero(flowc, ETID_FLUSH_LEN16 * 16);
5783 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
5784 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
5785 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
5786 V_FW_WR_FLOWID(cst->etid));
5788 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
5790 cst->flags |= EO_FLUSH_RPL_PENDING;
5791 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
5792 cst->tx_credits -= ETID_FLUSH_LEN16;
5797 write_ethofld_wr(struct cxgbe_snd_tag *cst, struct fw_eth_tx_eo_wr *wr,
5798 struct mbuf *m0, int compl)
5800 struct cpl_tx_pkt_core *cpl;
5802 uint32_t ctrl; /* used in many unrelated places */
5803 int len16, pktlen, nsegs, immhdrs;
5806 struct ulptx_sgl *usgl;
5808 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
5810 mtx_assert(&cst->lock, MA_OWNED);
5812 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5813 m0->m_pkthdr.l4hlen > 0,
5814 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
5816 len16 = mbuf_eo_len16(m0);
5817 nsegs = mbuf_eo_nsegs(m0);
5818 pktlen = m0->m_pkthdr.len;
5819 ctrl = sizeof(struct cpl_tx_pkt_core);
5821 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5822 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
5825 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
5826 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
5827 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
5828 V_FW_WR_FLOWID(cst->etid));
5830 if (needs_udp_csum(m0)) {
5831 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
5832 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
5833 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5834 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
5835 wr->u.udpseg.rtplen = 0;
5836 wr->u.udpseg.r4 = 0;
5837 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
5838 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
5839 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
5840 cpl = (void *)(wr + 1);
5842 MPASS(needs_tcp_csum(m0));
5843 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
5844 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
5845 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
5846 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
5847 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
5848 wr->u.tcpseg.r4 = 0;
5849 wr->u.tcpseg.r5 = 0;
5850 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
5852 if (needs_tso(m0)) {
5853 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
5855 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
5857 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5858 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5859 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5860 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5861 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
5862 ctrl |= V_LSO_ETHHDR_LEN(1);
5863 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5865 lso->lso_ctrl = htobe32(ctrl);
5866 lso->ipid_ofst = htobe16(0);
5867 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5868 lso->seqno_offset = htobe32(0);
5869 lso->len = htobe32(pktlen);
5871 cpl = (void *)(lso + 1);
5873 wr->u.tcpseg.mss = htobe16(0xffff);
5874 cpl = (void *)(wr + 1);
5878 /* Checksum offload must be requested for ethofld. */
5880 MPASS(needs_l4_csum(m0));
5882 /* VLAN tag insertion */
5883 if (needs_vlan_insertion(m0)) {
5884 ctrl1 |= F_TXPKT_VLAN_VLD |
5885 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5889 cpl->ctrl0 = cst->ctrl0;
5891 cpl->len = htobe16(pktlen);
5892 cpl->ctrl1 = htobe64(ctrl1);
5894 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
5895 p = (uintptr_t)(cpl + 1);
5896 m_copydata(m0, 0, immhdrs, (void *)p);
5899 dst = (void *)(cpl + 1);
5903 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
5905 pad = 16 - (immhdrs & 0xf);
5906 bzero((void *)p, pad);
5908 usgl = (void *)(p + pad);
5909 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5910 V_ULPTX_NSGE(nsegs));
5912 sglist_init(&sg, nitems(segs), segs);
5913 for (; m0 != NULL; m0 = m0->m_next) {
5914 if (__predict_false(m0->m_len == 0))
5916 if (immhdrs >= m0->m_len) {
5917 immhdrs -= m0->m_len;
5921 sglist_append(&sg, mtod(m0, char *) + immhdrs,
5922 m0->m_len - immhdrs);
5925 MPASS(sg.sg_nseg == nsegs);
5928 * Zero pad last 8B in case the WR doesn't end on a 16B
5931 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
5933 usgl->len0 = htobe32(segs[0].ss_len);
5934 usgl->addr0 = htobe64(segs[0].ss_paddr);
5935 for (i = 0; i < nsegs - 1; i++) {
5936 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
5937 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
5940 usgl->sge[i / 2].len[1] = htobe32(0);
5946 ethofld_tx(struct cxgbe_snd_tag *cst)
5949 struct wrq_cookie cookie;
5950 int next_credits, compl;
5951 struct fw_eth_tx_eo_wr *wr;
5953 mtx_assert(&cst->lock, MA_OWNED);
5955 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
5958 /* How many len16 credits do we need to send this mbuf. */
5959 next_credits = mbuf_eo_len16(m);
5960 MPASS(next_credits > 0);
5961 if (next_credits > cst->tx_credits) {
5963 * Tx will make progress eventually because there is at
5964 * least one outstanding fw4_ack that will return
5965 * credits and kick the tx.
5967 MPASS(cst->ncompl > 0);
5970 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie);
5971 if (__predict_false(wr == NULL)) {
5972 /* XXX: wishful thinking, not a real assertion. */
5973 MPASS(cst->ncompl > 0);
5976 cst->tx_credits -= next_credits;
5977 cst->tx_nocompl += next_credits;
5978 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
5979 ETHER_BPF_MTAP(cst->com.ifp, m);
5980 write_ethofld_wr(cst, wr, m, compl);
5981 commit_wrq_wr(cst->eo_txq, wr, &cookie);
5984 cst->tx_nocompl = 0;
5986 (void) mbufq_dequeue(&cst->pending_tx);
5989 * Drop the mbuf's reference on the tag now rather
5990 * than waiting until m_freem(). This ensures that
5991 * cxgbe_snd_tag_free gets called when the inp drops
5992 * its reference on the tag and there are no more
5993 * mbufs in the pending_tx queue and can flush any
5994 * pending requests. Otherwise if the last mbuf
5995 * doesn't request a completion the etid will never be
5998 m->m_pkthdr.snd_tag = NULL;
5999 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6000 m_snd_tag_rele(&cst->com);
6002 mbufq_enqueue(&cst->pending_fwack, m);
6007 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
6009 struct cxgbe_snd_tag *cst;
6012 MPASS(m0->m_nextpkt == NULL);
6013 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6014 MPASS(m0->m_pkthdr.snd_tag != NULL);
6015 cst = mst_to_cst(m0->m_pkthdr.snd_tag);
6017 mtx_lock(&cst->lock);
6018 MPASS(cst->flags & EO_SND_TAG_REF);
6020 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6021 struct vi_info *vi = ifp->if_softc;
6022 struct port_info *pi = vi->pi;
6023 struct adapter *sc = pi->adapter;
6024 const uint32_t rss_mask = vi->rss_size - 1;
6027 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6028 if (M_HASHTYPE_ISHASH(m0))
6029 rss_hash = m0->m_pkthdr.flowid;
6031 rss_hash = arc4random();
6032 /* We assume RSS hashing */
6033 cst->iqid = vi->rss[rss_hash & rss_mask];
6034 cst->eo_txq += rss_hash % vi->nofldtxq;
6035 rc = send_etid_flowc_wr(cst, pi, vi);
6040 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6045 mbufq_enqueue(&cst->pending_tx, m0);
6046 cst->plen += m0->m_pkthdr.len;
6049 * Hold an extra reference on the tag while generating work
6050 * requests to ensure that we don't try to free the tag during
6051 * ethofld_tx() in case we are sending the final mbuf after
6052 * the inp was freed.
6054 m_snd_tag_ref(&cst->com);
6056 mtx_unlock(&cst->lock);
6057 m_snd_tag_rele(&cst->com);
6061 mtx_unlock(&cst->lock);
6062 if (__predict_false(rc != 0))
6068 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6070 struct adapter *sc = iq->adapter;
6071 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6073 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6074 struct cxgbe_snd_tag *cst;
6075 uint8_t credits = cpl->credits;
6077 cst = lookup_etid(sc, etid);
6078 mtx_lock(&cst->lock);
6079 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6080 MPASS(credits >= ETID_FLOWC_LEN16);
6081 credits -= ETID_FLOWC_LEN16;
6082 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6085 KASSERT(cst->ncompl > 0,
6086 ("%s: etid %u (%p) wasn't expecting completion.",
6087 __func__, etid, cst));
6090 while (credits > 0) {
6091 m = mbufq_dequeue(&cst->pending_fwack);
6092 if (__predict_false(m == NULL)) {
6094 * The remaining credits are for the final flush that
6095 * was issued when the tag was freed by the kernel.
6098 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6099 EO_FLUSH_RPL_PENDING);
6100 MPASS(credits == ETID_FLUSH_LEN16);
6101 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6102 MPASS(cst->ncompl == 0);
6104 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6105 cst->tx_credits += cpl->credits;
6106 cxgbe_snd_tag_free_locked(cst);
6107 return (0); /* cst is gone. */
6110 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6112 KASSERT(credits >= mbuf_eo_len16(m),
6113 ("%s: too few credits (%u, %u, %u)", __func__,
6114 cpl->credits, credits, mbuf_eo_len16(m)));
6115 credits -= mbuf_eo_len16(m);
6116 cst->plen -= m->m_pkthdr.len;
6120 cst->tx_credits += cpl->credits;
6121 MPASS(cst->tx_credits <= cst->tx_total);
6123 if (cst->flags & EO_SND_TAG_REF) {
6125 * As with ethofld_transmit(), hold an extra reference
6126 * so that the tag is stable across ethold_tx().
6128 m_snd_tag_ref(&cst->com);
6129 m = mbufq_first(&cst->pending_tx);
6130 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6132 mtx_unlock(&cst->lock);
6133 m_snd_tag_rele(&cst->com);
6136 * There shouldn't be any pending packets if the tag
6137 * was freed by the kernel since any pending packet
6138 * should hold a reference to the tag.
6140 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6141 mtx_unlock(&cst->lock);