2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sglist.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/in_cksum.h>
57 #include <machine/md_var.h>
61 #include <machine/bus.h>
62 #include <sys/selinfo.h>
63 #include <net/if_var.h>
64 #include <net/netmap.h>
65 #include <dev/netmap/netmap_kern.h>
68 #include "common/common.h"
69 #include "common/t4_regs.h"
70 #include "common/t4_regs_values.h"
71 #include "common/t4_msg.h"
73 #include "t4_mp_ring.h"
75 #ifdef T4_PKT_TIMESTAMP
76 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
78 #define RX_COPY_THRESHOLD MINCLSIZE
82 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
83 * 0-7 are valid values.
85 static int fl_pktshift = 2;
86 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
89 * Pad ethernet payload up to this boundary.
90 * -1: driver should figure out a good value.
92 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
95 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
99 * -1: driver should figure out a good value.
100 * 64 or 128 are the only other valid values.
102 static int spg_len = -1;
103 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
107 * -1: no congestion feedback (not recommended).
108 * 0: backpressure the channel instead of dropping packets right away.
109 * 1: no backpressure, drop packets for the congested queue immediately.
111 static int cong_drop = 0;
112 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
115 * Deliver multiple frames in the same free list buffer if they fit.
116 * -1: let the driver decide whether to enable buffer packing or not.
117 * 0: disable buffer packing.
118 * 1: enable buffer packing.
120 static int buffer_packing = -1;
121 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
124 * Start next frame in a packed buffer at this boundary.
125 * -1: driver should figure out a good value.
126 * T4: driver will ignore this and use the same value as fl_pad above.
127 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
129 static int fl_pack = -1;
130 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
133 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
134 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
135 * 1: ok to create mbuf(s) within a cluster if there is room.
137 static int allow_mbufs_in_cluster = 1;
138 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
141 * Largest rx cluster size that the driver is allowed to allocate.
143 static int largest_rx_cluster = MJUM16BYTES;
144 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
147 * Size of cluster allocation that's most likely to succeed. The driver will
148 * fall back to this size if it fails to allocate clusters larger than this.
150 static int safest_rx_cluster = PAGE_SIZE;
151 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
154 * The interrupt holdoff timers are multiplied by this value on T6+.
155 * 1 and 3-17 (both inclusive) are legal values.
157 static int tscale = 1;
158 TUNABLE_INT("hw.cxgbe.tscale", &tscale);
161 * Number of LRO entries in the lro_ctrl structure per rx queue.
163 static int lro_entries = TCP_LRO_ENTRIES;
164 TUNABLE_INT("hw.cxgbe.lro_entries", &lro_entries);
167 * This enables presorting of frames before they're fed into tcp_lro_rx.
169 static int lro_mbufs = 0;
170 TUNABLE_INT("hw.cxgbe.lro_mbufs", &lro_mbufs);
173 u_int wr_type; /* type 0 or type 1 */
174 u_int npkt; /* # of packets in this work request */
175 u_int plen; /* total payload (sum of all packets) */
176 u_int len16; /* # of 16B pieces used by this work request */
179 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
182 struct sglist_seg seg[TX_SGL_SEGS];
185 static int service_iq(struct sge_iq *, int);
186 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
187 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
188 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
189 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
190 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
192 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
193 bus_addr_t *, void **);
194 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
196 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
198 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
199 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
200 struct sysctl_oid *, struct sge_fl *);
201 static int alloc_fwq(struct adapter *);
202 static int free_fwq(struct adapter *);
203 static int alloc_mgmtq(struct adapter *);
204 static int free_mgmtq(struct adapter *);
205 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
206 struct sysctl_oid *);
207 static int free_rxq(struct vi_info *, struct sge_rxq *);
209 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
210 struct sysctl_oid *);
211 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
214 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
215 struct sysctl_oid *);
216 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
217 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
218 struct sysctl_oid *);
219 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
221 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
222 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
224 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
226 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
227 static int free_eq(struct adapter *, struct sge_eq *);
228 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
229 struct sysctl_oid *);
230 static int free_wrq(struct adapter *, struct sge_wrq *);
231 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
232 struct sysctl_oid *);
233 static int free_txq(struct vi_info *, struct sge_txq *);
234 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
235 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
236 static int refill_fl(struct adapter *, struct sge_fl *, int);
237 static void refill_sfl(void *);
238 static int alloc_fl_sdesc(struct sge_fl *);
239 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
240 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
241 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
242 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
244 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
245 static inline u_int txpkt_len16(u_int, u_int);
246 static inline u_int txpkt_vm_len16(u_int, u_int);
247 static inline u_int txpkts0_len16(u_int);
248 static inline u_int txpkts1_len16(void);
249 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
250 struct mbuf *, u_int);
251 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
252 struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
253 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
254 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
255 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
256 struct mbuf *, const struct txpkts *, u_int);
257 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
258 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
259 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
260 static inline uint16_t read_hw_cidx(struct sge_eq *);
261 static inline u_int reclaimable_tx_desc(struct sge_eq *);
262 static inline u_int total_available_tx_desc(struct sge_eq *);
263 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
264 static void tx_reclaim(void *, int);
265 static __be64 get_flit(struct sglist_seg *, int, int);
266 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
268 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
270 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
271 static void wrq_tx_drain(void *, int);
272 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
274 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
275 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
276 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
278 static counter_u64_t extfree_refs;
279 static counter_u64_t extfree_rels;
281 an_handler_t t4_an_handler;
282 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
283 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
287 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
291 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
293 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
300 t4_register_an_handler(an_handler_t h)
304 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
305 loc = (uintptr_t *) &t4_an_handler;
306 atomic_store_rel_ptr(loc, new);
312 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
314 const struct cpl_fw6_msg *cpl =
315 __containerof(rpl, struct cpl_fw6_msg, data[0]);
318 panic("%s: fw_msg type %d", __func__, cpl->type);
320 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
326 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
330 if (type >= nitems(t4_fw_msg_handler))
334 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
335 * handler dispatch table. Reject any attempt to install a handler for
338 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
341 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
342 loc = (uintptr_t *) &t4_fw_msg_handler[type];
343 atomic_store_rel_ptr(loc, new);
349 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
353 panic("%s: opcode 0x%02x on iq %p with payload %p",
354 __func__, rss->opcode, iq, m);
356 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
357 __func__, rss->opcode, iq, m);
364 t4_register_cpl_handler(int opcode, cpl_handler_t h)
368 if (opcode >= nitems(t4_cpl_handler))
371 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
372 loc = (uintptr_t *) &t4_cpl_handler[opcode];
373 atomic_store_rel_ptr(loc, new);
379 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
386 if (fl_pktshift < 0 || fl_pktshift > 7) {
387 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
388 " using 2 instead.\n", fl_pktshift);
392 if (spg_len != 64 && spg_len != 128) {
395 #if defined(__i386__) || defined(__amd64__)
396 len = cpu_clflush_line_size > 64 ? 128 : 64;
401 printf("Invalid hw.cxgbe.spg_len value (%d),"
402 " using %d instead.\n", spg_len, len);
407 if (cong_drop < -1 || cong_drop > 1) {
408 printf("Invalid hw.cxgbe.cong_drop value (%d),"
409 " using 0 instead.\n", cong_drop);
413 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
414 printf("Invalid hw.cxgbe.tscale value (%d),"
415 " using 1 instead.\n", tscale);
419 extfree_refs = counter_u64_alloc(M_WAITOK);
420 extfree_rels = counter_u64_alloc(M_WAITOK);
421 counter_u64_zero(extfree_refs);
422 counter_u64_zero(extfree_rels);
424 t4_an_handler = an_not_handled;
425 for (i = 0; i < nitems(t4_fw_msg_handler); i++)
426 t4_fw_msg_handler[i] = fw_msg_not_handled;
427 for (i = 0; i < nitems(t4_cpl_handler); i++)
428 t4_cpl_handler[i] = cpl_not_handled;
430 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
431 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
432 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
433 t4_register_cpl_handler(CPL_RX_PKT, t4_eth_rx);
434 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
435 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
439 t4_sge_modunload(void)
442 counter_u64_free(extfree_refs);
443 counter_u64_free(extfree_rels);
447 t4_sge_extfree_refs(void)
451 rels = counter_u64_fetch(extfree_rels);
452 refs = counter_u64_fetch(extfree_refs);
454 return (refs - rels);
458 setup_pad_and_pack_boundaries(struct adapter *sc)
461 int pad, pack, pad_shift;
463 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
464 X_INGPADBOUNDARY_SHIFT;
466 if (fl_pad < (1 << pad_shift) ||
467 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
470 * If there is any chance that we might use buffer packing and
471 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
472 * it to the minimum allowed in all other cases.
474 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
477 * For fl_pad = 0 we'll still write a reasonable value to the
478 * register but all the freelists will opt out of padding.
479 * We'll complain here only if the user tried to set it to a
480 * value greater than 0 that was invalid.
483 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
484 " (%d), using %d instead.\n", fl_pad, pad);
487 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
488 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
489 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
492 if (fl_pack != -1 && fl_pack != pad) {
493 /* Complain but carry on. */
494 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
495 " using %d instead.\n", fl_pack, pad);
501 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
502 !powerof2(fl_pack)) {
503 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
504 MPASS(powerof2(pack));
512 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
513 " (%d), using %d instead.\n", fl_pack, pack);
516 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
518 v = V_INGPACKBOUNDARY(0);
520 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
522 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
523 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
527 * adap->params.vpd.cclk must be set up before this is called.
530 t4_tweak_chip_settings(struct adapter *sc)
534 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
535 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
536 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
537 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
538 static int sge_flbuf_sizes[] = {
540 #if MJUMPAGESIZE != MCLBYTES
542 MJUMPAGESIZE - CL_METADATA_SIZE,
543 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
547 MCLBYTES - MSIZE - CL_METADATA_SIZE,
548 MJUM9BYTES - CL_METADATA_SIZE,
549 MJUM16BYTES - CL_METADATA_SIZE,
552 KASSERT(sc->flags & MASTER_PF,
553 ("%s: trying to change chip settings when not master.", __func__));
555 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
556 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
557 V_EGRSTATUSPAGESIZE(spg_len == 128);
558 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
560 setup_pad_and_pack_boundaries(sc);
562 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
563 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
564 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
565 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
566 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
567 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
568 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
569 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
570 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
572 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
573 ("%s: hw buffer size table too big", __func__));
574 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
575 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
579 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
580 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
581 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
583 KASSERT(intr_timer[0] <= timer_max,
584 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
586 for (i = 1; i < nitems(intr_timer); i++) {
587 KASSERT(intr_timer[i] >= intr_timer[i - 1],
588 ("%s: timers not listed in increasing order (%d)",
591 while (intr_timer[i] > timer_max) {
592 if (i == nitems(intr_timer) - 1) {
593 intr_timer[i] = timer_max;
596 intr_timer[i] += intr_timer[i - 1];
601 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
602 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
603 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
604 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
605 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
606 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
607 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
608 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
609 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
611 if (chip_id(sc) >= CHELSIO_T6) {
612 m = V_TSCALE(M_TSCALE);
616 v = V_TSCALE(tscale - 2);
617 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
619 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
620 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
621 V_WRTHRTHRESH(M_WRTHRTHRESH);
622 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
624 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
626 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
630 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
631 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
632 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
635 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
636 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
637 * may have to deal with is MAXPHYS + 1 page.
639 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
640 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
642 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
643 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
644 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
646 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
648 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
649 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
653 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
654 * padding is in use, the buffer's start and end need to be aligned to the pad
655 * boundary as well. We'll just make sure that the size is a multiple of the
656 * boundary here, it is up to the buffer allocation code to make sure the start
657 * of the buffer is aligned as well.
660 hwsz_ok(struct adapter *sc, int hwsz)
662 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
664 return (hwsz >= 64 && (hwsz & mask) == 0);
668 * XXX: driver really should be able to deal with unexpected settings.
671 t4_read_chip_settings(struct adapter *sc)
673 struct sge *s = &sc->sge;
674 struct sge_params *sp = &sc->params.sge;
677 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
678 static int sw_buf_sizes[] = { /* Sorted by size */
680 #if MJUMPAGESIZE != MCLBYTES
686 struct sw_zone_info *swz, *safe_swz;
687 struct hw_buf_info *hwb;
691 r = sc->params.sge.sge_control;
693 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
698 * If this changes then every single use of PAGE_SHIFT in the driver
699 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
701 if (sp->page_shift != PAGE_SHIFT) {
702 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
706 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
707 hwb = &s->hw_buf_info[0];
708 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
709 r = sc->params.sge.sge_fl_buffer_size[i];
711 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
716 * Create a sorted list in decreasing order of hw buffer sizes (and so
717 * increasing order of spare area) for each software zone.
719 * If padding is enabled then the start and end of the buffer must align
720 * to the pad boundary; if packing is enabled then they must align with
721 * the pack boundary as well. Allocations from the cluster zones are
722 * aligned to min(size, 4K), so the buffer starts at that alignment and
723 * ends at hwb->size alignment. If mbuf inlining is allowed the
724 * starting alignment will be reduced to MSIZE and the driver will
725 * exercise appropriate caution when deciding on the best buffer layout
728 n = 0; /* no usable buffer size to begin with */
729 swz = &s->sw_zone_info[0];
731 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
732 int8_t head = -1, tail = -1;
734 swz->size = sw_buf_sizes[i];
735 swz->zone = m_getzone(swz->size);
736 swz->type = m_gettype(swz->size);
738 if (swz->size < PAGE_SIZE) {
739 MPASS(powerof2(swz->size));
740 if (fl_pad && (swz->size % sp->pad_boundary != 0))
744 if (swz->size == safest_rx_cluster)
747 hwb = &s->hw_buf_info[0];
748 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
749 if (hwb->zidx != -1 || hwb->size > swz->size)
753 MPASS(hwb->size % sp->pad_boundary == 0);
758 else if (hwb->size < s->hw_buf_info[tail].size) {
759 s->hw_buf_info[tail].next = j;
763 struct hw_buf_info *t;
765 for (cur = &head; *cur != -1; cur = &t->next) {
766 t = &s->hw_buf_info[*cur];
767 if (hwb->size == t->size) {
771 if (hwb->size > t->size) {
779 swz->head_hwidx = head;
780 swz->tail_hwidx = tail;
784 if (swz->size - s->hw_buf_info[tail].size >=
786 sc->flags |= BUF_PACKING_OK;
790 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
796 if (safe_swz != NULL) {
797 s->safe_hwidx1 = safe_swz->head_hwidx;
798 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
801 hwb = &s->hw_buf_info[i];
804 MPASS(hwb->size % sp->pad_boundary == 0);
806 spare = safe_swz->size - hwb->size;
807 if (spare >= CL_METADATA_SIZE) {
814 if (sc->flags & IS_VF)
817 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
818 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
820 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
824 m = v = F_TDDPTAGTCB;
825 r = t4_read_reg(sc, A_ULP_RX_CTL);
827 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
831 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
833 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
834 r = t4_read_reg(sc, A_TP_PARA_REG5);
836 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
840 t4_init_tp_params(sc, 1);
842 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
843 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
849 t4_create_dma_tag(struct adapter *sc)
853 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
854 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
855 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
858 device_printf(sc->dev,
859 "failed to create main DMA tag: %d\n", rc);
866 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
867 struct sysctl_oid_list *children)
869 struct sge_params *sp = &sc->params.sge;
871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
872 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
873 "freelist buffer sizes");
875 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
876 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
878 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
879 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
881 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
882 NULL, sp->spg_len, "status page size (bytes)");
884 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
885 NULL, cong_drop, "congestion drop setting");
887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
888 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
892 t4_destroy_dma_tag(struct adapter *sc)
895 bus_dma_tag_destroy(sc->dmat);
901 * Allocate and initialize the firmware event queue and the management queue.
903 * Returns errno on failure. Resources allocated up to that point may still be
904 * allocated. Caller is responsible for cleanup in case this function fails.
907 t4_setup_adapter_queues(struct adapter *sc)
911 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
913 sysctl_ctx_init(&sc->ctx);
914 sc->flags |= ADAP_SYSCTL_CTX;
917 * Firmware event queue
924 * Management queue. This is just a control queue that uses the fwq as
927 if (!(sc->flags & IS_VF))
928 rc = alloc_mgmtq(sc);
937 t4_teardown_adapter_queues(struct adapter *sc)
940 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
942 /* Do this before freeing the queue */
943 if (sc->flags & ADAP_SYSCTL_CTX) {
944 sysctl_ctx_free(&sc->ctx);
945 sc->flags &= ~ADAP_SYSCTL_CTX;
955 first_vector(struct vi_info *vi)
957 struct adapter *sc = vi->pi->adapter;
959 if (sc->intr_count == 1)
962 return (vi->first_intr);
966 * Given an arbitrary "index," come up with an iq that can be used by other
967 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
968 * The iq returned is guaranteed to be something that takes direct interrupts.
970 static struct sge_iq *
971 vi_intr_iq(struct vi_info *vi, int idx)
973 struct adapter *sc = vi->pi->adapter;
974 struct sge *s = &sc->sge;
975 struct sge_iq *iq = NULL;
978 if (sc->intr_count == 1)
979 return (&sc->sge.fwq);
983 /* Do not consider any netmap-only interrupts */
984 if (vi->flags & INTR_RXQ && vi->nnmrxq > vi->nrxq)
985 nintr -= vi->nnmrxq - vi->nrxq;
988 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
989 __func__, vi, sc->intr_count));
992 if (vi->flags & INTR_RXQ) {
994 iq = &s->rxq[vi->first_rxq + i].iq;
1000 if (vi->flags & INTR_OFLD_RXQ) {
1001 if (i < vi->nofldrxq) {
1002 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
1008 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
1009 vi, vi->flags & INTR_ALL, idx, nintr);
1012 KASSERT(iq->flags & IQ_INTR,
1013 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
1014 vi->flags & INTR_ALL, idx));
1018 /* Maximum payload that can be delivered with a single iq descriptor */
1020 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
1026 payload = sc->tt.rx_coalesce ?
1027 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
1030 /* large enough even when hw VLAN extraction is disabled */
1031 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1032 ETHER_VLAN_ENCAP_LEN + mtu;
1041 t4_setup_vi_queues(struct vi_info *vi)
1043 int rc = 0, i, j, intr_idx, iqid;
1044 struct sge_rxq *rxq;
1045 struct sge_txq *txq;
1046 struct sge_wrq *ctrlq;
1048 struct sge_ofld_rxq *ofld_rxq;
1049 struct sge_wrq *ofld_txq;
1053 struct sge_nm_rxq *nm_rxq;
1054 struct sge_nm_txq *nm_txq;
1057 struct port_info *pi = vi->pi;
1058 struct adapter *sc = pi->adapter;
1059 struct ifnet *ifp = vi->ifp;
1060 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1061 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1062 int maxp, mtu = ifp->if_mtu;
1064 /* Interrupt vector to start from (when using multiple vectors) */
1065 intr_idx = first_vector(vi);
1068 saved_idx = intr_idx;
1069 if (ifp->if_capabilities & IFCAP_NETMAP) {
1071 /* netmap is supported with direct interrupts only. */
1072 MPASS(vi->flags & INTR_RXQ);
1075 * We don't have buffers to back the netmap rx queues
1076 * right now so we create the queues in a way that
1077 * doesn't set off any congestion signal in the chip.
1079 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1080 CTLFLAG_RD, NULL, "rx queues");
1081 for_each_nm_rxq(vi, i, nm_rxq) {
1082 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1088 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1089 CTLFLAG_RD, NULL, "tx queues");
1090 for_each_nm_txq(vi, i, nm_txq) {
1091 iqid = vi->first_nm_rxq + (i % vi->nnmrxq);
1092 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
1098 /* Normal rx queues and netmap rx queues share the same interrupts. */
1099 intr_idx = saved_idx;
1103 * First pass over all NIC and TOE rx queues:
1104 * a) initialize iq and fl
1105 * b) allocate queue iff it will take direct interrupts.
1107 maxp = mtu_to_max_payload(sc, mtu, 0);
1108 if (vi->flags & INTR_RXQ) {
1109 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1110 CTLFLAG_RD, NULL, "rx queues");
1112 for_each_rxq(vi, i, rxq) {
1114 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1116 snprintf(name, sizeof(name), "%s rxq%d-fl",
1117 device_get_nameunit(vi->dev), i);
1118 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1120 if (vi->flags & INTR_RXQ) {
1121 rxq->iq.flags |= IQ_INTR;
1122 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1129 if (ifp->if_capabilities & IFCAP_NETMAP)
1130 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1133 maxp = mtu_to_max_payload(sc, mtu, 1);
1134 if (vi->flags & INTR_OFLD_RXQ) {
1135 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1137 "rx queues for offloaded TCP connections");
1139 for_each_ofld_rxq(vi, i, ofld_rxq) {
1141 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1144 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1145 device_get_nameunit(vi->dev), i);
1146 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1148 if (vi->flags & INTR_OFLD_RXQ) {
1149 ofld_rxq->iq.flags |= IQ_INTR;
1150 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1159 * Second pass over all NIC and TOE rx queues. The queues forwarding
1160 * their interrupts are allocated now.
1163 if (!(vi->flags & INTR_RXQ)) {
1164 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1165 CTLFLAG_RD, NULL, "rx queues");
1166 for_each_rxq(vi, i, rxq) {
1167 MPASS(!(rxq->iq.flags & IQ_INTR));
1169 intr_idx = vi_intr_iq(vi, j)->abs_id;
1171 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
1178 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
1179 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1181 "rx queues for offloaded TCP connections");
1182 for_each_ofld_rxq(vi, i, ofld_rxq) {
1183 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1185 intr_idx = vi_intr_iq(vi, j)->abs_id;
1187 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1196 * Now the tx queues. Only one pass needed.
1198 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1201 for_each_txq(vi, i, txq) {
1202 iqid = vi_intr_iq(vi, j)->cntxt_id;
1203 snprintf(name, sizeof(name), "%s txq%d",
1204 device_get_nameunit(vi->dev), i);
1205 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1208 rc = alloc_txq(vi, txq, i, oid);
1214 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1215 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1216 for_each_ofld_txq(vi, i, ofld_txq) {
1217 struct sysctl_oid *oid2;
1219 iqid = vi_intr_iq(vi, j)->cntxt_id;
1220 snprintf(name, sizeof(name), "%s ofld_txq%d",
1221 device_get_nameunit(vi->dev), i);
1222 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1225 snprintf(name, sizeof(name), "%d", i);
1226 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1227 name, CTLFLAG_RD, NULL, "offload tx queue");
1229 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1237 * Finally, the control queue.
1239 if (!IS_MAIN_VI(vi) || sc->flags & IS_VF)
1241 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1242 NULL, "ctrl queue");
1243 ctrlq = &sc->sge.ctrlq[pi->port_id];
1244 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1245 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1246 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1248 rc = alloc_wrq(sc, vi, ctrlq, oid);
1252 t4_teardown_vi_queues(vi);
1261 t4_teardown_vi_queues(struct vi_info *vi)
1264 struct port_info *pi = vi->pi;
1265 struct adapter *sc = pi->adapter;
1266 struct sge_rxq *rxq;
1267 struct sge_txq *txq;
1269 struct sge_ofld_rxq *ofld_rxq;
1270 struct sge_wrq *ofld_txq;
1273 struct sge_nm_rxq *nm_rxq;
1274 struct sge_nm_txq *nm_txq;
1277 /* Do this before freeing the queues */
1278 if (vi->flags & VI_SYSCTL_CTX) {
1279 sysctl_ctx_free(&vi->ctx);
1280 vi->flags &= ~VI_SYSCTL_CTX;
1284 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1285 for_each_nm_txq(vi, i, nm_txq) {
1286 free_nm_txq(vi, nm_txq);
1289 for_each_nm_rxq(vi, i, nm_rxq) {
1290 free_nm_rxq(vi, nm_rxq);
1296 * Take down all the tx queues first, as they reference the rx queues
1297 * (for egress updates, etc.).
1300 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
1301 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1303 for_each_txq(vi, i, txq) {
1307 for_each_ofld_txq(vi, i, ofld_txq) {
1308 free_wrq(sc, ofld_txq);
1313 * Then take down the rx queues that forward their interrupts, as they
1314 * reference other rx queues.
1317 for_each_rxq(vi, i, rxq) {
1318 if ((rxq->iq.flags & IQ_INTR) == 0)
1322 for_each_ofld_rxq(vi, i, ofld_rxq) {
1323 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1324 free_ofld_rxq(vi, ofld_rxq);
1329 * Then take down the rx queues that take direct interrupts.
1332 for_each_rxq(vi, i, rxq) {
1333 if (rxq->iq.flags & IQ_INTR)
1337 for_each_ofld_rxq(vi, i, ofld_rxq) {
1338 if (ofld_rxq->iq.flags & IQ_INTR)
1339 free_ofld_rxq(vi, ofld_rxq);
1347 * Deals with errors and the firmware event queue. All data rx queues forward
1348 * their interrupt to the firmware event queue.
1351 t4_intr_all(void *arg)
1353 struct adapter *sc = arg;
1354 struct sge_iq *fwq = &sc->sge.fwq;
1357 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1359 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1363 /* Deals with error interrupts */
1365 t4_intr_err(void *arg)
1367 struct adapter *sc = arg;
1369 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1370 t4_slow_intr_handler(sc);
1374 t4_intr_evt(void *arg)
1376 struct sge_iq *iq = arg;
1378 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1380 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1387 struct sge_iq *iq = arg;
1389 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1391 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1396 t4_vi_intr(void *arg)
1398 struct irq *irq = arg;
1401 if (atomic_cmpset_int(&irq->nm_state, NM_ON, NM_BUSY)) {
1402 t4_nm_intr(irq->nm_rxq);
1403 atomic_cmpset_int(&irq->nm_state, NM_BUSY, NM_ON);
1406 if (irq->rxq != NULL)
1411 sort_before_lro(struct lro_ctrl *lro)
1414 return (lro->lro_mbuf_max != 0);
1418 * Deals with anything and everything on the given ingress queue.
1421 service_iq(struct sge_iq *iq, int budget)
1424 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1425 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1426 struct adapter *sc = iq->adapter;
1427 struct iq_desc *d = &iq->desc[iq->cidx];
1428 int ndescs = 0, limit;
1429 int rsp_type, refill;
1431 uint16_t fl_hw_cidx;
1433 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1434 #if defined(INET) || defined(INET6)
1435 const struct timeval lro_timeout = {0, sc->lro_timeout};
1436 struct lro_ctrl *lro = &rxq->lro;
1439 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1441 limit = budget ? budget : iq->qsize / 16;
1443 if (iq->flags & IQ_HAS_FL) {
1445 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1448 fl_hw_cidx = 0; /* to silence gcc warning */
1451 #if defined(INET) || defined(INET6)
1452 if (iq->flags & IQ_ADJ_CREDIT) {
1453 MPASS(sort_before_lro(lro));
1454 iq->flags &= ~IQ_ADJ_CREDIT;
1455 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1456 tcp_lro_flush_all(lro);
1457 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1458 V_INGRESSQID((u32)iq->cntxt_id) |
1459 V_SEINTARM(iq->intr_params));
1465 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1469 * We always come back and check the descriptor ring for new indirect
1470 * interrupts and other responses after running a single handler.
1473 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1479 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1480 lq = be32toh(d->rsp.pldbuflen_qid);
1483 case X_RSPD_TYPE_FLBUF:
1485 KASSERT(iq->flags & IQ_HAS_FL,
1486 ("%s: data for an iq (%p) with no freelist",
1489 m0 = get_fl_payload(sc, fl, lq);
1490 if (__predict_false(m0 == NULL))
1492 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1493 #ifdef T4_PKT_TIMESTAMP
1495 * 60 bit timestamp for the payload is
1496 * *(uint64_t *)m0->m_pktdat. Note that it is
1497 * in the leading free-space in the mbuf. The
1498 * kernel can clobber it during a pullup,
1499 * m_copymdata, etc. You need to make sure that
1500 * the mbuf reaches you unmolested if you care
1501 * about the timestamp.
1503 *(uint64_t *)m0->m_pktdat =
1504 be64toh(ctrl->u.last_flit) &
1510 case X_RSPD_TYPE_CPL:
1511 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1512 ("%s: bad opcode %02x.", __func__,
1514 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1517 case X_RSPD_TYPE_INTR:
1520 * Interrupts should be forwarded only to queues
1521 * that are not forwarding their interrupts.
1522 * This means service_iq can recurse but only 1
1525 KASSERT(budget == 0,
1526 ("%s: budget %u, rsp_type %u", __func__,
1530 * There are 1K interrupt-capable queues (qids 0
1531 * through 1023). A response type indicating a
1532 * forwarded interrupt with a qid >= 1K is an
1533 * iWARP async notification.
1536 t4_an_handler(iq, &d->rsp);
1540 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1542 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1544 if (service_iq(q, q->qsize / 16) == 0) {
1545 atomic_cmpset_int(&q->state,
1546 IQS_BUSY, IQS_IDLE);
1548 STAILQ_INSERT_TAIL(&iql, q,
1556 ("%s: illegal response type %d on iq %p",
1557 __func__, rsp_type, iq));
1559 "%s: illegal response type %d on iq %p",
1560 device_get_nameunit(sc->dev), rsp_type, iq);
1565 if (__predict_false(++iq->cidx == iq->sidx)) {
1567 iq->gen ^= F_RSPD_GEN;
1570 if (__predict_false(++ndescs == limit)) {
1571 t4_write_reg(sc, sc->sge_gts_reg,
1573 V_INGRESSQID(iq->cntxt_id) |
1574 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1577 #if defined(INET) || defined(INET6)
1578 if (iq->flags & IQ_LRO_ENABLED &&
1579 !sort_before_lro(lro) &&
1580 sc->lro_timeout != 0) {
1581 tcp_lro_flush_inactive(lro,
1587 if (iq->flags & IQ_HAS_FL) {
1589 refill_fl(sc, fl, 32);
1592 return (EINPROGRESS);
1597 refill_fl(sc, fl, 32);
1599 fl_hw_cidx = fl->hw_cidx;
1604 if (STAILQ_EMPTY(&iql))
1608 * Process the head only, and send it to the back of the list if
1609 * it's still not done.
1611 q = STAILQ_FIRST(&iql);
1612 STAILQ_REMOVE_HEAD(&iql, link);
1613 if (service_iq(q, q->qsize / 8) == 0)
1614 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1616 STAILQ_INSERT_TAIL(&iql, q, link);
1619 #if defined(INET) || defined(INET6)
1620 if (iq->flags & IQ_LRO_ENABLED) {
1621 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1622 MPASS(sort_before_lro(lro));
1623 /* hold back one credit and don't flush LRO state */
1624 iq->flags |= IQ_ADJ_CREDIT;
1627 tcp_lro_flush_all(lro);
1632 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1633 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1635 if (iq->flags & IQ_HAS_FL) {
1639 starved = refill_fl(sc, fl, 64);
1641 if (__predict_false(starved != 0))
1642 add_fl_to_sfl(sc, fl);
1649 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1651 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1654 MPASS(cll->region3 >= CL_METADATA_SIZE);
1659 static inline struct cluster_metadata *
1660 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1664 if (cl_has_metadata(fl, cll)) {
1665 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1667 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1673 rxb_free(struct mbuf *m)
1675 uma_zone_t zone = m->m_ext.ext_arg1;
1676 void *cl = m->m_ext.ext_arg2;
1678 uma_zfree(zone, cl);
1679 counter_u64_add(extfree_rels, 1);
1683 * The mbuf returned by this function could be allocated from zone_mbuf or
1684 * constructed in spare room in the cluster.
1686 * The mbuf carries the payload in one of these ways
1687 * a) frame inside the mbuf (mbuf from zone_mbuf)
1688 * b) m_cljset (for clusters without metadata) zone_mbuf
1689 * c) m_extaddref (cluster with metadata) inline mbuf
1690 * d) m_extaddref (cluster with metadata) zone_mbuf
1692 static struct mbuf *
1693 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1697 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1698 struct cluster_layout *cll = &sd->cll;
1699 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1700 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1701 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1705 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1706 len = min(remaining, blen);
1707 payload = sd->cl + cll->region1 + fl->rx_offset;
1708 if (fl->flags & FL_BUF_PACKING) {
1709 const u_int l = fr_offset + len;
1710 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1712 if (fl->rx_offset + len + pad < hwb->size)
1714 MPASS(fl->rx_offset + blen <= hwb->size);
1716 MPASS(fl->rx_offset == 0); /* not packing */
1720 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1723 * Copy payload into a freshly allocated mbuf.
1726 m = fr_offset == 0 ?
1727 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1730 fl->mbuf_allocated++;
1731 #ifdef T4_PKT_TIMESTAMP
1732 /* Leave room for a timestamp */
1735 /* copy data to mbuf */
1736 bcopy(payload, mtod(m, caddr_t), len);
1738 } else if (sd->nmbuf * MSIZE < cll->region1) {
1741 * There's spare room in the cluster for an mbuf. Create one
1742 * and associate it with the payload that's in the cluster.
1746 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1747 /* No bzero required */
1748 if (m_init(m, M_NOWAIT, MT_DATA,
1749 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1752 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1754 if (sd->nmbuf++ == 0)
1755 counter_u64_add(extfree_refs, 1);
1760 * Grab an mbuf from zone_mbuf and associate it with the
1761 * payload in the cluster.
1764 m = fr_offset == 0 ?
1765 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1768 fl->mbuf_allocated++;
1770 m_extaddref(m, payload, blen, &clm->refcount,
1771 rxb_free, swz->zone, sd->cl);
1772 if (sd->nmbuf++ == 0)
1773 counter_u64_add(extfree_refs, 1);
1775 m_cljset(m, sd->cl, swz->type);
1776 sd->cl = NULL; /* consumed, not a recycle candidate */
1780 m->m_pkthdr.len = remaining;
1783 if (fl->flags & FL_BUF_PACKING) {
1784 fl->rx_offset += blen;
1785 MPASS(fl->rx_offset <= hwb->size);
1786 if (fl->rx_offset < hwb->size)
1787 return (m); /* without advancing the cidx */
1790 if (__predict_false(++fl->cidx % 8 == 0)) {
1791 uint16_t cidx = fl->cidx / 8;
1793 if (__predict_false(cidx == fl->sidx))
1794 fl->cidx = cidx = 0;
1802 static struct mbuf *
1803 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1805 struct mbuf *m0, *m, **pnext;
1807 const u_int total = G_RSPD_LEN(len_newbuf);
1809 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1810 M_ASSERTPKTHDR(fl->m0);
1811 MPASS(fl->m0->m_pkthdr.len == total);
1812 MPASS(fl->remaining < total);
1816 remaining = fl->remaining;
1817 fl->flags &= ~FL_BUF_RESUME;
1821 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1823 if (__predict_false(++fl->cidx % 8 == 0)) {
1824 uint16_t cidx = fl->cidx / 8;
1826 if (__predict_false(cidx == fl->sidx))
1827 fl->cidx = cidx = 0;
1833 * Payload starts at rx_offset in the current hw buffer. Its length is
1834 * 'len' and it may span multiple hw buffers.
1837 m0 = get_scatter_segment(sc, fl, 0, total);
1840 remaining = total - m0->m_len;
1841 pnext = &m0->m_next;
1842 while (remaining > 0) {
1844 MPASS(fl->rx_offset == 0);
1845 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1846 if (__predict_false(m == NULL)) {
1849 fl->remaining = remaining;
1850 fl->flags |= FL_BUF_RESUME;
1855 remaining -= m->m_len;
1864 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1866 struct sge_rxq *rxq = iq_to_rxq(iq);
1867 struct ifnet *ifp = rxq->ifp;
1868 struct adapter *sc = iq->adapter;
1869 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1870 #if defined(INET) || defined(INET6)
1871 struct lro_ctrl *lro = &rxq->lro;
1873 static const int sw_hashtype[4][2] = {
1874 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1875 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1876 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1877 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1880 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1883 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1884 m0->m_len -= sc->params.sge.fl_pktshift;
1885 m0->m_data += sc->params.sge.fl_pktshift;
1887 m0->m_pkthdr.rcvif = ifp;
1888 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1889 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1891 if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
1892 if (ifp->if_capenable & IFCAP_RXCSUM &&
1893 cpl->l2info & htobe32(F_RXF_IP)) {
1894 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1895 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1897 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1898 cpl->l2info & htobe32(F_RXF_IP6)) {
1899 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1904 if (__predict_false(cpl->ip_frag))
1905 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1907 m0->m_pkthdr.csum_data = 0xffff;
1911 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1912 m0->m_flags |= M_VLANTAG;
1913 rxq->vlan_extraction++;
1916 #if defined(INET) || defined(INET6)
1917 if (iq->flags & IQ_LRO_ENABLED) {
1918 if (sort_before_lro(lro)) {
1919 tcp_lro_queue_mbuf(lro, m0);
1920 return (0); /* queued for sort, then LRO */
1922 if (tcp_lro_rx(lro, m0, 0) == 0)
1923 return (0); /* queued for LRO */
1926 ifp->if_input(ifp, m0);
1932 * Must drain the wrq or make sure that someone else will.
1935 wrq_tx_drain(void *arg, int n)
1937 struct sge_wrq *wrq = arg;
1938 struct sge_eq *eq = &wrq->eq;
1941 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1942 drain_wrq_wr_list(wrq->adapter, wrq);
1947 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1949 struct sge_eq *eq = &wrq->eq;
1950 u_int available, dbdiff; /* # of hardware descriptors */
1953 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1955 EQ_LOCK_ASSERT_OWNED(eq);
1956 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1957 wr = STAILQ_FIRST(&wrq->wr_list);
1958 MPASS(wr != NULL); /* Must be called with something useful to do */
1959 MPASS(eq->pidx == eq->dbidx);
1963 eq->cidx = read_hw_cidx(eq);
1964 if (eq->pidx == eq->cidx)
1965 available = eq->sidx - 1;
1967 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1969 MPASS(wr->wrq == wrq);
1970 n = howmany(wr->wr_len, EQ_ESIZE);
1974 dst = (void *)&eq->desc[eq->pidx];
1975 if (__predict_true(eq->sidx - eq->pidx > n)) {
1976 /* Won't wrap, won't end exactly at the status page. */
1977 bcopy(&wr->wr[0], dst, wr->wr_len);
1980 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1982 bcopy(&wr->wr[0], dst, first_portion);
1983 if (wr->wr_len > first_portion) {
1984 bcopy(&wr->wr[first_portion], &eq->desc[0],
1985 wr->wr_len - first_portion);
1987 eq->pidx = n - (eq->sidx - eq->pidx);
1989 wrq->tx_wrs_copied++;
1991 if (available < eq->sidx / 4 &&
1992 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1993 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1995 eq->equeqidx = eq->pidx;
1996 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1997 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1998 eq->equeqidx = eq->pidx;
2003 ring_eq_db(sc, eq, dbdiff);
2007 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2009 MPASS(wrq->nwr_pending > 0);
2011 MPASS(wrq->ndesc_needed >= n);
2012 wrq->ndesc_needed -= n;
2013 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2016 ring_eq_db(sc, eq, dbdiff);
2020 * Doesn't fail. Holds on to work requests it can't send right away.
2023 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2026 struct sge_eq *eq = &wrq->eq;
2029 EQ_LOCK_ASSERT_OWNED(eq);
2031 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2032 MPASS((wr->wr_len & 0x7) == 0);
2034 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2036 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2038 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2039 return; /* commit_wrq_wr will drain wr_list as well. */
2041 drain_wrq_wr_list(sc, wrq);
2043 /* Doorbell must have caught up to the pidx. */
2044 MPASS(eq->pidx == eq->dbidx);
2048 t4_update_fl_bufsize(struct ifnet *ifp)
2050 struct vi_info *vi = ifp->if_softc;
2051 struct adapter *sc = vi->pi->adapter;
2052 struct sge_rxq *rxq;
2054 struct sge_ofld_rxq *ofld_rxq;
2057 int i, maxp, mtu = ifp->if_mtu;
2059 maxp = mtu_to_max_payload(sc, mtu, 0);
2060 for_each_rxq(vi, i, rxq) {
2064 find_best_refill_source(sc, fl, maxp);
2068 maxp = mtu_to_max_payload(sc, mtu, 1);
2069 for_each_ofld_rxq(vi, i, ofld_rxq) {
2073 find_best_refill_source(sc, fl, maxp);
2080 mbuf_nsegs(struct mbuf *m)
2084 KASSERT(m->m_pkthdr.l5hlen > 0,
2085 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2087 return (m->m_pkthdr.l5hlen);
2091 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2095 m->m_pkthdr.l5hlen = nsegs;
2099 mbuf_len16(struct mbuf *m)
2104 n = m->m_pkthdr.PH_loc.eight[0];
2105 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2111 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2115 m->m_pkthdr.PH_loc.eight[0] = len16;
2119 needs_tso(struct mbuf *m)
2124 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
2125 KASSERT(m->m_pkthdr.tso_segsz > 0,
2126 ("%s: TSO requested in mbuf %p but MSS not provided",
2135 needs_l3_csum(struct mbuf *m)
2140 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2146 needs_l4_csum(struct mbuf *m)
2151 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2152 CSUM_TCP_IPV6 | CSUM_TSO))
2158 needs_vlan_insertion(struct mbuf *m)
2163 if (m->m_flags & M_VLANTAG) {
2164 KASSERT(m->m_pkthdr.ether_vtag != 0,
2165 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2173 m_advance(struct mbuf **pm, int *poffset, int len)
2175 struct mbuf *m = *pm;
2176 int offset = *poffset;
2182 if (offset + len < m->m_len) {
2184 p = mtod(m, uintptr_t) + offset;
2187 len -= m->m_len - offset;
2198 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2199 * must have at least one mbuf that's not empty.
2202 count_mbuf_nsegs(struct mbuf *m)
2204 vm_paddr_t lastb, next;
2212 for (; m; m = m->m_next) {
2215 if (__predict_false(len == 0))
2217 va = mtod(m, vm_offset_t);
2218 next = pmap_kextract(va);
2219 nsegs += sglist_count(m->m_data, len);
2220 if (lastb + 1 == next)
2222 lastb = pmap_kextract(va + len - 1);
2230 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2231 * a) caller can assume it's been freed if this function returns with an error.
2232 * b) it may get defragged up if the gather list is too long for the hardware.
2235 parse_pkt(struct adapter *sc, struct mbuf **mp)
2237 struct mbuf *m0 = *mp, *m;
2238 int rc, nsegs, defragged = 0, offset;
2239 struct ether_header *eh;
2241 #if defined(INET) || defined(INET6)
2247 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2256 * First count the number of gather list segments in the payload.
2257 * Defrag the mbuf if nsegs exceeds the hardware limit.
2260 MPASS(m0->m_pkthdr.len > 0);
2261 nsegs = count_mbuf_nsegs(m0);
2262 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2263 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2267 *mp = m0 = m; /* update caller's copy after defrag */
2271 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2272 m0 = m_pullup(m0, m0->m_pkthdr.len);
2274 /* Should have left well enough alone. */
2278 *mp = m0; /* update caller's copy after pullup */
2281 set_mbuf_nsegs(m0, nsegs);
2282 if (sc->flags & IS_VF)
2283 set_mbuf_len16(m0, txpkt_vm_len16(nsegs, needs_tso(m0)));
2285 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2287 if (!needs_tso(m0) &&
2288 !(sc->flags & IS_VF && (needs_l3_csum(m0) || needs_l4_csum(m0))))
2292 eh = mtod(m, struct ether_header *);
2293 eh_type = ntohs(eh->ether_type);
2294 if (eh_type == ETHERTYPE_VLAN) {
2295 struct ether_vlan_header *evh = (void *)eh;
2297 eh_type = ntohs(evh->evl_proto);
2298 m0->m_pkthdr.l2hlen = sizeof(*evh);
2300 m0->m_pkthdr.l2hlen = sizeof(*eh);
2303 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2307 case ETHERTYPE_IPV6:
2309 struct ip6_hdr *ip6 = l3hdr;
2311 MPASS(!needs_tso(m0) || ip6->ip6_nxt == IPPROTO_TCP);
2313 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2320 struct ip *ip = l3hdr;
2322 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2327 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2328 " with the same INET/INET6 options as the kernel.",
2332 #if defined(INET) || defined(INET6)
2333 if (needs_tso(m0)) {
2334 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2335 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2343 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2345 struct sge_eq *eq = &wrq->eq;
2346 struct adapter *sc = wrq->adapter;
2347 int ndesc, available;
2352 ndesc = howmany(len16, EQ_ESIZE / 16);
2353 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2357 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2358 drain_wrq_wr_list(sc, wrq);
2360 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2363 wr = alloc_wrqe(len16 * 16, wrq);
2364 if (__predict_false(wr == NULL))
2367 cookie->ndesc = ndesc;
2371 eq->cidx = read_hw_cidx(eq);
2372 if (eq->pidx == eq->cidx)
2373 available = eq->sidx - 1;
2375 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2376 if (available < ndesc)
2379 cookie->pidx = eq->pidx;
2380 cookie->ndesc = ndesc;
2381 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2383 w = &eq->desc[eq->pidx];
2384 IDXINCR(eq->pidx, ndesc, eq->sidx);
2385 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2387 wrq->ss_pidx = cookie->pidx;
2388 wrq->ss_len = len16 * 16;
2397 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2399 struct sge_eq *eq = &wrq->eq;
2400 struct adapter *sc = wrq->adapter;
2402 struct wrq_cookie *prev, *next;
2404 if (cookie->pidx == -1) {
2405 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2411 if (__predict_false(w == &wrq->ss[0])) {
2412 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2414 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2415 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2416 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2419 wrq->tx_wrs_direct++;
2422 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2423 pidx = cookie->pidx;
2424 MPASS(pidx >= 0 && pidx < eq->sidx);
2425 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2426 next = TAILQ_NEXT(cookie, link);
2428 MPASS(pidx == eq->dbidx);
2429 if (next == NULL || ndesc >= 16)
2430 ring_eq_db(wrq->adapter, eq, ndesc);
2432 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2434 next->ndesc += ndesc;
2437 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2438 prev->ndesc += ndesc;
2440 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2442 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2443 drain_wrq_wr_list(sc, wrq);
2446 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2447 /* Doorbell must have caught up to the pidx. */
2448 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2455 can_resume_eth_tx(struct mp_ring *r)
2457 struct sge_eq *eq = r->cookie;
2459 return (total_available_tx_desc(eq) > eq->sidx / 8);
2463 cannot_use_txpkts(struct mbuf *m)
2465 /* maybe put a GL limit too, to avoid silliness? */
2467 return (needs_tso(m));
2471 discard_tx(struct sge_eq *eq)
2474 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
2478 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2479 * be consumed. Return the actual number consumed. 0 indicates a stall.
2482 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2484 struct sge_txq *txq = r->cookie;
2485 struct sge_eq *eq = &txq->eq;
2486 struct ifnet *ifp = txq->ifp;
2487 struct vi_info *vi = ifp->if_softc;
2488 struct port_info *pi = vi->pi;
2489 struct adapter *sc = pi->adapter;
2490 u_int total, remaining; /* # of packets */
2491 u_int available, dbdiff; /* # of hardware descriptors */
2493 struct mbuf *m0, *tail;
2495 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2497 remaining = IDXDIFF(pidx, cidx, r->size);
2498 MPASS(remaining > 0); /* Must not be called without work to do. */
2502 if (__predict_false(discard_tx(eq))) {
2503 while (cidx != pidx) {
2504 m0 = r->items[cidx];
2506 if (++cidx == r->size)
2509 reclaim_tx_descs(txq, 2048);
2514 /* How many hardware descriptors do we have readily available. */
2515 if (eq->pidx == eq->cidx)
2516 available = eq->sidx - 1;
2518 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2519 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2521 while (remaining > 0) {
2523 m0 = r->items[cidx];
2525 MPASS(m0->m_nextpkt == NULL);
2527 if (available < SGE_MAX_WR_NDESC) {
2528 available += reclaim_tx_descs(txq, 64);
2529 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2530 break; /* out of descriptors */
2533 next_cidx = cidx + 1;
2534 if (__predict_false(next_cidx == r->size))
2537 wr = (void *)&eq->desc[eq->pidx];
2538 if (sc->flags & IS_VF) {
2541 ETHER_BPF_MTAP(ifp, m0);
2542 n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
2544 } else if (remaining > 1 &&
2545 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2547 /* pkts at cidx, next_cidx should both be in txp. */
2548 MPASS(txp.npkt == 2);
2549 tail = r->items[next_cidx];
2550 MPASS(tail->m_nextpkt == NULL);
2551 ETHER_BPF_MTAP(ifp, m0);
2552 ETHER_BPF_MTAP(ifp, tail);
2553 m0->m_nextpkt = tail;
2555 if (__predict_false(++next_cidx == r->size))
2558 while (next_cidx != pidx) {
2559 if (add_to_txpkts(r->items[next_cidx], &txp,
2562 tail->m_nextpkt = r->items[next_cidx];
2563 tail = tail->m_nextpkt;
2564 ETHER_BPF_MTAP(ifp, tail);
2565 if (__predict_false(++next_cidx == r->size))
2569 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2571 remaining -= txp.npkt;
2575 ETHER_BPF_MTAP(ifp, m0);
2576 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2578 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2582 IDXINCR(eq->pidx, n, eq->sidx);
2584 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2585 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2586 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2588 eq->equeqidx = eq->pidx;
2589 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2590 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2591 eq->equeqidx = eq->pidx;
2594 if (dbdiff >= 16 && remaining >= 4) {
2595 ring_eq_db(sc, eq, dbdiff);
2596 available += reclaim_tx_descs(txq, 4 * dbdiff);
2603 ring_eq_db(sc, eq, dbdiff);
2604 reclaim_tx_descs(txq, 32);
2613 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2617 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2618 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2619 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2620 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2624 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2625 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2626 if (pktc_idx >= 0) {
2627 iq->intr_params |= F_QINTR_CNT_EN;
2628 iq->intr_pktc_idx = pktc_idx;
2630 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2631 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2635 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2639 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2640 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2641 if (sc->flags & BUF_PACKING_OK &&
2642 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2643 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2644 fl->flags |= FL_BUF_PACKING;
2645 find_best_refill_source(sc, fl, maxp);
2646 find_safe_refill_source(sc, fl);
2650 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2651 uint8_t tx_chan, uint16_t iqid, char *name)
2653 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2655 eq->flags = eqtype & EQ_TYPEMASK;
2656 eq->tx_chan = tx_chan;
2658 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2659 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2663 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2664 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2668 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2669 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2671 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2675 rc = bus_dmamem_alloc(*tag, va,
2676 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2678 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2682 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2684 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2689 free_ring(sc, *tag, *map, *pa, *va);
2695 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2696 bus_addr_t pa, void *va)
2699 bus_dmamap_unload(tag, map);
2701 bus_dmamem_free(tag, va, map);
2703 bus_dma_tag_destroy(tag);
2709 * Allocates the ring for an ingress queue and an optional freelist. If the
2710 * freelist is specified it will be allocated and then associated with the
2713 * Returns errno on failure. Resources allocated up to that point may still be
2714 * allocated. Caller is responsible for cleanup in case this function fails.
2716 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2717 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2718 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2721 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2722 int intr_idx, int cong)
2724 int rc, i, cntxt_id;
2727 struct port_info *pi = vi->pi;
2728 struct adapter *sc = iq->adapter;
2729 struct sge_params *sp = &sc->params.sge;
2732 len = iq->qsize * IQ_ESIZE;
2733 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2734 (void **)&iq->desc);
2738 bzero(&c, sizeof(c));
2739 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2740 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2741 V_FW_IQ_CMD_VFN(0));
2743 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2746 /* Special handling for firmware event queue */
2747 if (iq == &sc->sge.fwq)
2748 v |= F_FW_IQ_CMD_IQASYNCH;
2750 if (iq->flags & IQ_INTR) {
2751 KASSERT(intr_idx < sc->intr_count,
2752 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2754 v |= F_FW_IQ_CMD_IQANDST;
2755 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2757 c.type_to_iqandstindex = htobe32(v |
2758 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2759 V_FW_IQ_CMD_VIID(vi->viid) |
2760 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2761 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2762 F_FW_IQ_CMD_IQGTSMODE |
2763 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2764 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2765 c.iqsize = htobe16(iq->qsize);
2766 c.iqaddr = htobe64(iq->ba);
2768 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2771 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2773 len = fl->qsize * EQ_ESIZE;
2774 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2775 &fl->ba, (void **)&fl->desc);
2779 /* Allocate space for one software descriptor per buffer. */
2780 rc = alloc_fl_sdesc(fl);
2782 device_printf(sc->dev,
2783 "failed to setup fl software descriptors: %d\n",
2788 if (fl->flags & FL_BUF_PACKING) {
2789 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2790 fl->buf_boundary = sp->pack_boundary;
2792 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2793 fl->buf_boundary = 16;
2795 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2796 fl->buf_boundary = sp->pad_boundary;
2798 c.iqns_to_fl0congen |=
2799 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2800 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2801 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2802 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2805 c.iqns_to_fl0congen |=
2806 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2807 F_FW_IQ_CMD_FL0CONGCIF |
2808 F_FW_IQ_CMD_FL0CONGEN);
2810 c.fl0dcaen_to_fl0cidxfthresh =
2811 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
2812 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
2813 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
2814 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
2815 c.fl0size = htobe16(fl->qsize);
2816 c.fl0addr = htobe64(fl->ba);
2819 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2821 device_printf(sc->dev,
2822 "failed to create ingress queue: %d\n", rc);
2827 iq->gen = F_RSPD_GEN;
2828 iq->intr_next = iq->intr_params;
2829 iq->cntxt_id = be16toh(c.iqid);
2830 iq->abs_id = be16toh(c.physiqid);
2831 iq->flags |= IQ_ALLOCATED;
2833 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2834 if (cntxt_id >= sc->sge.niq) {
2835 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2836 cntxt_id, sc->sge.niq - 1);
2838 sc->sge.iqmap[cntxt_id] = iq;
2843 iq->flags |= IQ_HAS_FL;
2844 fl->cntxt_id = be16toh(c.fl0id);
2845 fl->pidx = fl->cidx = 0;
2847 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2848 if (cntxt_id >= sc->sge.neq) {
2849 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2850 __func__, cntxt_id, sc->sge.neq - 1);
2852 sc->sge.eqmap[cntxt_id] = (void *)fl;
2855 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2856 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2857 uint32_t mask = (1 << s_qpp) - 1;
2858 volatile uint8_t *udb;
2860 udb = sc->udbs_base + UDBS_DB_OFFSET;
2861 udb += (qid >> s_qpp) << PAGE_SHIFT;
2863 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2864 udb += qid << UDBS_SEG_SHIFT;
2867 fl->udb = (volatile void *)udb;
2869 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2872 /* Enough to make sure the SGE doesn't think it's starved */
2873 refill_fl(sc, fl, fl->lowat);
2877 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
2878 uint32_t param, val;
2880 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2881 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2882 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2887 for (i = 0; i < 4; i++) {
2888 if (cong & (1 << i))
2889 val |= 1 << (i << 2);
2893 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2895 /* report error but carry on */
2896 device_printf(sc->dev,
2897 "failed to set congestion manager context for "
2898 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2902 /* Enable IQ interrupts */
2903 atomic_store_rel_int(&iq->state, IQS_IDLE);
2904 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
2905 V_INGRESSQID(iq->cntxt_id));
2911 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2914 struct adapter *sc = iq->adapter;
2918 return (0); /* nothing to do */
2920 dev = vi ? vi->dev : sc->dev;
2922 if (iq->flags & IQ_ALLOCATED) {
2923 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2924 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2925 fl ? fl->cntxt_id : 0xffff, 0xffff);
2928 "failed to free queue %p: %d\n", iq, rc);
2931 iq->flags &= ~IQ_ALLOCATED;
2934 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2936 bzero(iq, sizeof(*iq));
2939 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2943 free_fl_sdesc(sc, fl);
2945 if (mtx_initialized(&fl->fl_lock))
2946 mtx_destroy(&fl->fl_lock);
2948 bzero(fl, sizeof(*fl));
2955 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
2956 struct sysctl_oid *oid, struct sge_fl *fl)
2958 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2960 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2962 children = SYSCTL_CHILDREN(oid);
2964 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
2965 &fl->ba, "bus address of descriptor ring");
2966 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
2967 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
2968 "desc ring size in bytes");
2969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2970 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2971 "SGE context id of the freelist");
2972 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2973 fl_pad ? 1 : 0, "padding enabled");
2974 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2975 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2976 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2977 0, "consumer index");
2978 if (fl->flags & FL_BUF_PACKING) {
2979 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2980 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2982 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2983 0, "producer index");
2984 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2985 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2986 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2987 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2988 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2989 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2990 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2991 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2992 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2993 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2997 alloc_fwq(struct adapter *sc)
3000 struct sge_iq *fwq = &sc->sge.fwq;
3001 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3002 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3004 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3005 fwq->flags |= IQ_INTR; /* always */
3006 if (sc->flags & IS_VF)
3009 intr_idx = sc->intr_count > 1 ? 1 : 0;
3010 fwq->set_tcb_rpl = t4_filter_rpl;
3011 fwq->l2t_write_rpl = do_l2t_write_rpl;
3013 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3015 device_printf(sc->dev,
3016 "failed to create firmware event queue: %d\n", rc);
3020 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
3021 NULL, "firmware event queue");
3022 children = SYSCTL_CHILDREN(oid);
3024 SYSCTL_ADD_UAUTO(&sc->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3025 &fwq->ba, "bus address of descriptor ring");
3026 SYSCTL_ADD_INT(&sc->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3027 fwq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3028 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
3029 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
3030 "absolute id of the queue");
3031 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
3032 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
3033 "SGE context id of the queue");
3034 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
3035 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
3042 free_fwq(struct adapter *sc)
3044 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3048 alloc_mgmtq(struct adapter *sc)
3051 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
3053 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3054 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3056 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
3057 NULL, "management queue");
3059 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
3060 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
3061 sc->sge.fwq.cntxt_id, name);
3062 rc = alloc_wrq(sc, NULL, mgmtq, oid);
3064 device_printf(sc->dev,
3065 "failed to create management queue: %d\n", rc);
3073 free_mgmtq(struct adapter *sc)
3076 return free_wrq(sc, &sc->sge.mgmtq);
3080 tnl_cong(struct port_info *pi, int drop)
3088 return (pi->rx_e_chan_map);
3092 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3093 struct sysctl_oid *oid)
3096 struct adapter *sc = vi->pi->adapter;
3097 struct sysctl_oid_list *children;
3100 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3101 tnl_cong(vi->pi, cong_drop));
3106 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3108 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3109 ("iq_base mismatch"));
3110 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3111 ("PF with non-zero iq_base"));
3114 * The freelist is just barely above the starvation threshold right now,
3115 * fill it up a bit more.
3118 refill_fl(sc, &rxq->fl, 128);
3119 FL_UNLOCK(&rxq->fl);
3121 #if defined(INET) || defined(INET6)
3122 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3125 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3127 if (vi->ifp->if_capenable & IFCAP_LRO)
3128 rxq->iq.flags |= IQ_LRO_ENABLED;
3132 children = SYSCTL_CHILDREN(oid);
3134 snprintf(name, sizeof(name), "%d", idx);
3135 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3137 children = SYSCTL_CHILDREN(oid);
3139 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3140 &rxq->iq.ba, "bus address of descriptor ring");
3141 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3142 rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3143 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3144 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
3145 "absolute id of the queue");
3146 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3147 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
3148 "SGE context id of the queue");
3149 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3150 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
3152 #if defined(INET) || defined(INET6)
3153 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3154 &rxq->lro.lro_queued, 0, NULL);
3155 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3156 &rxq->lro.lro_flushed, 0, NULL);
3158 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3159 &rxq->rxcsum, "# of times hardware assisted with checksum");
3160 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3161 CTLFLAG_RD, &rxq->vlan_extraction,
3162 "# of times hardware extracted 802.1Q tag");
3164 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3170 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3174 #if defined(INET) || defined(INET6)
3176 tcp_lro_free(&rxq->lro);
3177 rxq->lro.ifp = NULL;
3181 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3183 bzero(rxq, sizeof(*rxq));
3190 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3191 int intr_idx, int idx, struct sysctl_oid *oid)
3193 struct port_info *pi = vi->pi;
3195 struct sysctl_oid_list *children;
3198 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3202 children = SYSCTL_CHILDREN(oid);
3204 snprintf(name, sizeof(name), "%d", idx);
3205 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3207 children = SYSCTL_CHILDREN(oid);
3209 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3210 &ofld_rxq->iq.ba, "bus address of descriptor ring");
3211 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3212 ofld_rxq->iq.qsize * IQ_ESIZE, "descriptor ring size in bytes");
3213 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
3214 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3215 "I", "absolute id of the queue");
3216 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
3217 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3218 "I", "SGE context id of the queue");
3219 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3220 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3223 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3229 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3233 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3235 bzero(ofld_rxq, sizeof(*ofld_rxq));
3243 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3244 int idx, struct sysctl_oid *oid)
3247 struct sysctl_oid_list *children;
3248 struct sysctl_ctx_list *ctx;
3251 struct adapter *sc = vi->pi->adapter;
3252 struct netmap_adapter *na = NA(vi->ifp);
3256 len = vi->qsize_rxq * IQ_ESIZE;
3257 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3258 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3262 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3263 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3264 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3270 nm_rxq->iq_cidx = 0;
3271 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3272 nm_rxq->iq_gen = F_RSPD_GEN;
3273 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3274 nm_rxq->fl_sidx = na->num_rx_desc;
3275 nm_rxq->intr_idx = intr_idx;
3276 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
3279 children = SYSCTL_CHILDREN(oid);
3281 snprintf(name, sizeof(name), "%d", idx);
3282 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3284 children = SYSCTL_CHILDREN(oid);
3286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3287 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3288 "I", "absolute id of the queue");
3289 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3290 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3291 "I", "SGE context id of the queue");
3292 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3293 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3296 children = SYSCTL_CHILDREN(oid);
3297 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3299 children = SYSCTL_CHILDREN(oid);
3301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3302 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3303 "I", "SGE context id of the freelist");
3304 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3305 &nm_rxq->fl_cidx, 0, "consumer index");
3306 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3307 &nm_rxq->fl_pidx, 0, "producer index");
3314 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3316 struct adapter *sc = vi->pi->adapter;
3318 if (vi->flags & VI_INIT_DONE)
3319 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
3321 MPASS(nm_rxq->iq_cntxt_id == 0);
3323 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3325 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3332 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3333 struct sysctl_oid *oid)
3337 struct port_info *pi = vi->pi;
3338 struct adapter *sc = pi->adapter;
3339 struct netmap_adapter *na = NA(vi->ifp);
3341 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3343 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3344 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3345 &nm_txq->ba, (void **)&nm_txq->desc);
3349 nm_txq->pidx = nm_txq->cidx = 0;
3350 nm_txq->sidx = na->num_tx_desc;
3352 nm_txq->iqidx = iqidx;
3353 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3354 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3355 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3356 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3357 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
3359 snprintf(name, sizeof(name), "%d", idx);
3360 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3361 NULL, "netmap tx queue");
3362 children = SYSCTL_CHILDREN(oid);
3364 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3365 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3366 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3367 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3369 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3370 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3377 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3379 struct adapter *sc = vi->pi->adapter;
3381 if (vi->flags & VI_INIT_DONE)
3382 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
3384 MPASS(nm_txq->cntxt_id == 0);
3386 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3394 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3397 struct fw_eq_ctrl_cmd c;
3398 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3400 bzero(&c, sizeof(c));
3402 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3403 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3404 V_FW_EQ_CTRL_CMD_VFN(0));
3405 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3406 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3407 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3408 c.physeqid_pkd = htobe32(0);
3409 c.fetchszm_to_iqid =
3410 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
3411 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3412 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3414 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3415 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3416 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
3417 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3418 c.eqaddr = htobe64(eq->ba);
3420 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3422 device_printf(sc->dev,
3423 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3426 eq->flags |= EQ_ALLOCATED;
3428 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3429 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3430 if (cntxt_id >= sc->sge.neq)
3431 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3432 cntxt_id, sc->sge.neq - 1);
3433 sc->sge.eqmap[cntxt_id] = eq;
3439 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3442 struct fw_eq_eth_cmd c;
3443 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3445 bzero(&c, sizeof(c));
3447 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3448 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3449 V_FW_EQ_ETH_CMD_VFN(0));
3450 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3451 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3452 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3453 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3454 c.fetchszm_to_iqid =
3455 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3456 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3457 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3458 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3459 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3460 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3461 c.eqaddr = htobe64(eq->ba);
3463 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3465 device_printf(vi->dev,
3466 "failed to create Ethernet egress queue: %d\n", rc);
3469 eq->flags |= EQ_ALLOCATED;
3471 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3472 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
3473 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3474 if (cntxt_id >= sc->sge.neq)
3475 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3476 cntxt_id, sc->sge.neq - 1);
3477 sc->sge.eqmap[cntxt_id] = eq;
3484 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3487 struct fw_eq_ofld_cmd c;
3488 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3490 bzero(&c, sizeof(c));
3492 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3493 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3494 V_FW_EQ_OFLD_CMD_VFN(0));
3495 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3496 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3497 c.fetchszm_to_iqid =
3498 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3499 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3500 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3502 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3503 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3504 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3505 c.eqaddr = htobe64(eq->ba);
3507 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3509 device_printf(vi->dev,
3510 "failed to create egress queue for TCP offload: %d\n", rc);
3513 eq->flags |= EQ_ALLOCATED;
3515 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3516 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3517 if (cntxt_id >= sc->sge.neq)
3518 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3519 cntxt_id, sc->sge.neq - 1);
3520 sc->sge.eqmap[cntxt_id] = eq;
3527 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3532 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3534 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3535 len = qsize * EQ_ESIZE;
3536 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3537 &eq->ba, (void **)&eq->desc);
3541 eq->pidx = eq->cidx = 0;
3542 eq->equeqidx = eq->dbidx = 0;
3543 eq->doorbells = sc->doorbells;
3545 switch (eq->flags & EQ_TYPEMASK) {
3547 rc = ctrl_eq_alloc(sc, eq);
3551 rc = eth_eq_alloc(sc, vi, eq);
3556 rc = ofld_eq_alloc(sc, vi, eq);
3561 panic("%s: invalid eq type %d.", __func__,
3562 eq->flags & EQ_TYPEMASK);
3565 device_printf(sc->dev,
3566 "failed to allocate egress queue(%d): %d\n",
3567 eq->flags & EQ_TYPEMASK, rc);
3570 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3571 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3572 isset(&eq->doorbells, DOORBELL_WCWR)) {
3573 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3574 uint32_t mask = (1 << s_qpp) - 1;
3575 volatile uint8_t *udb;
3577 udb = sc->udbs_base + UDBS_DB_OFFSET;
3578 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3579 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3580 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3581 clrbit(&eq->doorbells, DOORBELL_WCWR);
3583 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3586 eq->udb = (volatile void *)udb;
3593 free_eq(struct adapter *sc, struct sge_eq *eq)
3597 if (eq->flags & EQ_ALLOCATED) {
3598 switch (eq->flags & EQ_TYPEMASK) {
3600 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3605 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3611 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3617 panic("%s: invalid eq type %d.", __func__,
3618 eq->flags & EQ_TYPEMASK);
3621 device_printf(sc->dev,
3622 "failed to free egress queue (%d): %d\n",
3623 eq->flags & EQ_TYPEMASK, rc);
3626 eq->flags &= ~EQ_ALLOCATED;
3629 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3631 if (mtx_initialized(&eq->eq_lock))
3632 mtx_destroy(&eq->eq_lock);
3634 bzero(eq, sizeof(*eq));
3639 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3640 struct sysctl_oid *oid)
3643 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3644 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3646 rc = alloc_eq(sc, vi, &wrq->eq);
3651 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3652 TAILQ_INIT(&wrq->incomplete_wrs);
3653 STAILQ_INIT(&wrq->wr_list);
3654 wrq->nwr_pending = 0;
3655 wrq->ndesc_needed = 0;
3657 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3658 &wrq->eq.ba, "bus address of descriptor ring");
3659 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3660 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
3661 "desc ring size in bytes");
3662 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3663 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3665 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3667 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3668 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3670 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3671 wrq->eq.sidx, "status page index");
3672 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3673 &wrq->tx_wrs_direct, "# of work requests (direct)");
3674 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3675 &wrq->tx_wrs_copied, "# of work requests (copied)");
3676 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
3677 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
3683 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3687 rc = free_eq(sc, &wrq->eq);
3691 bzero(wrq, sizeof(*wrq));
3696 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3697 struct sysctl_oid *oid)
3700 struct port_info *pi = vi->pi;
3701 struct adapter *sc = pi->adapter;
3702 struct sge_eq *eq = &txq->eq;
3704 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3706 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3709 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3713 rc = alloc_eq(sc, vi, eq);
3715 mp_ring_free(txq->r);
3720 /* Can't fail after this point. */
3723 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
3725 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
3726 ("eq_base mismatch"));
3727 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
3728 ("PF with non-zero eq_base"));
3730 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3732 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3733 if (sc->flags & IS_VF)
3734 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
3735 V_TXPKT_INTF(pi->tx_chan));
3737 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3738 V_TXPKT_INTF(pi->tx_chan) |
3739 V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
3740 V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
3741 V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
3743 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3746 snprintf(name, sizeof(name), "%d", idx);
3747 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3749 children = SYSCTL_CHILDREN(oid);
3751 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3752 &eq->ba, "bus address of descriptor ring");
3753 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3754 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3755 "desc ring size in bytes");
3756 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3757 &eq->abs_id, 0, "absolute id of the queue");
3758 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3759 &eq->cntxt_id, 0, "SGE context id of the queue");
3760 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3761 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3763 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3764 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3766 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
3767 eq->sidx, "status page index");
3769 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3770 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3771 "traffic class (-1 means none)");
3773 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3774 &txq->txcsum, "# of times hardware assisted with checksum");
3775 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3776 CTLFLAG_RD, &txq->vlan_insertion,
3777 "# of times hardware inserted 802.1Q tag");
3778 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3779 &txq->tso_wrs, "# of TSO work requests");
3780 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3781 &txq->imm_wrs, "# of work requests with immediate data");
3782 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3783 &txq->sgl_wrs, "# of work requests with direct SGL");
3784 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3785 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3786 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3787 CTLFLAG_RD, &txq->txpkts0_wrs,
3788 "# of txpkts (type 0) work requests");
3789 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3790 CTLFLAG_RD, &txq->txpkts1_wrs,
3791 "# of txpkts (type 1) work requests");
3792 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3793 CTLFLAG_RD, &txq->txpkts0_pkts,
3794 "# of frames tx'd using type0 txpkts work requests");
3795 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3796 CTLFLAG_RD, &txq->txpkts1_pkts,
3797 "# of frames tx'd using type1 txpkts work requests");
3799 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3800 CTLFLAG_RD, &txq->r->enqueues,
3801 "# of enqueues to the mp_ring for this queue");
3802 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3803 CTLFLAG_RD, &txq->r->drops,
3804 "# of drops in the mp_ring for this queue");
3805 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3806 CTLFLAG_RD, &txq->r->starts,
3807 "# of normal consumer starts in the mp_ring for this queue");
3808 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3809 CTLFLAG_RD, &txq->r->stalls,
3810 "# of consumer stalls in the mp_ring for this queue");
3811 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3812 CTLFLAG_RD, &txq->r->restarts,
3813 "# of consumer restarts in the mp_ring for this queue");
3814 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3815 CTLFLAG_RD, &txq->r->abdications,
3816 "# of consumer abdications in the mp_ring for this queue");
3822 free_txq(struct vi_info *vi, struct sge_txq *txq)
3825 struct adapter *sc = vi->pi->adapter;
3826 struct sge_eq *eq = &txq->eq;
3828 rc = free_eq(sc, eq);
3832 sglist_free(txq->gl);
3833 free(txq->sdesc, M_CXGBE);
3834 mp_ring_free(txq->r);
3836 bzero(txq, sizeof(*txq));
3841 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3843 bus_addr_t *ba = arg;
3846 ("%s meant for single segment mappings only.", __func__));
3848 *ba = error ? 0 : segs->ds_addr;
3852 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3856 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3860 v = fl->dbval | V_PIDX(n);
3862 *fl->udb = htole32(v);
3864 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
3865 IDXINCR(fl->dbidx, n, fl->sidx);
3869 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
3870 * recycled do not count towards this allocation budget.
3872 * Returns non-zero to indicate that this freelist should be added to the list
3873 * of starving freelists.
3876 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3879 struct fl_sdesc *sd;
3882 struct cluster_layout *cll;
3883 struct sw_zone_info *swz;
3884 struct cluster_metadata *clm;
3886 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3888 FL_LOCK_ASSERT_OWNED(fl);
3891 * We always stop at the beginning of the hardware descriptor that's just
3892 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3893 * which would mean an empty freelist to the chip.
3895 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3896 if (fl->pidx == max_pidx * 8)
3899 d = &fl->desc[fl->pidx];
3900 sd = &fl->sdesc[fl->pidx];
3901 cll = &fl->cll_def; /* default layout */
3902 swz = &sc->sge.sw_zone_info[cll->zidx];
3906 if (sd->cl != NULL) {
3908 if (sd->nmbuf == 0) {
3910 * Fast recycle without involving any atomics on
3911 * the cluster's metadata (if the cluster has
3912 * metadata). This happens when all frames
3913 * received in the cluster were small enough to
3914 * fit within a single mbuf each.
3916 fl->cl_fast_recycled++;
3918 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3920 MPASS(clm->refcount == 1);
3926 * Cluster is guaranteed to have metadata. Clusters
3927 * without metadata always take the fast recycle path
3928 * when they're recycled.
3930 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3933 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3935 counter_u64_add(extfree_rels, 1);
3938 sd->cl = NULL; /* gave up my reference */
3940 MPASS(sd->cl == NULL);
3942 cl = uma_zalloc(swz->zone, M_NOWAIT);
3943 if (__predict_false(cl == NULL)) {
3944 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3945 fl->cll_def.zidx == fl->cll_alt.zidx)
3948 /* fall back to the safe zone */
3950 swz = &sc->sge.sw_zone_info[cll->zidx];
3956 pa = pmap_kextract((vm_offset_t)cl);
3960 *d = htobe64(pa | cll->hwidx);
3961 clm = cl_metadata(sc, fl, cll, cl);
3973 if (__predict_false(++fl->pidx % 8 == 0)) {
3974 uint16_t pidx = fl->pidx / 8;
3976 if (__predict_false(pidx == fl->sidx)) {
3982 if (pidx == max_pidx)
3985 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3990 if (fl->pidx / 8 != fl->dbidx)
3993 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3997 * Attempt to refill all starving freelists.
4000 refill_sfl(void *arg)
4002 struct adapter *sc = arg;
4003 struct sge_fl *fl, *fl_temp;
4005 mtx_assert(&sc->sfl_lock, MA_OWNED);
4006 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4008 refill_fl(sc, fl, 64);
4009 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4010 TAILQ_REMOVE(&sc->sfl, fl, link);
4011 fl->flags &= ~FL_STARVING;
4016 if (!TAILQ_EMPTY(&sc->sfl))
4017 callout_schedule(&sc->sfl_callout, hz / 5);
4021 alloc_fl_sdesc(struct sge_fl *fl)
4024 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4031 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4033 struct fl_sdesc *sd;
4034 struct cluster_metadata *clm;
4035 struct cluster_layout *cll;
4039 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4044 clm = cl_metadata(sc, fl, cll, sd->cl);
4046 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4047 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4048 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
4049 counter_u64_add(extfree_rels, 1);
4054 free(fl->sdesc, M_CXGBE);
4059 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4066 rc = sglist_append_mbuf(gl, m);
4067 if (__predict_false(rc != 0)) {
4068 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4069 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4072 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4073 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4074 mbuf_nsegs(m), gl->sg_nseg));
4075 KASSERT(gl->sg_nseg > 0 &&
4076 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
4077 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4078 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
4082 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4085 txpkt_len16(u_int nsegs, u_int tso)
4091 nsegs--; /* first segment is part of ulptx_sgl */
4092 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
4093 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4095 n += sizeof(struct cpl_tx_pkt_lso_core);
4097 return (howmany(n, 16));
4101 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4105 txpkt_vm_len16(u_int nsegs, u_int tso)
4111 nsegs--; /* first segment is part of ulptx_sgl */
4112 n = sizeof(struct fw_eth_tx_pkt_vm_wr) +
4113 sizeof(struct cpl_tx_pkt_core) +
4114 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4116 n += sizeof(struct cpl_tx_pkt_lso_core);
4118 return (howmany(n, 16));
4122 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4126 txpkts0_len16(u_int nsegs)
4132 nsegs--; /* first segment is part of ulptx_sgl */
4133 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4134 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4135 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4137 return (howmany(n, 16));
4141 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4149 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4151 return (howmany(n, 16));
4155 imm_payload(u_int ndesc)
4159 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4160 sizeof(struct cpl_tx_pkt_core);
4166 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4167 * software descriptor, and advance the pidx. It is guaranteed that enough
4168 * descriptors are available.
4170 * The return value is the # of hardware descriptors used.
4173 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
4174 struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
4176 struct sge_eq *eq = &txq->eq;
4177 struct tx_sdesc *txsd;
4178 struct cpl_tx_pkt_core *cpl;
4179 uint32_t ctrl; /* used in many unrelated places */
4181 int csum_type, len16, ndesc, pktlen, nsegs;
4184 TXQ_LOCK_ASSERT_OWNED(txq);
4186 MPASS(available > 0 && available < eq->sidx);
4188 len16 = mbuf_len16(m0);
4189 nsegs = mbuf_nsegs(m0);
4190 pktlen = m0->m_pkthdr.len;
4191 ctrl = sizeof(struct cpl_tx_pkt_core);
4193 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4194 ndesc = howmany(len16, EQ_ESIZE / 16);
4195 MPASS(ndesc <= available);
4197 /* Firmware work request header */
4198 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4199 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
4200 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4202 ctrl = V_FW_WR_LEN16(len16);
4203 wr->equiq_to_len16 = htobe32(ctrl);
4208 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
4209 * vlantci is ignored unless the ethtype is 0x8100, so it's
4210 * simpler to always copy it rather than making it
4211 * conditional. Also, it seems that we do not have to set
4212 * vlantci or fake the ethtype when doing VLAN tag insertion.
4214 m_copydata(m0, 0, sizeof(struct ether_header) + 2, wr->ethmacdst);
4217 if (needs_tso(m0)) {
4218 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4220 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4221 m0->m_pkthdr.l4hlen > 0,
4222 ("%s: mbuf %p needs TSO but missing header lengths",
4225 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4226 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4227 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4228 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4229 ctrl |= V_LSO_ETHHDR_LEN(1);
4230 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4233 lso->lso_ctrl = htobe32(ctrl);
4234 lso->ipid_ofst = htobe16(0);
4235 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4236 lso->seqno_offset = htobe32(0);
4237 lso->len = htobe32(pktlen);
4239 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4240 csum_type = TX_CSUM_TCPIP6;
4242 csum_type = TX_CSUM_TCPIP;
4244 cpl = (void *)(lso + 1);
4248 if (m0->m_pkthdr.csum_flags & CSUM_IP_TCP)
4249 csum_type = TX_CSUM_TCPIP;
4250 else if (m0->m_pkthdr.csum_flags & CSUM_IP_UDP)
4251 csum_type = TX_CSUM_UDPIP;
4252 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_TCP)
4253 csum_type = TX_CSUM_TCPIP6;
4254 else if (m0->m_pkthdr.csum_flags & CSUM_IP6_UDP)
4255 csum_type = TX_CSUM_UDPIP6;
4257 else if (m0->m_pkthdr.csum_flags & CSUM_IP) {
4259 * XXX: The firmware appears to stomp on the
4260 * fragment/flags field of the IP header when
4261 * using TX_CSUM_IP. Fall back to doing
4262 * software checksums.
4270 sump = m_advance(&m, &offset, m0->m_pkthdr.l2hlen +
4271 offsetof(struct ip, ip_sum));
4272 *sump = in_cksum_skip(m0, m0->m_pkthdr.l2hlen +
4273 m0->m_pkthdr.l3hlen, m0->m_pkthdr.l2hlen);
4274 m0->m_pkthdr.csum_flags &= ~CSUM_IP;
4278 cpl = (void *)(wr + 1);
4281 /* Checksum offload */
4283 if (needs_l3_csum(m0) == 0)
4284 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4285 if (csum_type >= 0) {
4286 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0,
4287 ("%s: mbuf %p needs checksum offload but missing header lengths",
4290 if (chip_id(sc) <= CHELSIO_T5) {
4291 ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4294 ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
4297 ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
4298 ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
4300 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4301 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4302 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4303 txq->txcsum++; /* some hardware assistance provided */
4305 /* VLAN tag insertion */
4306 if (needs_vlan_insertion(m0)) {
4307 ctrl1 |= F_TXPKT_VLAN_VLD |
4308 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4309 txq->vlan_insertion++;
4313 cpl->ctrl0 = txq->cpl_ctrl0;
4315 cpl->len = htobe16(pktlen);
4316 cpl->ctrl1 = htobe64(ctrl1);
4319 dst = (void *)(cpl + 1);
4322 * A packet using TSO will use up an entire descriptor for the
4323 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
4324 * If this descriptor is the last descriptor in the ring, wrap
4325 * around to the front of the ring explicitly for the start of
4328 if (dst == (void *)&eq->desc[eq->sidx]) {
4329 dst = (void *)&eq->desc[0];
4330 write_gl_to_txd(txq, m0, &dst, 0);
4332 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4337 txsd = &txq->sdesc[eq->pidx];
4339 txsd->desc_used = ndesc;
4345 * Write a txpkt WR for this packet to the hardware descriptors, update the
4346 * software descriptor, and advance the pidx. It is guaranteed that enough
4347 * descriptors are available.
4349 * The return value is the # of hardware descriptors used.
4352 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
4353 struct mbuf *m0, u_int available)
4355 struct sge_eq *eq = &txq->eq;
4356 struct tx_sdesc *txsd;
4357 struct cpl_tx_pkt_core *cpl;
4358 uint32_t ctrl; /* used in many unrelated places */
4360 int len16, ndesc, pktlen, nsegs;
4363 TXQ_LOCK_ASSERT_OWNED(txq);
4365 MPASS(available > 0 && available < eq->sidx);
4367 len16 = mbuf_len16(m0);
4368 nsegs = mbuf_nsegs(m0);
4369 pktlen = m0->m_pkthdr.len;
4370 ctrl = sizeof(struct cpl_tx_pkt_core);
4372 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
4373 else if (pktlen <= imm_payload(2) && available >= 2) {
4374 /* Immediate data. Recalculate len16 and set nsegs to 0. */
4376 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
4377 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
4380 ndesc = howmany(len16, EQ_ESIZE / 16);
4381 MPASS(ndesc <= available);
4383 /* Firmware work request header */
4384 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4385 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
4386 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
4388 ctrl = V_FW_WR_LEN16(len16);
4389 wr->equiq_to_len16 = htobe32(ctrl);
4392 if (needs_tso(m0)) {
4393 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
4395 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4396 m0->m_pkthdr.l4hlen > 0,
4397 ("%s: mbuf %p needs TSO but missing header lengths",
4400 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
4401 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
4402 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4403 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
4404 ctrl |= V_LSO_ETHHDR_LEN(1);
4405 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4408 lso->lso_ctrl = htobe32(ctrl);
4409 lso->ipid_ofst = htobe16(0);
4410 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4411 lso->seqno_offset = htobe32(0);
4412 lso->len = htobe32(pktlen);
4414 cpl = (void *)(lso + 1);
4418 cpl = (void *)(wr + 1);
4420 /* Checksum offload */
4422 if (needs_l3_csum(m0) == 0)
4423 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4424 if (needs_l4_csum(m0) == 0)
4425 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4426 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4427 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4428 txq->txcsum++; /* some hardware assistance provided */
4430 /* VLAN tag insertion */
4431 if (needs_vlan_insertion(m0)) {
4432 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
4433 txq->vlan_insertion++;
4437 cpl->ctrl0 = txq->cpl_ctrl0;
4439 cpl->len = htobe16(pktlen);
4440 cpl->ctrl1 = htobe64(ctrl1);
4443 dst = (void *)(cpl + 1);
4446 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4451 for (m = m0; m != NULL; m = m->m_next) {
4452 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4458 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4465 txsd = &txq->sdesc[eq->pidx];
4467 txsd->desc_used = ndesc;
4473 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4475 u_int needed, nsegs1, nsegs2, l1, l2;
4477 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4480 nsegs1 = mbuf_nsegs(m);
4481 nsegs2 = mbuf_nsegs(n);
4482 if (nsegs1 + nsegs2 == 2) {
4484 l1 = l2 = txpkts1_len16();
4487 l1 = txpkts0_len16(nsegs1);
4488 l2 = txpkts0_len16(nsegs2);
4490 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4491 needed = howmany(txp->len16, EQ_ESIZE / 16);
4492 if (needed > SGE_MAX_WR_NDESC || needed > available)
4495 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4496 if (txp->plen > 65535)
4500 set_mbuf_len16(m, l1);
4501 set_mbuf_len16(n, l2);
4507 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4509 u_int plen, len16, needed, nsegs;
4511 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4513 nsegs = mbuf_nsegs(m);
4514 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4517 plen = txp->plen + m->m_pkthdr.len;
4521 if (txp->wr_type == 0)
4522 len16 = txpkts0_len16(nsegs);
4524 len16 = txpkts1_len16();
4525 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4526 if (needed > SGE_MAX_WR_NDESC || needed > available)
4531 txp->len16 += len16;
4532 set_mbuf_len16(m, len16);
4538 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4539 * the software descriptor, and advance the pidx. It is guaranteed that enough
4540 * descriptors are available.
4542 * The return value is the # of hardware descriptors used.
4545 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4546 struct mbuf *m0, const struct txpkts *txp, u_int available)
4548 struct sge_eq *eq = &txq->eq;
4549 struct tx_sdesc *txsd;
4550 struct cpl_tx_pkt_core *cpl;
4553 int ndesc, checkwrap;
4557 TXQ_LOCK_ASSERT_OWNED(txq);
4558 MPASS(txp->npkt > 0);
4559 MPASS(txp->plen < 65536);
4561 MPASS(m0->m_nextpkt != NULL);
4562 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4563 MPASS(available > 0 && available < eq->sidx);
4565 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4566 MPASS(ndesc <= available);
4568 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4569 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4570 ctrl = V_FW_WR_LEN16(txp->len16);
4571 wr->equiq_to_len16 = htobe32(ctrl);
4572 wr->plen = htobe16(txp->plen);
4573 wr->npkt = txp->npkt;
4575 wr->type = txp->wr_type;
4579 * At this point we are 16B into a hardware descriptor. If checkwrap is
4580 * set then we know the WR is going to wrap around somewhere. We'll
4581 * check for that at appropriate points.
4583 checkwrap = eq->sidx - ndesc < eq->pidx;
4584 for (m = m0; m != NULL; m = m->m_nextpkt) {
4585 if (txp->wr_type == 0) {
4586 struct ulp_txpkt *ulpmc;
4587 struct ulptx_idata *ulpsc;
4589 /* ULP master command */
4591 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4592 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4593 ulpmc->len = htobe32(mbuf_len16(m));
4595 /* ULP subcommand */
4596 ulpsc = (void *)(ulpmc + 1);
4597 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4599 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4601 cpl = (void *)(ulpsc + 1);
4603 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4604 cpl = (void *)&eq->desc[0];
4609 /* Checksum offload */
4611 if (needs_l3_csum(m) == 0)
4612 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4613 if (needs_l4_csum(m) == 0)
4614 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4615 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4616 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4617 txq->txcsum++; /* some hardware assistance provided */
4619 /* VLAN tag insertion */
4620 if (needs_vlan_insertion(m)) {
4621 ctrl1 |= F_TXPKT_VLAN_VLD |
4622 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4623 txq->vlan_insertion++;
4627 cpl->ctrl0 = txq->cpl_ctrl0;
4629 cpl->len = htobe16(m->m_pkthdr.len);
4630 cpl->ctrl1 = htobe64(ctrl1);
4634 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4635 flitp = (void *)&eq->desc[0];
4637 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4641 if (txp->wr_type == 0) {
4642 txq->txpkts0_pkts += txp->npkt;
4645 txq->txpkts1_pkts += txp->npkt;
4649 txsd = &txq->sdesc[eq->pidx];
4651 txsd->desc_used = ndesc;
4657 * If the SGL ends on an address that is not 16 byte aligned, this function will
4658 * add a 0 filled flit at the end.
4661 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4663 struct sge_eq *eq = &txq->eq;
4664 struct sglist *gl = txq->gl;
4665 struct sglist_seg *seg;
4666 __be64 *flitp, *wrap;
4667 struct ulptx_sgl *usgl;
4668 int i, nflits, nsegs;
4670 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4671 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4672 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4673 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4676 nsegs = gl->sg_nseg;
4679 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4680 flitp = (__be64 *)(*to);
4681 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4682 seg = &gl->sg_segs[0];
4683 usgl = (void *)flitp;
4686 * We start at a 16 byte boundary somewhere inside the tx descriptor
4687 * ring, so we're at least 16 bytes away from the status page. There is
4688 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4691 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4692 V_ULPTX_NSGE(nsegs));
4693 usgl->len0 = htobe32(seg->ss_len);
4694 usgl->addr0 = htobe64(seg->ss_paddr);
4697 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4699 /* Won't wrap around at all */
4701 for (i = 0; i < nsegs - 1; i++, seg++) {
4702 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4703 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4706 usgl->sge[i / 2].len[1] = htobe32(0);
4710 /* Will wrap somewhere in the rest of the SGL */
4712 /* 2 flits already written, write the rest flit by flit */
4713 flitp = (void *)(usgl + 1);
4714 for (i = 0; i < nflits - 2; i++) {
4716 flitp = (void *)eq->desc;
4717 *flitp++ = get_flit(seg, nsegs - 1, i);
4722 MPASS(((uintptr_t)flitp) & 0xf);
4726 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4727 if (__predict_false(flitp == wrap))
4728 *to = (void *)eq->desc;
4730 *to = (void *)flitp;
4734 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4737 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4738 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4740 if (__predict_true((uintptr_t)(*to) + len <=
4741 (uintptr_t)&eq->desc[eq->sidx])) {
4742 bcopy(from, *to, len);
4745 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4747 bcopy(from, *to, portion);
4749 portion = len - portion; /* remaining */
4750 bcopy(from, (void *)eq->desc, portion);
4751 (*to) = (caddr_t)eq->desc + portion;
4756 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4764 clrbit(&db, DOORBELL_WCWR);
4767 switch (ffs(db) - 1) {
4769 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4772 case DOORBELL_WCWR: {
4773 volatile uint64_t *dst, *src;
4777 * Queues whose 128B doorbell segment fits in the page do not
4778 * use relative qid (udb_qid is always 0). Only queues with
4779 * doorbell segments can do WCWR.
4781 KASSERT(eq->udb_qid == 0 && n == 1,
4782 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4783 __func__, eq->doorbells, n, eq->dbidx, eq));
4785 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4788 src = (void *)&eq->desc[i];
4789 while (src != (void *)&eq->desc[i + 1])
4795 case DOORBELL_UDBWC:
4796 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4801 t4_write_reg(sc, sc->sge_kdoorbell_reg,
4802 V_QID(eq->cntxt_id) | V_PIDX(n));
4806 IDXINCR(eq->dbidx, n, eq->sidx);
4810 reclaimable_tx_desc(struct sge_eq *eq)
4814 hw_cidx = read_hw_cidx(eq);
4815 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4819 total_available_tx_desc(struct sge_eq *eq)
4821 uint16_t hw_cidx, pidx;
4823 hw_cidx = read_hw_cidx(eq);
4826 if (pidx == hw_cidx)
4827 return (eq->sidx - 1);
4829 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4832 static inline uint16_t
4833 read_hw_cidx(struct sge_eq *eq)
4835 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4836 uint16_t cidx = spg->cidx; /* stable snapshot */
4838 return (be16toh(cidx));
4842 * Reclaim 'n' descriptors approximately.
4845 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4847 struct tx_sdesc *txsd;
4848 struct sge_eq *eq = &txq->eq;
4849 u_int can_reclaim, reclaimed;
4851 TXQ_LOCK_ASSERT_OWNED(txq);
4855 can_reclaim = reclaimable_tx_desc(eq);
4856 while (can_reclaim && reclaimed < n) {
4858 struct mbuf *m, *nextpkt;
4860 txsd = &txq->sdesc[eq->cidx];
4861 ndesc = txsd->desc_used;
4863 /* Firmware doesn't return "partial" credits. */
4864 KASSERT(can_reclaim >= ndesc,
4865 ("%s: unexpected number of credits: %d, %d",
4866 __func__, can_reclaim, ndesc));
4868 for (m = txsd->m; m != NULL; m = nextpkt) {
4869 nextpkt = m->m_nextpkt;
4870 m->m_nextpkt = NULL;
4874 can_reclaim -= ndesc;
4875 IDXINCR(eq->cidx, ndesc, eq->sidx);
4882 tx_reclaim(void *arg, int n)
4884 struct sge_txq *txq = arg;
4885 struct sge_eq *eq = &txq->eq;
4888 if (TXQ_TRYLOCK(txq) == 0)
4890 n = reclaim_tx_descs(txq, 32);
4891 if (eq->cidx == eq->pidx)
4892 eq->equeqidx = eq->pidx;
4898 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4900 int i = (idx / 3) * 2;
4906 rc = htobe32(segs[i].ss_len);
4908 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4913 return (htobe64(segs[i].ss_paddr));
4915 return (htobe64(segs[i + 1].ss_paddr));
4922 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4924 int8_t zidx, hwidx, idx;
4925 uint16_t region1, region3;
4926 int spare, spare_needed, n;
4927 struct sw_zone_info *swz;
4928 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4931 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4932 * large enough for the max payload and cluster metadata. Otherwise
4933 * settle for the largest bufsize that leaves enough room in the cluster
4936 * Without buffer packing: Look for the smallest zone which has a
4937 * bufsize large enough for the max payload. Settle for the largest
4938 * bufsize available if there's nothing big enough for max payload.
4940 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4941 swz = &sc->sge.sw_zone_info[0];
4943 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4944 if (swz->size > largest_rx_cluster) {
4945 if (__predict_true(hwidx != -1))
4949 * This is a misconfiguration. largest_rx_cluster is
4950 * preventing us from finding a refill source. See
4951 * dev.t5nex.<n>.buffer_sizes to figure out why.
4953 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4954 " refill source for fl %p (dma %u). Ignored.\n",
4955 largest_rx_cluster, fl, maxp);
4957 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4958 hwb = &hwb_list[idx];
4959 spare = swz->size - hwb->size;
4960 if (spare < spare_needed)
4963 hwidx = idx; /* best option so far */
4964 if (hwb->size >= maxp) {
4966 if ((fl->flags & FL_BUF_PACKING) == 0)
4967 goto done; /* stop looking (not packing) */
4969 if (swz->size >= safest_rx_cluster)
4970 goto done; /* stop looking (packing) */
4972 break; /* keep looking, next zone */
4976 /* A usable hwidx has been located. */
4978 hwb = &hwb_list[hwidx];
4980 swz = &sc->sge.sw_zone_info[zidx];
4982 region3 = swz->size - hwb->size;
4985 * Stay within this zone and see if there is a better match when mbuf
4986 * inlining is allowed. Remember that the hwidx's are sorted in
4987 * decreasing order of size (so in increasing order of spare area).
4989 for (idx = hwidx; idx != -1; idx = hwb->next) {
4990 hwb = &hwb_list[idx];
4991 spare = swz->size - hwb->size;
4993 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4997 * Do not inline mbufs if doing so would violate the pad/pack
4998 * boundary alignment requirement.
5000 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
5002 if (fl->flags & FL_BUF_PACKING &&
5003 (MSIZE % sc->params.sge.pack_boundary) != 0)
5006 if (spare < CL_METADATA_SIZE + MSIZE)
5008 n = (spare - CL_METADATA_SIZE) / MSIZE;
5009 if (n > howmany(hwb->size, maxp))
5013 if (fl->flags & FL_BUF_PACKING) {
5014 region1 = n * MSIZE;
5015 region3 = spare - region1;
5018 region3 = spare - region1;
5023 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
5024 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
5025 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
5026 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
5027 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
5028 sc->sge.sw_zone_info[zidx].size,
5029 ("%s: bad buffer layout for fl %p, maxp %d. "
5030 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5031 sc->sge.sw_zone_info[zidx].size, region1,
5032 sc->sge.hw_buf_info[hwidx].size, region3));
5033 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
5034 KASSERT(region3 >= CL_METADATA_SIZE,
5035 ("%s: no room for metadata. fl %p, maxp %d; "
5036 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5037 sc->sge.sw_zone_info[zidx].size, region1,
5038 sc->sge.hw_buf_info[hwidx].size, region3));
5039 KASSERT(region1 % MSIZE == 0,
5040 ("%s: bad mbuf region for fl %p, maxp %d. "
5041 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
5042 sc->sge.sw_zone_info[zidx].size, region1,
5043 sc->sge.hw_buf_info[hwidx].size, region3));
5046 fl->cll_def.zidx = zidx;
5047 fl->cll_def.hwidx = hwidx;
5048 fl->cll_def.region1 = region1;
5049 fl->cll_def.region3 = region3;
5053 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
5055 struct sge *s = &sc->sge;
5056 struct hw_buf_info *hwb;
5057 struct sw_zone_info *swz;
5061 if (fl->flags & FL_BUF_PACKING)
5062 hwidx = s->safe_hwidx2; /* with room for metadata */
5063 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
5064 hwidx = s->safe_hwidx2;
5065 hwb = &s->hw_buf_info[hwidx];
5066 swz = &s->sw_zone_info[hwb->zidx];
5067 spare = swz->size - hwb->size;
5069 /* no good if there isn't room for an mbuf as well */
5070 if (spare < CL_METADATA_SIZE + MSIZE)
5071 hwidx = s->safe_hwidx1;
5073 hwidx = s->safe_hwidx1;
5076 /* No fallback source */
5077 fl->cll_alt.hwidx = -1;
5078 fl->cll_alt.zidx = -1;
5083 hwb = &s->hw_buf_info[hwidx];
5084 swz = &s->sw_zone_info[hwb->zidx];
5085 spare = swz->size - hwb->size;
5086 fl->cll_alt.hwidx = hwidx;
5087 fl->cll_alt.zidx = hwb->zidx;
5088 if (allow_mbufs_in_cluster &&
5089 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
5090 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
5092 fl->cll_alt.region1 = 0;
5093 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
5097 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5099 mtx_lock(&sc->sfl_lock);
5101 if ((fl->flags & FL_DOOMED) == 0) {
5102 fl->flags |= FL_STARVING;
5103 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5104 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5107 mtx_unlock(&sc->sfl_lock);
5111 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5113 struct sge_wrq *wrq = (void *)eq;
5115 atomic_readandclear_int(&eq->equiq);
5116 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5120 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5122 struct sge_txq *txq = (void *)eq;
5124 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5126 atomic_readandclear_int(&eq->equiq);
5127 mp_ring_check_drainage(txq->r, 0);
5128 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5132 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5135 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5136 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5137 struct adapter *sc = iq->adapter;
5138 struct sge *s = &sc->sge;
5140 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5141 &handle_wrq_egr_update, &handle_eth_egr_update,
5142 &handle_wrq_egr_update};
5144 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5147 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5148 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5153 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5154 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5155 offsetof(struct cpl_fw6_msg, data));
5158 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5160 struct adapter *sc = iq->adapter;
5161 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5163 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5166 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5167 const struct rss_header *rss2;
5169 rss2 = (const struct rss_header *)&cpl->data[0];
5170 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5173 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5177 * t4_handle_wrerr_rpl - process a FW work request error message
5178 * @adap: the adapter
5179 * @rpl: start of the FW message
5182 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5184 u8 opcode = *(const u8 *)rpl;
5185 const struct fw_error_cmd *e = (const void *)rpl;
5188 if (opcode != FW_ERROR_CMD) {
5190 "%s: Received WRERR_RPL message with opcode %#x\n",
5191 device_get_nameunit(adap->dev), opcode);
5194 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5195 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5197 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5198 case FW_ERROR_TYPE_EXCEPTION:
5199 log(LOG_ERR, "exception info:\n");
5200 for (i = 0; i < nitems(e->u.exception.info); i++)
5201 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5202 be32toh(e->u.exception.info[i]));
5205 case FW_ERROR_TYPE_HWMODULE:
5206 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5207 be32toh(e->u.hwmodule.regaddr),
5208 be32toh(e->u.hwmodule.regval));
5210 case FW_ERROR_TYPE_WR:
5211 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5212 be16toh(e->u.wr.cidx),
5213 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
5214 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
5215 be32toh(e->u.wr.eqid));
5216 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
5217 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
5221 case FW_ERROR_TYPE_ACL:
5222 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
5223 be16toh(e->u.acl.cidx),
5224 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
5225 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
5226 be32toh(e->u.acl.eqid),
5227 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
5229 for (i = 0; i < nitems(e->u.acl.val); i++)
5230 log(LOG_ERR, " %02x", e->u.acl.val[i]);
5234 log(LOG_ERR, "type %#x\n",
5235 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
5242 sysctl_uint16(SYSCTL_HANDLER_ARGS)
5244 uint16_t *id = arg1;
5247 return sysctl_handle_int(oidp, &i, 0, req);
5251 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
5253 struct sge *s = arg1;
5254 struct hw_buf_info *hwb = &s->hw_buf_info[0];
5255 struct sw_zone_info *swz = &s->sw_zone_info[0];
5260 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5261 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
5262 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
5267 sbuf_printf(&sb, "%u%c ", hwb->size, c);
5271 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5277 sysctl_tc(SYSCTL_HANDLER_ARGS)
5279 struct vi_info *vi = arg1;
5280 struct port_info *pi;
5282 struct sge_txq *txq;
5283 struct tx_cl_rl_params *tc;
5284 int qidx = arg2, rc, tc_idx;
5285 uint32_t fw_queue, fw_class;
5287 MPASS(qidx >= 0 && qidx < vi->ntxq);
5290 txq = &sc->sge.txq[vi->first_txq + qidx];
5292 tc_idx = txq->tc_idx;
5293 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
5294 if (rc != 0 || req->newptr == NULL)
5297 if (sc->flags & IS_VF)
5300 /* Note that -1 is legitimate input (it means unbind). */
5301 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
5304 mtx_lock(&sc->tc_lock);
5305 if (tc_idx == txq->tc_idx) {
5306 rc = 0; /* No change, nothing to do. */
5310 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
5311 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
5312 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
5315 fw_class = 0xffffffff; /* Unbind. */
5318 * Bind to a different class.
5320 tc = &pi->sched_params->cl_rl[tc_idx];
5321 if (tc->flags & TX_CLRL_ERROR) {
5322 /* Previous attempt to set the cl-rl params failed. */
5327 * Ok to proceed. Place a reference on the new class
5328 * while still holding on to the reference on the
5329 * previous class, if any.
5335 mtx_unlock(&sc->tc_lock);
5337 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
5340 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
5341 end_synchronized_op(sc, 0);
5343 mtx_lock(&sc->tc_lock);
5345 if (txq->tc_idx != -1) {
5346 tc = &pi->sched_params->cl_rl[txq->tc_idx];
5347 MPASS(tc->refcount > 0);
5350 txq->tc_idx = tc_idx;
5351 } else if (tc_idx != -1) {
5352 tc = &pi->sched_params->cl_rl[tc_idx];
5353 MPASS(tc->refcount > 0);
5357 mtx_unlock(&sc->tc_lock);