2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
35 #include <sys/eventhandler.h>
37 #include <sys/socket.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sglist.h>
45 #include <sys/sysctl.h>
47 #include <sys/counter.h>
49 #include <net/ethernet.h>
51 #include <net/if_vlan_var.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h>
54 #include <netinet/ip6.h>
55 #include <netinet/tcp.h>
56 #include <machine/md_var.h>
60 #include <machine/bus.h>
61 #include <sys/selinfo.h>
62 #include <net/if_var.h>
63 #include <net/netmap.h>
64 #include <dev/netmap/netmap_kern.h>
67 #include "common/common.h"
68 #include "common/t4_regs.h"
69 #include "common/t4_regs_values.h"
70 #include "common/t4_msg.h"
71 #include "t4_mp_ring.h"
73 #ifdef T4_PKT_TIMESTAMP
74 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
76 #define RX_COPY_THRESHOLD MINCLSIZE
80 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
81 * 0-7 are valid values.
84 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
87 * Pad ethernet payload up to this boundary.
88 * -1: driver should figure out a good value.
90 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
93 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
97 * -1: driver should figure out a good value.
98 * 64 or 128 are the only other valid values.
101 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
105 * -1: no congestion feedback (not recommended).
106 * 0: backpressure the channel instead of dropping packets right away.
107 * 1: no backpressure, drop packets for the congested queue immediately.
109 static int cong_drop = 0;
110 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
113 * Deliver multiple frames in the same free list buffer if they fit.
114 * -1: let the driver decide whether to enable buffer packing or not.
115 * 0: disable buffer packing.
116 * 1: enable buffer packing.
118 static int buffer_packing = -1;
119 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
122 * Start next frame in a packed buffer at this boundary.
123 * -1: driver should figure out a good value.
124 * T4: driver will ignore this and use the same value as fl_pad above.
125 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
127 static int fl_pack = -1;
128 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
131 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
132 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
133 * 1: ok to create mbuf(s) within a cluster if there is room.
135 static int allow_mbufs_in_cluster = 1;
136 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
139 * Largest rx cluster size that the driver is allowed to allocate.
141 static int largest_rx_cluster = MJUM16BYTES;
142 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
145 * Size of cluster allocation that's most likely to succeed. The driver will
146 * fall back to this size if it fails to allocate clusters larger than this.
148 static int safest_rx_cluster = PAGE_SIZE;
149 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
152 u_int wr_type; /* type 0 or type 1 */
153 u_int npkt; /* # of packets in this work request */
154 u_int plen; /* total payload (sum of all packets) */
155 u_int len16; /* # of 16B pieces used by this work request */
158 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
161 struct sglist_seg seg[TX_SGL_SEGS];
164 static int service_iq(struct sge_iq *, int);
165 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
166 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
167 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
168 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
169 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
171 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
172 bus_addr_t *, void **);
173 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
175 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
177 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
178 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
180 static int alloc_fwq(struct adapter *);
181 static int free_fwq(struct adapter *);
182 static int alloc_mgmtq(struct adapter *);
183 static int free_mgmtq(struct adapter *);
184 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
185 struct sysctl_oid *);
186 static int free_rxq(struct vi_info *, struct sge_rxq *);
188 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
189 struct sysctl_oid *);
190 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
193 static int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int,
194 struct sysctl_oid *);
195 static int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
196 static int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int,
197 struct sysctl_oid *);
198 static int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
200 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
201 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
203 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
205 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
206 static int free_eq(struct adapter *, struct sge_eq *);
207 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
208 struct sysctl_oid *);
209 static int free_wrq(struct adapter *, struct sge_wrq *);
210 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
211 struct sysctl_oid *);
212 static int free_txq(struct vi_info *, struct sge_txq *);
213 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
214 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
215 static int refill_fl(struct adapter *, struct sge_fl *, int);
216 static void refill_sfl(void *);
217 static int alloc_fl_sdesc(struct sge_fl *);
218 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
219 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
220 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
221 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
223 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
224 static inline u_int txpkt_len16(u_int, u_int);
225 static inline u_int txpkts0_len16(u_int);
226 static inline u_int txpkts1_len16(void);
227 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
228 struct mbuf *, u_int);
229 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
230 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
231 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
232 struct mbuf *, const struct txpkts *, u_int);
233 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
234 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
235 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
236 static inline uint16_t read_hw_cidx(struct sge_eq *);
237 static inline u_int reclaimable_tx_desc(struct sge_eq *);
238 static inline u_int total_available_tx_desc(struct sge_eq *);
239 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
240 static void tx_reclaim(void *, int);
241 static __be64 get_flit(struct sglist_seg *, int, int);
242 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
244 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
246 static void wrq_tx_drain(void *, int);
247 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
249 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
250 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
251 static int sysctl_tc(SYSCTL_HANDLER_ARGS);
253 static counter_u64_t extfree_refs;
254 static counter_u64_t extfree_rels;
257 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
263 if (fl_pktshift < 0 || fl_pktshift > 7) {
264 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
265 " using 2 instead.\n", fl_pktshift);
269 if (spg_len != 64 && spg_len != 128) {
272 #if defined(__i386__) || defined(__amd64__)
273 len = cpu_clflush_line_size > 64 ? 128 : 64;
278 printf("Invalid hw.cxgbe.spg_len value (%d),"
279 " using %d instead.\n", spg_len, len);
284 if (cong_drop < -1 || cong_drop > 1) {
285 printf("Invalid hw.cxgbe.cong_drop value (%d),"
286 " using 0 instead.\n", cong_drop);
290 extfree_refs = counter_u64_alloc(M_WAITOK);
291 extfree_rels = counter_u64_alloc(M_WAITOK);
292 counter_u64_zero(extfree_refs);
293 counter_u64_zero(extfree_rels);
297 t4_sge_modunload(void)
300 counter_u64_free(extfree_refs);
301 counter_u64_free(extfree_rels);
305 t4_sge_extfree_refs(void)
309 rels = counter_u64_fetch(extfree_rels);
310 refs = counter_u64_fetch(extfree_refs);
312 return (refs - rels);
316 t4_init_sge_cpl_handlers(struct adapter *sc)
319 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
320 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
321 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
322 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
323 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
327 setup_pad_and_pack_boundaries(struct adapter *sc)
333 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
335 * If there is any chance that we might use buffer packing and
336 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
337 * it to 32 in all other cases.
339 pad = is_t4(sc) && buffer_packing ? 64 : 32;
342 * For fl_pad = 0 we'll still write a reasonable value to the
343 * register but all the freelists will opt out of padding.
344 * We'll complain here only if the user tried to set it to a
345 * value greater than 0 that was invalid.
348 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
349 " (%d), using %d instead.\n", fl_pad, pad);
352 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
353 v = V_INGPADBOUNDARY(ilog2(pad) - 5);
354 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
357 if (fl_pack != -1 && fl_pack != pad) {
358 /* Complain but carry on. */
359 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
360 " using %d instead.\n", fl_pack, pad);
366 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
367 !powerof2(fl_pack)) {
368 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
369 MPASS(powerof2(pack));
377 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
378 " (%d), using %d instead.\n", fl_pack, pack);
381 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
383 v = V_INGPACKBOUNDARY(0);
385 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
387 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
388 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
392 * adap->params.vpd.cclk must be set up before this is called.
395 t4_tweak_chip_settings(struct adapter *sc)
399 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
400 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
401 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
402 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
403 static int sge_flbuf_sizes[] = {
405 #if MJUMPAGESIZE != MCLBYTES
407 MJUMPAGESIZE - CL_METADATA_SIZE,
408 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
412 MCLBYTES - MSIZE - CL_METADATA_SIZE,
413 MJUM9BYTES - CL_METADATA_SIZE,
414 MJUM16BYTES - CL_METADATA_SIZE,
417 KASSERT(sc->flags & MASTER_PF,
418 ("%s: trying to change chip settings when not master.", __func__));
420 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
421 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
422 V_EGRSTATUSPAGESIZE(spg_len == 128);
423 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
425 setup_pad_and_pack_boundaries(sc);
427 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
428 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
429 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
430 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
431 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
432 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
433 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
434 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
435 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
437 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
438 ("%s: hw buffer size table too big", __func__));
439 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
440 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
444 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
445 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
446 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
448 KASSERT(intr_timer[0] <= timer_max,
449 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
451 for (i = 1; i < nitems(intr_timer); i++) {
452 KASSERT(intr_timer[i] >= intr_timer[i - 1],
453 ("%s: timers not listed in increasing order (%d)",
456 while (intr_timer[i] > timer_max) {
457 if (i == nitems(intr_timer) - 1) {
458 intr_timer[i] = timer_max;
461 intr_timer[i] += intr_timer[i - 1];
466 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
467 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
468 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
469 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
470 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
471 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
472 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
473 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
474 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
476 /* 4K, 16K, 64K, 256K DDP "page sizes" */
477 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
478 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
480 m = v = F_TDDPTAGTCB;
481 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
483 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
485 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
486 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
490 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
491 * padding is is use the buffer's start and end need to be aligned to the pad
492 * boundary as well. We'll just make sure that the size is a multiple of the
493 * boundary here, it is up to the buffer allocation code to make sure the start
494 * of the buffer is aligned as well.
497 hwsz_ok(struct adapter *sc, int hwsz)
499 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
501 return (hwsz >= 64 && (hwsz & mask) == 0);
505 * XXX: driver really should be able to deal with unexpected settings.
508 t4_read_chip_settings(struct adapter *sc)
510 struct sge *s = &sc->sge;
511 struct sge_params *sp = &sc->params.sge;
514 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
515 static int sw_buf_sizes[] = { /* Sorted by size */
517 #if MJUMPAGESIZE != MCLBYTES
523 struct sw_zone_info *swz, *safe_swz;
524 struct hw_buf_info *hwb;
526 t4_init_sge_params(sc);
530 r = t4_read_reg(sc, A_SGE_CONTROL);
532 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
537 * If this changes then every single use of PAGE_SHIFT in the driver
538 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
540 if (sp->page_shift != PAGE_SHIFT) {
541 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
545 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
546 hwb = &s->hw_buf_info[0];
547 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
548 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
550 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
555 * Create a sorted list in decreasing order of hw buffer sizes (and so
556 * increasing order of spare area) for each software zone.
558 * If padding is enabled then the start and end of the buffer must align
559 * to the pad boundary; if packing is enabled then they must align with
560 * the pack boundary as well. Allocations from the cluster zones are
561 * aligned to min(size, 4K), so the buffer starts at that alignment and
562 * ends at hwb->size alignment. If mbuf inlining is allowed the
563 * starting alignment will be reduced to MSIZE and the driver will
564 * exercise appropriate caution when deciding on the best buffer layout
567 n = 0; /* no usable buffer size to begin with */
568 swz = &s->sw_zone_info[0];
570 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
571 int8_t head = -1, tail = -1;
573 swz->size = sw_buf_sizes[i];
574 swz->zone = m_getzone(swz->size);
575 swz->type = m_gettype(swz->size);
577 if (swz->size < PAGE_SIZE) {
578 MPASS(powerof2(swz->size));
579 if (fl_pad && (swz->size % sp->pad_boundary != 0))
583 if (swz->size == safest_rx_cluster)
586 hwb = &s->hw_buf_info[0];
587 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
588 if (hwb->zidx != -1 || hwb->size > swz->size)
592 MPASS(hwb->size % sp->pad_boundary == 0);
597 else if (hwb->size < s->hw_buf_info[tail].size) {
598 s->hw_buf_info[tail].next = j;
602 struct hw_buf_info *t;
604 for (cur = &head; *cur != -1; cur = &t->next) {
605 t = &s->hw_buf_info[*cur];
606 if (hwb->size == t->size) {
610 if (hwb->size > t->size) {
618 swz->head_hwidx = head;
619 swz->tail_hwidx = tail;
623 if (swz->size - s->hw_buf_info[tail].size >=
625 sc->flags |= BUF_PACKING_OK;
629 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
635 if (safe_swz != NULL) {
636 s->safe_hwidx1 = safe_swz->head_hwidx;
637 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
640 hwb = &s->hw_buf_info[i];
643 MPASS(hwb->size % sp->pad_boundary == 0);
645 spare = safe_swz->size - hwb->size;
646 if (spare >= CL_METADATA_SIZE) {
653 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
654 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
656 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
660 m = v = F_TDDPTAGTCB;
661 r = t4_read_reg(sc, A_ULP_RX_CTL);
663 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
667 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
669 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
670 r = t4_read_reg(sc, A_TP_PARA_REG5);
672 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
676 t4_init_tp_params(sc);
678 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
679 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
685 t4_create_dma_tag(struct adapter *sc)
689 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
690 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
691 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
694 device_printf(sc->dev,
695 "failed to create main DMA tag: %d\n", rc);
702 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
703 struct sysctl_oid_list *children)
705 struct sge_params *sp = &sc->params.sge;
707 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
708 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
709 "freelist buffer sizes");
711 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
712 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
714 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
715 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
717 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
718 NULL, sp->spg_len, "status page size (bytes)");
720 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
721 NULL, cong_drop, "congestion drop setting");
723 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
724 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
728 t4_destroy_dma_tag(struct adapter *sc)
731 bus_dma_tag_destroy(sc->dmat);
737 * Allocate and initialize the firmware event queue and the management queue.
739 * Returns errno on failure. Resources allocated up to that point may still be
740 * allocated. Caller is responsible for cleanup in case this function fails.
743 t4_setup_adapter_queues(struct adapter *sc)
747 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
749 sysctl_ctx_init(&sc->ctx);
750 sc->flags |= ADAP_SYSCTL_CTX;
753 * Firmware event queue
760 * Management queue. This is just a control queue that uses the fwq as
763 rc = alloc_mgmtq(sc);
772 t4_teardown_adapter_queues(struct adapter *sc)
775 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
777 /* Do this before freeing the queue */
778 if (sc->flags & ADAP_SYSCTL_CTX) {
779 sysctl_ctx_free(&sc->ctx);
780 sc->flags &= ~ADAP_SYSCTL_CTX;
790 first_vector(struct vi_info *vi)
792 struct adapter *sc = vi->pi->adapter;
794 if (sc->intr_count == 1)
797 return (vi->first_intr);
801 * Given an arbitrary "index," come up with an iq that can be used by other
802 * queues (of this VI) for interrupt forwarding, SGE egress updates, etc.
803 * The iq returned is guaranteed to be something that takes direct interrupts.
805 static struct sge_iq *
806 vi_intr_iq(struct vi_info *vi, int idx)
808 struct adapter *sc = vi->pi->adapter;
809 struct sge *s = &sc->sge;
810 struct sge_iq *iq = NULL;
813 if (sc->intr_count == 1)
814 return (&sc->sge.fwq);
816 KASSERT(!(vi->flags & VI_NETMAP),
817 ("%s: called on netmap VI", __func__));
820 ("%s: vi %p has no exclusive interrupts, total interrupts = %d",
821 __func__, vi, sc->intr_count));
824 if (vi->flags & INTR_RXQ) {
826 iq = &s->rxq[vi->first_rxq + i].iq;
832 if (vi->flags & INTR_OFLD_RXQ) {
833 if (i < vi->nofldrxq) {
834 iq = &s->ofld_rxq[vi->first_ofld_rxq + i].iq;
840 panic("%s: vi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
841 vi, vi->flags & INTR_ALL, idx, nintr);
844 KASSERT(iq->flags & IQ_INTR,
845 ("%s: iq %p (vi %p, intr_flags 0x%lx, idx %d)", __func__, iq, vi,
846 vi->flags & INTR_ALL, idx));
850 /* Maximum payload that can be delivered with a single iq descriptor */
852 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
858 payload = sc->tt.rx_coalesce ?
859 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
862 /* large enough even when hw VLAN extraction is disabled */
863 payload = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
864 ETHER_VLAN_ENCAP_LEN + mtu;
873 t4_setup_vi_queues(struct vi_info *vi)
875 int rc = 0, i, j, intr_idx, iqid;
878 struct sge_wrq *ctrlq;
880 struct sge_ofld_rxq *ofld_rxq;
881 struct sge_wrq *ofld_txq;
884 struct sge_nm_rxq *nm_rxq;
885 struct sge_nm_txq *nm_txq;
888 struct port_info *pi = vi->pi;
889 struct adapter *sc = pi->adapter;
890 struct ifnet *ifp = vi->ifp;
891 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
892 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
893 int maxp, mtu = ifp->if_mtu;
895 /* Interrupt vector to start from (when using multiple vectors) */
896 intr_idx = first_vector(vi);
899 if (vi->flags & VI_NETMAP) {
901 * We don't have buffers to back the netmap rx queues
902 * right now so we create the queues in a way that
903 * doesn't set off any congestion signal in the chip.
905 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
906 CTLFLAG_RD, NULL, "rx queues");
907 for_each_nm_rxq(vi, i, nm_rxq) {
908 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
914 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq",
915 CTLFLAG_RD, NULL, "tx queues");
916 for_each_nm_txq(vi, i, nm_txq) {
917 iqid = vi->first_rxq + (i % vi->nrxq);
918 rc = alloc_nm_txq(vi, nm_txq, iqid, i, oid);
927 * First pass over all NIC and TOE rx queues:
928 * a) initialize iq and fl
929 * b) allocate queue iff it will take direct interrupts.
931 maxp = mtu_to_max_payload(sc, mtu, 0);
932 if (vi->flags & INTR_RXQ) {
933 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
934 CTLFLAG_RD, NULL, "rx queues");
936 for_each_rxq(vi, i, rxq) {
938 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
940 snprintf(name, sizeof(name), "%s rxq%d-fl",
941 device_get_nameunit(vi->dev), i);
942 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
944 if (vi->flags & INTR_RXQ) {
945 rxq->iq.flags |= IQ_INTR;
946 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
953 maxp = mtu_to_max_payload(sc, mtu, 1);
954 if (vi->flags & INTR_OFLD_RXQ) {
955 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
957 "rx queues for offloaded TCP connections");
959 for_each_ofld_rxq(vi, i, ofld_rxq) {
961 init_iq(&ofld_rxq->iq, sc, vi->tmr_idx, vi->pktc_idx,
964 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
965 device_get_nameunit(vi->dev), i);
966 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
968 if (vi->flags & INTR_OFLD_RXQ) {
969 ofld_rxq->iq.flags |= IQ_INTR;
970 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
979 * Second pass over all NIC and TOE rx queues. The queues forwarding
980 * their interrupts are allocated now.
983 if (!(vi->flags & INTR_RXQ)) {
984 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
985 CTLFLAG_RD, NULL, "rx queues");
986 for_each_rxq(vi, i, rxq) {
987 MPASS(!(rxq->iq.flags & IQ_INTR));
989 intr_idx = vi_intr_iq(vi, j)->abs_id;
991 rc = alloc_rxq(vi, rxq, intr_idx, i, oid);
998 if (vi->nofldrxq != 0 && !(vi->flags & INTR_OFLD_RXQ)) {
999 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1001 "rx queues for offloaded TCP connections");
1002 for_each_ofld_rxq(vi, i, ofld_rxq) {
1003 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1005 intr_idx = vi_intr_iq(vi, j)->abs_id;
1007 rc = alloc_ofld_rxq(vi, ofld_rxq, intr_idx, i, oid);
1016 * Now the tx queues. Only one pass needed.
1018 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1021 for_each_txq(vi, i, txq) {
1022 iqid = vi_intr_iq(vi, j)->cntxt_id;
1023 snprintf(name, sizeof(name), "%s txq%d",
1024 device_get_nameunit(vi->dev), i);
1025 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan, iqid,
1028 rc = alloc_txq(vi, txq, i, oid);
1034 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1035 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1036 for_each_ofld_txq(vi, i, ofld_txq) {
1037 struct sysctl_oid *oid2;
1039 iqid = vi_intr_iq(vi, j)->cntxt_id;
1040 snprintf(name, sizeof(name), "%s ofld_txq%d",
1041 device_get_nameunit(vi->dev), i);
1042 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq, pi->tx_chan,
1045 snprintf(name, sizeof(name), "%d", i);
1046 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1047 name, CTLFLAG_RD, NULL, "offload tx queue");
1049 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1057 * Finally, the control queue.
1059 if (!IS_MAIN_VI(vi))
1061 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1062 NULL, "ctrl queue");
1063 ctrlq = &sc->sge.ctrlq[pi->port_id];
1064 iqid = vi_intr_iq(vi, 0)->cntxt_id;
1065 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(vi->dev));
1066 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid,
1068 rc = alloc_wrq(sc, vi, ctrlq, oid);
1072 t4_teardown_vi_queues(vi);
1081 t4_teardown_vi_queues(struct vi_info *vi)
1084 struct port_info *pi = vi->pi;
1085 struct adapter *sc = pi->adapter;
1086 struct sge_rxq *rxq;
1087 struct sge_txq *txq;
1089 struct sge_ofld_rxq *ofld_rxq;
1090 struct sge_wrq *ofld_txq;
1093 struct sge_nm_rxq *nm_rxq;
1094 struct sge_nm_txq *nm_txq;
1097 /* Do this before freeing the queues */
1098 if (vi->flags & VI_SYSCTL_CTX) {
1099 sysctl_ctx_free(&vi->ctx);
1100 vi->flags &= ~VI_SYSCTL_CTX;
1104 if (vi->flags & VI_NETMAP) {
1105 for_each_nm_txq(vi, i, nm_txq) {
1106 free_nm_txq(vi, nm_txq);
1109 for_each_nm_rxq(vi, i, nm_rxq) {
1110 free_nm_rxq(vi, nm_rxq);
1117 * Take down all the tx queues first, as they reference the rx queues
1118 * (for egress updates, etc.).
1122 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1124 for_each_txq(vi, i, txq) {
1128 for_each_ofld_txq(vi, i, ofld_txq) {
1129 free_wrq(sc, ofld_txq);
1134 * Then take down the rx queues that forward their interrupts, as they
1135 * reference other rx queues.
1138 for_each_rxq(vi, i, rxq) {
1139 if ((rxq->iq.flags & IQ_INTR) == 0)
1143 for_each_ofld_rxq(vi, i, ofld_rxq) {
1144 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1145 free_ofld_rxq(vi, ofld_rxq);
1150 * Then take down the rx queues that take direct interrupts.
1153 for_each_rxq(vi, i, rxq) {
1154 if (rxq->iq.flags & IQ_INTR)
1158 for_each_ofld_rxq(vi, i, ofld_rxq) {
1159 if (ofld_rxq->iq.flags & IQ_INTR)
1160 free_ofld_rxq(vi, ofld_rxq);
1168 * Deals with errors and the firmware event queue. All data rx queues forward
1169 * their interrupt to the firmware event queue.
1172 t4_intr_all(void *arg)
1174 struct adapter *sc = arg;
1175 struct sge_iq *fwq = &sc->sge.fwq;
1178 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1180 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1184 /* Deals with error interrupts */
1186 t4_intr_err(void *arg)
1188 struct adapter *sc = arg;
1190 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1191 t4_slow_intr_handler(sc);
1195 t4_intr_evt(void *arg)
1197 struct sge_iq *iq = arg;
1199 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1201 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1208 struct sge_iq *iq = arg;
1210 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1212 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1217 * Deals with anything and everything on the given ingress queue.
1220 service_iq(struct sge_iq *iq, int budget)
1223 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1224 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1225 struct adapter *sc = iq->adapter;
1226 struct iq_desc *d = &iq->desc[iq->cidx];
1227 int ndescs = 0, limit;
1228 int rsp_type, refill;
1230 uint16_t fl_hw_cidx;
1232 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1233 #if defined(INET) || defined(INET6)
1234 const struct timeval lro_timeout = {0, sc->lro_timeout};
1237 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1239 limit = budget ? budget : iq->qsize / 16;
1241 if (iq->flags & IQ_HAS_FL) {
1243 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1246 fl_hw_cidx = 0; /* to silence gcc warning */
1250 * We always come back and check the descriptor ring for new indirect
1251 * interrupts and other responses after running a single handler.
1254 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1260 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1261 lq = be32toh(d->rsp.pldbuflen_qid);
1264 case X_RSPD_TYPE_FLBUF:
1266 KASSERT(iq->flags & IQ_HAS_FL,
1267 ("%s: data for an iq (%p) with no freelist",
1270 m0 = get_fl_payload(sc, fl, lq);
1271 if (__predict_false(m0 == NULL))
1273 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1274 #ifdef T4_PKT_TIMESTAMP
1276 * 60 bit timestamp for the payload is
1277 * *(uint64_t *)m0->m_pktdat. Note that it is
1278 * in the leading free-space in the mbuf. The
1279 * kernel can clobber it during a pullup,
1280 * m_copymdata, etc. You need to make sure that
1281 * the mbuf reaches you unmolested if you care
1282 * about the timestamp.
1284 *(uint64_t *)m0->m_pktdat =
1285 be64toh(ctrl->u.last_flit) &
1291 case X_RSPD_TYPE_CPL:
1292 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1293 ("%s: bad opcode %02x.", __func__,
1295 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1298 case X_RSPD_TYPE_INTR:
1301 * Interrupts should be forwarded only to queues
1302 * that are not forwarding their interrupts.
1303 * This means service_iq can recurse but only 1
1306 KASSERT(budget == 0,
1307 ("%s: budget %u, rsp_type %u", __func__,
1311 * There are 1K interrupt-capable queues (qids 0
1312 * through 1023). A response type indicating a
1313 * forwarded interrupt with a qid >= 1K is an
1314 * iWARP async notification.
1317 sc->an_handler(iq, &d->rsp);
1321 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1322 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1324 if (service_iq(q, q->qsize / 16) == 0) {
1325 atomic_cmpset_int(&q->state,
1326 IQS_BUSY, IQS_IDLE);
1328 STAILQ_INSERT_TAIL(&iql, q,
1336 ("%s: illegal response type %d on iq %p",
1337 __func__, rsp_type, iq));
1339 "%s: illegal response type %d on iq %p",
1340 device_get_nameunit(sc->dev), rsp_type, iq);
1345 if (__predict_false(++iq->cidx == iq->sidx)) {
1347 iq->gen ^= F_RSPD_GEN;
1350 if (__predict_false(++ndescs == limit)) {
1351 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1353 V_INGRESSQID(iq->cntxt_id) |
1354 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1357 #if defined(INET) || defined(INET6)
1358 if (iq->flags & IQ_LRO_ENABLED &&
1359 sc->lro_timeout != 0) {
1360 tcp_lro_flush_inactive(&rxq->lro,
1366 if (iq->flags & IQ_HAS_FL) {
1368 refill_fl(sc, fl, 32);
1371 return (EINPROGRESS);
1376 refill_fl(sc, fl, 32);
1378 fl_hw_cidx = fl->hw_cidx;
1383 if (STAILQ_EMPTY(&iql))
1387 * Process the head only, and send it to the back of the list if
1388 * it's still not done.
1390 q = STAILQ_FIRST(&iql);
1391 STAILQ_REMOVE_HEAD(&iql, link);
1392 if (service_iq(q, q->qsize / 8) == 0)
1393 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1395 STAILQ_INSERT_TAIL(&iql, q, link);
1398 #if defined(INET) || defined(INET6)
1399 if (iq->flags & IQ_LRO_ENABLED) {
1400 struct lro_ctrl *lro = &rxq->lro;
1402 tcp_lro_flush_all(lro);
1406 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1407 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1409 if (iq->flags & IQ_HAS_FL) {
1413 starved = refill_fl(sc, fl, 64);
1415 if (__predict_false(starved != 0))
1416 add_fl_to_sfl(sc, fl);
1423 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1425 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1428 MPASS(cll->region3 >= CL_METADATA_SIZE);
1433 static inline struct cluster_metadata *
1434 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1438 if (cl_has_metadata(fl, cll)) {
1439 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1441 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1447 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1449 uma_zone_t zone = arg1;
1452 uma_zfree(zone, cl);
1453 counter_u64_add(extfree_rels, 1);
1457 * The mbuf returned by this function could be allocated from zone_mbuf or
1458 * constructed in spare room in the cluster.
1460 * The mbuf carries the payload in one of these ways
1461 * a) frame inside the mbuf (mbuf from zone_mbuf)
1462 * b) m_cljset (for clusters without metadata) zone_mbuf
1463 * c) m_extaddref (cluster with metadata) inline mbuf
1464 * d) m_extaddref (cluster with metadata) zone_mbuf
1466 static struct mbuf *
1467 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1471 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1472 struct cluster_layout *cll = &sd->cll;
1473 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1474 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1475 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1479 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1480 len = min(remaining, blen);
1481 payload = sd->cl + cll->region1 + fl->rx_offset;
1482 if (fl->flags & FL_BUF_PACKING) {
1483 const u_int l = fr_offset + len;
1484 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1486 if (fl->rx_offset + len + pad < hwb->size)
1488 MPASS(fl->rx_offset + blen <= hwb->size);
1490 MPASS(fl->rx_offset == 0); /* not packing */
1494 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1497 * Copy payload into a freshly allocated mbuf.
1500 m = fr_offset == 0 ?
1501 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1504 fl->mbuf_allocated++;
1505 #ifdef T4_PKT_TIMESTAMP
1506 /* Leave room for a timestamp */
1509 /* copy data to mbuf */
1510 bcopy(payload, mtod(m, caddr_t), len);
1512 } else if (sd->nmbuf * MSIZE < cll->region1) {
1515 * There's spare room in the cluster for an mbuf. Create one
1516 * and associate it with the payload that's in the cluster.
1520 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1521 /* No bzero required */
1522 if (m_init(m, M_NOWAIT, MT_DATA,
1523 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1526 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1528 if (sd->nmbuf++ == 0)
1529 counter_u64_add(extfree_refs, 1);
1534 * Grab an mbuf from zone_mbuf and associate it with the
1535 * payload in the cluster.
1538 m = fr_offset == 0 ?
1539 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1542 fl->mbuf_allocated++;
1544 m_extaddref(m, payload, blen, &clm->refcount,
1545 rxb_free, swz->zone, sd->cl);
1546 if (sd->nmbuf++ == 0)
1547 counter_u64_add(extfree_refs, 1);
1549 m_cljset(m, sd->cl, swz->type);
1550 sd->cl = NULL; /* consumed, not a recycle candidate */
1554 m->m_pkthdr.len = remaining;
1557 if (fl->flags & FL_BUF_PACKING) {
1558 fl->rx_offset += blen;
1559 MPASS(fl->rx_offset <= hwb->size);
1560 if (fl->rx_offset < hwb->size)
1561 return (m); /* without advancing the cidx */
1564 if (__predict_false(++fl->cidx % 8 == 0)) {
1565 uint16_t cidx = fl->cidx / 8;
1567 if (__predict_false(cidx == fl->sidx))
1568 fl->cidx = cidx = 0;
1576 static struct mbuf *
1577 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1579 struct mbuf *m0, *m, **pnext;
1581 const u_int total = G_RSPD_LEN(len_newbuf);
1583 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1584 M_ASSERTPKTHDR(fl->m0);
1585 MPASS(fl->m0->m_pkthdr.len == total);
1586 MPASS(fl->remaining < total);
1590 remaining = fl->remaining;
1591 fl->flags &= ~FL_BUF_RESUME;
1595 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1597 if (__predict_false(++fl->cidx % 8 == 0)) {
1598 uint16_t cidx = fl->cidx / 8;
1600 if (__predict_false(cidx == fl->sidx))
1601 fl->cidx = cidx = 0;
1607 * Payload starts at rx_offset in the current hw buffer. Its length is
1608 * 'len' and it may span multiple hw buffers.
1611 m0 = get_scatter_segment(sc, fl, 0, total);
1614 remaining = total - m0->m_len;
1615 pnext = &m0->m_next;
1616 while (remaining > 0) {
1618 MPASS(fl->rx_offset == 0);
1619 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1620 if (__predict_false(m == NULL)) {
1623 fl->remaining = remaining;
1624 fl->flags |= FL_BUF_RESUME;
1629 remaining -= m->m_len;
1638 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1640 struct sge_rxq *rxq = iq_to_rxq(iq);
1641 struct ifnet *ifp = rxq->ifp;
1642 struct adapter *sc = iq->adapter;
1643 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1644 #if defined(INET) || defined(INET6)
1645 struct lro_ctrl *lro = &rxq->lro;
1647 static const int sw_hashtype[4][2] = {
1648 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1649 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1650 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1651 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1654 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1657 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
1658 m0->m_len -= sc->params.sge.fl_pktshift;
1659 m0->m_data += sc->params.sge.fl_pktshift;
1661 m0->m_pkthdr.rcvif = ifp;
1662 M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
1663 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1665 if (cpl->csum_calc && !cpl->err_vec) {
1666 if (ifp->if_capenable & IFCAP_RXCSUM &&
1667 cpl->l2info & htobe32(F_RXF_IP)) {
1668 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1669 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1671 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1672 cpl->l2info & htobe32(F_RXF_IP6)) {
1673 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1678 if (__predict_false(cpl->ip_frag))
1679 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1681 m0->m_pkthdr.csum_data = 0xffff;
1685 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1686 m0->m_flags |= M_VLANTAG;
1687 rxq->vlan_extraction++;
1690 #if defined(INET) || defined(INET6)
1691 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1692 iq->flags & IQ_LRO_ENABLED &&
1693 tcp_lro_rx(lro, m0, 0) == 0) {
1694 /* queued for LRO */
1697 ifp->if_input(ifp, m0);
1703 * Must drain the wrq or make sure that someone else will.
1706 wrq_tx_drain(void *arg, int n)
1708 struct sge_wrq *wrq = arg;
1709 struct sge_eq *eq = &wrq->eq;
1712 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1713 drain_wrq_wr_list(wrq->adapter, wrq);
1718 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1720 struct sge_eq *eq = &wrq->eq;
1721 u_int available, dbdiff; /* # of hardware descriptors */
1724 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1726 EQ_LOCK_ASSERT_OWNED(eq);
1727 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1728 wr = STAILQ_FIRST(&wrq->wr_list);
1729 MPASS(wr != NULL); /* Must be called with something useful to do */
1730 MPASS(eq->pidx == eq->dbidx);
1734 eq->cidx = read_hw_cidx(eq);
1735 if (eq->pidx == eq->cidx)
1736 available = eq->sidx - 1;
1738 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1740 MPASS(wr->wrq == wrq);
1741 n = howmany(wr->wr_len, EQ_ESIZE);
1745 dst = (void *)&eq->desc[eq->pidx];
1746 if (__predict_true(eq->sidx - eq->pidx > n)) {
1747 /* Won't wrap, won't end exactly at the status page. */
1748 bcopy(&wr->wr[0], dst, wr->wr_len);
1751 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1753 bcopy(&wr->wr[0], dst, first_portion);
1754 if (wr->wr_len > first_portion) {
1755 bcopy(&wr->wr[first_portion], &eq->desc[0],
1756 wr->wr_len - first_portion);
1758 eq->pidx = n - (eq->sidx - eq->pidx);
1761 if (available < eq->sidx / 4 &&
1762 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1763 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1765 eq->equeqidx = eq->pidx;
1766 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1767 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1768 eq->equeqidx = eq->pidx;
1773 ring_eq_db(sc, eq, dbdiff);
1777 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1779 MPASS(wrq->nwr_pending > 0);
1781 MPASS(wrq->ndesc_needed >= n);
1782 wrq->ndesc_needed -= n;
1783 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1786 ring_eq_db(sc, eq, dbdiff);
1790 * Doesn't fail. Holds on to work requests it can't send right away.
1793 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1796 struct sge_eq *eq = &wrq->eq;
1799 EQ_LOCK_ASSERT_OWNED(eq);
1801 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1802 MPASS((wr->wr_len & 0x7) == 0);
1804 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1806 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1808 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1809 return; /* commit_wrq_wr will drain wr_list as well. */
1811 drain_wrq_wr_list(sc, wrq);
1813 /* Doorbell must have caught up to the pidx. */
1814 MPASS(eq->pidx == eq->dbidx);
1818 t4_update_fl_bufsize(struct ifnet *ifp)
1820 struct vi_info *vi = ifp->if_softc;
1821 struct adapter *sc = vi->pi->adapter;
1822 struct sge_rxq *rxq;
1824 struct sge_ofld_rxq *ofld_rxq;
1827 int i, maxp, mtu = ifp->if_mtu;
1829 maxp = mtu_to_max_payload(sc, mtu, 0);
1830 for_each_rxq(vi, i, rxq) {
1834 find_best_refill_source(sc, fl, maxp);
1838 maxp = mtu_to_max_payload(sc, mtu, 1);
1839 for_each_ofld_rxq(vi, i, ofld_rxq) {
1843 find_best_refill_source(sc, fl, maxp);
1850 mbuf_nsegs(struct mbuf *m)
1854 KASSERT(m->m_pkthdr.l5hlen > 0,
1855 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1857 return (m->m_pkthdr.l5hlen);
1861 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1865 m->m_pkthdr.l5hlen = nsegs;
1869 mbuf_len16(struct mbuf *m)
1874 n = m->m_pkthdr.PH_loc.eight[0];
1875 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1881 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1885 m->m_pkthdr.PH_loc.eight[0] = len16;
1889 needs_tso(struct mbuf *m)
1894 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1895 KASSERT(m->m_pkthdr.tso_segsz > 0,
1896 ("%s: TSO requested in mbuf %p but MSS not provided",
1905 needs_l3_csum(struct mbuf *m)
1910 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
1916 needs_l4_csum(struct mbuf *m)
1921 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
1922 CSUM_TCP_IPV6 | CSUM_TSO))
1928 needs_vlan_insertion(struct mbuf *m)
1933 if (m->m_flags & M_VLANTAG) {
1934 KASSERT(m->m_pkthdr.ether_vtag != 0,
1935 ("%s: HWVLAN requested in mbuf %p but tag not provided",
1943 m_advance(struct mbuf **pm, int *poffset, int len)
1945 struct mbuf *m = *pm;
1946 int offset = *poffset;
1952 if (offset + len < m->m_len) {
1954 p = mtod(m, uintptr_t) + offset;
1957 len -= m->m_len - offset;
1968 same_paddr(char *a, char *b)
1973 else if (a != NULL && b != NULL) {
1974 vm_offset_t x = (vm_offset_t)a;
1975 vm_offset_t y = (vm_offset_t)b;
1977 if ((x & PAGE_MASK) == (y & PAGE_MASK) &&
1978 pmap_kextract(x) == pmap_kextract(y))
1986 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
1987 * must have at least one mbuf that's not empty.
1990 count_mbuf_nsegs(struct mbuf *m)
1992 char *prev_end, *start;
1999 for (; m; m = m->m_next) {
2002 if (__predict_false(len == 0))
2004 start = mtod(m, char *);
2006 nsegs += sglist_count(start, len);
2007 if (same_paddr(prev_end, start))
2009 prev_end = start + len;
2017 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2018 * a) caller can assume it's been freed if this function returns with an error.
2019 * b) it may get defragged up if the gather list is too long for the hardware.
2022 parse_pkt(struct mbuf **mp)
2024 struct mbuf *m0 = *mp, *m;
2025 int rc, nsegs, defragged = 0, offset;
2026 struct ether_header *eh;
2028 #if defined(INET) || defined(INET6)
2034 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2043 * First count the number of gather list segments in the payload.
2044 * Defrag the mbuf if nsegs exceeds the hardware limit.
2047 MPASS(m0->m_pkthdr.len > 0);
2048 nsegs = count_mbuf_nsegs(m0);
2049 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2050 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2054 *mp = m0 = m; /* update caller's copy after defrag */
2058 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2059 m0 = m_pullup(m0, m0->m_pkthdr.len);
2061 /* Should have left well enough alone. */
2065 *mp = m0; /* update caller's copy after pullup */
2068 set_mbuf_nsegs(m0, nsegs);
2069 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2075 eh = mtod(m, struct ether_header *);
2076 eh_type = ntohs(eh->ether_type);
2077 if (eh_type == ETHERTYPE_VLAN) {
2078 struct ether_vlan_header *evh = (void *)eh;
2080 eh_type = ntohs(evh->evl_proto);
2081 m0->m_pkthdr.l2hlen = sizeof(*evh);
2083 m0->m_pkthdr.l2hlen = sizeof(*eh);
2086 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2090 case ETHERTYPE_IPV6:
2092 struct ip6_hdr *ip6 = l3hdr;
2094 MPASS(ip6->ip6_nxt == IPPROTO_TCP);
2096 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2103 struct ip *ip = l3hdr;
2105 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2110 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2111 " with the same INET/INET6 options as the kernel.",
2115 #if defined(INET) || defined(INET6)
2116 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2117 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2124 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2126 struct sge_eq *eq = &wrq->eq;
2127 struct adapter *sc = wrq->adapter;
2128 int ndesc, available;
2133 ndesc = howmany(len16, EQ_ESIZE / 16);
2134 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2138 if (!STAILQ_EMPTY(&wrq->wr_list))
2139 drain_wrq_wr_list(sc, wrq);
2141 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2144 wr = alloc_wrqe(len16 * 16, wrq);
2145 if (__predict_false(wr == NULL))
2148 cookie->ndesc = ndesc;
2152 eq->cidx = read_hw_cidx(eq);
2153 if (eq->pidx == eq->cidx)
2154 available = eq->sidx - 1;
2156 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2157 if (available < ndesc)
2160 cookie->pidx = eq->pidx;
2161 cookie->ndesc = ndesc;
2162 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2164 w = &eq->desc[eq->pidx];
2165 IDXINCR(eq->pidx, ndesc, eq->sidx);
2166 if (__predict_false(eq->pidx < ndesc - 1)) {
2168 wrq->ss_pidx = cookie->pidx;
2169 wrq->ss_len = len16 * 16;
2178 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2180 struct sge_eq *eq = &wrq->eq;
2181 struct adapter *sc = wrq->adapter;
2183 struct wrq_cookie *prev, *next;
2185 if (cookie->pidx == -1) {
2186 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2192 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2193 pidx = cookie->pidx;
2194 MPASS(pidx >= 0 && pidx < eq->sidx);
2195 if (__predict_false(w == &wrq->ss[0])) {
2196 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2198 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2199 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2200 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2203 wrq->tx_wrs_direct++;
2206 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2207 next = TAILQ_NEXT(cookie, link);
2209 MPASS(pidx == eq->dbidx);
2210 if (next == NULL || ndesc >= 16)
2211 ring_eq_db(wrq->adapter, eq, ndesc);
2213 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2215 next->ndesc += ndesc;
2218 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2219 prev->ndesc += ndesc;
2221 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2223 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2224 drain_wrq_wr_list(sc, wrq);
2227 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2228 /* Doorbell must have caught up to the pidx. */
2229 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2236 can_resume_eth_tx(struct mp_ring *r)
2238 struct sge_eq *eq = r->cookie;
2240 return (total_available_tx_desc(eq) > eq->sidx / 8);
2244 cannot_use_txpkts(struct mbuf *m)
2246 /* maybe put a GL limit too, to avoid silliness? */
2248 return (needs_tso(m));
2252 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2253 * be consumed. Return the actual number consumed. 0 indicates a stall.
2256 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2258 struct sge_txq *txq = r->cookie;
2259 struct sge_eq *eq = &txq->eq;
2260 struct ifnet *ifp = txq->ifp;
2261 struct vi_info *vi = ifp->if_softc;
2262 struct port_info *pi = vi->pi;
2263 struct adapter *sc = pi->adapter;
2264 u_int total, remaining; /* # of packets */
2265 u_int available, dbdiff; /* # of hardware descriptors */
2267 struct mbuf *m0, *tail;
2269 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2271 remaining = IDXDIFF(pidx, cidx, r->size);
2272 MPASS(remaining > 0); /* Must not be called without work to do. */
2276 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2277 while (cidx != pidx) {
2278 m0 = r->items[cidx];
2280 if (++cidx == r->size)
2283 reclaim_tx_descs(txq, 2048);
2288 /* How many hardware descriptors do we have readily available. */
2289 if (eq->pidx == eq->cidx)
2290 available = eq->sidx - 1;
2292 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2293 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2295 while (remaining > 0) {
2297 m0 = r->items[cidx];
2299 MPASS(m0->m_nextpkt == NULL);
2301 if (available < SGE_MAX_WR_NDESC) {
2302 available += reclaim_tx_descs(txq, 64);
2303 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2304 break; /* out of descriptors */
2307 next_cidx = cidx + 1;
2308 if (__predict_false(next_cidx == r->size))
2311 wr = (void *)&eq->desc[eq->pidx];
2312 if (remaining > 1 &&
2313 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2315 /* pkts at cidx, next_cidx should both be in txp. */
2316 MPASS(txp.npkt == 2);
2317 tail = r->items[next_cidx];
2318 MPASS(tail->m_nextpkt == NULL);
2319 ETHER_BPF_MTAP(ifp, m0);
2320 ETHER_BPF_MTAP(ifp, tail);
2321 m0->m_nextpkt = tail;
2323 if (__predict_false(++next_cidx == r->size))
2326 while (next_cidx != pidx) {
2327 if (add_to_txpkts(r->items[next_cidx], &txp,
2330 tail->m_nextpkt = r->items[next_cidx];
2331 tail = tail->m_nextpkt;
2332 ETHER_BPF_MTAP(ifp, tail);
2333 if (__predict_false(++next_cidx == r->size))
2337 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2339 remaining -= txp.npkt;
2343 ETHER_BPF_MTAP(ifp, m0);
2344 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2346 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2350 IDXINCR(eq->pidx, n, eq->sidx);
2352 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2353 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2354 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2356 eq->equeqidx = eq->pidx;
2357 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2358 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2359 eq->equeqidx = eq->pidx;
2362 if (dbdiff >= 16 && remaining >= 4) {
2363 ring_eq_db(sc, eq, dbdiff);
2364 available += reclaim_tx_descs(txq, 4 * dbdiff);
2371 ring_eq_db(sc, eq, dbdiff);
2372 reclaim_tx_descs(txq, 32);
2381 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2385 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2386 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2387 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2388 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2392 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2393 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2394 if (pktc_idx >= 0) {
2395 iq->intr_params |= F_QINTR_CNT_EN;
2396 iq->intr_pktc_idx = pktc_idx;
2398 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2399 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
2403 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2407 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2408 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2409 if (sc->flags & BUF_PACKING_OK &&
2410 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2411 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2412 fl->flags |= FL_BUF_PACKING;
2413 find_best_refill_source(sc, fl, maxp);
2414 find_safe_refill_source(sc, fl);
2418 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
2419 uint8_t tx_chan, uint16_t iqid, char *name)
2421 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2423 eq->flags = eqtype & EQ_TYPEMASK;
2424 eq->tx_chan = tx_chan;
2426 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
2427 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2431 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2432 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2436 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2437 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2439 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2443 rc = bus_dmamem_alloc(*tag, va,
2444 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2446 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2450 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2452 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2457 free_ring(sc, *tag, *map, *pa, *va);
2463 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2464 bus_addr_t pa, void *va)
2467 bus_dmamap_unload(tag, map);
2469 bus_dmamem_free(tag, va, map);
2471 bus_dma_tag_destroy(tag);
2477 * Allocates the ring for an ingress queue and an optional freelist. If the
2478 * freelist is specified it will be allocated and then associated with the
2481 * Returns errno on failure. Resources allocated up to that point may still be
2482 * allocated. Caller is responsible for cleanup in case this function fails.
2484 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2485 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2486 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2489 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
2490 int intr_idx, int cong)
2492 int rc, i, cntxt_id;
2495 struct port_info *pi = vi->pi;
2496 struct adapter *sc = iq->adapter;
2497 struct sge_params *sp = &sc->params.sge;
2500 len = iq->qsize * IQ_ESIZE;
2501 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2502 (void **)&iq->desc);
2506 bzero(&c, sizeof(c));
2507 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2508 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2509 V_FW_IQ_CMD_VFN(0));
2511 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2514 /* Special handling for firmware event queue */
2515 if (iq == &sc->sge.fwq)
2516 v |= F_FW_IQ_CMD_IQASYNCH;
2518 if (iq->flags & IQ_INTR) {
2519 KASSERT(intr_idx < sc->intr_count,
2520 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2522 v |= F_FW_IQ_CMD_IQANDST;
2523 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2525 c.type_to_iqandstindex = htobe32(v |
2526 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2527 V_FW_IQ_CMD_VIID(vi->viid) |
2528 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2529 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2530 F_FW_IQ_CMD_IQGTSMODE |
2531 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2532 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2533 c.iqsize = htobe16(iq->qsize);
2534 c.iqaddr = htobe64(iq->ba);
2536 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2539 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2541 len = fl->qsize * EQ_ESIZE;
2542 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2543 &fl->ba, (void **)&fl->desc);
2547 /* Allocate space for one software descriptor per buffer. */
2548 rc = alloc_fl_sdesc(fl);
2550 device_printf(sc->dev,
2551 "failed to setup fl software descriptors: %d\n",
2556 if (fl->flags & FL_BUF_PACKING) {
2557 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
2558 fl->buf_boundary = sp->pack_boundary;
2560 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
2561 fl->buf_boundary = 16;
2563 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
2564 fl->buf_boundary = sp->pad_boundary;
2566 c.iqns_to_fl0congen |=
2567 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2568 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2569 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2570 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2573 c.iqns_to_fl0congen |=
2574 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2575 F_FW_IQ_CMD_FL0CONGCIF |
2576 F_FW_IQ_CMD_FL0CONGEN);
2578 c.fl0dcaen_to_fl0cidxfthresh =
2579 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
2580 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2581 c.fl0size = htobe16(fl->qsize);
2582 c.fl0addr = htobe64(fl->ba);
2585 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2587 device_printf(sc->dev,
2588 "failed to create ingress queue: %d\n", rc);
2593 iq->gen = F_RSPD_GEN;
2594 iq->intr_next = iq->intr_params;
2595 iq->cntxt_id = be16toh(c.iqid);
2596 iq->abs_id = be16toh(c.physiqid);
2597 iq->flags |= IQ_ALLOCATED;
2599 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2600 if (cntxt_id >= sc->sge.niq) {
2601 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2602 cntxt_id, sc->sge.niq - 1);
2604 sc->sge.iqmap[cntxt_id] = iq;
2609 iq->flags |= IQ_HAS_FL;
2610 fl->cntxt_id = be16toh(c.fl0id);
2611 fl->pidx = fl->cidx = 0;
2613 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2614 if (cntxt_id >= sc->sge.neq) {
2615 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2616 __func__, cntxt_id, sc->sge.neq - 1);
2618 sc->sge.eqmap[cntxt_id] = (void *)fl;
2621 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2622 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
2623 uint32_t mask = (1 << s_qpp) - 1;
2624 volatile uint8_t *udb;
2626 udb = sc->udbs_base + UDBS_DB_OFFSET;
2627 udb += (qid >> s_qpp) << PAGE_SHIFT;
2629 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2630 udb += qid << UDBS_SEG_SHIFT;
2633 fl->udb = (volatile void *)udb;
2635 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
2638 /* Enough to make sure the SGE doesn't think it's starved */
2639 refill_fl(sc, fl, fl->lowat);
2643 if (is_t5(sc) && cong >= 0) {
2644 uint32_t param, val;
2646 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2647 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2648 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2653 for (i = 0; i < 4; i++) {
2654 if (cong & (1 << i))
2655 val |= 1 << (i << 2);
2659 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2661 /* report error but carry on */
2662 device_printf(sc->dev,
2663 "failed to set congestion manager context for "
2664 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2668 /* Enable IQ interrupts */
2669 atomic_store_rel_int(&iq->state, IQS_IDLE);
2670 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2671 V_INGRESSQID(iq->cntxt_id));
2677 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
2680 struct adapter *sc = iq->adapter;
2684 return (0); /* nothing to do */
2686 dev = vi ? vi->dev : sc->dev;
2688 if (iq->flags & IQ_ALLOCATED) {
2689 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2690 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2691 fl ? fl->cntxt_id : 0xffff, 0xffff);
2694 "failed to free queue %p: %d\n", iq, rc);
2697 iq->flags &= ~IQ_ALLOCATED;
2700 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2702 bzero(iq, sizeof(*iq));
2705 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2709 free_fl_sdesc(sc, fl);
2711 if (mtx_initialized(&fl->fl_lock))
2712 mtx_destroy(&fl->fl_lock);
2714 bzero(fl, sizeof(*fl));
2721 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2724 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2726 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2728 children = SYSCTL_CHILDREN(oid);
2730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2731 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2732 "SGE context id of the freelist");
2733 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2734 fl_pad ? 1 : 0, "padding enabled");
2735 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2736 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2737 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2738 0, "consumer index");
2739 if (fl->flags & FL_BUF_PACKING) {
2740 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2741 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2743 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2744 0, "producer index");
2745 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2746 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2747 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2748 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2749 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2750 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2751 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2752 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2753 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2754 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2758 alloc_fwq(struct adapter *sc)
2761 struct sge_iq *fwq = &sc->sge.fwq;
2762 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2763 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2765 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2766 fwq->flags |= IQ_INTR; /* always */
2767 intr_idx = sc->intr_count > 1 ? 1 : 0;
2768 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
2770 device_printf(sc->dev,
2771 "failed to create firmware event queue: %d\n", rc);
2775 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2776 NULL, "firmware event queue");
2777 children = SYSCTL_CHILDREN(oid);
2779 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2780 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2781 "absolute id of the queue");
2782 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2783 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2784 "SGE context id of the queue");
2785 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2786 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2793 free_fwq(struct adapter *sc)
2795 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2799 alloc_mgmtq(struct adapter *sc)
2802 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2804 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2805 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2807 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2808 NULL, "management queue");
2810 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2811 init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2812 sc->sge.fwq.cntxt_id, name);
2813 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2815 device_printf(sc->dev,
2816 "failed to create management queue: %d\n", rc);
2824 free_mgmtq(struct adapter *sc)
2827 return free_wrq(sc, &sc->sge.mgmtq);
2831 tnl_cong(struct port_info *pi, int drop)
2839 return (pi->rx_chan_map);
2843 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
2844 struct sysctl_oid *oid)
2847 struct sysctl_oid_list *children;
2850 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
2851 tnl_cong(vi->pi, cong_drop));
2856 * The freelist is just barely above the starvation threshold right now,
2857 * fill it up a bit more.
2860 refill_fl(vi->pi->adapter, &rxq->fl, 128);
2861 FL_UNLOCK(&rxq->fl);
2863 #if defined(INET) || defined(INET6)
2864 rc = tcp_lro_init(&rxq->lro);
2867 rxq->lro.ifp = vi->ifp; /* also indicates LRO init'ed */
2869 if (vi->ifp->if_capenable & IFCAP_LRO)
2870 rxq->iq.flags |= IQ_LRO_ENABLED;
2874 children = SYSCTL_CHILDREN(oid);
2876 snprintf(name, sizeof(name), "%d", idx);
2877 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2879 children = SYSCTL_CHILDREN(oid);
2881 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
2882 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2883 "absolute id of the queue");
2884 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
2885 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2886 "SGE context id of the queue");
2887 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
2888 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2890 #if defined(INET) || defined(INET6)
2891 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2892 &rxq->lro.lro_queued, 0, NULL);
2893 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2894 &rxq->lro.lro_flushed, 0, NULL);
2896 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2897 &rxq->rxcsum, "# of times hardware assisted with checksum");
2898 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
2899 CTLFLAG_RD, &rxq->vlan_extraction,
2900 "# of times hardware extracted 802.1Q tag");
2902 add_fl_sysctls(&vi->ctx, oid, &rxq->fl);
2908 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
2912 #if defined(INET) || defined(INET6)
2914 tcp_lro_free(&rxq->lro);
2915 rxq->lro.ifp = NULL;
2919 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
2921 bzero(rxq, sizeof(*rxq));
2928 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
2929 int intr_idx, int idx, struct sysctl_oid *oid)
2932 struct sysctl_oid_list *children;
2935 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
2936 vi->pi->rx_chan_map);
2940 children = SYSCTL_CHILDREN(oid);
2942 snprintf(name, sizeof(name), "%d", idx);
2943 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2945 children = SYSCTL_CHILDREN(oid);
2947 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "abs_id",
2948 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
2949 "I", "absolute id of the queue");
2950 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cntxt_id",
2951 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
2952 "I", "SGE context id of the queue");
2953 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
2954 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
2957 add_fl_sysctls(&vi->ctx, oid, &ofld_rxq->fl);
2963 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
2967 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
2969 bzero(ofld_rxq, sizeof(*ofld_rxq));
2977 alloc_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int intr_idx,
2978 int idx, struct sysctl_oid *oid)
2981 struct sysctl_oid_list *children;
2982 struct sysctl_ctx_list *ctx;
2985 struct adapter *sc = vi->pi->adapter;
2986 struct netmap_adapter *na = NA(vi->ifp);
2990 len = vi->qsize_rxq * IQ_ESIZE;
2991 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
2992 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
2996 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
2997 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
2998 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3004 nm_rxq->iq_cidx = 0;
3005 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
3006 nm_rxq->iq_gen = F_RSPD_GEN;
3007 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3008 nm_rxq->fl_sidx = na->num_rx_desc;
3009 nm_rxq->intr_idx = intr_idx;
3012 children = SYSCTL_CHILDREN(oid);
3014 snprintf(name, sizeof(name), "%d", idx);
3015 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3017 children = SYSCTL_CHILDREN(oid);
3019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3020 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3021 "I", "absolute id of the queue");
3022 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3023 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3024 "I", "SGE context id of the queue");
3025 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3026 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3029 children = SYSCTL_CHILDREN(oid);
3030 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3032 children = SYSCTL_CHILDREN(oid);
3034 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3035 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3036 "I", "SGE context id of the freelist");
3037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3038 &nm_rxq->fl_cidx, 0, "consumer index");
3039 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3040 &nm_rxq->fl_pidx, 0, "producer index");
3047 free_nm_rxq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq)
3049 struct adapter *sc = vi->pi->adapter;
3051 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3053 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3060 alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3061 struct sysctl_oid *oid)
3065 struct port_info *pi = vi->pi;
3066 struct adapter *sc = pi->adapter;
3067 struct netmap_adapter *na = NA(vi->ifp);
3069 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3071 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
3072 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3073 &nm_txq->ba, (void **)&nm_txq->desc);
3077 nm_txq->pidx = nm_txq->cidx = 0;
3078 nm_txq->sidx = na->num_tx_desc;
3080 nm_txq->iqidx = iqidx;
3081 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3082 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
3083 V_TXPKT_VF(vi->viid));
3085 snprintf(name, sizeof(name), "%d", idx);
3086 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3087 NULL, "netmap tx queue");
3088 children = SYSCTL_CHILDREN(oid);
3090 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3091 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3092 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3093 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3095 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3096 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3103 free_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq)
3105 struct adapter *sc = vi->pi->adapter;
3107 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3115 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3118 struct fw_eq_ctrl_cmd c;
3119 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3121 bzero(&c, sizeof(c));
3123 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3124 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3125 V_FW_EQ_CTRL_CMD_VFN(0));
3126 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3127 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3128 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3129 c.physeqid_pkd = htobe32(0);
3130 c.fetchszm_to_iqid =
3131 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3132 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3133 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3135 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3136 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3137 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3138 c.eqaddr = htobe64(eq->ba);
3140 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3142 device_printf(sc->dev,
3143 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3146 eq->flags |= EQ_ALLOCATED;
3148 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3149 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3150 if (cntxt_id >= sc->sge.neq)
3151 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3152 cntxt_id, sc->sge.neq - 1);
3153 sc->sge.eqmap[cntxt_id] = eq;
3159 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3162 struct fw_eq_eth_cmd c;
3163 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3165 bzero(&c, sizeof(c));
3167 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3168 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3169 V_FW_EQ_ETH_CMD_VFN(0));
3170 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3171 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3172 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3173 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
3174 c.fetchszm_to_iqid =
3175 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3176 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3177 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3178 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3179 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3180 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3181 c.eqaddr = htobe64(eq->ba);
3183 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3185 device_printf(vi->dev,
3186 "failed to create Ethernet egress queue: %d\n", rc);
3189 eq->flags |= EQ_ALLOCATED;
3191 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3192 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3193 if (cntxt_id >= sc->sge.neq)
3194 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3195 cntxt_id, sc->sge.neq - 1);
3196 sc->sge.eqmap[cntxt_id] = eq;
3203 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3206 struct fw_eq_ofld_cmd c;
3207 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3209 bzero(&c, sizeof(c));
3211 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3212 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3213 V_FW_EQ_OFLD_CMD_VFN(0));
3214 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3215 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3216 c.fetchszm_to_iqid =
3217 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3218 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3219 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3221 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3222 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3223 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3224 c.eqaddr = htobe64(eq->ba);
3226 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3228 device_printf(vi->dev,
3229 "failed to create egress queue for TCP offload: %d\n", rc);
3232 eq->flags |= EQ_ALLOCATED;
3234 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3235 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3236 if (cntxt_id >= sc->sge.neq)
3237 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3238 cntxt_id, sc->sge.neq - 1);
3239 sc->sge.eqmap[cntxt_id] = eq;
3246 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
3251 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3253 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
3254 len = qsize * EQ_ESIZE;
3255 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3256 &eq->ba, (void **)&eq->desc);
3260 eq->pidx = eq->cidx = 0;
3261 eq->equeqidx = eq->dbidx = 0;
3262 eq->doorbells = sc->doorbells;
3264 switch (eq->flags & EQ_TYPEMASK) {
3266 rc = ctrl_eq_alloc(sc, eq);
3270 rc = eth_eq_alloc(sc, vi, eq);
3275 rc = ofld_eq_alloc(sc, vi, eq);
3280 panic("%s: invalid eq type %d.", __func__,
3281 eq->flags & EQ_TYPEMASK);
3284 device_printf(sc->dev,
3285 "failed to allocate egress queue(%d): %d\n",
3286 eq->flags & EQ_TYPEMASK, rc);
3289 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3290 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3291 isset(&eq->doorbells, DOORBELL_WCWR)) {
3292 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3293 uint32_t mask = (1 << s_qpp) - 1;
3294 volatile uint8_t *udb;
3296 udb = sc->udbs_base + UDBS_DB_OFFSET;
3297 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3298 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3299 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3300 clrbit(&eq->doorbells, DOORBELL_WCWR);
3302 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3305 eq->udb = (volatile void *)udb;
3312 free_eq(struct adapter *sc, struct sge_eq *eq)
3316 if (eq->flags & EQ_ALLOCATED) {
3317 switch (eq->flags & EQ_TYPEMASK) {
3319 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3324 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3330 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3336 panic("%s: invalid eq type %d.", __func__,
3337 eq->flags & EQ_TYPEMASK);
3340 device_printf(sc->dev,
3341 "failed to free egress queue (%d): %d\n",
3342 eq->flags & EQ_TYPEMASK, rc);
3345 eq->flags &= ~EQ_ALLOCATED;
3348 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3350 if (mtx_initialized(&eq->eq_lock))
3351 mtx_destroy(&eq->eq_lock);
3353 bzero(eq, sizeof(*eq));
3358 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
3359 struct sysctl_oid *oid)
3362 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
3363 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3365 rc = alloc_eq(sc, vi, &wrq->eq);
3370 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3371 TAILQ_INIT(&wrq->incomplete_wrs);
3372 STAILQ_INIT(&wrq->wr_list);
3373 wrq->nwr_pending = 0;
3374 wrq->ndesc_needed = 0;
3376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3377 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3378 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3379 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3381 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3382 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3384 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3385 &wrq->tx_wrs_direct, "# of work requests (direct)");
3386 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3387 &wrq->tx_wrs_copied, "# of work requests (copied)");
3393 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3397 rc = free_eq(sc, &wrq->eq);
3401 bzero(wrq, sizeof(*wrq));
3406 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
3407 struct sysctl_oid *oid)
3410 struct port_info *pi = vi->pi;
3411 struct adapter *sc = pi->adapter;
3412 struct sge_eq *eq = &txq->eq;
3414 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3416 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3419 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3423 rc = alloc_eq(sc, vi, eq);
3425 mp_ring_free(txq->r);
3430 /* Can't fail after this point. */
3432 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3434 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3435 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3436 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
3437 V_TXPKT_VF(vi->viid));
3439 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3442 snprintf(name, sizeof(name), "%d", idx);
3443 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3445 children = SYSCTL_CHILDREN(oid);
3447 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3448 &eq->cntxt_id, 0, "SGE context id of the queue");
3449 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "cidx",
3450 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3452 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "pidx",
3453 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3456 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
3457 CTLTYPE_INT | CTLFLAG_RW, vi, idx, sysctl_tc, "I",
3458 "traffic class (-1 means none)");
3460 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3461 &txq->txcsum, "# of times hardware assisted with checksum");
3462 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
3463 CTLFLAG_RD, &txq->vlan_insertion,
3464 "# of times hardware inserted 802.1Q tag");
3465 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3466 &txq->tso_wrs, "# of TSO work requests");
3467 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3468 &txq->imm_wrs, "# of work requests with immediate data");
3469 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3470 &txq->sgl_wrs, "# of work requests with direct SGL");
3471 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3472 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3473 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
3474 CTLFLAG_RD, &txq->txpkts0_wrs,
3475 "# of txpkts (type 0) work requests");
3476 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
3477 CTLFLAG_RD, &txq->txpkts1_wrs,
3478 "# of txpkts (type 1) work requests");
3479 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
3480 CTLFLAG_RD, &txq->txpkts0_pkts,
3481 "# of frames tx'd using type0 txpkts work requests");
3482 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
3483 CTLFLAG_RD, &txq->txpkts1_pkts,
3484 "# of frames tx'd using type1 txpkts work requests");
3486 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_enqueues",
3487 CTLFLAG_RD, &txq->r->enqueues,
3488 "# of enqueues to the mp_ring for this queue");
3489 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_drops",
3490 CTLFLAG_RD, &txq->r->drops,
3491 "# of drops in the mp_ring for this queue");
3492 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_starts",
3493 CTLFLAG_RD, &txq->r->starts,
3494 "# of normal consumer starts in the mp_ring for this queue");
3495 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_stalls",
3496 CTLFLAG_RD, &txq->r->stalls,
3497 "# of consumer stalls in the mp_ring for this queue");
3498 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_restarts",
3499 CTLFLAG_RD, &txq->r->restarts,
3500 "# of consumer restarts in the mp_ring for this queue");
3501 SYSCTL_ADD_COUNTER_U64(&vi->ctx, children, OID_AUTO, "r_abdications",
3502 CTLFLAG_RD, &txq->r->abdications,
3503 "# of consumer abdications in the mp_ring for this queue");
3509 free_txq(struct vi_info *vi, struct sge_txq *txq)
3512 struct adapter *sc = vi->pi->adapter;
3513 struct sge_eq *eq = &txq->eq;
3515 rc = free_eq(sc, eq);
3519 sglist_free(txq->gl);
3520 free(txq->sdesc, M_CXGBE);
3521 mp_ring_free(txq->r);
3523 bzero(txq, sizeof(*txq));
3528 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3530 bus_addr_t *ba = arg;
3533 ("%s meant for single segment mappings only.", __func__));
3535 *ba = error ? 0 : segs->ds_addr;
3539 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3543 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3547 v = fl->dbval | V_PIDX(n);
3549 *fl->udb = htole32(v);
3551 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3552 IDXINCR(fl->dbidx, n, fl->sidx);
3556 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
3557 * recycled do not count towards this allocation budget.
3559 * Returns non-zero to indicate that this freelist should be added to the list
3560 * of starving freelists.
3563 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3566 struct fl_sdesc *sd;
3569 struct cluster_layout *cll;
3570 struct sw_zone_info *swz;
3571 struct cluster_metadata *clm;
3573 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3575 FL_LOCK_ASSERT_OWNED(fl);
3578 * We always stop at the beginning of the hardware descriptor that's just
3579 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3580 * which would mean an empty freelist to the chip.
3582 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3583 if (fl->pidx == max_pidx * 8)
3586 d = &fl->desc[fl->pidx];
3587 sd = &fl->sdesc[fl->pidx];
3588 cll = &fl->cll_def; /* default layout */
3589 swz = &sc->sge.sw_zone_info[cll->zidx];
3593 if (sd->cl != NULL) {
3595 if (sd->nmbuf == 0) {
3597 * Fast recycle without involving any atomics on
3598 * the cluster's metadata (if the cluster has
3599 * metadata). This happens when all frames
3600 * received in the cluster were small enough to
3601 * fit within a single mbuf each.
3603 fl->cl_fast_recycled++;
3605 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3607 MPASS(clm->refcount == 1);
3613 * Cluster is guaranteed to have metadata. Clusters
3614 * without metadata always take the fast recycle path
3615 * when they're recycled.
3617 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3620 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3622 counter_u64_add(extfree_rels, 1);
3625 sd->cl = NULL; /* gave up my reference */
3627 MPASS(sd->cl == NULL);
3629 cl = uma_zalloc(swz->zone, M_NOWAIT);
3630 if (__predict_false(cl == NULL)) {
3631 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3632 fl->cll_def.zidx == fl->cll_alt.zidx)
3635 /* fall back to the safe zone */
3637 swz = &sc->sge.sw_zone_info[cll->zidx];
3643 pa = pmap_kextract((vm_offset_t)cl);
3647 *d = htobe64(pa | cll->hwidx);
3648 clm = cl_metadata(sc, fl, cll, cl);
3660 if (__predict_false(++fl->pidx % 8 == 0)) {
3661 uint16_t pidx = fl->pidx / 8;
3663 if (__predict_false(pidx == fl->sidx)) {
3669 if (pidx == max_pidx)
3672 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3677 if (fl->pidx / 8 != fl->dbidx)
3680 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3684 * Attempt to refill all starving freelists.
3687 refill_sfl(void *arg)
3689 struct adapter *sc = arg;
3690 struct sge_fl *fl, *fl_temp;
3692 mtx_assert(&sc->sfl_lock, MA_OWNED);
3693 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3695 refill_fl(sc, fl, 64);
3696 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3697 TAILQ_REMOVE(&sc->sfl, fl, link);
3698 fl->flags &= ~FL_STARVING;
3703 if (!TAILQ_EMPTY(&sc->sfl))
3704 callout_schedule(&sc->sfl_callout, hz / 5);
3708 alloc_fl_sdesc(struct sge_fl *fl)
3711 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3718 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3720 struct fl_sdesc *sd;
3721 struct cluster_metadata *clm;
3722 struct cluster_layout *cll;
3726 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3731 clm = cl_metadata(sc, fl, cll, sd->cl);
3733 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3734 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3735 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3736 counter_u64_add(extfree_rels, 1);
3741 free(fl->sdesc, M_CXGBE);
3746 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3753 rc = sglist_append_mbuf(gl, m);
3754 if (__predict_false(rc != 0)) {
3755 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3756 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3759 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3760 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3761 mbuf_nsegs(m), gl->sg_nseg));
3762 KASSERT(gl->sg_nseg > 0 &&
3763 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3764 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3765 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3769 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3772 txpkt_len16(u_int nsegs, u_int tso)
3778 nsegs--; /* first segment is part of ulptx_sgl */
3779 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3780 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3782 n += sizeof(struct cpl_tx_pkt_lso_core);
3784 return (howmany(n, 16));
3788 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
3792 txpkts0_len16(u_int nsegs)
3798 nsegs--; /* first segment is part of ulptx_sgl */
3799 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
3800 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
3801 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3803 return (howmany(n, 16));
3807 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
3815 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
3817 return (howmany(n, 16));
3821 imm_payload(u_int ndesc)
3825 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
3826 sizeof(struct cpl_tx_pkt_core);
3832 * Write a txpkt WR for this packet to the hardware descriptors, update the
3833 * software descriptor, and advance the pidx. It is guaranteed that enough
3834 * descriptors are available.
3836 * The return value is the # of hardware descriptors used.
3839 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
3840 struct mbuf *m0, u_int available)
3842 struct sge_eq *eq = &txq->eq;
3843 struct tx_sdesc *txsd;
3844 struct cpl_tx_pkt_core *cpl;
3845 uint32_t ctrl; /* used in many unrelated places */
3847 int len16, ndesc, pktlen, nsegs;
3850 TXQ_LOCK_ASSERT_OWNED(txq);
3852 MPASS(available > 0 && available < eq->sidx);
3854 len16 = mbuf_len16(m0);
3855 nsegs = mbuf_nsegs(m0);
3856 pktlen = m0->m_pkthdr.len;
3857 ctrl = sizeof(struct cpl_tx_pkt_core);
3859 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3860 else if (pktlen <= imm_payload(2) && available >= 2) {
3861 /* Immediate data. Recalculate len16 and set nsegs to 0. */
3863 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
3864 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
3867 ndesc = howmany(len16, EQ_ESIZE / 16);
3868 MPASS(ndesc <= available);
3870 /* Firmware work request header */
3871 MPASS(wr == (void *)&eq->desc[eq->pidx]);
3872 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3873 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3875 ctrl = V_FW_WR_LEN16(len16);
3876 wr->equiq_to_len16 = htobe32(ctrl);
3879 if (needs_tso(m0)) {
3880 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3882 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
3883 m0->m_pkthdr.l4hlen > 0,
3884 ("%s: mbuf %p needs TSO but missing header lengths",
3887 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3888 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
3889 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
3890 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
3891 ctrl |= V_LSO_ETHHDR_LEN(1);
3892 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
3895 lso->lso_ctrl = htobe32(ctrl);
3896 lso->ipid_ofst = htobe16(0);
3897 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
3898 lso->seqno_offset = htobe32(0);
3899 lso->len = htobe32(pktlen);
3901 cpl = (void *)(lso + 1);
3905 cpl = (void *)(wr + 1);
3907 /* Checksum offload */
3909 if (needs_l3_csum(m0) == 0)
3910 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3911 if (needs_l4_csum(m0) == 0)
3912 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3913 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3914 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3915 txq->txcsum++; /* some hardware assistance provided */
3917 /* VLAN tag insertion */
3918 if (needs_vlan_insertion(m0)) {
3919 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
3920 txq->vlan_insertion++;
3924 cpl->ctrl0 = txq->cpl_ctrl0;
3926 cpl->len = htobe16(pktlen);
3927 cpl->ctrl1 = htobe64(ctrl1);
3930 dst = (void *)(cpl + 1);
3933 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
3938 for (m = m0; m != NULL; m = m->m_next) {
3939 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
3945 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
3952 txsd = &txq->sdesc[eq->pidx];
3954 txsd->desc_used = ndesc;
3960 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
3962 u_int needed, nsegs1, nsegs2, l1, l2;
3964 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
3967 nsegs1 = mbuf_nsegs(m);
3968 nsegs2 = mbuf_nsegs(n);
3969 if (nsegs1 + nsegs2 == 2) {
3971 l1 = l2 = txpkts1_len16();
3974 l1 = txpkts0_len16(nsegs1);
3975 l2 = txpkts0_len16(nsegs2);
3977 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
3978 needed = howmany(txp->len16, EQ_ESIZE / 16);
3979 if (needed > SGE_MAX_WR_NDESC || needed > available)
3982 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
3983 if (txp->plen > 65535)
3987 set_mbuf_len16(m, l1);
3988 set_mbuf_len16(n, l2);
3994 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
3996 u_int plen, len16, needed, nsegs;
3998 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4000 nsegs = mbuf_nsegs(m);
4001 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4004 plen = txp->plen + m->m_pkthdr.len;
4008 if (txp->wr_type == 0)
4009 len16 = txpkts0_len16(nsegs);
4011 len16 = txpkts1_len16();
4012 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4013 if (needed > SGE_MAX_WR_NDESC || needed > available)
4018 txp->len16 += len16;
4019 set_mbuf_len16(m, len16);
4025 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4026 * the software descriptor, and advance the pidx. It is guaranteed that enough
4027 * descriptors are available.
4029 * The return value is the # of hardware descriptors used.
4032 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4033 struct mbuf *m0, const struct txpkts *txp, u_int available)
4035 struct sge_eq *eq = &txq->eq;
4036 struct tx_sdesc *txsd;
4037 struct cpl_tx_pkt_core *cpl;
4040 int ndesc, checkwrap;
4044 TXQ_LOCK_ASSERT_OWNED(txq);
4045 MPASS(txp->npkt > 0);
4046 MPASS(txp->plen < 65536);
4048 MPASS(m0->m_nextpkt != NULL);
4049 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4050 MPASS(available > 0 && available < eq->sidx);
4052 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4053 MPASS(ndesc <= available);
4055 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4056 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4057 ctrl = V_FW_WR_LEN16(txp->len16);
4058 wr->equiq_to_len16 = htobe32(ctrl);
4059 wr->plen = htobe16(txp->plen);
4060 wr->npkt = txp->npkt;
4062 wr->type = txp->wr_type;
4066 * At this point we are 16B into a hardware descriptor. If checkwrap is
4067 * set then we know the WR is going to wrap around somewhere. We'll
4068 * check for that at appropriate points.
4070 checkwrap = eq->sidx - ndesc < eq->pidx;
4071 for (m = m0; m != NULL; m = m->m_nextpkt) {
4072 if (txp->wr_type == 0) {
4073 struct ulp_txpkt *ulpmc;
4074 struct ulptx_idata *ulpsc;
4076 /* ULP master command */
4078 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4079 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4080 ulpmc->len = htobe32(mbuf_len16(m));
4082 /* ULP subcommand */
4083 ulpsc = (void *)(ulpmc + 1);
4084 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4086 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4088 cpl = (void *)(ulpsc + 1);
4090 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4091 cpl = (void *)&eq->desc[0];
4092 txq->txpkts0_pkts += txp->npkt;
4096 txq->txpkts1_pkts += txp->npkt;
4100 /* Checksum offload */
4102 if (needs_l3_csum(m) == 0)
4103 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4104 if (needs_l4_csum(m) == 0)
4105 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4106 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4107 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4108 txq->txcsum++; /* some hardware assistance provided */
4110 /* VLAN tag insertion */
4111 if (needs_vlan_insertion(m)) {
4112 ctrl1 |= F_TXPKT_VLAN_VLD |
4113 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4114 txq->vlan_insertion++;
4118 cpl->ctrl0 = txq->cpl_ctrl0;
4120 cpl->len = htobe16(m->m_pkthdr.len);
4121 cpl->ctrl1 = htobe64(ctrl1);
4125 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4126 flitp = (void *)&eq->desc[0];
4128 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4132 txsd = &txq->sdesc[eq->pidx];
4134 txsd->desc_used = ndesc;
4140 * If the SGL ends on an address that is not 16 byte aligned, this function will
4141 * add a 0 filled flit at the end.
4144 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4146 struct sge_eq *eq = &txq->eq;
4147 struct sglist *gl = txq->gl;
4148 struct sglist_seg *seg;
4149 __be64 *flitp, *wrap;
4150 struct ulptx_sgl *usgl;
4151 int i, nflits, nsegs;
4153 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4154 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4155 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4156 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4159 nsegs = gl->sg_nseg;
4162 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4163 flitp = (__be64 *)(*to);
4164 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4165 seg = &gl->sg_segs[0];
4166 usgl = (void *)flitp;
4169 * We start at a 16 byte boundary somewhere inside the tx descriptor
4170 * ring, so we're at least 16 bytes away from the status page. There is
4171 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4174 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4175 V_ULPTX_NSGE(nsegs));
4176 usgl->len0 = htobe32(seg->ss_len);
4177 usgl->addr0 = htobe64(seg->ss_paddr);
4180 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4182 /* Won't wrap around at all */
4184 for (i = 0; i < nsegs - 1; i++, seg++) {
4185 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4186 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4189 usgl->sge[i / 2].len[1] = htobe32(0);
4193 /* Will wrap somewhere in the rest of the SGL */
4195 /* 2 flits already written, write the rest flit by flit */
4196 flitp = (void *)(usgl + 1);
4197 for (i = 0; i < nflits - 2; i++) {
4199 flitp = (void *)eq->desc;
4200 *flitp++ = get_flit(seg, nsegs - 1, i);
4205 MPASS(((uintptr_t)flitp) & 0xf);
4209 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4210 if (__predict_false(flitp == wrap))
4211 *to = (void *)eq->desc;
4213 *to = (void *)flitp;
4217 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4220 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4221 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4223 if (__predict_true((uintptr_t)(*to) + len <=
4224 (uintptr_t)&eq->desc[eq->sidx])) {
4225 bcopy(from, *to, len);
4228 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4230 bcopy(from, *to, portion);
4232 portion = len - portion; /* remaining */
4233 bcopy(from, (void *)eq->desc, portion);
4234 (*to) = (caddr_t)eq->desc + portion;
4239 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4247 clrbit(&db, DOORBELL_WCWR);
4250 switch (ffs(db) - 1) {
4252 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4255 case DOORBELL_WCWR: {
4256 volatile uint64_t *dst, *src;
4260 * Queues whose 128B doorbell segment fits in the page do not
4261 * use relative qid (udb_qid is always 0). Only queues with
4262 * doorbell segments can do WCWR.
4264 KASSERT(eq->udb_qid == 0 && n == 1,
4265 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4266 __func__, eq->doorbells, n, eq->dbidx, eq));
4268 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4271 src = (void *)&eq->desc[i];
4272 while (src != (void *)&eq->desc[i + 1])
4278 case DOORBELL_UDBWC:
4279 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4284 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4285 V_QID(eq->cntxt_id) | V_PIDX(n));
4289 IDXINCR(eq->dbidx, n, eq->sidx);
4293 reclaimable_tx_desc(struct sge_eq *eq)
4297 hw_cidx = read_hw_cidx(eq);
4298 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4302 total_available_tx_desc(struct sge_eq *eq)
4304 uint16_t hw_cidx, pidx;
4306 hw_cidx = read_hw_cidx(eq);
4309 if (pidx == hw_cidx)
4310 return (eq->sidx - 1);
4312 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4315 static inline uint16_t
4316 read_hw_cidx(struct sge_eq *eq)
4318 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4319 uint16_t cidx = spg->cidx; /* stable snapshot */
4321 return (be16toh(cidx));
4325 * Reclaim 'n' descriptors approximately.
4328 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4330 struct tx_sdesc *txsd;
4331 struct sge_eq *eq = &txq->eq;
4332 u_int can_reclaim, reclaimed;
4334 TXQ_LOCK_ASSERT_OWNED(txq);
4338 can_reclaim = reclaimable_tx_desc(eq);
4339 while (can_reclaim && reclaimed < n) {
4341 struct mbuf *m, *nextpkt;
4343 txsd = &txq->sdesc[eq->cidx];
4344 ndesc = txsd->desc_used;
4346 /* Firmware doesn't return "partial" credits. */
4347 KASSERT(can_reclaim >= ndesc,
4348 ("%s: unexpected number of credits: %d, %d",
4349 __func__, can_reclaim, ndesc));
4351 for (m = txsd->m; m != NULL; m = nextpkt) {
4352 nextpkt = m->m_nextpkt;
4353 m->m_nextpkt = NULL;
4357 can_reclaim -= ndesc;
4358 IDXINCR(eq->cidx, ndesc, eq->sidx);
4365 tx_reclaim(void *arg, int n)
4367 struct sge_txq *txq = arg;
4368 struct sge_eq *eq = &txq->eq;
4371 if (TXQ_TRYLOCK(txq) == 0)
4373 n = reclaim_tx_descs(txq, 32);
4374 if (eq->cidx == eq->pidx)
4375 eq->equeqidx = eq->pidx;
4381 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4383 int i = (idx / 3) * 2;
4389 rc = htobe32(segs[i].ss_len);
4391 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4396 return (htobe64(segs[i].ss_paddr));
4398 return (htobe64(segs[i + 1].ss_paddr));
4405 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4407 int8_t zidx, hwidx, idx;
4408 uint16_t region1, region3;
4409 int spare, spare_needed, n;
4410 struct sw_zone_info *swz;
4411 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4414 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4415 * large enough for the max payload and cluster metadata. Otherwise
4416 * settle for the largest bufsize that leaves enough room in the cluster
4419 * Without buffer packing: Look for the smallest zone which has a
4420 * bufsize large enough for the max payload. Settle for the largest
4421 * bufsize available if there's nothing big enough for max payload.
4423 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4424 swz = &sc->sge.sw_zone_info[0];
4426 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4427 if (swz->size > largest_rx_cluster) {
4428 if (__predict_true(hwidx != -1))
4432 * This is a misconfiguration. largest_rx_cluster is
4433 * preventing us from finding a refill source. See
4434 * dev.t5nex.<n>.buffer_sizes to figure out why.
4436 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4437 " refill source for fl %p (dma %u). Ignored.\n",
4438 largest_rx_cluster, fl, maxp);
4440 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4441 hwb = &hwb_list[idx];
4442 spare = swz->size - hwb->size;
4443 if (spare < spare_needed)
4446 hwidx = idx; /* best option so far */
4447 if (hwb->size >= maxp) {
4449 if ((fl->flags & FL_BUF_PACKING) == 0)
4450 goto done; /* stop looking (not packing) */
4452 if (swz->size >= safest_rx_cluster)
4453 goto done; /* stop looking (packing) */
4455 break; /* keep looking, next zone */
4459 /* A usable hwidx has been located. */
4461 hwb = &hwb_list[hwidx];
4463 swz = &sc->sge.sw_zone_info[zidx];
4465 region3 = swz->size - hwb->size;
4468 * Stay within this zone and see if there is a better match when mbuf
4469 * inlining is allowed. Remember that the hwidx's are sorted in
4470 * decreasing order of size (so in increasing order of spare area).
4472 for (idx = hwidx; idx != -1; idx = hwb->next) {
4473 hwb = &hwb_list[idx];
4474 spare = swz->size - hwb->size;
4476 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4480 * Do not inline mbufs if doing so would violate the pad/pack
4481 * boundary alignment requirement.
4483 if (fl_pad && (MSIZE % sc->params.sge.pad_boundary) != 0)
4485 if (fl->flags & FL_BUF_PACKING &&
4486 (MSIZE % sc->params.sge.pack_boundary) != 0)
4489 if (spare < CL_METADATA_SIZE + MSIZE)
4491 n = (spare - CL_METADATA_SIZE) / MSIZE;
4492 if (n > howmany(hwb->size, maxp))
4496 if (fl->flags & FL_BUF_PACKING) {
4497 region1 = n * MSIZE;
4498 region3 = spare - region1;
4501 region3 = spare - region1;
4506 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4507 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4508 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4509 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4510 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4511 sc->sge.sw_zone_info[zidx].size,
4512 ("%s: bad buffer layout for fl %p, maxp %d. "
4513 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4514 sc->sge.sw_zone_info[zidx].size, region1,
4515 sc->sge.hw_buf_info[hwidx].size, region3));
4516 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4517 KASSERT(region3 >= CL_METADATA_SIZE,
4518 ("%s: no room for metadata. fl %p, maxp %d; "
4519 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4520 sc->sge.sw_zone_info[zidx].size, region1,
4521 sc->sge.hw_buf_info[hwidx].size, region3));
4522 KASSERT(region1 % MSIZE == 0,
4523 ("%s: bad mbuf region for fl %p, maxp %d. "
4524 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4525 sc->sge.sw_zone_info[zidx].size, region1,
4526 sc->sge.hw_buf_info[hwidx].size, region3));
4529 fl->cll_def.zidx = zidx;
4530 fl->cll_def.hwidx = hwidx;
4531 fl->cll_def.region1 = region1;
4532 fl->cll_def.region3 = region3;
4536 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4538 struct sge *s = &sc->sge;
4539 struct hw_buf_info *hwb;
4540 struct sw_zone_info *swz;
4544 if (fl->flags & FL_BUF_PACKING)
4545 hwidx = s->safe_hwidx2; /* with room for metadata */
4546 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4547 hwidx = s->safe_hwidx2;
4548 hwb = &s->hw_buf_info[hwidx];
4549 swz = &s->sw_zone_info[hwb->zidx];
4550 spare = swz->size - hwb->size;
4552 /* no good if there isn't room for an mbuf as well */
4553 if (spare < CL_METADATA_SIZE + MSIZE)
4554 hwidx = s->safe_hwidx1;
4556 hwidx = s->safe_hwidx1;
4559 /* No fallback source */
4560 fl->cll_alt.hwidx = -1;
4561 fl->cll_alt.zidx = -1;
4566 hwb = &s->hw_buf_info[hwidx];
4567 swz = &s->sw_zone_info[hwb->zidx];
4568 spare = swz->size - hwb->size;
4569 fl->cll_alt.hwidx = hwidx;
4570 fl->cll_alt.zidx = hwb->zidx;
4571 if (allow_mbufs_in_cluster &&
4572 (fl_pad == 0 || (MSIZE % sc->params.sge.pad_boundary) == 0))
4573 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4575 fl->cll_alt.region1 = 0;
4576 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4580 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4582 mtx_lock(&sc->sfl_lock);
4584 if ((fl->flags & FL_DOOMED) == 0) {
4585 fl->flags |= FL_STARVING;
4586 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4587 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4590 mtx_unlock(&sc->sfl_lock);
4594 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
4596 struct sge_wrq *wrq = (void *)eq;
4598 atomic_readandclear_int(&eq->equiq);
4599 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
4603 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
4605 struct sge_txq *txq = (void *)eq;
4607 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
4609 atomic_readandclear_int(&eq->equiq);
4610 mp_ring_check_drainage(txq->r, 0);
4611 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
4615 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4618 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4619 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4620 struct adapter *sc = iq->adapter;
4621 struct sge *s = &sc->sge;
4623 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
4624 &handle_wrq_egr_update, &handle_eth_egr_update,
4625 &handle_wrq_egr_update};
4627 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4630 eq = s->eqmap[qid - s->eq_start];
4631 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
4636 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4637 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4638 offsetof(struct cpl_fw6_msg, data));
4641 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4643 struct adapter *sc = iq->adapter;
4644 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4646 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4649 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4650 const struct rss_header *rss2;
4652 rss2 = (const struct rss_header *)&cpl->data[0];
4653 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4656 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4660 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4662 uint16_t *id = arg1;
4665 return sysctl_handle_int(oidp, &i, 0, req);
4669 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4671 struct sge *s = arg1;
4672 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4673 struct sw_zone_info *swz = &s->sw_zone_info[0];
4678 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4679 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4680 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4685 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4689 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
4695 sysctl_tc(SYSCTL_HANDLER_ARGS)
4697 struct vi_info *vi = arg1;
4698 struct port_info *pi;
4700 struct sge_txq *txq;
4701 struct tx_sched_class *tc;
4702 int qidx = arg2, rc, tc_idx;
4703 uint32_t fw_queue, fw_class;
4705 MPASS(qidx >= 0 && qidx < vi->ntxq);
4708 txq = &sc->sge.txq[vi->first_txq + qidx];
4710 tc_idx = txq->tc_idx;
4711 rc = sysctl_handle_int(oidp, &tc_idx, 0, req);
4712 if (rc != 0 || req->newptr == NULL)
4715 /* Note that -1 is legitimate input (it means unbind). */
4716 if (tc_idx < -1 || tc_idx >= sc->chip_params->nsched_cls)
4719 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4stc");
4723 if (tc_idx == txq->tc_idx) {
4724 rc = 0; /* No change, nothing to do. */
4728 fw_queue = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
4729 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) |
4730 V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id);
4733 fw_class = 0xffffffff; /* Unbind. */
4736 * Bind to a different class. Ethernet txq's are only allowed
4737 * to bind to cl-rl mode-class for now. XXX: too restrictive.
4739 tc = &pi->tc[tc_idx];
4740 if (tc->flags & TX_SC_OK &&
4741 tc->params.level == SCHED_CLASS_LEVEL_CL_RL &&
4742 tc->params.mode == SCHED_CLASS_MODE_CLASS) {
4743 /* Ok to proceed. */
4746 rc = tc->flags & TX_SC_OK ? EBUSY : ENXIO;
4751 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, &fw_class);
4753 if (txq->tc_idx != -1) {
4754 tc = &pi->tc[txq->tc_idx];
4755 MPASS(tc->refcount > 0);
4759 tc = &pi->tc[tc_idx];
4762 txq->tc_idx = tc_idx;
4765 end_synchronized_op(sc, 0);