2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_inet6.h"
35 #include "opt_kern_tls.h"
36 #include "opt_ratelimit.h"
38 #include <sys/types.h>
39 #include <sys/eventhandler.h>
41 #include <sys/socket.h>
42 #include <sys/kernel.h>
44 #include <sys/malloc.h>
45 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
49 #include <sys/sglist.h>
50 #include <sys/sysctl.h>
52 #include <sys/socketvar.h>
53 #include <sys/counter.h>
55 #include <net/ethernet.h>
57 #include <net/if_vlan_var.h>
58 #include <net/if_vxlan.h>
59 #include <netinet/in.h>
60 #include <netinet/ip.h>
61 #include <netinet/ip6.h>
62 #include <netinet/tcp.h>
63 #include <netinet/udp.h>
64 #include <machine/in_cksum.h>
65 #include <machine/md_var.h>
69 #include <machine/bus.h>
70 #include <sys/selinfo.h>
71 #include <net/if_var.h>
72 #include <net/netmap.h>
73 #include <dev/netmap/netmap_kern.h>
76 #include "common/common.h"
77 #include "common/t4_regs.h"
78 #include "common/t4_regs_values.h"
79 #include "common/t4_msg.h"
81 #include "t4_mp_ring.h"
83 #ifdef T4_PKT_TIMESTAMP
84 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
86 #define RX_COPY_THRESHOLD MINCLSIZE
89 /* Internal mbuf flags stored in PH_loc.eight[1]. */
91 #define MC_RAW_WR 0x02
95 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
96 * 0-7 are valid values.
98 static int fl_pktshift = 0;
99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
100 "payload DMA offset in rx buffer (bytes)");
103 * Pad ethernet payload up to this boundary.
104 * -1: driver should figure out a good value.
105 * 0: disable padding.
106 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
109 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
110 "payload pad boundary (bytes)");
113 * Status page length.
114 * -1: driver should figure out a good value.
115 * 64 or 128 are the only other valid values.
117 static int spg_len = -1;
118 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
119 "status page size (bytes)");
123 * -1: no congestion feedback (not recommended).
124 * 0: backpressure the channel instead of dropping packets right away.
125 * 1: no backpressure, drop packets for the congested queue immediately.
127 static int cong_drop = 0;
128 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
129 "Congestion control for RX queues (0 = backpressure, 1 = drop");
132 * Deliver multiple frames in the same free list buffer if they fit.
133 * -1: let the driver decide whether to enable buffer packing or not.
134 * 0: disable buffer packing.
135 * 1: enable buffer packing.
137 static int buffer_packing = -1;
138 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
139 0, "Enable buffer packing");
142 * Start next frame in a packed buffer at this boundary.
143 * -1: driver should figure out a good value.
144 * T4: driver will ignore this and use the same value as fl_pad above.
145 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
147 static int fl_pack = -1;
148 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
149 "payload pack boundary (bytes)");
152 * Largest rx cluster size that the driver is allowed to allocate.
154 static int largest_rx_cluster = MJUM16BYTES;
155 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
156 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
159 * Size of cluster allocation that's most likely to succeed. The driver will
160 * fall back to this size if it fails to allocate clusters larger than this.
162 static int safest_rx_cluster = PAGE_SIZE;
163 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
164 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
168 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
169 * for rewriting. -1 and 0-3 are all valid values.
170 * -1: hardware should leave the TCP timestamps alone.
176 static int tsclk = -1;
177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
178 "Control TCP timestamp rewriting when using pacing");
180 static int eo_max_backlog = 1024 * 1024;
181 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
182 0, "Maximum backlog of ratelimited data per flow");
186 * The interrupt holdoff timers are multiplied by this value on T6+.
187 * 1 and 3-17 (both inclusive) are legal values.
189 static int tscale = 1;
190 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
191 "Interrupt holdoff timer scale on T6+");
194 * Number of LRO entries in the lro_ctrl structure per rx queue.
196 static int lro_entries = TCP_LRO_ENTRIES;
197 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
198 "Number of LRO entries per RX queue");
201 * This enables presorting of frames before they're fed into tcp_lro_rx.
203 static int lro_mbufs = 0;
204 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
205 "Enable presorting of LRO frames");
207 static counter_u64_t pullups;
208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups,
209 "Number of mbuf pullups performed");
211 static counter_u64_t defrags;
212 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags,
213 "Number of mbuf defrags performed");
215 static int t4_tx_coalesce = 1;
216 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0,
217 "tx coalescing allowed");
220 * The driver will make aggressive attempts at tx coalescing if it sees these
221 * many packets eligible for coalescing in quick succession, with no more than
222 * the specified gap in between the eth_tx calls that delivered the packets.
224 static int t4_tx_coalesce_pkts = 32;
225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN,
226 &t4_tx_coalesce_pkts, 0,
227 "# of consecutive packets (1 - 255) that will trigger tx coalescing");
228 static int t4_tx_coalesce_gap = 5;
229 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN,
230 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)");
232 static int service_iq(struct sge_iq *, int);
233 static int service_iq_fl(struct sge_iq *, int);
234 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
235 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
237 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
238 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
239 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
241 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
243 static int free_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *);
244 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
246 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
247 struct sysctl_oid *, struct sge_fl *);
248 static int alloc_fwq(struct adapter *);
249 static int free_fwq(struct adapter *);
250 static int alloc_ctrlq(struct adapter *, struct sge_wrq *, int,
251 struct sysctl_oid *);
252 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int,
253 struct sysctl_oid *);
254 static int free_rxq(struct vi_info *, struct sge_rxq *);
256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
257 struct sysctl_oid *);
258 static int free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
260 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
261 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
262 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
263 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
265 static int alloc_eq(struct adapter *, struct vi_info *, struct sge_eq *);
266 static int free_eq(struct adapter *, struct sge_eq *);
267 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
268 struct sysctl_oid *);
269 static int free_wrq(struct adapter *, struct sge_wrq *);
270 static int alloc_txq(struct vi_info *, struct sge_txq *, int,
271 struct sysctl_oid *);
272 static int free_txq(struct vi_info *, struct sge_txq *);
273 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
274 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
275 static int refill_fl(struct adapter *, struct sge_fl *, int);
276 static void refill_sfl(void *);
277 static int alloc_fl_sdesc(struct sge_fl *);
278 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
279 static int find_refill_source(struct adapter *, int, bool);
280 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
282 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
283 static inline u_int txpkt_len16(u_int, const u_int);
284 static inline u_int txpkt_vm_len16(u_int, const u_int);
285 static inline void calculate_mbuf_len16(struct mbuf *, bool);
286 static inline u_int txpkts0_len16(u_int);
287 static inline u_int txpkts1_len16(void);
288 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
289 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *,
291 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
293 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *,
295 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *,
297 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *);
298 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *);
299 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
300 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
301 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
302 static inline uint16_t read_hw_cidx(struct sge_eq *);
303 static inline u_int reclaimable_tx_desc(struct sge_eq *);
304 static inline u_int total_available_tx_desc(struct sge_eq *);
305 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
306 static void tx_reclaim(void *, int);
307 static __be64 get_flit(struct sglist_seg *, int, int);
308 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
310 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
312 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
313 static void wrq_tx_drain(void *, int);
314 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
316 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
318 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
319 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
323 static counter_u64_t extfree_refs;
324 static counter_u64_t extfree_rels;
326 an_handler_t t4_an_handler;
327 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
328 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
329 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
330 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
331 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
332 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
333 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
336 t4_register_an_handler(an_handler_t h)
340 MPASS(h == NULL || t4_an_handler == NULL);
342 loc = (uintptr_t *)&t4_an_handler;
343 atomic_store_rel_ptr(loc, (uintptr_t)h);
347 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
351 MPASS(type < nitems(t4_fw_msg_handler));
352 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
354 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
355 * handler dispatch table. Reject any attempt to install a handler for
358 MPASS(type != FW_TYPE_RSSCPL);
359 MPASS(type != FW6_TYPE_RSSCPL);
361 loc = (uintptr_t *)&t4_fw_msg_handler[type];
362 atomic_store_rel_ptr(loc, (uintptr_t)h);
366 t4_register_cpl_handler(int opcode, cpl_handler_t h)
370 MPASS(opcode < nitems(t4_cpl_handler));
371 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
373 loc = (uintptr_t *)&t4_cpl_handler[opcode];
374 atomic_store_rel_ptr(loc, (uintptr_t)h);
378 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
381 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
388 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
390 * The return code for filter-write is put in the CPL cookie so
391 * we have to rely on the hardware tid (is_ftid) to determine
392 * that this is a response to a filter.
394 cookie = CPL_COOKIE_FILTER;
396 cookie = G_COOKIE(cpl->cookie);
398 MPASS(cookie > CPL_COOKIE_RESERVED);
399 MPASS(cookie < nitems(set_tcb_rpl_handlers));
401 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
405 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
408 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
413 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
414 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
418 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
421 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
422 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
425 MPASS(cookie != CPL_COOKIE_RESERVED);
427 return (act_open_rpl_handlers[cookie](iq, rss, m));
431 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
434 struct adapter *sc = iq->adapter;
438 if (is_hashfilter(sc))
439 cookie = CPL_COOKIE_HASHFILTER;
441 cookie = CPL_COOKIE_TOM;
443 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
447 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
449 struct adapter *sc = iq->adapter;
450 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
451 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
455 if (is_etid(sc, tid))
456 cookie = CPL_COOKIE_ETHOFLD;
458 cookie = CPL_COOKIE_TOM;
460 return (fw4_ack_handlers[cookie](iq, rss, m));
464 t4_init_shared_cpl_handlers(void)
467 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
468 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
469 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
470 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
471 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
475 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
479 MPASS(opcode < nitems(t4_cpl_handler));
480 MPASS(cookie > CPL_COOKIE_RESERVED);
481 MPASS(cookie < NUM_CPL_COOKIES);
482 MPASS(t4_cpl_handler[opcode] != NULL);
485 case CPL_SET_TCB_RPL:
486 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
488 case CPL_L2T_WRITE_RPL:
489 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
491 case CPL_ACT_OPEN_RPL:
492 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
494 case CPL_ABORT_RPL_RSS:
495 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
498 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
504 MPASS(h == NULL || *loc == (uintptr_t)NULL);
505 atomic_store_rel_ptr(loc, (uintptr_t)h);
509 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
515 if (fl_pktshift < 0 || fl_pktshift > 7) {
516 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
517 " using 0 instead.\n", fl_pktshift);
521 if (spg_len != 64 && spg_len != 128) {
524 #if defined(__i386__) || defined(__amd64__)
525 len = cpu_clflush_line_size > 64 ? 128 : 64;
530 printf("Invalid hw.cxgbe.spg_len value (%d),"
531 " using %d instead.\n", spg_len, len);
536 if (cong_drop < -1 || cong_drop > 1) {
537 printf("Invalid hw.cxgbe.cong_drop value (%d),"
538 " using 0 instead.\n", cong_drop);
542 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
543 printf("Invalid hw.cxgbe.tscale value (%d),"
544 " using 1 instead.\n", tscale);
548 if (largest_rx_cluster != MCLBYTES &&
549 #if MJUMPAGESIZE != MCLBYTES
550 largest_rx_cluster != MJUMPAGESIZE &&
552 largest_rx_cluster != MJUM9BYTES &&
553 largest_rx_cluster != MJUM16BYTES) {
554 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d),"
555 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES);
556 largest_rx_cluster = MJUM16BYTES;
559 if (safest_rx_cluster != MCLBYTES &&
560 #if MJUMPAGESIZE != MCLBYTES
561 safest_rx_cluster != MJUMPAGESIZE &&
563 safest_rx_cluster != MJUM9BYTES &&
564 safest_rx_cluster != MJUM16BYTES) {
565 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d),"
566 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE);
567 safest_rx_cluster = MJUMPAGESIZE;
570 extfree_refs = counter_u64_alloc(M_WAITOK);
571 extfree_rels = counter_u64_alloc(M_WAITOK);
572 pullups = counter_u64_alloc(M_WAITOK);
573 defrags = counter_u64_alloc(M_WAITOK);
574 counter_u64_zero(extfree_refs);
575 counter_u64_zero(extfree_rels);
576 counter_u64_zero(pullups);
577 counter_u64_zero(defrags);
579 t4_init_shared_cpl_handlers();
580 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
581 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
582 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
584 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
587 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
588 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
592 t4_sge_modunload(void)
595 counter_u64_free(extfree_refs);
596 counter_u64_free(extfree_rels);
597 counter_u64_free(pullups);
598 counter_u64_free(defrags);
602 t4_sge_extfree_refs(void)
606 rels = counter_u64_fetch(extfree_rels);
607 refs = counter_u64_fetch(extfree_refs);
609 return (refs - rels);
613 #define MAX_PACK_BOUNDARY 512
616 setup_pad_and_pack_boundaries(struct adapter *sc)
619 int pad, pack, pad_shift;
621 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
622 X_INGPADBOUNDARY_SHIFT;
624 if (fl_pad < (1 << pad_shift) ||
625 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
628 * If there is any chance that we might use buffer packing and
629 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
630 * it to the minimum allowed in all other cases.
632 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
635 * For fl_pad = 0 we'll still write a reasonable value to the
636 * register but all the freelists will opt out of padding.
637 * We'll complain here only if the user tried to set it to a
638 * value greater than 0 that was invalid.
641 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
642 " (%d), using %d instead.\n", fl_pad, pad);
645 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
646 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
647 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
650 if (fl_pack != -1 && fl_pack != pad) {
651 /* Complain but carry on. */
652 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
653 " using %d instead.\n", fl_pack, pad);
659 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
660 !powerof2(fl_pack)) {
661 if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
662 pack = MAX_PACK_BOUNDARY;
664 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
665 MPASS(powerof2(pack));
673 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
674 " (%d), using %d instead.\n", fl_pack, pack);
677 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
679 v = V_INGPACKBOUNDARY(0);
681 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
683 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
684 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
688 * adap->params.vpd.cclk must be set up before this is called.
691 t4_tweak_chip_settings(struct adapter *sc)
695 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
696 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
697 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
698 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
699 static int sw_buf_sizes[] = {
701 #if MJUMPAGESIZE != MCLBYTES
708 KASSERT(sc->flags & MASTER_PF,
709 ("%s: trying to change chip settings when not master.", __func__));
711 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
712 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
713 V_EGRSTATUSPAGESIZE(spg_len == 128);
714 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
716 setup_pad_and_pack_boundaries(sc);
718 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
719 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
720 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
721 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
722 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
723 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
724 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
725 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
726 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
728 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
729 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
730 reg = A_SGE_FL_BUFFER_SIZE2;
731 for (i = 0; i < nitems(sw_buf_sizes); i++) {
732 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
733 t4_write_reg(sc, reg, sw_buf_sizes[i]);
735 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
736 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
740 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
741 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
742 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
744 KASSERT(intr_timer[0] <= timer_max,
745 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
747 for (i = 1; i < nitems(intr_timer); i++) {
748 KASSERT(intr_timer[i] >= intr_timer[i - 1],
749 ("%s: timers not listed in increasing order (%d)",
752 while (intr_timer[i] > timer_max) {
753 if (i == nitems(intr_timer) - 1) {
754 intr_timer[i] = timer_max;
757 intr_timer[i] += intr_timer[i - 1];
762 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
763 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
764 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
765 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
766 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
767 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
768 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
769 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
770 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
772 if (chip_id(sc) >= CHELSIO_T6) {
773 m = V_TSCALE(M_TSCALE);
777 v = V_TSCALE(tscale - 2);
778 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
780 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
781 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
782 V_WRTHRTHRESH(M_WRTHRTHRESH);
783 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
785 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
787 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
791 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
792 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
793 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
796 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
797 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
798 * may have to deal with is MAXPHYS + 1 page.
800 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
801 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
803 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
804 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
805 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
807 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
809 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
810 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
814 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its
815 * address mut be 16B aligned. If padding is in use the buffer's start and end
816 * need to be aligned to the pad boundary as well. We'll just make sure that
817 * the size is a multiple of the pad boundary here, it is up to the buffer
818 * allocation code to make sure the start of the buffer is aligned.
821 hwsz_ok(struct adapter *sc, int hwsz)
823 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
825 return (hwsz >= 64 && (hwsz & mask) == 0);
829 * Initialize the rx buffer sizes and figure out which zones the buffers will
833 t4_init_rx_buf_info(struct adapter *sc)
835 struct sge *s = &sc->sge;
836 struct sge_params *sp = &sc->params.sge;
838 static int sw_buf_sizes[] = { /* Sorted by size */
840 #if MJUMPAGESIZE != MCLBYTES
846 struct rx_buf_info *rxb;
849 rxb = &s->rx_buf_info[0];
850 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
851 rxb->size1 = sw_buf_sizes[i];
852 rxb->zone = m_getzone(rxb->size1);
853 rxb->type = m_gettype(rxb->size1);
857 for (j = 0; j < SGE_FLBUF_SIZES; j++) {
858 int hwsize = sp->sge_fl_buffer_size[j];
860 if (!hwsz_ok(sc, hwsize))
863 /* hwidx for size1 */
864 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
867 /* hwidx for size2 (buffer packing) */
868 if (rxb->size1 - CL_METADATA_SIZE < hwsize)
870 n = rxb->size1 - hwsize - CL_METADATA_SIZE;
874 break; /* stop looking */
876 if (rxb->hwidx2 != -1) {
877 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
878 hwsize - CL_METADATA_SIZE) {
882 } else if (n <= 2 * CL_METADATA_SIZE) {
887 if (rxb->hwidx2 != -1)
888 sc->flags |= BUF_PACKING_OK;
889 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
895 * Verify some basic SGE settings for the PF and VF driver, and other
896 * miscellaneous settings for the PF driver.
899 t4_verify_chip_settings(struct adapter *sc)
901 struct sge_params *sp = &sc->params.sge;
904 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
910 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
915 * If this changes then every single use of PAGE_SHIFT in the driver
916 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
918 if (sp->page_shift != PAGE_SHIFT) {
919 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
923 if (sc->flags & IS_VF)
926 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
927 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
929 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
930 if (sc->vres.ddp.size != 0)
934 m = v = F_TDDPTAGTCB;
935 r = t4_read_reg(sc, A_ULP_RX_CTL);
937 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
938 if (sc->vres.ddp.size != 0)
942 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
944 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
945 r = t4_read_reg(sc, A_TP_PARA_REG5);
947 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
948 if (sc->vres.ddp.size != 0)
956 t4_create_dma_tag(struct adapter *sc)
960 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
961 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
962 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
965 device_printf(sc->dev,
966 "failed to create main DMA tag: %d\n", rc);
973 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
974 struct sysctl_oid_list *children)
976 struct sge_params *sp = &sc->params.sge;
978 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
979 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
980 sysctl_bufsizes, "A", "freelist buffer sizes");
982 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
983 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
985 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
986 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
988 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
989 NULL, sp->spg_len, "status page size (bytes)");
991 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
992 NULL, cong_drop, "congestion drop setting");
994 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
995 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
999 t4_destroy_dma_tag(struct adapter *sc)
1002 bus_dma_tag_destroy(sc->dmat);
1008 * Allocate and initialize the firmware event queue, control queues, and special
1009 * purpose rx queues owned by the adapter.
1011 * Returns errno on failure. Resources allocated up to that point may still be
1012 * allocated. Caller is responsible for cleanup in case this function fails.
1015 t4_setup_adapter_queues(struct adapter *sc)
1017 struct sysctl_oid *oid;
1018 struct sysctl_oid_list *children;
1021 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1023 sysctl_ctx_init(&sc->ctx);
1024 sc->flags |= ADAP_SYSCTL_CTX;
1027 * Firmware event queue
1034 * That's all for the VF driver.
1036 if (sc->flags & IS_VF)
1039 oid = device_get_sysctl_tree(sc->dev);
1040 children = SYSCTL_CHILDREN(oid);
1043 * XXX: General purpose rx queues, one per port.
1047 * Control queues, one per port.
1049 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq",
1050 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "control queues");
1051 for_each_port(sc, i) {
1052 struct sge_wrq *ctrlq = &sc->sge.ctrlq[i];
1054 rc = alloc_ctrlq(sc, ctrlq, i, oid);
1066 t4_teardown_adapter_queues(struct adapter *sc)
1070 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1072 /* Do this before freeing the queue */
1073 if (sc->flags & ADAP_SYSCTL_CTX) {
1074 sysctl_ctx_free(&sc->ctx);
1075 sc->flags &= ~ADAP_SYSCTL_CTX;
1078 if (!(sc->flags & IS_VF)) {
1079 for_each_port(sc, i)
1080 free_wrq(sc, &sc->sge.ctrlq[i]);
1087 /* Maximum payload that could arrive with a single iq descriptor. */
1089 max_rx_payload(struct adapter *sc, struct ifnet *ifp, const bool ofld)
1093 /* large enough even when hw VLAN extraction is disabled */
1094 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1095 ETHER_VLAN_ENCAP_LEN + ifp->if_mtu;
1096 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
1097 maxp < sc->params.tp.max_rx_pdu)
1098 maxp = sc->params.tp.max_rx_pdu;
1103 t4_setup_vi_queues(struct vi_info *vi)
1105 int rc = 0, i, intr_idx, iqidx;
1106 struct sge_rxq *rxq;
1107 struct sge_txq *txq;
1109 struct sge_ofld_rxq *ofld_rxq;
1111 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1112 struct sge_wrq *ofld_txq;
1116 struct sge_nm_rxq *nm_rxq;
1117 struct sge_nm_txq *nm_txq;
1120 struct port_info *pi = vi->pi;
1121 struct adapter *sc = pi->adapter;
1122 struct ifnet *ifp = vi->ifp;
1123 struct sysctl_oid *oid = device_get_sysctl_tree(vi->dev);
1124 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
1127 /* Interrupt vector to start from (when using multiple vectors) */
1128 intr_idx = vi->first_intr;
1131 saved_idx = intr_idx;
1132 if (ifp->if_capabilities & IFCAP_NETMAP) {
1134 /* netmap is supported with direct interrupts only. */
1135 MPASS(!forwarding_intr_to_fwq(sc));
1138 * We don't have buffers to back the netmap rx queues
1139 * right now so we create the queues in a way that
1140 * doesn't set off any congestion signal in the chip.
1142 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_rxq",
1143 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues");
1144 for_each_nm_rxq(vi, i, nm_rxq) {
1145 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i, oid);
1151 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "nm_txq",
1152 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues");
1153 for_each_nm_txq(vi, i, nm_txq) {
1154 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1155 rc = alloc_nm_txq(vi, nm_txq, iqidx, i, oid);
1161 /* Normal rx queues and netmap rx queues share the same interrupts. */
1162 intr_idx = saved_idx;
1166 * Allocate rx queues first because a default iqid is required when
1167 * creating a tx queue.
1169 maxp = max_rx_payload(sc, ifp, false);
1170 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "rxq",
1171 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues");
1172 for_each_rxq(vi, i, rxq) {
1174 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq);
1176 snprintf(name, sizeof(name), "%s rxq%d-fl",
1177 device_get_nameunit(vi->dev), i);
1178 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
1180 rc = alloc_rxq(vi, rxq,
1181 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1187 if (ifp->if_capabilities & IFCAP_NETMAP)
1188 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1191 maxp = max_rx_payload(sc, ifp, true);
1192 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_rxq",
1193 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queues for offloaded TCP connections");
1194 for_each_ofld_rxq(vi, i, ofld_rxq) {
1196 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
1199 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1200 device_get_nameunit(vi->dev), i);
1201 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
1203 rc = alloc_ofld_rxq(vi, ofld_rxq,
1204 forwarding_intr_to_fwq(sc) ? -1 : intr_idx, i, oid);
1212 * Now the tx queues.
1214 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "txq",
1215 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues");
1216 for_each_txq(vi, i, txq) {
1217 iqidx = vi->first_rxq + (i % vi->nrxq);
1218 snprintf(name, sizeof(name), "%s txq%d",
1219 device_get_nameunit(vi->dev), i);
1220 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->tx_chan,
1221 sc->sge.rxq[iqidx].iq.cntxt_id, name);
1223 rc = alloc_txq(vi, txq, i, oid);
1227 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1228 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, "ofld_txq",
1229 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queues for TOE/ETHOFLD");
1230 for_each_ofld_txq(vi, i, ofld_txq) {
1231 struct sysctl_oid *oid2;
1233 snprintf(name, sizeof(name), "%s ofld_txq%d",
1234 device_get_nameunit(vi->dev), i);
1235 if (vi->nofldrxq > 0) {
1236 iqidx = vi->first_ofld_rxq + (i % vi->nofldrxq);
1237 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1238 pi->tx_chan, sc->sge.ofld_rxq[iqidx].iq.cntxt_id,
1241 iqidx = vi->first_rxq + (i % vi->nrxq);
1242 init_eq(sc, &ofld_txq->eq, EQ_OFLD, vi->qsize_txq,
1243 pi->tx_chan, sc->sge.rxq[iqidx].iq.cntxt_id, name);
1246 snprintf(name, sizeof(name), "%d", i);
1247 oid2 = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1248 name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
1250 rc = alloc_wrq(sc, vi, ofld_txq, oid2);
1257 t4_teardown_vi_queues(vi);
1266 t4_teardown_vi_queues(struct vi_info *vi)
1269 struct sge_rxq *rxq;
1270 struct sge_txq *txq;
1271 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1272 struct port_info *pi = vi->pi;
1273 struct adapter *sc = pi->adapter;
1274 struct sge_wrq *ofld_txq;
1277 struct sge_ofld_rxq *ofld_rxq;
1280 struct sge_nm_rxq *nm_rxq;
1281 struct sge_nm_txq *nm_txq;
1284 /* Do this before freeing the queues */
1285 if (vi->flags & VI_SYSCTL_CTX) {
1286 sysctl_ctx_free(&vi->ctx);
1287 vi->flags &= ~VI_SYSCTL_CTX;
1291 if (vi->ifp->if_capabilities & IFCAP_NETMAP) {
1292 for_each_nm_txq(vi, i, nm_txq) {
1293 free_nm_txq(vi, nm_txq);
1296 for_each_nm_rxq(vi, i, nm_rxq) {
1297 free_nm_rxq(vi, nm_rxq);
1303 * Take down all the tx queues first, as they reference the rx queues
1304 * (for egress updates, etc.).
1307 for_each_txq(vi, i, txq) {
1310 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1311 for_each_ofld_txq(vi, i, ofld_txq) {
1312 free_wrq(sc, ofld_txq);
1317 * Then take down the rx queues.
1320 for_each_rxq(vi, i, rxq) {
1324 for_each_ofld_rxq(vi, i, ofld_rxq) {
1325 free_ofld_rxq(vi, ofld_rxq);
1333 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1336 * a) Deals with errors, if any.
1337 * b) Services firmware event queue, which is taking interrupts for all other
1341 t4_intr_all(void *arg)
1343 struct adapter *sc = arg;
1344 struct sge_iq *fwq = &sc->sge.fwq;
1346 MPASS(sc->intr_count == 1);
1348 if (sc->intr_type == INTR_INTX)
1349 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1356 * Interrupt handler for errors (installed directly when multiple interrupts are
1357 * being used, or called by t4_intr_all).
1360 t4_intr_err(void *arg)
1362 struct adapter *sc = arg;
1364 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1366 if (sc->flags & ADAP_ERR)
1369 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1372 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1375 t4_slow_intr_handler(sc, verbose);
1379 * Interrupt handler for iq-only queues. The firmware event queue is the only
1380 * such queue right now.
1383 t4_intr_evt(void *arg)
1385 struct sge_iq *iq = arg;
1387 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1389 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1394 * Interrupt handler for iq+fl queues.
1399 struct sge_iq *iq = arg;
1401 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1402 service_iq_fl(iq, 0);
1403 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1409 * Interrupt handler for netmap rx queues.
1412 t4_nm_intr(void *arg)
1414 struct sge_nm_rxq *nm_rxq = arg;
1416 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1417 service_nm_rxq(nm_rxq);
1418 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1423 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1426 t4_vi_intr(void *arg)
1428 struct irq *irq = arg;
1430 MPASS(irq->nm_rxq != NULL);
1431 t4_nm_intr(irq->nm_rxq);
1433 MPASS(irq->rxq != NULL);
1439 * Deals with interrupts on an iq-only (no freelist) queue.
1442 service_iq(struct sge_iq *iq, int budget)
1445 struct adapter *sc = iq->adapter;
1446 struct iq_desc *d = &iq->desc[iq->cidx];
1447 int ndescs = 0, limit;
1450 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1452 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1453 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1454 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1456 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1457 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1459 limit = budget ? budget : iq->qsize / 16;
1462 * We always come back and check the descriptor ring for new indirect
1463 * interrupts and other responses after running a single handler.
1466 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1470 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1471 lq = be32toh(d->rsp.pldbuflen_qid);
1474 case X_RSPD_TYPE_FLBUF:
1475 panic("%s: data for an iq (%p) with no freelist",
1480 case X_RSPD_TYPE_CPL:
1481 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1482 ("%s: bad opcode %02x.", __func__,
1484 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1487 case X_RSPD_TYPE_INTR:
1489 * There are 1K interrupt-capable queues (qids 0
1490 * through 1023). A response type indicating a
1491 * forwarded interrupt with a qid >= 1K is an
1492 * iWARP async notification.
1494 if (__predict_true(lq >= 1024)) {
1495 t4_an_handler(iq, &d->rsp);
1499 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1501 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1503 if (service_iq_fl(q, q->qsize / 16) == 0) {
1504 (void) atomic_cmpset_int(&q->state,
1505 IQS_BUSY, IQS_IDLE);
1507 STAILQ_INSERT_TAIL(&iql, q,
1515 ("%s: illegal response type %d on iq %p",
1516 __func__, rsp_type, iq));
1518 "%s: illegal response type %d on iq %p",
1519 device_get_nameunit(sc->dev), rsp_type, iq);
1524 if (__predict_false(++iq->cidx == iq->sidx)) {
1526 iq->gen ^= F_RSPD_GEN;
1529 if (__predict_false(++ndescs == limit)) {
1530 t4_write_reg(sc, sc->sge_gts_reg,
1532 V_INGRESSQID(iq->cntxt_id) |
1533 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1537 return (EINPROGRESS);
1542 if (STAILQ_EMPTY(&iql))
1546 * Process the head only, and send it to the back of the list if
1547 * it's still not done.
1549 q = STAILQ_FIRST(&iql);
1550 STAILQ_REMOVE_HEAD(&iql, link);
1551 if (service_iq_fl(q, q->qsize / 8) == 0)
1552 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1554 STAILQ_INSERT_TAIL(&iql, q, link);
1557 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1558 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1564 sort_before_lro(struct lro_ctrl *lro)
1567 return (lro->lro_mbuf_max != 0);
1570 static inline uint64_t
1571 last_flit_to_ns(struct adapter *sc, uint64_t lf)
1573 uint64_t n = be64toh(lf) & 0xfffffffffffffff; /* 60b, not 64b. */
1575 if (n > UINT64_MAX / 1000000)
1576 return (n / sc->params.vpd.cclk * 1000000);
1578 return (n * 1000000 / sc->params.vpd.cclk);
1582 move_to_next_rxbuf(struct sge_fl *fl)
1586 if (__predict_false((++fl->cidx & 7) == 0)) {
1587 uint16_t cidx = fl->cidx >> 3;
1589 if (__predict_false(cidx == fl->sidx))
1590 fl->cidx = cidx = 0;
1596 * Deals with interrupts on an iq+fl queue.
1599 service_iq_fl(struct sge_iq *iq, int budget)
1601 struct sge_rxq *rxq = iq_to_rxq(iq);
1603 struct adapter *sc = iq->adapter;
1604 struct iq_desc *d = &iq->desc[iq->cidx];
1606 int rsp_type, starved;
1608 uint16_t fl_hw_cidx;
1610 #if defined(INET) || defined(INET6)
1611 const struct timeval lro_timeout = {0, sc->lro_timeout};
1612 struct lro_ctrl *lro = &rxq->lro;
1615 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1616 MPASS(iq->flags & IQ_HAS_FL);
1619 #if defined(INET) || defined(INET6)
1620 if (iq->flags & IQ_ADJ_CREDIT) {
1621 MPASS(sort_before_lro(lro));
1622 iq->flags &= ~IQ_ADJ_CREDIT;
1623 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1624 tcp_lro_flush_all(lro);
1625 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1626 V_INGRESSQID((u32)iq->cntxt_id) |
1627 V_SEINTARM(iq->intr_params));
1633 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1636 limit = budget ? budget : iq->qsize / 16;
1638 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1639 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1644 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1645 lq = be32toh(d->rsp.pldbuflen_qid);
1648 case X_RSPD_TYPE_FLBUF:
1649 if (lq & F_RSPD_NEWBUF) {
1650 if (fl->rx_offset > 0)
1651 move_to_next_rxbuf(fl);
1652 lq = G_RSPD_LEN(lq);
1654 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1656 refill_fl(sc, fl, 64);
1658 fl_hw_cidx = fl->hw_cidx;
1661 if (d->rss.opcode == CPL_RX_PKT) {
1662 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1666 m0 = get_fl_payload(sc, fl, lq);
1667 if (__predict_false(m0 == NULL))
1672 case X_RSPD_TYPE_CPL:
1673 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1674 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1675 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1678 case X_RSPD_TYPE_INTR:
1681 * There are 1K interrupt-capable queues (qids 0
1682 * through 1023). A response type indicating a
1683 * forwarded interrupt with a qid >= 1K is an
1684 * iWARP async notification. That is the only
1685 * acceptable indirect interrupt on this queue.
1687 if (__predict_false(lq < 1024)) {
1688 panic("%s: indirect interrupt on iq_fl %p "
1689 "with qid %u", __func__, iq, lq);
1692 t4_an_handler(iq, &d->rsp);
1696 KASSERT(0, ("%s: illegal response type %d on iq %p",
1697 __func__, rsp_type, iq));
1698 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1699 device_get_nameunit(sc->dev), rsp_type, iq);
1704 if (__predict_false(++iq->cidx == iq->sidx)) {
1706 iq->gen ^= F_RSPD_GEN;
1709 if (__predict_false(++ndescs == limit)) {
1710 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1711 V_INGRESSQID(iq->cntxt_id) |
1712 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1714 #if defined(INET) || defined(INET6)
1715 if (iq->flags & IQ_LRO_ENABLED &&
1716 !sort_before_lro(lro) &&
1717 sc->lro_timeout != 0) {
1718 tcp_lro_flush_inactive(lro, &lro_timeout);
1722 return (EINPROGRESS);
1727 #if defined(INET) || defined(INET6)
1728 if (iq->flags & IQ_LRO_ENABLED) {
1729 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1730 MPASS(sort_before_lro(lro));
1731 /* hold back one credit and don't flush LRO state */
1732 iq->flags |= IQ_ADJ_CREDIT;
1735 tcp_lro_flush_all(lro);
1740 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1741 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1744 starved = refill_fl(sc, fl, 64);
1746 if (__predict_false(starved != 0))
1747 add_fl_to_sfl(sc, fl);
1752 static inline struct cluster_metadata *
1753 cl_metadata(struct fl_sdesc *sd)
1756 return ((void *)(sd->cl + sd->moff));
1760 rxb_free(struct mbuf *m)
1762 struct cluster_metadata *clm = m->m_ext.ext_arg1;
1764 uma_zfree(clm->zone, clm->cl);
1765 counter_u64_add(extfree_rels, 1);
1769 * The mbuf returned comes from zone_muf and carries the payload in one of these
1771 * a) complete frame inside the mbuf
1772 * b) m_cljset (for clusters without metadata)
1773 * d) m_extaddref (cluster with metadata)
1775 static struct mbuf *
1776 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1780 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1781 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1782 struct cluster_metadata *clm;
1786 if (fl->flags & FL_BUF_PACKING) {
1789 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1790 len = min(remaining, blen);
1791 payload = sd->cl + fl->rx_offset;
1793 l = fr_offset + len;
1794 pad = roundup2(l, fl->buf_boundary) - l;
1795 if (fl->rx_offset + len + pad < rxb->size2)
1797 MPASS(fl->rx_offset + blen <= rxb->size2);
1799 MPASS(fl->rx_offset == 0); /* not packing */
1801 len = min(remaining, blen);
1805 if (fr_offset == 0) {
1806 m = m_gethdr(M_NOWAIT, MT_DATA);
1807 if (__predict_false(m == NULL))
1809 m->m_pkthdr.len = remaining;
1811 m = m_get(M_NOWAIT, MT_DATA);
1812 if (__predict_false(m == NULL))
1817 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1818 /* copy data to mbuf */
1819 bcopy(payload, mtod(m, caddr_t), len);
1820 if (fl->flags & FL_BUF_PACKING) {
1821 fl->rx_offset += blen;
1822 MPASS(fl->rx_offset <= rxb->size2);
1823 if (fl->rx_offset < rxb->size2)
1824 return (m); /* without advancing the cidx */
1826 } else if (fl->flags & FL_BUF_PACKING) {
1827 clm = cl_metadata(sd);
1828 if (sd->nmbuf++ == 0) {
1830 clm->zone = rxb->zone;
1832 counter_u64_add(extfree_refs, 1);
1834 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1837 fl->rx_offset += blen;
1838 MPASS(fl->rx_offset <= rxb->size2);
1839 if (fl->rx_offset < rxb->size2)
1840 return (m); /* without advancing the cidx */
1842 m_cljset(m, sd->cl, rxb->type);
1843 sd->cl = NULL; /* consumed, not a recycle candidate */
1846 move_to_next_rxbuf(fl);
1851 static struct mbuf *
1852 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1854 struct mbuf *m0, *m, **pnext;
1857 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1858 M_ASSERTPKTHDR(fl->m0);
1859 MPASS(fl->m0->m_pkthdr.len == plen);
1860 MPASS(fl->remaining < plen);
1864 remaining = fl->remaining;
1865 fl->flags &= ~FL_BUF_RESUME;
1870 * Payload starts at rx_offset in the current hw buffer. Its length is
1871 * 'len' and it may span multiple hw buffers.
1874 m0 = get_scatter_segment(sc, fl, 0, plen);
1877 remaining = plen - m0->m_len;
1878 pnext = &m0->m_next;
1879 while (remaining > 0) {
1881 MPASS(fl->rx_offset == 0);
1882 m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1883 if (__predict_false(m == NULL)) {
1886 fl->remaining = remaining;
1887 fl->flags |= FL_BUF_RESUME;
1892 remaining -= m->m_len;
1901 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1904 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1905 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1908 if (fl->flags & FL_BUF_PACKING) {
1911 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1912 len = min(remaining, blen);
1914 l = fr_offset + len;
1915 pad = roundup2(l, fl->buf_boundary) - l;
1916 if (fl->rx_offset + len + pad < rxb->size2)
1918 fl->rx_offset += blen;
1919 MPASS(fl->rx_offset <= rxb->size2);
1920 if (fl->rx_offset < rxb->size2)
1921 return (len); /* without advancing the cidx */
1923 MPASS(fl->rx_offset == 0); /* not packing */
1925 len = min(remaining, blen);
1927 move_to_next_rxbuf(fl);
1932 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1934 int remaining, fr_offset, len;
1938 while (remaining > 0) {
1939 len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1946 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1949 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1950 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1952 if (fl->flags & FL_BUF_PACKING)
1953 len = rxb->size2 - fl->rx_offset;
1957 return (min(plen, len));
1961 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1965 struct ifnet *ifp = rxq->ifp;
1966 struct sge_fl *fl = &rxq->fl;
1967 struct vi_info *vi = ifp->if_softc;
1968 const struct cpl_rx_pkt *cpl;
1969 #if defined(INET) || defined(INET6)
1970 struct lro_ctrl *lro = &rxq->lro;
1972 uint16_t err_vec, tnl_type, tnlhdr_len;
1973 static const int sw_hashtype[4][2] = {
1974 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1975 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1976 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1977 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1979 static const int sw_csum_flags[2][2] = {
1983 CSUM_L3_CALC | CSUM_L3_VALID |
1984 CSUM_L4_CALC | CSUM_L4_VALID |
1985 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1986 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1990 CSUM_L3_CALC | CSUM_L3_VALID |
1991 CSUM_L4_CALC | CSUM_L4_VALID |
1992 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1997 CSUM_L4_CALC | CSUM_L4_VALID |
1998 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1999 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
2001 /* IP6, inner IP6 */
2003 CSUM_L4_CALC | CSUM_L4_VALID |
2004 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
2008 MPASS(plen > sc->params.sge.fl_pktshift);
2009 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
2010 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
2011 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
2015 slen = get_segment_len(sc, fl, plen) -
2016 sc->params.sge.fl_pktshift;
2017 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
2018 CURVNET_SET_QUIET(ifp->if_vnet);
2019 rc = pfil_run_hooks(vi->pfil, frame, ifp,
2020 slen | PFIL_MEMPTR | PFIL_IN, NULL);
2022 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
2023 skip_fl_payload(sc, fl, plen);
2026 if (rc == PFIL_REALLOCED) {
2027 skip_fl_payload(sc, fl, plen);
2028 m0 = pfil_mem2mbuf(frame);
2033 m0 = get_fl_payload(sc, fl, plen);
2034 if (__predict_false(m0 == NULL))
2037 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
2038 m0->m_len -= sc->params.sge.fl_pktshift;
2039 m0->m_data += sc->params.sge.fl_pktshift;
2042 m0->m_pkthdr.rcvif = ifp;
2043 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
2044 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
2046 cpl = (const void *)(&d->rss + 1);
2047 if (sc->params.tp.rx_pkt_encap) {
2048 const uint16_t ev = be16toh(cpl->err_vec);
2050 err_vec = G_T6_COMPR_RXERR_VEC(ev);
2051 tnl_type = G_T6_RX_TNL_TYPE(ev);
2052 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev);
2054 err_vec = be16toh(cpl->err_vec);
2058 if (cpl->csum_calc && err_vec == 0) {
2059 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6));
2061 /* checksum(s) calculated and found to be correct. */
2063 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^
2064 (cpl->l2info & htobe32(F_RXF_IP6)));
2065 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2066 if (tnl_type == 0) {
2067 if (!ipv6 && ifp->if_capenable & IFCAP_RXCSUM) {
2068 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2069 CSUM_L3_VALID | CSUM_L4_CALC |
2071 } else if (ipv6 && ifp->if_capenable & IFCAP_RXCSUM_IPV6) {
2072 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2077 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN);
2078 if (__predict_false(cpl->ip_frag)) {
2080 * csum_data is for the inner frame (which is an
2081 * IP fragment) and is not 0xffff. There is no
2082 * way to pass the inner csum_data to the stack.
2083 * We don't want the stack to use the inner
2084 * csum_data to validate the outer frame or it
2085 * will get rejected. So we fix csum_data here
2086 * and let sw do the checksum of inner IP
2089 * XXX: Need 32b for csum_data2 in an rx mbuf.
2090 * Maybe stuff it into rcv_tstmp?
2092 m0->m_pkthdr.csum_data = 0xffff;
2094 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2097 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2098 CSUM_L3_VALID | CSUM_L4_CALC |
2104 MPASS(m0->m_pkthdr.csum_data == 0xffff);
2106 outer_ipv6 = tnlhdr_len >=
2107 sizeof(struct ether_header) +
2108 sizeof(struct ip6_hdr);
2109 m0->m_pkthdr.csum_flags =
2110 sw_csum_flags[outer_ipv6][ipv6];
2112 rxq->vxlan_rxcsum++;
2117 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2118 m0->m_flags |= M_VLANTAG;
2119 rxq->vlan_extraction++;
2122 if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
2124 * Fill up rcv_tstmp but do not set M_TSTMP.
2125 * rcv_tstmp is not in the format that the
2126 * kernel expects and we don't want to mislead
2127 * it. For now this is only for custom code
2128 * that knows how to interpret cxgbe's stamp.
2130 m0->m_pkthdr.rcv_tstmp =
2131 last_flit_to_ns(sc, d->rsp.u.last_flit);
2133 m0->m_flags |= M_TSTMP;
2138 m0->m_pkthdr.numa_domain = ifp->if_numa_domain;
2140 #if defined(INET) || defined(INET6)
2141 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 &&
2142 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2143 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2144 if (sort_before_lro(lro)) {
2145 tcp_lro_queue_mbuf(lro, m0);
2146 return (0); /* queued for sort, then LRO */
2148 if (tcp_lro_rx(lro, m0, 0) == 0)
2149 return (0); /* queued for LRO */
2152 ifp->if_input(ifp, m0);
2158 * Must drain the wrq or make sure that someone else will.
2161 wrq_tx_drain(void *arg, int n)
2163 struct sge_wrq *wrq = arg;
2164 struct sge_eq *eq = &wrq->eq;
2167 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2168 drain_wrq_wr_list(wrq->adapter, wrq);
2173 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2175 struct sge_eq *eq = &wrq->eq;
2176 u_int available, dbdiff; /* # of hardware descriptors */
2179 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2181 EQ_LOCK_ASSERT_OWNED(eq);
2182 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2183 wr = STAILQ_FIRST(&wrq->wr_list);
2184 MPASS(wr != NULL); /* Must be called with something useful to do */
2185 MPASS(eq->pidx == eq->dbidx);
2189 eq->cidx = read_hw_cidx(eq);
2190 if (eq->pidx == eq->cidx)
2191 available = eq->sidx - 1;
2193 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2195 MPASS(wr->wrq == wrq);
2196 n = howmany(wr->wr_len, EQ_ESIZE);
2200 dst = (void *)&eq->desc[eq->pidx];
2201 if (__predict_true(eq->sidx - eq->pidx > n)) {
2202 /* Won't wrap, won't end exactly at the status page. */
2203 bcopy(&wr->wr[0], dst, wr->wr_len);
2206 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2208 bcopy(&wr->wr[0], dst, first_portion);
2209 if (wr->wr_len > first_portion) {
2210 bcopy(&wr->wr[first_portion], &eq->desc[0],
2211 wr->wr_len - first_portion);
2213 eq->pidx = n - (eq->sidx - eq->pidx);
2215 wrq->tx_wrs_copied++;
2217 if (available < eq->sidx / 4 &&
2218 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2220 * XXX: This is not 100% reliable with some
2221 * types of WRs. But this is a very unusual
2222 * situation for an ofld/ctrl queue anyway.
2224 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2230 ring_eq_db(sc, eq, dbdiff);
2234 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2236 MPASS(wrq->nwr_pending > 0);
2238 MPASS(wrq->ndesc_needed >= n);
2239 wrq->ndesc_needed -= n;
2240 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2243 ring_eq_db(sc, eq, dbdiff);
2247 * Doesn't fail. Holds on to work requests it can't send right away.
2250 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2253 struct sge_eq *eq = &wrq->eq;
2256 EQ_LOCK_ASSERT_OWNED(eq);
2258 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2259 MPASS((wr->wr_len & 0x7) == 0);
2261 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2263 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2265 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2266 return; /* commit_wrq_wr will drain wr_list as well. */
2268 drain_wrq_wr_list(sc, wrq);
2270 /* Doorbell must have caught up to the pidx. */
2271 MPASS(eq->pidx == eq->dbidx);
2275 t4_update_fl_bufsize(struct ifnet *ifp)
2277 struct vi_info *vi = ifp->if_softc;
2278 struct adapter *sc = vi->adapter;
2279 struct sge_rxq *rxq;
2281 struct sge_ofld_rxq *ofld_rxq;
2286 maxp = max_rx_payload(sc, ifp, false);
2287 for_each_rxq(vi, i, rxq) {
2291 fl->zidx = find_refill_source(sc, maxp,
2292 fl->flags & FL_BUF_PACKING);
2296 maxp = max_rx_payload(sc, ifp, true);
2297 for_each_ofld_rxq(vi, i, ofld_rxq) {
2301 fl->zidx = find_refill_source(sc, maxp,
2302 fl->flags & FL_BUF_PACKING);
2309 mbuf_nsegs(struct mbuf *m)
2313 KASSERT(m->m_pkthdr.inner_l5hlen > 0,
2314 ("%s: mbuf %p missing information on # of segments.", __func__, m));
2316 return (m->m_pkthdr.inner_l5hlen);
2320 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
2324 m->m_pkthdr.inner_l5hlen = nsegs;
2328 mbuf_cflags(struct mbuf *m)
2332 return (m->m_pkthdr.PH_loc.eight[4]);
2336 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
2340 m->m_pkthdr.PH_loc.eight[4] = flags;
2344 mbuf_len16(struct mbuf *m)
2349 n = m->m_pkthdr.PH_loc.eight[0];
2350 if (!(mbuf_cflags(m) & MC_TLS))
2351 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2357 set_mbuf_len16(struct mbuf *m, uint8_t len16)
2361 if (!(mbuf_cflags(m) & MC_TLS))
2362 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
2363 m->m_pkthdr.PH_loc.eight[0] = len16;
2368 mbuf_eo_nsegs(struct mbuf *m)
2372 return (m->m_pkthdr.PH_loc.eight[1]);
2376 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2380 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2384 mbuf_eo_len16(struct mbuf *m)
2389 n = m->m_pkthdr.PH_loc.eight[2];
2390 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2396 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2400 m->m_pkthdr.PH_loc.eight[2] = len16;
2404 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2408 return (m->m_pkthdr.PH_loc.eight[3]);
2412 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2416 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2420 needs_eo(struct m_snd_tag *mst)
2423 return (mst != NULL && mst->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2428 * Try to allocate an mbuf to contain a raw work request. To make it
2429 * easy to construct the work request, don't allocate a chain but a
2433 alloc_wr_mbuf(int len, int how)
2438 m = m_gethdr(how, MT_DATA);
2439 else if (len <= MCLBYTES)
2440 m = m_getcl(how, MT_DATA, M_PKTHDR);
2445 m->m_pkthdr.len = len;
2447 set_mbuf_cflags(m, MC_RAW_WR);
2448 set_mbuf_len16(m, howmany(len, 16));
2453 needs_hwcsum(struct mbuf *m)
2455 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
2456 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2457 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP |
2458 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP |
2459 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO;
2463 return (m->m_pkthdr.csum_flags & csum_flags);
2467 needs_tso(struct mbuf *m)
2469 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO |
2470 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2474 return (m->m_pkthdr.csum_flags & csum_flags);
2478 needs_vxlan_csum(struct mbuf *m)
2483 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN);
2487 needs_vxlan_tso(struct mbuf *m)
2489 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO |
2494 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 &&
2495 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN);
2499 needs_inner_tcp_csum(struct mbuf *m)
2501 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2505 return (m->m_pkthdr.csum_flags & csum_flags);
2509 needs_l3_csum(struct mbuf *m)
2511 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP |
2516 return (m->m_pkthdr.csum_flags & csum_flags);
2520 needs_outer_tcp_csum(struct mbuf *m)
2522 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP |
2527 return (m->m_pkthdr.csum_flags & csum_flags);
2532 needs_outer_l4_csum(struct mbuf *m)
2534 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO |
2535 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO;
2539 return (m->m_pkthdr.csum_flags & csum_flags);
2543 needs_outer_udp_csum(struct mbuf *m)
2545 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP;
2549 return (m->m_pkthdr.csum_flags & csum_flags);
2554 needs_vlan_insertion(struct mbuf *m)
2559 return (m->m_flags & M_VLANTAG);
2563 m_advance(struct mbuf **pm, int *poffset, int len)
2565 struct mbuf *m = *pm;
2566 int offset = *poffset;
2572 if (offset + len < m->m_len) {
2574 p = mtod(m, uintptr_t) + offset;
2577 len -= m->m_len - offset;
2588 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2591 int i, len, off, pglen, pgoff, seglen, segoff;
2595 off = mtod(m, vm_offset_t);
2600 if (m->m_epg_hdrlen != 0) {
2601 if (off >= m->m_epg_hdrlen) {
2602 off -= m->m_epg_hdrlen;
2604 seglen = m->m_epg_hdrlen - off;
2606 seglen = min(seglen, len);
2609 paddr = pmap_kextract(
2610 (vm_offset_t)&m->m_epg_hdr[segoff]);
2611 if (*nextaddr != paddr)
2613 *nextaddr = paddr + seglen;
2616 pgoff = m->m_epg_1st_off;
2617 for (i = 0; i < m->m_epg_npgs && len > 0; i++) {
2618 pglen = m_epg_pagelen(m, i, pgoff);
2624 seglen = pglen - off;
2625 segoff = pgoff + off;
2627 seglen = min(seglen, len);
2629 paddr = m->m_epg_pa[i] + segoff;
2630 if (*nextaddr != paddr)
2632 *nextaddr = paddr + seglen;
2636 seglen = min(len, m->m_epg_trllen - off);
2638 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]);
2639 if (*nextaddr != paddr)
2641 *nextaddr = paddr + seglen;
2649 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2650 * must have at least one mbuf that's not empty. It is possible for this
2651 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2654 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2656 vm_paddr_t nextaddr, paddr;
2661 MPASS(m->m_pkthdr.len > 0);
2662 MPASS(m->m_pkthdr.len >= skip);
2666 for (; m; m = m->m_next) {
2668 if (__predict_false(len == 0))
2674 if ((m->m_flags & M_EXTPG) != 0) {
2675 *cflags |= MC_NOMAP;
2676 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2680 va = mtod(m, vm_offset_t) + skip;
2683 paddr = pmap_kextract(va);
2684 nsegs += sglist_count((void *)(uintptr_t)va, len);
2685 if (paddr == nextaddr)
2687 nextaddr = pmap_kextract(va + len - 1) + 1;
2694 * The maximum number of segments that can fit in a WR.
2697 max_nsegs_allowed(struct mbuf *m, bool vm_wr)
2702 return (TX_SGL_SEGS_VM_TSO);
2703 return (TX_SGL_SEGS_VM);
2707 if (needs_vxlan_tso(m))
2708 return (TX_SGL_SEGS_VXLAN_TSO);
2710 return (TX_SGL_SEGS_TSO);
2713 return (TX_SGL_SEGS);
2717 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2718 * a) caller can assume it's been freed if this function returns with an error.
2719 * b) it may get defragged up if the gather list is too long for the hardware.
2722 parse_pkt(struct mbuf **mp, bool vm_wr)
2724 struct mbuf *m0 = *mp, *m;
2725 int rc, nsegs, defragged = 0, offset;
2726 struct ether_header *eh;
2728 #if defined(INET) || defined(INET6)
2731 #if defined(KERN_TLS) || defined(RATELIMIT)
2732 struct m_snd_tag *mst;
2739 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2748 * First count the number of gather list segments in the payload.
2749 * Defrag the mbuf if nsegs exceeds the hardware limit.
2752 MPASS(m0->m_pkthdr.len > 0);
2753 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2754 #if defined(KERN_TLS) || defined(RATELIMIT)
2755 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2756 mst = m0->m_pkthdr.snd_tag;
2761 if (mst != NULL && mst->type == IF_SND_TAG_TYPE_TLS) {
2765 set_mbuf_cflags(m0, cflags);
2766 rc = t6_ktls_parse_pkt(m0, &nsegs, &len16);
2769 set_mbuf_nsegs(m0, nsegs);
2770 set_mbuf_len16(m0, len16);
2774 if (nsegs > max_nsegs_allowed(m0, vm_wr)) {
2775 if (defragged++ > 0) {
2779 counter_u64_add(defrags, 1);
2780 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) {
2784 *mp = m0 = m; /* update caller's copy after defrag */
2788 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2789 !(cflags & MC_NOMAP))) {
2790 counter_u64_add(pullups, 1);
2791 m0 = m_pullup(m0, m0->m_pkthdr.len);
2793 /* Should have left well enough alone. */
2797 *mp = m0; /* update caller's copy after pullup */
2800 set_mbuf_nsegs(m0, nsegs);
2801 set_mbuf_cflags(m0, cflags);
2802 calculate_mbuf_len16(m0, vm_wr);
2806 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2807 * checksumming is enabled. needs_outer_l4_csum happens to check for
2808 * all the right things.
2810 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) {
2811 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2812 m0->m_pkthdr.snd_tag = NULL;
2813 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2818 if (!needs_hwcsum(m0)
2826 eh = mtod(m, struct ether_header *);
2827 eh_type = ntohs(eh->ether_type);
2828 if (eh_type == ETHERTYPE_VLAN) {
2829 struct ether_vlan_header *evh = (void *)eh;
2831 eh_type = ntohs(evh->evl_proto);
2832 m0->m_pkthdr.l2hlen = sizeof(*evh);
2834 m0->m_pkthdr.l2hlen = sizeof(*eh);
2837 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2841 case ETHERTYPE_IPV6:
2842 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
2848 struct ip *ip = l3hdr;
2850 if (needs_vxlan_csum(m0)) {
2851 /* Driver will do the outer IP hdr checksum. */
2853 if (needs_vxlan_tso(m0)) {
2854 const uint16_t ipl = ip->ip_len;
2857 ip->ip_sum = ~in_cksum_hdr(ip);
2860 ip->ip_sum = in_cksum_hdr(ip);
2862 m0->m_pkthdr.l3hlen = ip->ip_hl << 2;
2867 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2868 " with the same INET/INET6 options as the kernel.",
2872 if (needs_vxlan_csum(m0)) {
2873 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2874 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header);
2876 /* Inner headers. */
2877 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen +
2878 sizeof(struct udphdr) + sizeof(struct vxlan_header));
2879 eh_type = ntohs(eh->ether_type);
2880 if (eh_type == ETHERTYPE_VLAN) {
2881 struct ether_vlan_header *evh = (void *)eh;
2883 eh_type = ntohs(evh->evl_proto);
2884 m0->m_pkthdr.inner_l2hlen = sizeof(*evh);
2886 m0->m_pkthdr.inner_l2hlen = sizeof(*eh);
2887 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2891 case ETHERTYPE_IPV6:
2892 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr);
2898 struct ip *ip = l3hdr;
2900 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2;
2905 panic("%s: VXLAN hw offload requested with unknown "
2906 "ethertype 0x%04x. if_cxgbe must be compiled"
2907 " with the same INET/INET6 options as the kernel.",
2910 #if defined(INET) || defined(INET6)
2911 if (needs_inner_tcp_csum(m0)) {
2912 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen);
2913 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4;
2916 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0);
2917 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP |
2918 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP |
2919 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO |
2923 #if defined(INET) || defined(INET6)
2924 if (needs_outer_tcp_csum(m0)) {
2925 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2926 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2928 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2929 set_mbuf_eo_tsclk_tsoff(m0,
2930 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2931 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2933 set_mbuf_eo_tsclk_tsoff(m0, 0);
2934 } else if (needs_outer_udp_csum(m0)) {
2935 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2939 if (needs_eo(mst)) {
2942 /* EO WRs have the headers in the WR and not the GL. */
2943 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2944 m0->m_pkthdr.l4hlen;
2946 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2947 MPASS(cflags == mbuf_cflags(m0));
2948 set_mbuf_eo_nsegs(m0, nsegs);
2949 set_mbuf_eo_len16(m0,
2950 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2959 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2961 struct sge_eq *eq = &wrq->eq;
2962 struct adapter *sc = wrq->adapter;
2963 int ndesc, available;
2968 ndesc = tx_len16_to_desc(len16);
2969 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2973 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2974 drain_wrq_wr_list(sc, wrq);
2976 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2979 wr = alloc_wrqe(len16 * 16, wrq);
2980 if (__predict_false(wr == NULL))
2983 cookie->ndesc = ndesc;
2987 eq->cidx = read_hw_cidx(eq);
2988 if (eq->pidx == eq->cidx)
2989 available = eq->sidx - 1;
2991 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2992 if (available < ndesc)
2995 cookie->pidx = eq->pidx;
2996 cookie->ndesc = ndesc;
2997 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2999 w = &eq->desc[eq->pidx];
3000 IDXINCR(eq->pidx, ndesc, eq->sidx);
3001 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
3003 wrq->ss_pidx = cookie->pidx;
3004 wrq->ss_len = len16 * 16;
3013 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
3015 struct sge_eq *eq = &wrq->eq;
3016 struct adapter *sc = wrq->adapter;
3018 struct wrq_cookie *prev, *next;
3020 if (cookie->pidx == -1) {
3021 struct wrqe *wr = __containerof(w, struct wrqe, wr);
3027 if (__predict_false(w == &wrq->ss[0])) {
3028 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
3030 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
3031 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
3032 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
3035 wrq->tx_wrs_direct++;
3038 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
3039 pidx = cookie->pidx;
3040 MPASS(pidx >= 0 && pidx < eq->sidx);
3041 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
3042 next = TAILQ_NEXT(cookie, link);
3044 MPASS(pidx == eq->dbidx);
3045 if (next == NULL || ndesc >= 16) {
3047 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
3050 * Note that the WR via which we'll request tx updates
3051 * is at pidx and not eq->pidx, which has moved on
3054 dst = (void *)&eq->desc[pidx];
3055 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3056 if (available < eq->sidx / 4 &&
3057 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3059 * XXX: This is not 100% reliable with some
3060 * types of WRs. But this is a very unusual
3061 * situation for an ofld/ctrl queue anyway.
3063 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3067 ring_eq_db(wrq->adapter, eq, ndesc);
3069 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
3071 next->ndesc += ndesc;
3074 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
3075 prev->ndesc += ndesc;
3077 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
3079 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
3080 drain_wrq_wr_list(sc, wrq);
3083 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
3084 /* Doorbell must have caught up to the pidx. */
3085 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
3092 can_resume_eth_tx(struct mp_ring *r)
3094 struct sge_eq *eq = r->cookie;
3096 return (total_available_tx_desc(eq) > eq->sidx / 8);
3100 cannot_use_txpkts(struct mbuf *m)
3102 /* maybe put a GL limit too, to avoid silliness? */
3104 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
3108 discard_tx(struct sge_eq *eq)
3111 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
3115 wr_can_update_eq(void *p)
3117 struct fw_eth_tx_pkts_wr *wr = p;
3119 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
3121 case FW_ETH_TX_PKT_WR:
3122 case FW_ETH_TX_PKTS_WR:
3123 case FW_ETH_TX_PKTS2_WR:
3124 case FW_ETH_TX_PKT_VM_WR:
3125 case FW_ETH_TX_PKTS_VM_WR:
3133 set_txupdate_flags(struct sge_txq *txq, u_int avail,
3134 struct fw_eth_tx_pkt_wr *wr)
3136 struct sge_eq *eq = &txq->eq;
3137 struct txpkts *txp = &txq->txp;
3139 if ((txp->npkt > 0 || avail < eq->sidx / 2) &&
3140 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3141 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
3142 eq->equeqidx = eq->pidx;
3143 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
3144 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3145 eq->equeqidx = eq->pidx;
3149 #if defined(__i386__) || defined(__amd64__)
3150 extern uint64_t tsc_freq;
3154 record_eth_tx_time(struct sge_txq *txq)
3156 const uint64_t cycles = get_cyclecount();
3157 const uint64_t last_tx = txq->last_tx;
3158 #if defined(__i386__) || defined(__amd64__)
3159 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000;
3161 const uint64_t itg = 0;
3164 MPASS(cycles >= last_tx);
3165 txq->last_tx = cycles;
3166 return (cycles - last_tx < itg);
3170 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
3171 * be consumed. Return the actual number consumed. 0 indicates a stall.
3174 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing)
3176 struct sge_txq *txq = r->cookie;
3177 struct ifnet *ifp = txq->ifp;
3178 struct sge_eq *eq = &txq->eq;
3179 struct txpkts *txp = &txq->txp;
3180 struct vi_info *vi = ifp->if_softc;
3181 struct adapter *sc = vi->adapter;
3182 u_int total, remaining; /* # of packets */
3183 u_int n, avail, dbdiff; /* # of hardware descriptors */
3186 bool snd, recent_tx;
3187 void *wr; /* start of the last WR written to the ring */
3189 TXQ_LOCK_ASSERT_OWNED(txq);
3190 recent_tx = record_eth_tx_time(txq);
3192 remaining = IDXDIFF(pidx, cidx, r->size);
3193 if (__predict_false(discard_tx(eq))) {
3194 for (i = 0; i < txp->npkt; i++)
3195 m_freem(txp->mb[i]);
3197 while (cidx != pidx) {
3198 m0 = r->items[cidx];
3200 if (++cidx == r->size)
3203 reclaim_tx_descs(txq, eq->sidx);
3204 *coalescing = false;
3205 return (remaining); /* emptied */
3208 /* How many hardware descriptors do we have readily available. */
3209 if (eq->pidx == eq->cidx)
3210 avail = eq->sidx - 1;
3212 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3215 if (remaining == 0) {
3217 txq->txpkts_flush++;
3222 MPASS(remaining > 0);
3223 while (remaining > 0) {
3224 m0 = r->items[cidx];
3226 MPASS(m0->m_nextpkt == NULL);
3228 if (avail < 2 * SGE_MAX_WR_NDESC)
3229 avail += reclaim_tx_descs(txq, 64);
3231 if (t4_tx_coalesce == 0 && txp->npkt == 0)
3232 goto skip_coalescing;
3233 if (cannot_use_txpkts(m0))
3235 else if (recent_tx) {
3236 if (++txp->score == 0)
3237 txp->score = UINT8_MAX;
3240 if (txp->npkt > 0 || remaining > 1 ||
3241 txp->score >= t4_tx_coalesce_pkts ||
3242 atomic_load_int(&txq->eq.equiq) != 0) {
3243 if (vi->flags & TX_USES_VM_WR)
3244 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd);
3246 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd);
3252 MPASS(txp->npkt > 0);
3253 for (i = 0; i < txp->npkt; i++)
3254 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3255 if (txp->npkt > 1) {
3256 MPASS(avail >= tx_len16_to_desc(txp->len16));
3257 if (vi->flags & TX_USES_VM_WR)
3258 n = write_txpkts_vm_wr(sc, txq);
3260 n = write_txpkts_wr(sc, txq);
3263 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3264 if (vi->flags & TX_USES_VM_WR)
3265 n = write_txpkt_vm_wr(sc, txq,
3268 n = write_txpkt_wr(sc, txq, txp->mb[0],
3271 MPASS(n <= SGE_MAX_WR_NDESC);
3274 wr = &eq->desc[eq->pidx];
3275 IDXINCR(eq->pidx, n, eq->sidx);
3276 txp->npkt = 0; /* emptied */
3279 /* m0 was coalesced into txq->txpkts. */
3284 * m0 is suitable for tx coalescing but could not be
3285 * combined with the existing txq->txpkts, which has now
3286 * been transmitted. Start a new txpkts with m0.
3289 MPASS(txp->npkt == 0);
3293 MPASS(rc != 0 && rc != EAGAIN);
3294 MPASS(txp->npkt == 0);
3296 n = tx_len16_to_desc(mbuf_len16(m0));
3297 if (__predict_false(avail < n)) {
3298 avail += reclaim_tx_descs(txq, min(n, 32));
3300 break; /* out of descriptors */
3303 wr = &eq->desc[eq->pidx];
3304 if (mbuf_cflags(m0) & MC_RAW_WR) {
3305 n = write_raw_wr(txq, wr, m0, avail);
3307 } else if (mbuf_cflags(m0) & MC_TLS) {
3308 ETHER_BPF_MTAP(ifp, m0);
3309 n = t6_ktls_write_wr(txq, wr, m0, mbuf_nsegs(m0),
3313 ETHER_BPF_MTAP(ifp, m0);
3314 if (vi->flags & TX_USES_VM_WR)
3315 n = write_txpkt_vm_wr(sc, txq, m0);
3317 n = write_txpkt_wr(sc, txq, m0, avail);
3319 MPASS(n >= 1 && n <= avail);
3320 if (!(mbuf_cflags(m0) & MC_TLS))
3321 MPASS(n <= SGE_MAX_WR_NDESC);
3325 IDXINCR(eq->pidx, n, eq->sidx);
3327 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */
3328 if (wr_can_update_eq(wr))
3329 set_txupdate_flags(txq, avail, wr);
3330 ring_eq_db(sc, eq, dbdiff);
3331 avail += reclaim_tx_descs(txq, 32);
3337 if (__predict_false(++cidx == r->size))
3341 if (wr_can_update_eq(wr))
3342 set_txupdate_flags(txq, avail, wr);
3343 ring_eq_db(sc, eq, dbdiff);
3344 reclaim_tx_descs(txq, 32);
3345 } else if (eq->pidx == eq->cidx && txp->npkt > 0 &&
3346 atomic_load_int(&txq->eq.equiq) == 0) {
3348 * If nothing was submitted to the chip for tx (it was coalesced
3349 * into txpkts instead) and there is no tx update outstanding
3350 * then we need to send txpkts now.
3353 MPASS(txp->npkt > 0);
3354 for (i = 0; i < txp->npkt; i++)
3355 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3356 if (txp->npkt > 1) {
3357 MPASS(avail >= tx_len16_to_desc(txp->len16));
3358 if (vi->flags & TX_USES_VM_WR)
3359 n = write_txpkts_vm_wr(sc, txq);
3361 n = write_txpkts_wr(sc, txq);
3364 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3365 if (vi->flags & TX_USES_VM_WR)
3366 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]);
3368 n = write_txpkt_wr(sc, txq, txp->mb[0], avail);
3370 MPASS(n <= SGE_MAX_WR_NDESC);
3371 wr = &eq->desc[eq->pidx];
3372 IDXINCR(eq->pidx, n, eq->sidx);
3373 txp->npkt = 0; /* emptied */
3375 MPASS(wr_can_update_eq(wr));
3376 set_txupdate_flags(txq, avail - n, wr);
3377 ring_eq_db(sc, eq, n);
3378 reclaim_tx_descs(txq, 32);
3380 *coalescing = txp->npkt > 0;
3386 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3390 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3391 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3392 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3393 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3397 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3398 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3399 if (pktc_idx >= 0) {
3400 iq->intr_params |= F_QINTR_CNT_EN;
3401 iq->intr_pktc_idx = pktc_idx;
3403 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3404 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3408 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3412 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3413 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3414 if (sc->flags & BUF_PACKING_OK &&
3415 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3416 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3417 fl->flags |= FL_BUF_PACKING;
3418 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3419 fl->safe_zidx = sc->sge.safe_zidx;
3423 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3424 uint8_t tx_chan, uint16_t iqid, char *name)
3426 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
3428 eq->flags = eqtype & EQ_TYPEMASK;
3429 eq->tx_chan = tx_chan;
3431 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3432 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3436 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3437 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3441 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3442 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3444 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
3448 rc = bus_dmamem_alloc(*tag, va,
3449 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3451 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
3455 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3457 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
3462 free_ring(sc, *tag, *map, *pa, *va);
3468 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3469 bus_addr_t pa, void *va)
3472 bus_dmamap_unload(tag, map);
3474 bus_dmamem_free(tag, va, map);
3476 bus_dma_tag_destroy(tag);
3482 * Allocates the ring for an ingress queue and an optional freelist. If the
3483 * freelist is specified it will be allocated and then associated with the
3486 * Returns errno on failure. Resources allocated up to that point may still be
3487 * allocated. Caller is responsible for cleanup in case this function fails.
3489 * If the ingress queue will take interrupts directly then the intr_idx
3490 * specifies the vector, starting from 0. -1 means the interrupts for this
3491 * queue should be forwarded to the fwq.
3494 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3495 int intr_idx, int cong)
3497 int rc, i, cntxt_id;
3500 struct port_info *pi = vi->pi;
3501 struct adapter *sc = iq->adapter;
3502 struct sge_params *sp = &sc->params.sge;
3505 len = iq->qsize * IQ_ESIZE;
3506 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3507 (void **)&iq->desc);
3511 bzero(&c, sizeof(c));
3512 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3513 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3514 V_FW_IQ_CMD_VFN(0));
3516 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3519 /* Special handling for firmware event queue */
3520 if (iq == &sc->sge.fwq)
3521 v |= F_FW_IQ_CMD_IQASYNCH;
3524 /* Forwarded interrupts, all headed to fwq */
3525 v |= F_FW_IQ_CMD_IQANDST;
3526 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3528 KASSERT(intr_idx < sc->intr_count,
3529 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
3530 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
3533 c.type_to_iqandstindex = htobe32(v |
3534 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3535 V_FW_IQ_CMD_VIID(vi->viid) |
3536 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3537 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3538 F_FW_IQ_CMD_IQGTSMODE |
3539 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3540 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3541 c.iqsize = htobe16(iq->qsize);
3542 c.iqaddr = htobe64(iq->ba);
3544 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3547 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3549 len = fl->qsize * EQ_ESIZE;
3550 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3551 &fl->ba, (void **)&fl->desc);
3555 /* Allocate space for one software descriptor per buffer. */
3556 rc = alloc_fl_sdesc(fl);
3558 device_printf(sc->dev,
3559 "failed to setup fl software descriptors: %d\n",
3564 if (fl->flags & FL_BUF_PACKING) {
3565 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3566 fl->buf_boundary = sp->pack_boundary;
3568 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3569 fl->buf_boundary = 16;
3571 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3572 fl->buf_boundary = sp->pad_boundary;
3574 c.iqns_to_fl0congen |=
3575 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3576 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3577 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3578 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3581 c.iqns_to_fl0congen |=
3582 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
3583 F_FW_IQ_CMD_FL0CONGCIF |
3584 F_FW_IQ_CMD_FL0CONGEN);
3586 c.fl0dcaen_to_fl0cidxfthresh =
3587 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3588 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3589 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3590 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3591 c.fl0size = htobe16(fl->qsize);
3592 c.fl0addr = htobe64(fl->ba);
3595 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3597 device_printf(sc->dev,
3598 "failed to create ingress queue: %d\n", rc);
3603 iq->gen = F_RSPD_GEN;
3604 iq->intr_next = iq->intr_params;
3605 iq->cntxt_id = be16toh(c.iqid);
3606 iq->abs_id = be16toh(c.physiqid);
3607 iq->flags |= IQ_ALLOCATED;
3609 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3610 if (cntxt_id >= sc->sge.iqmap_sz) {
3611 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3612 cntxt_id, sc->sge.iqmap_sz - 1);
3614 sc->sge.iqmap[cntxt_id] = iq;
3619 iq->flags |= IQ_HAS_FL;
3620 fl->cntxt_id = be16toh(c.fl0id);
3621 fl->pidx = fl->cidx = 0;
3623 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3624 if (cntxt_id >= sc->sge.eqmap_sz) {
3625 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3626 __func__, cntxt_id, sc->sge.eqmap_sz - 1);
3628 sc->sge.eqmap[cntxt_id] = (void *)fl;
3631 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3632 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3633 uint32_t mask = (1 << s_qpp) - 1;
3634 volatile uint8_t *udb;
3636 udb = sc->udbs_base + UDBS_DB_OFFSET;
3637 udb += (qid >> s_qpp) << PAGE_SHIFT;
3639 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3640 udb += qid << UDBS_SEG_SHIFT;
3643 fl->udb = (volatile void *)udb;
3645 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3648 /* Enough to make sure the SGE doesn't think it's starved */
3649 refill_fl(sc, fl, fl->lowat);
3653 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
3654 uint32_t param, val;
3656 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3657 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3658 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
3663 for (i = 0; i < 4; i++) {
3664 if (cong & (1 << i))
3665 val |= 1 << (i << 2);
3669 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3671 /* report error but carry on */
3672 device_printf(sc->dev,
3673 "failed to set congestion manager context for "
3674 "ingress queue %d: %d\n", iq->cntxt_id, rc);
3678 /* Enable IQ interrupts */
3679 atomic_store_rel_int(&iq->state, IQS_IDLE);
3680 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3681 V_INGRESSQID(iq->cntxt_id));
3687 free_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3690 struct adapter *sc = iq->adapter;
3694 return (0); /* nothing to do */
3696 dev = vi ? vi->dev : sc->dev;
3698 if (iq->flags & IQ_ALLOCATED) {
3699 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
3700 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
3701 fl ? fl->cntxt_id : 0xffff, 0xffff);
3704 "failed to free queue %p: %d\n", iq, rc);
3707 iq->flags &= ~IQ_ALLOCATED;
3710 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3712 bzero(iq, sizeof(*iq));
3715 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
3719 free_fl_sdesc(sc, fl);
3721 if (mtx_initialized(&fl->fl_lock))
3722 mtx_destroy(&fl->fl_lock);
3724 bzero(fl, sizeof(*fl));
3731 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3734 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3736 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3737 "bus address of descriptor ring");
3738 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3739 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3740 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3741 &iq->abs_id, 0, "absolute id of the queue");
3742 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3743 &iq->cntxt_id, 0, "SGE context id of the queue");
3744 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx,
3745 0, "consumer index");
3749 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3750 struct sysctl_oid *oid, struct sge_fl *fl)
3752 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3754 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3755 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3756 children = SYSCTL_CHILDREN(oid);
3758 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3759 &fl->ba, "bus address of descriptor ring");
3760 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3761 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3762 "desc ring size in bytes");
3763 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3764 &fl->cntxt_id, 0, "SGE context id of the freelist");
3765 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3766 fl_pad ? 1 : 0, "padding enabled");
3767 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3768 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3769 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3770 0, "consumer index");
3771 if (fl->flags & FL_BUF_PACKING) {
3772 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3773 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3775 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3776 0, "producer index");
3777 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3778 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3779 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3780 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3781 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3782 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3786 alloc_fwq(struct adapter *sc)
3789 struct sge_iq *fwq = &sc->sge.fwq;
3790 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
3791 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3793 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
3794 if (sc->flags & IS_VF)
3797 intr_idx = sc->intr_count > 1 ? 1 : 0;
3798 rc = alloc_iq_fl(&sc->port[0]->vi[0], fwq, NULL, intr_idx, -1);
3800 device_printf(sc->dev,
3801 "failed to create firmware event queue: %d\n", rc);
3805 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq",
3806 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "firmware event queue");
3807 add_iq_sysctls(&sc->ctx, oid, fwq);
3813 free_fwq(struct adapter *sc)
3815 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
3819 alloc_ctrlq(struct adapter *sc, struct sge_wrq *ctrlq, int idx,
3820 struct sysctl_oid *oid)
3824 struct sysctl_oid_list *children;
3826 snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev),
3828 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[idx]->tx_chan,
3829 sc->sge.fwq.cntxt_id, name);
3831 children = SYSCTL_CHILDREN(oid);
3832 snprintf(name, sizeof(name), "%d", idx);
3833 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name,
3834 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ctrl queue");
3835 rc = alloc_wrq(sc, NULL, ctrlq, oid);
3841 tnl_cong(struct port_info *pi, int drop)
3849 return (pi->rx_e_chan_map);
3853 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int intr_idx, int idx,
3854 struct sysctl_oid *oid)
3857 struct adapter *sc = vi->adapter;
3858 struct sysctl_oid_list *children;
3861 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, intr_idx,
3862 tnl_cong(vi->pi, cong_drop));
3867 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
3869 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
3870 ("iq_base mismatch"));
3871 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
3872 ("PF with non-zero iq_base"));
3875 * The freelist is just barely above the starvation threshold right now,
3876 * fill it up a bit more.
3879 refill_fl(sc, &rxq->fl, 128);
3880 FL_UNLOCK(&rxq->fl);
3882 #if defined(INET) || defined(INET6)
3883 rc = tcp_lro_init_args(&rxq->lro, vi->ifp, lro_entries, lro_mbufs);
3886 MPASS(rxq->lro.ifp == vi->ifp); /* also indicates LRO init'ed */
3888 if (vi->ifp->if_capenable & IFCAP_LRO)
3889 rxq->iq.flags |= IQ_LRO_ENABLED;
3891 if (vi->ifp->if_capenable & IFCAP_HWRXTSTMP)
3892 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3895 children = SYSCTL_CHILDREN(oid);
3897 snprintf(name, sizeof(name), "%d", idx);
3898 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
3899 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue");
3900 children = SYSCTL_CHILDREN(oid);
3902 add_iq_sysctls(&vi->ctx, oid, &rxq->iq);
3903 #if defined(INET) || defined(INET6)
3904 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
3905 &rxq->lro.lro_queued, 0, NULL);
3906 SYSCTL_ADD_U64(&vi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
3907 &rxq->lro.lro_flushed, 0, NULL);
3909 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
3910 &rxq->rxcsum, "# of times hardware assisted with checksum");
3911 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_extraction",
3912 CTLFLAG_RD, &rxq->vlan_extraction,
3913 "# of times hardware extracted 802.1Q tag");
3914 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_rxcsum",
3915 CTLFLAG_RD, &rxq->vxlan_rxcsum,
3916 "# of times hardware assisted with inner checksum (VXLAN) ");
3918 add_fl_sysctls(sc, &vi->ctx, oid, &rxq->fl);
3924 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
3928 #if defined(INET) || defined(INET6)
3930 tcp_lro_free(&rxq->lro);
3931 rxq->lro.ifp = NULL;
3935 rc = free_iq_fl(vi, &rxq->iq, &rxq->fl);
3937 bzero(rxq, sizeof(*rxq));
3944 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq,
3945 int intr_idx, int idx, struct sysctl_oid *oid)
3947 struct port_info *pi = vi->pi;
3949 struct sysctl_oid_list *children;
3952 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx, 0);
3956 children = SYSCTL_CHILDREN(oid);
3958 snprintf(name, sizeof(name), "%d", idx);
3959 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
3960 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "rx queue");
3961 add_iq_sysctls(&vi->ctx, oid, &ofld_rxq->iq);
3962 add_fl_sysctls(pi->adapter, &vi->ctx, oid, &ofld_rxq->fl);
3968 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
3972 rc = free_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl);
3974 bzero(ofld_rxq, sizeof(*ofld_rxq));
3981 * Returns a reasonable automatic cidx flush threshold for a given queue size.
3984 qsize_to_fthresh(int qsize)
3988 while (!powerof2(qsize))
3990 fthresh = ilog2(qsize);
3991 if (fthresh > X_CIDXFLUSHTHRESH_128)
3992 fthresh = X_CIDXFLUSHTHRESH_128;
3998 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
4001 struct fw_eq_ctrl_cmd c;
4002 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4004 bzero(&c, sizeof(c));
4006 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
4007 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
4008 V_FW_EQ_CTRL_CMD_VFN(0));
4009 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
4010 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
4011 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
4012 c.physeqid_pkd = htobe32(0);
4013 c.fetchszm_to_iqid =
4014 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4015 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
4016 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
4018 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4019 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4020 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4021 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4022 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
4023 c.eqaddr = htobe64(eq->ba);
4025 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4027 device_printf(sc->dev,
4028 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
4031 eq->flags |= EQ_ALLOCATED;
4033 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
4034 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4035 if (cntxt_id >= sc->sge.eqmap_sz)
4036 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4037 cntxt_id, sc->sge.eqmap_sz - 1);
4038 sc->sge.eqmap[cntxt_id] = eq;
4044 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4047 struct fw_eq_eth_cmd c;
4048 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4050 bzero(&c, sizeof(c));
4052 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
4053 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
4054 V_FW_EQ_ETH_CMD_VFN(0));
4055 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
4056 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
4057 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
4058 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
4059 c.fetchszm_to_iqid =
4060 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
4061 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
4062 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
4064 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4065 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4066 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4067 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
4068 c.eqaddr = htobe64(eq->ba);
4070 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4072 device_printf(vi->dev,
4073 "failed to create Ethernet egress queue: %d\n", rc);
4076 eq->flags |= EQ_ALLOCATED;
4078 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
4079 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4080 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4081 if (cntxt_id >= sc->sge.eqmap_sz)
4082 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4083 cntxt_id, sc->sge.eqmap_sz - 1);
4084 sc->sge.eqmap[cntxt_id] = eq;
4089 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4091 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4094 struct fw_eq_ofld_cmd c;
4095 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4097 bzero(&c, sizeof(c));
4099 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
4100 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
4101 V_FW_EQ_OFLD_CMD_VFN(0));
4102 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
4103 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
4104 c.fetchszm_to_iqid =
4105 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4106 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
4107 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
4109 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4110 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4111 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4112 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4113 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
4114 c.eqaddr = htobe64(eq->ba);
4116 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4118 device_printf(vi->dev,
4119 "failed to create egress queue for TCP offload: %d\n", rc);
4122 eq->flags |= EQ_ALLOCATED;
4124 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
4125 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4126 if (cntxt_id >= sc->sge.eqmap_sz)
4127 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4128 cntxt_id, sc->sge.eqmap_sz - 1);
4129 sc->sge.eqmap[cntxt_id] = eq;
4136 alloc_eq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4141 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
4143 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4144 len = qsize * EQ_ESIZE;
4145 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
4146 &eq->ba, (void **)&eq->desc);
4150 eq->pidx = eq->cidx = eq->dbidx = 0;
4151 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
4153 eq->doorbells = sc->doorbells;
4155 switch (eq->flags & EQ_TYPEMASK) {
4157 rc = ctrl_eq_alloc(sc, eq);
4161 rc = eth_eq_alloc(sc, vi, eq);
4164 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4166 rc = ofld_eq_alloc(sc, vi, eq);
4171 panic("%s: invalid eq type %d.", __func__,
4172 eq->flags & EQ_TYPEMASK);
4175 device_printf(sc->dev,
4176 "failed to allocate egress queue(%d): %d\n",
4177 eq->flags & EQ_TYPEMASK, rc);
4180 if (isset(&eq->doorbells, DOORBELL_UDB) ||
4181 isset(&eq->doorbells, DOORBELL_UDBWC) ||
4182 isset(&eq->doorbells, DOORBELL_WCWR)) {
4183 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4184 uint32_t mask = (1 << s_qpp) - 1;
4185 volatile uint8_t *udb;
4187 udb = sc->udbs_base + UDBS_DB_OFFSET;
4188 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
4189 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
4190 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4191 clrbit(&eq->doorbells, DOORBELL_WCWR);
4193 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
4196 eq->udb = (volatile void *)udb;
4203 free_eq(struct adapter *sc, struct sge_eq *eq)
4207 if (eq->flags & EQ_ALLOCATED) {
4208 switch (eq->flags & EQ_TYPEMASK) {
4210 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
4215 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
4219 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4221 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
4227 panic("%s: invalid eq type %d.", __func__,
4228 eq->flags & EQ_TYPEMASK);
4231 device_printf(sc->dev,
4232 "failed to free egress queue (%d): %d\n",
4233 eq->flags & EQ_TYPEMASK, rc);
4236 eq->flags &= ~EQ_ALLOCATED;
4239 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4241 if (mtx_initialized(&eq->eq_lock))
4242 mtx_destroy(&eq->eq_lock);
4244 bzero(eq, sizeof(*eq));
4249 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4250 struct sysctl_oid *oid)
4253 struct sysctl_ctx_list *ctx = vi ? &vi->ctx : &sc->ctx;
4254 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4256 rc = alloc_eq(sc, vi, &wrq->eq);
4261 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4262 TAILQ_INIT(&wrq->incomplete_wrs);
4263 STAILQ_INIT(&wrq->wr_list);
4264 wrq->nwr_pending = 0;
4265 wrq->ndesc_needed = 0;
4267 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4268 &wrq->eq.ba, "bus address of descriptor ring");
4269 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4270 wrq->eq.sidx * EQ_ESIZE + sc->params.sge.spg_len,
4271 "desc ring size in bytes");
4272 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4273 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
4274 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
4275 &wrq->eq.cidx, 0, "consumer index");
4276 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
4277 &wrq->eq.pidx, 0, "producer index");
4278 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4279 wrq->eq.sidx, "status page index");
4280 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4281 &wrq->tx_wrs_direct, "# of work requests (direct)");
4282 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4283 &wrq->tx_wrs_copied, "# of work requests (copied)");
4284 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4285 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4291 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4295 rc = free_eq(sc, &wrq->eq);
4299 bzero(wrq, sizeof(*wrq));
4304 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
4305 struct sysctl_oid *oid)
4308 struct port_info *pi = vi->pi;
4309 struct adapter *sc = pi->adapter;
4310 struct sge_eq *eq = &txq->eq;
4313 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4315 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
4316 M_CXGBE, &eq->eq_lock, M_WAITOK);
4318 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
4322 rc = alloc_eq(sc, vi, eq);
4324 mp_ring_free(txq->r);
4329 /* Can't fail after this point. */
4332 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4334 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4335 ("eq_base mismatch"));
4336 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4337 ("PF with non-zero eq_base"));
4339 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4341 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4342 if (vi->flags & TX_USES_VM_WR)
4343 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4344 V_TXPKT_INTF(pi->tx_chan));
4346 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4347 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4348 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4350 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4354 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr);
4355 txq->txp.max_npkt = min(nitems(txp->mb),
4356 sc->params.max_pkts_per_eth_tx_pkts_wr);
4357 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF))
4358 txq->txp.max_npkt--;
4360 snprintf(name, sizeof(name), "%d", idx);
4361 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
4362 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "tx queue");
4363 children = SYSCTL_CHILDREN(oid);
4365 SYSCTL_ADD_UAUTO(&vi->ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
4366 &eq->ba, "bus address of descriptor ring");
4367 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4368 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4369 "desc ring size in bytes");
4370 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4371 &eq->abs_id, 0, "absolute id of the queue");
4372 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4373 &eq->cntxt_id, 0, "SGE context id of the queue");
4374 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
4375 &eq->cidx, 0, "consumer index");
4376 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
4377 &eq->pidx, 0, "producer index");
4378 SYSCTL_ADD_INT(&vi->ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4379 eq->sidx, "status page index");
4381 SYSCTL_ADD_PROC(&vi->ctx, children, OID_AUTO, "tc",
4382 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, idx, sysctl_tc,
4383 "I", "traffic class (-1 means none)");
4385 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4386 &txq->txcsum, "# of times hardware assisted with checksum");
4387 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vlan_insertion",
4388 CTLFLAG_RD, &txq->vlan_insertion,
4389 "# of times hardware inserted 802.1Q tag");
4390 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4391 &txq->tso_wrs, "# of TSO work requests");
4392 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4393 &txq->imm_wrs, "# of work requests with immediate data");
4394 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4395 &txq->sgl_wrs, "# of work requests with direct SGL");
4396 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4397 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4398 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_wrs",
4399 CTLFLAG_RD, &txq->txpkts0_wrs,
4400 "# of txpkts (type 0) work requests");
4401 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_wrs",
4402 CTLFLAG_RD, &txq->txpkts1_wrs,
4403 "# of txpkts (type 1) work requests");
4404 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts0_pkts",
4405 CTLFLAG_RD, &txq->txpkts0_pkts,
4406 "# of frames tx'd using type0 txpkts work requests");
4407 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts1_pkts",
4408 CTLFLAG_RD, &txq->txpkts1_pkts,
4409 "# of frames tx'd using type1 txpkts work requests");
4410 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "txpkts_flush",
4411 CTLFLAG_RD, &txq->txpkts_flush,
4412 "# of times txpkts had to be flushed out by an egress-update");
4413 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4414 &txq->raw_wrs, "# of raw work requests (non-packets)");
4415 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_tso_wrs",
4416 CTLFLAG_RD, &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests");
4417 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO, "vxlan_txcsum",
4418 CTLFLAG_RD, &txq->vxlan_txcsum,
4419 "# of times hardware assisted with inner checksums (VXLAN)");
4422 if (sc->flags & KERN_TLS_OK) {
4423 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4424 "kern_tls_records", CTLFLAG_RD, &txq->kern_tls_records,
4425 "# of NIC TLS records transmitted");
4426 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4427 "kern_tls_short", CTLFLAG_RD, &txq->kern_tls_short,
4428 "# of short NIC TLS records transmitted");
4429 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4430 "kern_tls_partial", CTLFLAG_RD, &txq->kern_tls_partial,
4431 "# of partial NIC TLS records transmitted");
4432 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4433 "kern_tls_full", CTLFLAG_RD, &txq->kern_tls_full,
4434 "# of full NIC TLS records transmitted");
4435 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4436 "kern_tls_octets", CTLFLAG_RD, &txq->kern_tls_octets,
4437 "# of payload octets in transmitted NIC TLS records");
4438 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4439 "kern_tls_waste", CTLFLAG_RD, &txq->kern_tls_waste,
4440 "# of octets DMAd but not transmitted in NIC TLS records");
4441 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4442 "kern_tls_options", CTLFLAG_RD, &txq->kern_tls_options,
4443 "# of NIC TLS options-only packets transmitted");
4444 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4445 "kern_tls_header", CTLFLAG_RD, &txq->kern_tls_header,
4446 "# of NIC TLS header-only packets transmitted");
4447 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4448 "kern_tls_fin", CTLFLAG_RD, &txq->kern_tls_fin,
4449 "# of NIC TLS FIN-only packets transmitted");
4450 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4451 "kern_tls_fin_short", CTLFLAG_RD, &txq->kern_tls_fin_short,
4452 "# of NIC TLS padded FIN packets on short TLS records");
4453 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4454 "kern_tls_cbc", CTLFLAG_RD, &txq->kern_tls_cbc,
4455 "# of NIC TLS sessions using AES-CBC");
4456 SYSCTL_ADD_UQUAD(&vi->ctx, children, OID_AUTO,
4457 "kern_tls_gcm", CTLFLAG_RD, &txq->kern_tls_gcm,
4458 "# of NIC TLS sessions using AES-GCM");
4461 mp_ring_sysctls(txq->r, &vi->ctx, children);
4467 free_txq(struct vi_info *vi, struct sge_txq *txq)
4470 struct adapter *sc = vi->adapter;
4471 struct sge_eq *eq = &txq->eq;
4473 rc = free_eq(sc, eq);
4477 sglist_free(txq->gl);
4478 free(txq->sdesc, M_CXGBE);
4479 mp_ring_free(txq->r);
4481 bzero(txq, sizeof(*txq));
4486 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4488 bus_addr_t *ba = arg;
4491 ("%s meant for single segment mappings only.", __func__));
4493 *ba = error ? 0 : segs->ds_addr;
4497 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4501 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4505 v = fl->dbval | V_PIDX(n);
4507 *fl->udb = htole32(v);
4509 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4510 IDXINCR(fl->dbidx, n, fl->sidx);
4514 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4515 * recycled do not count towards this allocation budget.
4517 * Returns non-zero to indicate that this freelist should be added to the list
4518 * of starving freelists.
4521 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4524 struct fl_sdesc *sd;
4527 struct rx_buf_info *rxb;
4528 struct cluster_metadata *clm;
4529 uint16_t max_pidx, zidx = fl->zidx;
4530 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4532 FL_LOCK_ASSERT_OWNED(fl);
4535 * We always stop at the beginning of the hardware descriptor that's just
4536 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4537 * which would mean an empty freelist to the chip.
4539 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4540 if (fl->pidx == max_pidx * 8)
4543 d = &fl->desc[fl->pidx];
4544 sd = &fl->sdesc[fl->pidx];
4545 rxb = &sc->sge.rx_buf_info[zidx];
4549 if (sd->cl != NULL) {
4551 if (sd->nmbuf == 0) {
4553 * Fast recycle without involving any atomics on
4554 * the cluster's metadata (if the cluster has
4555 * metadata). This happens when all frames
4556 * received in the cluster were small enough to
4557 * fit within a single mbuf each.
4559 fl->cl_fast_recycled++;
4564 * Cluster is guaranteed to have metadata. Clusters
4565 * without metadata always take the fast recycle path
4566 * when they're recycled.
4568 clm = cl_metadata(sd);
4571 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4573 counter_u64_add(extfree_rels, 1);
4576 sd->cl = NULL; /* gave up my reference */
4578 MPASS(sd->cl == NULL);
4579 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4580 if (__predict_false(cl == NULL)) {
4581 if (zidx != fl->safe_zidx) {
4582 zidx = fl->safe_zidx;
4583 rxb = &sc->sge.rx_buf_info[zidx];
4584 cl = uma_zalloc(rxb->zone, M_NOWAIT);
4592 pa = pmap_kextract((vm_offset_t)cl);
4596 if (fl->flags & FL_BUF_PACKING) {
4597 *d = htobe64(pa | rxb->hwidx2);
4598 sd->moff = rxb->size2;
4600 *d = htobe64(pa | rxb->hwidx1);
4607 if (__predict_false((++fl->pidx & 7) == 0)) {
4608 uint16_t pidx = fl->pidx >> 3;
4610 if (__predict_false(pidx == fl->sidx)) {
4616 if (n < 8 || pidx == max_pidx)
4619 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
4624 if ((fl->pidx >> 3) != fl->dbidx)
4627 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
4631 * Attempt to refill all starving freelists.
4634 refill_sfl(void *arg)
4636 struct adapter *sc = arg;
4637 struct sge_fl *fl, *fl_temp;
4639 mtx_assert(&sc->sfl_lock, MA_OWNED);
4640 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
4642 refill_fl(sc, fl, 64);
4643 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
4644 TAILQ_REMOVE(&sc->sfl, fl, link);
4645 fl->flags &= ~FL_STARVING;
4650 if (!TAILQ_EMPTY(&sc->sfl))
4651 callout_schedule(&sc->sfl_callout, hz / 5);
4655 alloc_fl_sdesc(struct sge_fl *fl)
4658 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
4665 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
4667 struct fl_sdesc *sd;
4668 struct cluster_metadata *clm;
4672 for (i = 0; i < fl->sidx * 8; i++, sd++) {
4677 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
4678 else if (fl->flags & FL_BUF_PACKING) {
4679 clm = cl_metadata(sd);
4680 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
4681 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
4683 counter_u64_add(extfree_rels, 1);
4689 free(fl->sdesc, M_CXGBE);
4694 get_pkt_gl(struct mbuf *m, struct sglist *gl)
4701 rc = sglist_append_mbuf(gl, m);
4702 if (__predict_false(rc != 0)) {
4703 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
4704 "with %d.", __func__, m, mbuf_nsegs(m), rc);
4707 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
4708 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
4709 mbuf_nsegs(m), gl->sg_nseg));
4710 #if 0 /* vm_wr not readily available here. */
4711 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr),
4712 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
4713 gl->sg_nseg, max_nsegs_allowed(m, vm_wr)));
4718 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
4721 txpkt_len16(u_int nsegs, const u_int extra)
4727 nsegs--; /* first segment is part of ulptx_sgl */
4728 n = extra + sizeof(struct fw_eth_tx_pkt_wr) +
4729 sizeof(struct cpl_tx_pkt_core) +
4730 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4732 return (howmany(n, 16));
4736 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
4740 txpkt_vm_len16(u_int nsegs, const u_int extra)
4746 nsegs--; /* first segment is part of ulptx_sgl */
4747 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) +
4748 sizeof(struct cpl_tx_pkt_core) +
4749 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4751 return (howmany(n, 16));
4755 calculate_mbuf_len16(struct mbuf *m, bool vm_wr)
4757 const int lso = sizeof(struct cpl_tx_pkt_lso_core);
4758 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso);
4762 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso));
4764 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0));
4769 if (needs_vxlan_tso(m))
4770 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso));
4772 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso));
4774 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0));
4778 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
4782 txpkts0_len16(u_int nsegs)
4788 nsegs--; /* first segment is part of ulptx_sgl */
4789 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
4790 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
4791 8 * ((3 * nsegs) / 2 + (nsegs & 1));
4793 return (howmany(n, 16));
4797 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
4805 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
4807 return (howmany(n, 16));
4811 imm_payload(u_int ndesc)
4815 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
4816 sizeof(struct cpl_tx_pkt_core);
4821 static inline uint64_t
4822 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
4825 int csum_type, l2hlen, l3hlen;
4827 static const int csum_types[3][2] = {
4828 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6},
4829 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6},
4835 if (!needs_hwcsum(m))
4836 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
4838 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN);
4839 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip));
4841 if (needs_vxlan_csum(m)) {
4842 MPASS(m->m_pkthdr.l4hlen > 0);
4843 MPASS(m->m_pkthdr.l5hlen > 0);
4844 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN);
4845 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip));
4847 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
4848 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen +
4849 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN;
4850 l3hlen = m->m_pkthdr.inner_l3hlen;
4852 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN;
4853 l3hlen = m->m_pkthdr.l3hlen;
4857 if (!needs_l3_csum(m))
4858 ctrl |= F_TXPKT_IPCSUM_DIS;
4860 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP |
4861 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP))
4863 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP |
4864 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP))
4869 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP |
4870 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP))
4873 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP |
4874 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP));
4878 * needs_hwcsum returned true earlier so there must be some kind of
4879 * checksum to calculate.
4881 csum_type = csum_types[x][y];
4882 MPASS(csum_type != 0);
4883 if (csum_type == TX_CSUM_IP)
4884 ctrl |= F_TXPKT_L4CSUM_DIS;
4885 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);
4886 if (chip_id(sc) <= CHELSIO_T5)
4887 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);
4889 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);
4894 static inline void *
4895 write_lso_cpl(void *cpl, struct mbuf *m0)
4897 struct cpl_tx_pkt_lso_core *lso;
4900 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4901 m0->m_pkthdr.l4hlen > 0,
4902 ("%s: mbuf %p needs TSO but missing header lengths",
4905 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
4906 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
4907 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
4908 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
4909 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
4910 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4914 lso->lso_ctrl = htobe32(ctrl);
4915 lso->ipid_ofst = htobe16(0);
4916 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
4917 lso->seqno_offset = htobe32(0);
4918 lso->len = htobe32(m0->m_pkthdr.len);
4924 write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
4926 struct cpl_tx_tnl_lso *tnl_lso = cpl;
4929 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 &&
4930 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 &&
4931 m0->m_pkthdr.inner_l5hlen > 0,
4932 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths",
4934 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
4935 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0,
4936 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths",
4939 /* Outer headers. */
4940 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |
4941 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST |
4942 V_CPL_TX_TNL_LSO_ETHHDRLENOUT(
4943 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
4944 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) |
4945 F_CPL_TX_TNL_LSO_IPLENSETOUT;
4946 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
4947 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;
4949 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |
4950 F_CPL_TX_TNL_LSO_IPIDINCOUT;
4952 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);
4953 tnl_lso->IpIdOffsetOut = 0;
4954 tnl_lso->UdpLenSetOut_to_TnlHdrLen =
4955 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT |
4956 F_CPL_TX_TNL_LSO_UDPLENSETOUT |
4957 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen +
4958 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
4959 m0->m_pkthdr.l5hlen) |
4960 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
4963 /* Inner headers. */
4964 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
4965 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) |
4966 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) |
4967 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2);
4968 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr))
4969 ctrl |= F_CPL_TX_TNL_LSO_IPV6;
4970 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);
4971 tnl_lso->IpIdOffset = 0;
4972 tnl_lso->IpIdSplit_to_Mss =
4973 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz));
4974 tnl_lso->TCPSeqOffset = 0;
4975 tnl_lso->EthLenOffset_Size =
4976 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len));
4978 return (tnl_lso + 1);
4981 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */
4984 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
4985 * software descriptor, and advance the pidx. It is guaranteed that enough
4986 * descriptors are available.
4988 * The return value is the # of hardware descriptors used.
4991 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0)
4994 struct fw_eth_tx_pkt_vm_wr *wr;
4995 struct tx_sdesc *txsd;
4996 struct cpl_tx_pkt_core *cpl;
4997 uint32_t ctrl; /* used in many unrelated places */
4999 int len16, ndesc, pktlen, nsegs;
5002 TXQ_LOCK_ASSERT_OWNED(txq);
5005 len16 = mbuf_len16(m0);
5006 nsegs = mbuf_nsegs(m0);
5007 pktlen = m0->m_pkthdr.len;
5008 ctrl = sizeof(struct cpl_tx_pkt_core);
5010 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5011 ndesc = tx_len16_to_desc(len16);
5013 /* Firmware work request header */
5015 wr = (void *)&eq->desc[eq->pidx];
5016 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
5017 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5019 ctrl = V_FW_WR_LEN16(len16);
5020 wr->equiq_to_len16 = htobe32(ctrl);
5025 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
5026 * vlantci is ignored unless the ethtype is 0x8100, so it's
5027 * simpler to always copy it rather than making it
5028 * conditional. Also, it seems that we do not have to set
5029 * vlantci or fake the ethtype when doing VLAN tag insertion.
5031 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst);
5033 if (needs_tso(m0)) {
5034 cpl = write_lso_cpl(wr + 1, m0);
5037 cpl = (void *)(wr + 1);
5039 /* Checksum offload */
5040 ctrl1 = csum_to_ctrl(sc, m0);
5041 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5042 txq->txcsum++; /* some hardware assistance provided */
5044 /* VLAN tag insertion */
5045 if (needs_vlan_insertion(m0)) {
5046 ctrl1 |= F_TXPKT_VLAN_VLD |
5047 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5048 txq->vlan_insertion++;
5052 cpl->ctrl0 = txq->cpl_ctrl0;
5054 cpl->len = htobe16(pktlen);
5055 cpl->ctrl1 = htobe64(ctrl1);
5058 dst = (void *)(cpl + 1);
5061 * A packet using TSO will use up an entire descriptor for the
5062 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
5063 * If this descriptor is the last descriptor in the ring, wrap
5064 * around to the front of the ring explicitly for the start of
5067 if (dst == (void *)&eq->desc[eq->sidx]) {
5068 dst = (void *)&eq->desc[0];
5069 write_gl_to_txd(txq, m0, &dst, 0);
5071 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5075 txsd = &txq->sdesc[eq->pidx];
5077 txsd->desc_used = ndesc;
5083 * Write a raw WR to the hardware descriptors, update the software
5084 * descriptor, and advance the pidx. It is guaranteed that enough
5085 * descriptors are available.
5087 * The return value is the # of hardware descriptors used.
5090 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
5092 struct sge_eq *eq = &txq->eq;
5093 struct tx_sdesc *txsd;
5098 len16 = mbuf_len16(m0);
5099 ndesc = tx_len16_to_desc(len16);
5100 MPASS(ndesc <= available);
5103 for (m = m0; m != NULL; m = m->m_next)
5104 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5108 txsd = &txq->sdesc[eq->pidx];
5110 txsd->desc_used = ndesc;
5116 * Write a txpkt WR for this packet to the hardware descriptors, update the
5117 * software descriptor, and advance the pidx. It is guaranteed that enough
5118 * descriptors are available.
5120 * The return value is the # of hardware descriptors used.
5123 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0,
5127 struct fw_eth_tx_pkt_wr *wr;
5128 struct tx_sdesc *txsd;
5129 struct cpl_tx_pkt_core *cpl;
5130 uint32_t ctrl; /* used in many unrelated places */
5132 int len16, ndesc, pktlen, nsegs;
5135 TXQ_LOCK_ASSERT_OWNED(txq);
5138 len16 = mbuf_len16(m0);
5139 nsegs = mbuf_nsegs(m0);
5140 pktlen = m0->m_pkthdr.len;
5141 ctrl = sizeof(struct cpl_tx_pkt_core);
5142 if (needs_tso(m0)) {
5143 if (needs_vxlan_tso(m0))
5144 ctrl += sizeof(struct cpl_tx_tnl_lso);
5146 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5147 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
5149 /* Immediate data. Recalculate len16 and set nsegs to 0. */
5151 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
5152 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
5155 ndesc = tx_len16_to_desc(len16);
5156 MPASS(ndesc <= available);
5158 /* Firmware work request header */
5160 wr = (void *)&eq->desc[eq->pidx];
5161 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
5162 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5164 ctrl = V_FW_WR_LEN16(len16);
5165 wr->equiq_to_len16 = htobe32(ctrl);
5168 if (needs_tso(m0)) {
5169 if (needs_vxlan_tso(m0)) {
5170 cpl = write_tnl_lso_cpl(wr + 1, m0);
5171 txq->vxlan_tso_wrs++;
5173 cpl = write_lso_cpl(wr + 1, m0);
5177 cpl = (void *)(wr + 1);
5179 /* Checksum offload */
5180 ctrl1 = csum_to_ctrl(sc, m0);
5181 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5182 /* some hardware assistance provided */
5183 if (needs_vxlan_csum(m0))
5184 txq->vxlan_txcsum++;
5189 /* VLAN tag insertion */
5190 if (needs_vlan_insertion(m0)) {
5191 ctrl1 |= F_TXPKT_VLAN_VLD |
5192 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5193 txq->vlan_insertion++;
5197 cpl->ctrl0 = txq->cpl_ctrl0;
5199 cpl->len = htobe16(pktlen);
5200 cpl->ctrl1 = htobe64(ctrl1);
5203 dst = (void *)(cpl + 1);
5204 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx]))
5205 dst = (caddr_t)&eq->desc[0];
5208 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5213 for (m = m0; m != NULL; m = m->m_next) {
5214 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5220 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
5227 txsd = &txq->sdesc[eq->pidx];
5229 txsd->desc_used = ndesc;
5235 cmp_l2hdr(struct txpkts *txp, struct mbuf *m)
5239 MPASS(txp->npkt > 0);
5240 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5242 if (txp->ethtype == be16toh(ETHERTYPE_VLAN))
5243 len = VM_TX_L2HDR_LEN;
5245 len = sizeof(struct ether_header);
5247 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0);
5251 save_l2hdr(struct txpkts *txp, struct mbuf *m)
5253 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5255 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN);
5259 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5260 int avail, bool *send)
5262 struct txpkts *txp = &txq->txp;
5264 /* Cannot have TSO and coalesce at the same time. */
5265 if (cannot_use_txpkts(m)) {
5267 *send = txp->npkt > 0;
5271 /* VF allows coalescing of type 1 (1 GL) only */
5272 if (mbuf_nsegs(m) > 1)
5273 goto cannot_coalesce;
5276 if (txp->npkt > 0) {
5277 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5278 MPASS(txp->npkt < txp->max_npkt);
5279 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5281 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) {
5286 if (m->m_pkthdr.len + txp->plen > 65535)
5287 goto retry_after_send;
5288 if (cmp_l2hdr(txp, m))
5289 goto retry_after_send;
5291 txp->len16 += txpkts1_len16();
5292 txp->plen += m->m_pkthdr.len;
5293 txp->mb[txp->npkt++] = m;
5294 if (txp->npkt == txp->max_npkt)
5297 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) +
5299 if (tx_len16_to_desc(txp->len16) > avail)
5300 goto cannot_coalesce;
5303 txp->plen = m->m_pkthdr.len;
5311 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5312 int avail, bool *send)
5314 struct txpkts *txp = &txq->txp;
5317 MPASS(!(sc->flags & IS_VF));
5319 /* Cannot have TSO and coalesce at the same time. */
5320 if (cannot_use_txpkts(m)) {
5322 *send = txp->npkt > 0;
5327 nsegs = mbuf_nsegs(m);
5328 if (txp->npkt == 0) {
5329 if (m->m_pkthdr.len > 65535)
5330 goto cannot_coalesce;
5334 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5335 txpkts0_len16(nsegs);
5339 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5342 if (tx_len16_to_desc(txp->len16) > avail)
5343 goto cannot_coalesce;
5345 txp->plen = m->m_pkthdr.len;
5348 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5349 MPASS(txp->npkt < txp->max_npkt);
5351 if (m->m_pkthdr.len + txp->plen > 65535) {
5357 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5358 if (txp->wr_type == 0) {
5359 if (tx_len16_to_desc(txp->len16 +
5360 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC))
5361 goto retry_after_send;
5362 txp->len16 += txpkts0_len16(nsegs);
5365 goto retry_after_send;
5366 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) >
5368 goto retry_after_send;
5369 txp->len16 += txpkts1_len16();
5372 txp->plen += m->m_pkthdr.len;
5373 txp->mb[txp->npkt++] = m;
5374 if (txp->npkt == txp->max_npkt)
5381 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5382 * the software descriptor, and advance the pidx. It is guaranteed that enough
5383 * descriptors are available.
5385 * The return value is the # of hardware descriptors used.
5388 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq)
5390 const struct txpkts *txp = &txq->txp;
5391 struct sge_eq *eq = &txq->eq;
5392 struct fw_eth_tx_pkts_wr *wr;
5393 struct tx_sdesc *txsd;
5394 struct cpl_tx_pkt_core *cpl;
5396 int ndesc, i, checkwrap;
5397 struct mbuf *m, *last;
5400 TXQ_LOCK_ASSERT_OWNED(txq);
5401 MPASS(txp->npkt > 0);
5402 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5404 wr = (void *)&eq->desc[eq->pidx];
5405 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5406 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5407 wr->plen = htobe16(txp->plen);
5408 wr->npkt = txp->npkt;
5410 wr->type = txp->wr_type;
5414 * At this point we are 16B into a hardware descriptor. If checkwrap is
5415 * set then we know the WR is going to wrap around somewhere. We'll
5416 * check for that at appropriate points.
5418 ndesc = tx_len16_to_desc(txp->len16);
5420 checkwrap = eq->sidx - ndesc < eq->pidx;
5421 for (i = 0; i < txp->npkt; i++) {
5423 if (txp->wr_type == 0) {
5424 struct ulp_txpkt *ulpmc;
5425 struct ulptx_idata *ulpsc;
5427 /* ULP master command */
5429 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5430 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5431 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m)));
5433 /* ULP subcommand */
5434 ulpsc = (void *)(ulpmc + 1);
5435 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5437 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5439 cpl = (void *)(ulpsc + 1);
5441 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5442 cpl = (void *)&eq->desc[0];
5447 /* Checksum offload */
5448 ctrl1 = csum_to_ctrl(sc, m);
5449 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5450 /* some hardware assistance provided */
5451 if (needs_vxlan_csum(m))
5452 txq->vxlan_txcsum++;
5457 /* VLAN tag insertion */
5458 if (needs_vlan_insertion(m)) {
5459 ctrl1 |= F_TXPKT_VLAN_VLD |
5460 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5461 txq->vlan_insertion++;
5465 cpl->ctrl0 = txq->cpl_ctrl0;
5467 cpl->len = htobe16(m->m_pkthdr.len);
5468 cpl->ctrl1 = htobe64(ctrl1);
5472 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5473 flitp = (void *)&eq->desc[0];
5475 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5478 last->m_nextpkt = m;
5483 if (txp->wr_type == 0) {
5484 txq->txpkts0_pkts += txp->npkt;
5487 txq->txpkts1_pkts += txp->npkt;
5491 txsd = &txq->sdesc[eq->pidx];
5492 txsd->m = txp->mb[0];
5493 txsd->desc_used = ndesc;
5499 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq)
5501 const struct txpkts *txp = &txq->txp;
5502 struct sge_eq *eq = &txq->eq;
5503 struct fw_eth_tx_pkts_vm_wr *wr;
5504 struct tx_sdesc *txsd;
5505 struct cpl_tx_pkt_core *cpl;
5508 struct mbuf *m, *last;
5511 TXQ_LOCK_ASSERT_OWNED(txq);
5512 MPASS(txp->npkt > 0);
5513 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5514 MPASS(txp->mb[0] != NULL);
5515 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5517 wr = (void *)&eq->desc[eq->pidx];
5518 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
5519 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5521 wr->plen = htobe16(txp->plen);
5522 wr->npkt = txp->npkt;
5524 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16);
5528 * At this point we are 32B into a hardware descriptor. Each mbuf in
5529 * the WR will take 32B so we check for the end of the descriptor ring
5530 * before writing odd mbufs (mb[1], 3, 5, ..)
5532 ndesc = tx_len16_to_desc(txp->len16);
5534 for (i = 0; i < txp->npkt; i++) {
5536 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5537 flitp = &eq->desc[0];
5540 /* Checksum offload */
5541 ctrl1 = csum_to_ctrl(sc, m);
5542 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5543 txq->txcsum++; /* some hardware assistance provided */
5545 /* VLAN tag insertion */
5546 if (needs_vlan_insertion(m)) {
5547 ctrl1 |= F_TXPKT_VLAN_VLD |
5548 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5549 txq->vlan_insertion++;
5553 cpl->ctrl0 = txq->cpl_ctrl0;
5555 cpl->len = htobe16(m->m_pkthdr.len);
5556 cpl->ctrl1 = htobe64(ctrl1);
5559 MPASS(mbuf_nsegs(m) == 1);
5560 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0);
5563 last->m_nextpkt = m;
5568 txq->txpkts1_pkts += txp->npkt;
5571 txsd = &txq->sdesc[eq->pidx];
5572 txsd->m = txp->mb[0];
5573 txsd->desc_used = ndesc;
5579 * If the SGL ends on an address that is not 16 byte aligned, this function will
5580 * add a 0 filled flit at the end.
5583 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
5585 struct sge_eq *eq = &txq->eq;
5586 struct sglist *gl = txq->gl;
5587 struct sglist_seg *seg;
5588 __be64 *flitp, *wrap;
5589 struct ulptx_sgl *usgl;
5590 int i, nflits, nsegs;
5592 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
5593 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
5594 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5595 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5598 nsegs = gl->sg_nseg;
5601 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
5602 flitp = (__be64 *)(*to);
5603 wrap = (__be64 *)(&eq->desc[eq->sidx]);
5604 seg = &gl->sg_segs[0];
5605 usgl = (void *)flitp;
5608 * We start at a 16 byte boundary somewhere inside the tx descriptor
5609 * ring, so we're at least 16 bytes away from the status page. There is
5610 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
5613 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
5614 V_ULPTX_NSGE(nsegs));
5615 usgl->len0 = htobe32(seg->ss_len);
5616 usgl->addr0 = htobe64(seg->ss_paddr);
5619 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
5621 /* Won't wrap around at all */
5623 for (i = 0; i < nsegs - 1; i++, seg++) {
5624 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
5625 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
5628 usgl->sge[i / 2].len[1] = htobe32(0);
5632 /* Will wrap somewhere in the rest of the SGL */
5634 /* 2 flits already written, write the rest flit by flit */
5635 flitp = (void *)(usgl + 1);
5636 for (i = 0; i < nflits - 2; i++) {
5638 flitp = (void *)eq->desc;
5639 *flitp++ = get_flit(seg, nsegs - 1, i);
5644 MPASS(((uintptr_t)flitp) & 0xf);
5648 MPASS((((uintptr_t)flitp) & 0xf) == 0);
5649 if (__predict_false(flitp == wrap))
5650 *to = (void *)eq->desc;
5652 *to = (void *)flitp;
5656 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
5659 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
5660 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
5662 if (__predict_true((uintptr_t)(*to) + len <=
5663 (uintptr_t)&eq->desc[eq->sidx])) {
5664 bcopy(from, *to, len);
5667 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
5669 bcopy(from, *to, portion);
5671 portion = len - portion; /* remaining */
5672 bcopy(from, (void *)eq->desc, portion);
5673 (*to) = (caddr_t)eq->desc + portion;
5678 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
5686 clrbit(&db, DOORBELL_WCWR);
5689 switch (ffs(db) - 1) {
5691 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5694 case DOORBELL_WCWR: {
5695 volatile uint64_t *dst, *src;
5699 * Queues whose 128B doorbell segment fits in the page do not
5700 * use relative qid (udb_qid is always 0). Only queues with
5701 * doorbell segments can do WCWR.
5703 KASSERT(eq->udb_qid == 0 && n == 1,
5704 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
5705 __func__, eq->doorbells, n, eq->dbidx, eq));
5707 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
5710 src = (void *)&eq->desc[i];
5711 while (src != (void *)&eq->desc[i + 1])
5717 case DOORBELL_UDBWC:
5718 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
5723 t4_write_reg(sc, sc->sge_kdoorbell_reg,
5724 V_QID(eq->cntxt_id) | V_PIDX(n));
5728 IDXINCR(eq->dbidx, n, eq->sidx);
5732 reclaimable_tx_desc(struct sge_eq *eq)
5736 hw_cidx = read_hw_cidx(eq);
5737 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
5741 total_available_tx_desc(struct sge_eq *eq)
5743 uint16_t hw_cidx, pidx;
5745 hw_cidx = read_hw_cidx(eq);
5748 if (pidx == hw_cidx)
5749 return (eq->sidx - 1);
5751 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
5754 static inline uint16_t
5755 read_hw_cidx(struct sge_eq *eq)
5757 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
5758 uint16_t cidx = spg->cidx; /* stable snapshot */
5760 return (be16toh(cidx));
5764 * Reclaim 'n' descriptors approximately.
5767 reclaim_tx_descs(struct sge_txq *txq, u_int n)
5769 struct tx_sdesc *txsd;
5770 struct sge_eq *eq = &txq->eq;
5771 u_int can_reclaim, reclaimed;
5773 TXQ_LOCK_ASSERT_OWNED(txq);
5777 can_reclaim = reclaimable_tx_desc(eq);
5778 while (can_reclaim && reclaimed < n) {
5780 struct mbuf *m, *nextpkt;
5782 txsd = &txq->sdesc[eq->cidx];
5783 ndesc = txsd->desc_used;
5785 /* Firmware doesn't return "partial" credits. */
5786 KASSERT(can_reclaim >= ndesc,
5787 ("%s: unexpected number of credits: %d, %d",
5788 __func__, can_reclaim, ndesc));
5790 ("%s: descriptor with no credits: cidx %d",
5791 __func__, eq->cidx));
5793 for (m = txsd->m; m != NULL; m = nextpkt) {
5794 nextpkt = m->m_nextpkt;
5795 m->m_nextpkt = NULL;
5799 can_reclaim -= ndesc;
5800 IDXINCR(eq->cidx, ndesc, eq->sidx);
5807 tx_reclaim(void *arg, int n)
5809 struct sge_txq *txq = arg;
5810 struct sge_eq *eq = &txq->eq;
5813 if (TXQ_TRYLOCK(txq) == 0)
5815 n = reclaim_tx_descs(txq, 32);
5816 if (eq->cidx == eq->pidx)
5817 eq->equeqidx = eq->pidx;
5823 get_flit(struct sglist_seg *segs, int nsegs, int idx)
5825 int i = (idx / 3) * 2;
5831 rc = (uint64_t)segs[i].ss_len << 32;
5833 rc |= (uint64_t)(segs[i + 1].ss_len);
5835 return (htobe64(rc));
5838 return (htobe64(segs[i].ss_paddr));
5840 return (htobe64(segs[i + 1].ss_paddr));
5847 find_refill_source(struct adapter *sc, int maxp, bool packing)
5850 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
5853 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
5854 if (rxb->hwidx2 == -1)
5856 if (rxb->size1 < PAGE_SIZE &&
5857 rxb->size1 < largest_rx_cluster)
5859 if (rxb->size1 > largest_rx_cluster)
5861 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
5862 if (rxb->size2 >= maxp)
5867 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
5868 if (rxb->hwidx1 == -1)
5870 if (rxb->size1 > largest_rx_cluster)
5872 if (rxb->size1 >= maxp)
5882 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
5884 mtx_lock(&sc->sfl_lock);
5886 if ((fl->flags & FL_DOOMED) == 0) {
5887 fl->flags |= FL_STARVING;
5888 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
5889 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
5892 mtx_unlock(&sc->sfl_lock);
5896 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
5898 struct sge_wrq *wrq = (void *)eq;
5900 atomic_readandclear_int(&eq->equiq);
5901 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
5905 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
5907 struct sge_txq *txq = (void *)eq;
5909 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
5911 atomic_readandclear_int(&eq->equiq);
5912 if (mp_ring_is_idle(txq->r))
5913 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
5915 mp_ring_check_drainage(txq->r, 64);
5919 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
5922 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
5923 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
5924 struct adapter *sc = iq->adapter;
5925 struct sge *s = &sc->sge;
5927 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
5928 &handle_wrq_egr_update, &handle_eth_egr_update,
5929 &handle_wrq_egr_update};
5931 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5934 eq = s->eqmap[qid - s->eq_start - s->eq_base];
5935 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
5940 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
5941 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
5942 offsetof(struct cpl_fw6_msg, data));
5945 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
5947 struct adapter *sc = iq->adapter;
5948 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
5950 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
5953 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
5954 const struct rss_header *rss2;
5956 rss2 = (const struct rss_header *)&cpl->data[0];
5957 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
5960 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
5964 * t4_handle_wrerr_rpl - process a FW work request error message
5965 * @adap: the adapter
5966 * @rpl: start of the FW message
5969 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
5971 u8 opcode = *(const u8 *)rpl;
5972 const struct fw_error_cmd *e = (const void *)rpl;
5975 if (opcode != FW_ERROR_CMD) {
5977 "%s: Received WRERR_RPL message with opcode %#x\n",
5978 device_get_nameunit(adap->dev), opcode);
5981 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
5982 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
5984 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
5985 case FW_ERROR_TYPE_EXCEPTION:
5986 log(LOG_ERR, "exception info:\n");
5987 for (i = 0; i < nitems(e->u.exception.info); i++)
5988 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
5989 be32toh(e->u.exception.info[i]));
5992 case FW_ERROR_TYPE_HWMODULE:
5993 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
5994 be32toh(e->u.hwmodule.regaddr),
5995 be32toh(e->u.hwmodule.regval));
5997 case FW_ERROR_TYPE_WR:
5998 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
5999 be16toh(e->u.wr.cidx),
6000 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
6001 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
6002 be32toh(e->u.wr.eqid));
6003 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
6004 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
6008 case FW_ERROR_TYPE_ACL:
6009 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
6010 be16toh(e->u.acl.cidx),
6011 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
6012 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
6013 be32toh(e->u.acl.eqid),
6014 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
6016 for (i = 0; i < nitems(e->u.acl.val); i++)
6017 log(LOG_ERR, " %02x", e->u.acl.val[i]);
6021 log(LOG_ERR, "type %#x\n",
6022 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
6029 bufidx_used(struct adapter *sc, int idx)
6031 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6034 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6035 if (rxb->size1 > largest_rx_cluster)
6037 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
6045 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
6047 struct adapter *sc = arg1;
6048 struct sge_params *sp = &sc->params.sge;
6053 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
6054 for (i = 0; i < SGE_FLBUF_SIZES; i++) {
6055 if (bufidx_used(sc, i))
6060 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
6064 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
6071 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
6074 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
6080 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
6081 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
6082 if (__predict_false(nsegs == 0))
6085 nsegs--; /* first segment is part of ulptx_sgl */
6086 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
6088 n += sizeof(struct cpl_tx_pkt_lso_core);
6091 return (howmany(n, 16));
6094 #define ETID_FLOWC_NPARAMS 6
6095 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
6096 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
6097 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
6100 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
6103 struct wrq_cookie cookie;
6104 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
6105 struct fw_flowc_wr *flowc;
6107 mtx_assert(&cst->lock, MA_OWNED);
6108 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
6111 flowc = start_wrq_wr(cst->eo_txq, ETID_FLOWC_LEN16, &cookie);
6112 if (__predict_false(flowc == NULL))
6115 bzero(flowc, ETID_FLOWC_LEN);
6116 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6117 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
6118 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
6119 V_FW_WR_FLOWID(cst->etid));
6120 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
6121 flowc->mnemval[0].val = htobe32(pfvf);
6122 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
6123 flowc->mnemval[1].val = htobe32(pi->tx_chan);
6124 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
6125 flowc->mnemval[2].val = htobe32(pi->tx_chan);
6126 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
6127 flowc->mnemval[3].val = htobe32(cst->iqid);
6128 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
6129 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
6130 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
6131 flowc->mnemval[5].val = htobe32(cst->schedcl);
6133 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
6135 cst->flags &= ~EO_FLOWC_PENDING;
6136 cst->flags |= EO_FLOWC_RPL_PENDING;
6137 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
6138 cst->tx_credits -= ETID_FLOWC_LEN16;
6143 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
6146 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
6148 struct fw_flowc_wr *flowc;
6149 struct wrq_cookie cookie;
6151 mtx_assert(&cst->lock, MA_OWNED);
6153 flowc = start_wrq_wr(cst->eo_txq, ETID_FLUSH_LEN16, &cookie);
6154 if (__predict_false(flowc == NULL))
6155 CXGBE_UNIMPLEMENTED(__func__);
6157 bzero(flowc, ETID_FLUSH_LEN16 * 16);
6158 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6159 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
6160 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
6161 V_FW_WR_FLOWID(cst->etid));
6163 commit_wrq_wr(cst->eo_txq, flowc, &cookie);
6165 cst->flags |= EO_FLUSH_RPL_PENDING;
6166 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
6167 cst->tx_credits -= ETID_FLUSH_LEN16;
6172 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
6173 struct mbuf *m0, int compl)
6175 struct cpl_tx_pkt_core *cpl;
6177 uint32_t ctrl; /* used in many unrelated places */
6178 int len16, pktlen, nsegs, immhdrs;
6181 struct ulptx_sgl *usgl;
6183 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
6185 mtx_assert(&cst->lock, MA_OWNED);
6187 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
6188 m0->m_pkthdr.l4hlen > 0,
6189 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
6191 len16 = mbuf_eo_len16(m0);
6192 nsegs = mbuf_eo_nsegs(m0);
6193 pktlen = m0->m_pkthdr.len;
6194 ctrl = sizeof(struct cpl_tx_pkt_core);
6196 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
6197 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
6200 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
6201 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
6202 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
6203 V_FW_WR_FLOWID(cst->etid));
6205 if (needs_outer_udp_csum(m0)) {
6206 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
6207 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
6208 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6209 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
6210 wr->u.udpseg.rtplen = 0;
6211 wr->u.udpseg.r4 = 0;
6212 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
6213 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
6214 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
6215 cpl = (void *)(wr + 1);
6217 MPASS(needs_outer_tcp_csum(m0));
6218 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
6219 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
6220 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6221 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
6222 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
6223 wr->u.tcpseg.r4 = 0;
6224 wr->u.tcpseg.r5 = 0;
6225 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
6227 if (needs_tso(m0)) {
6228 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
6230 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
6232 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
6233 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
6234 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
6235 ETHER_HDR_LEN) >> 2) |
6236 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
6237 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
6238 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
6240 lso->lso_ctrl = htobe32(ctrl);
6241 lso->ipid_ofst = htobe16(0);
6242 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
6243 lso->seqno_offset = htobe32(0);
6244 lso->len = htobe32(pktlen);
6246 cpl = (void *)(lso + 1);
6248 wr->u.tcpseg.mss = htobe16(0xffff);
6249 cpl = (void *)(wr + 1);
6253 /* Checksum offload must be requested for ethofld. */
6254 MPASS(needs_outer_l4_csum(m0));
6255 ctrl1 = csum_to_ctrl(cst->adapter, m0);
6257 /* VLAN tag insertion */
6258 if (needs_vlan_insertion(m0)) {
6259 ctrl1 |= F_TXPKT_VLAN_VLD |
6260 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
6264 cpl->ctrl0 = cst->ctrl0;
6266 cpl->len = htobe16(pktlen);
6267 cpl->ctrl1 = htobe64(ctrl1);
6269 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
6270 p = (uintptr_t)(cpl + 1);
6271 m_copydata(m0, 0, immhdrs, (void *)p);
6274 dst = (void *)(cpl + 1);
6278 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
6280 pad = 16 - (immhdrs & 0xf);
6281 bzero((void *)p, pad);
6283 usgl = (void *)(p + pad);
6284 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6285 V_ULPTX_NSGE(nsegs));
6287 sglist_init(&sg, nitems(segs), segs);
6288 for (; m0 != NULL; m0 = m0->m_next) {
6289 if (__predict_false(m0->m_len == 0))
6291 if (immhdrs >= m0->m_len) {
6292 immhdrs -= m0->m_len;
6295 if (m0->m_flags & M_EXTPG)
6296 sglist_append_mbuf_epg(&sg, m0,
6297 mtod(m0, vm_offset_t), m0->m_len);
6299 sglist_append(&sg, mtod(m0, char *) + immhdrs,
6300 m0->m_len - immhdrs);
6303 MPASS(sg.sg_nseg == nsegs);
6306 * Zero pad last 8B in case the WR doesn't end on a 16B
6309 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6311 usgl->len0 = htobe32(segs[0].ss_len);
6312 usgl->addr0 = htobe64(segs[0].ss_paddr);
6313 for (i = 0; i < nsegs - 1; i++) {
6314 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6315 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6318 usgl->sge[i / 2].len[1] = htobe32(0);
6324 ethofld_tx(struct cxgbe_rate_tag *cst)
6327 struct wrq_cookie cookie;
6328 int next_credits, compl;
6329 struct fw_eth_tx_eo_wr *wr;
6331 mtx_assert(&cst->lock, MA_OWNED);
6333 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6336 /* How many len16 credits do we need to send this mbuf. */
6337 next_credits = mbuf_eo_len16(m);
6338 MPASS(next_credits > 0);
6339 if (next_credits > cst->tx_credits) {
6341 * Tx will make progress eventually because there is at
6342 * least one outstanding fw4_ack that will return
6343 * credits and kick the tx.
6345 MPASS(cst->ncompl > 0);
6348 wr = start_wrq_wr(cst->eo_txq, next_credits, &cookie);
6349 if (__predict_false(wr == NULL)) {
6350 /* XXX: wishful thinking, not a real assertion. */
6351 MPASS(cst->ncompl > 0);
6354 cst->tx_credits -= next_credits;
6355 cst->tx_nocompl += next_credits;
6356 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6357 ETHER_BPF_MTAP(cst->com.ifp, m);
6358 write_ethofld_wr(cst, wr, m, compl);
6359 commit_wrq_wr(cst->eo_txq, wr, &cookie);
6362 cst->tx_nocompl = 0;
6364 (void) mbufq_dequeue(&cst->pending_tx);
6367 * Drop the mbuf's reference on the tag now rather
6368 * than waiting until m_freem(). This ensures that
6369 * cxgbe_rate_tag_free gets called when the inp drops
6370 * its reference on the tag and there are no more
6371 * mbufs in the pending_tx queue and can flush any
6372 * pending requests. Otherwise if the last mbuf
6373 * doesn't request a completion the etid will never be
6376 m->m_pkthdr.snd_tag = NULL;
6377 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6378 m_snd_tag_rele(&cst->com);
6380 mbufq_enqueue(&cst->pending_fwack, m);
6385 ethofld_transmit(struct ifnet *ifp, struct mbuf *m0)
6387 struct cxgbe_rate_tag *cst;
6390 MPASS(m0->m_nextpkt == NULL);
6391 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6392 MPASS(m0->m_pkthdr.snd_tag != NULL);
6393 cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6395 mtx_lock(&cst->lock);
6396 MPASS(cst->flags & EO_SND_TAG_REF);
6398 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6399 struct vi_info *vi = ifp->if_softc;
6400 struct port_info *pi = vi->pi;
6401 struct adapter *sc = pi->adapter;
6402 const uint32_t rss_mask = vi->rss_size - 1;
6405 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6406 if (M_HASHTYPE_ISHASH(m0))
6407 rss_hash = m0->m_pkthdr.flowid;
6409 rss_hash = arc4random();
6410 /* We assume RSS hashing */
6411 cst->iqid = vi->rss[rss_hash & rss_mask];
6412 cst->eo_txq += rss_hash % vi->nofldtxq;
6413 rc = send_etid_flowc_wr(cst, pi, vi);
6418 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6423 mbufq_enqueue(&cst->pending_tx, m0);
6424 cst->plen += m0->m_pkthdr.len;
6427 * Hold an extra reference on the tag while generating work
6428 * requests to ensure that we don't try to free the tag during
6429 * ethofld_tx() in case we are sending the final mbuf after
6430 * the inp was freed.
6432 m_snd_tag_ref(&cst->com);
6434 mtx_unlock(&cst->lock);
6435 m_snd_tag_rele(&cst->com);
6439 mtx_unlock(&cst->lock);
6440 if (__predict_false(rc != 0))
6446 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6448 struct adapter *sc = iq->adapter;
6449 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6451 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6452 struct cxgbe_rate_tag *cst;
6453 uint8_t credits = cpl->credits;
6455 cst = lookup_etid(sc, etid);
6456 mtx_lock(&cst->lock);
6457 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6458 MPASS(credits >= ETID_FLOWC_LEN16);
6459 credits -= ETID_FLOWC_LEN16;
6460 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6463 KASSERT(cst->ncompl > 0,
6464 ("%s: etid %u (%p) wasn't expecting completion.",
6465 __func__, etid, cst));
6468 while (credits > 0) {
6469 m = mbufq_dequeue(&cst->pending_fwack);
6470 if (__predict_false(m == NULL)) {
6472 * The remaining credits are for the final flush that
6473 * was issued when the tag was freed by the kernel.
6476 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6477 EO_FLUSH_RPL_PENDING);
6478 MPASS(credits == ETID_FLUSH_LEN16);
6479 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6480 MPASS(cst->ncompl == 0);
6482 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6483 cst->tx_credits += cpl->credits;
6484 cxgbe_rate_tag_free_locked(cst);
6485 return (0); /* cst is gone. */
6488 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6490 KASSERT(credits >= mbuf_eo_len16(m),
6491 ("%s: too few credits (%u, %u, %u)", __func__,
6492 cpl->credits, credits, mbuf_eo_len16(m)));
6493 credits -= mbuf_eo_len16(m);
6494 cst->plen -= m->m_pkthdr.len;
6498 cst->tx_credits += cpl->credits;
6499 MPASS(cst->tx_credits <= cst->tx_total);
6501 if (cst->flags & EO_SND_TAG_REF) {
6503 * As with ethofld_transmit(), hold an extra reference
6504 * so that the tag is stable across ethold_tx().
6506 m_snd_tag_ref(&cst->com);
6507 m = mbufq_first(&cst->pending_tx);
6508 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6510 mtx_unlock(&cst->lock);
6511 m_snd_tag_rele(&cst->com);
6514 * There shouldn't be any pending packets if the tag
6515 * was freed by the kernel since any pending packet
6516 * should hold a reference to the tag.
6518 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6519 mtx_unlock(&cst->lock);