2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
30 #include "opt_inet6.h"
32 #include <sys/param.h>
33 #include <sys/eventhandler.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/rwlock.h>
41 #include <sys/socket.h>
43 #include <netinet/in.h>
45 #include "common/common.h"
46 #include "common/t4_msg.h"
50 * Module locking notes: There is a RW lock protecting the SMAC table as a
51 * whole plus a spinlock per SMT entry. Entry lookups and allocations happen
52 * under the protection of the table lock, individual entry changes happen
53 * while holding that entry's spinlock. The table lock nests outside the
54 * entry locks. Allocations of new entries take the table lock as writers so
55 * no other lookups can happen while allocating new entries. Entry updates
56 * take the table lock as readers so multiple entries can be updated in
57 * parallel. An SMT entry can be dropped by decrementing its reference count
58 * and therefore can happen in parallel with entry allocation but no entry
59 * can change state or increment its ref count during allocation as both of
60 * these perform lookups.
62 * Note: We do not take references to ifnets in this module because both
63 * the TOE and the sockets already hold references to the interfaces and the
64 * lifetime of an SMT entry is fully contained in the lifetime of the TOE.
68 * Allocate a free SMT entry. Must be called with smt_data.lock held.
71 t4_find_or_alloc_sme(struct smt_data *s, uint8_t *smac)
73 struct smt_entry *end, *e;
74 struct smt_entry *first_free = NULL;
76 rw_assert(&s->lock, RA_WLOCKED);
77 for (e = &s->smtab[0], end = &s->smtab[s->smt_size]; e != end; ++e) {
78 if (atomic_load_acq_int(&e->refcnt) == 0) {
82 if (e->state == SMT_STATE_SWITCHING) {
84 * This entry is actually in use. See if we can
87 if (memcmp(e->smac, smac, ETHER_ADDR_LEN) == 0)
99 e->state = SMT_STATE_UNUSED;
101 atomic_add_int(&e->refcnt, 1);
106 * Write an SMT entry. Must be called with the entry locked.
109 t4_write_sme(struct smt_entry *e)
114 struct wrq_cookie cookie;
115 struct cpl_smt_write_req *req;
116 struct cpl_t6_smt_write_req *t6req;
119 mtx_assert(&e->lock, MA_OWNED);
121 MPASS(e->wrq != NULL);
124 MPASS(wrq->adapter != NULL);
128 if (chip_id(sc) <= CHELSIO_T5) {
129 /* Source MAC Table (SMT) contains 256 SMAC entries
130 * organized in 128 rows of 2 entries each.
132 req = start_wrq_wr(wrq, howmany(sizeof(*req), 16), &cookie);
136 /* Each row contains an SMAC pair.
137 * LSB selects the SMAC entry within a row
142 memcpy(req->src_mac1, e->smac, ETHER_ADDR_LEN);
143 /* fill pfvf0/src_mac0 with entry
144 * at prev index from smt-tab.
147 memcpy(req->src_mac0, s->smtab[e->idx - 1].smac,
151 memcpy(req->src_mac0, e->smac, ETHER_ADDR_LEN);
152 /* fill pfvf1/src_mac1 with entry
153 * at next index from smt-tab
156 memcpy(req->src_mac1, s->smtab[e->idx + 1].smac,
160 /* Source MAC Table (SMT) contains 256 SMAC entries */
161 t6req = start_wrq_wr(wrq, howmany(sizeof(*t6req), 16), &cookie);
164 INIT_TP_WR(t6req, 0);
165 req = (struct cpl_smt_write_req *)t6req;
167 /* fill pfvf0/src_mac0 from smt-tab */
169 memcpy(req->src_mac0, s->smtab[e->idx].smac, ETHER_ADDR_LEN);
172 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, e->idx |
173 V_TID_QID(e->iqid)));
174 req->params = htonl(V_SMTW_NORPL(0) |
176 V_SMTW_OVLAN_IDX(0));
178 commit_wrq_wr(wrq, req, &cookie);
184 * Allocate an SMT entry for use by a switching rule.
187 t4_smt_alloc_switching(struct smt_data *s, uint8_t *smac)
193 e = t4_find_or_alloc_sme(s, smac);
194 rw_wunlock(&s->lock);
199 * Sets/updates the contents of a switching SMT entry that has been allocated
200 * with an earlier call to @t4_smt_alloc_switching.
203 t4_smt_set_switching(struct adapter *sc, struct smt_entry *e, uint16_t pfvf,
208 if (atomic_load_acq_int(&e->refcnt) == 1) {
209 /* Setup the entry for the first time */
211 e->wrq = &sc->sge.ctrlq[0];
212 e->iqid = sc->sge.fwq.abs_id;
214 e->state = SMT_STATE_SWITCHING;
215 memcpy(e->smac, smac, ETHER_ADDR_LEN);
216 rc = t4_write_sme(e);
217 mtx_unlock(&e->lock);
224 t4_init_smt(struct adapter *sc, int flags)
230 s = malloc(sizeof(*s) + smt_size * sizeof (struct smt_entry), M_CXGBE,
235 s->smt_size = smt_size;
236 rw_init(&s->lock, "SMT");
238 for (i = 0; i < smt_size; i++) {
239 struct smt_entry *e = &s->smtab[i];
242 e->state = SMT_STATE_UNUSED;
243 mtx_init(&e->lock, "SMT_E", NULL, MTX_DEF);
244 atomic_store_rel_int(&e->refcnt, 0);
253 t4_free_smt(struct smt_data *s)
257 for (i = 0; i < s->smt_size; i++)
258 mtx_destroy(&s->smtab[i].lock);
259 rw_destroy(&s->lock);
266 do_smt_write_rpl(struct sge_iq *iq, const struct rss_header *rss,
269 struct adapter *sc = iq->adapter;
270 const struct cpl_smt_write_rpl *rpl = (const void *)(rss + 1);
271 unsigned int tid = GET_TID(rpl);
272 unsigned int smtidx = G_TID_TID(tid);
274 if (__predict_false(rpl->status != CPL_ERR_NONE)) {
275 struct smt_entry *e = &sc->smt->smtab[smtidx];
277 "Unexpected SMT_WRITE_RPL (%u) for entry at hw_idx %u\n",
278 rpl->status, smtidx);
280 e->state = SMT_STATE_ERROR;
281 mtx_unlock(&e->lock);
289 smt_state(const struct smt_entry *e)
292 case SMT_STATE_SWITCHING: return 'X';
293 case SMT_STATE_ERROR: return 'E';
299 sysctl_smt(SYSCTL_HANDLER_ARGS)
301 struct adapter *sc = arg1;
302 struct smt_data *smt = sc->smt;
305 int rc, i, header = 0;
310 rc = sysctl_wire_old_buffer(req, 0);
314 sb = sbuf_new_for_sysctl(NULL, NULL, SMT_SIZE, req);
319 for (i = 0; i < smt->smt_size; i++, e++) {
321 if (e->state == SMT_STATE_UNUSED)
325 sbuf_printf(sb, " Idx "
326 "Ethernet address State Users");
329 sbuf_printf(sb, "\n%4u %02x:%02x:%02x:%02x:%02x:%02x "
331 e->idx, e->smac[0], e->smac[1], e->smac[2],
332 e->smac[3], e->smac[4], e->smac[5],
333 smt_state(e), atomic_load_acq_int(&e->refcnt));
335 mtx_unlock(&e->lock);
338 rc = sbuf_finish(sb);