2 * Copyright (c) 2016 Chelsio Communications, Inc.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
40 #include <dev/pci/pcivar.h>
41 #if defined(__i386__) || defined(__amd64__)
46 #include "common/common.h"
47 #include "common/t4_regs.h"
49 #include "t4_mp_ring.h"
54 * The Virtual Interfaces are connected to an internal switch on the chip
55 * which allows VIs attached to the same port to talk to each other even when
56 * the port link is down. As a result, we might want to always report a
57 * VF's link as being "up".
59 * XXX: Add a TUNABLE and possible per-device sysctl for this?
62 struct intrs_and_queues {
63 uint16_t intr_type; /* MSI, or MSI-X */
64 uint16_t nirq; /* Total # of vectors */
65 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
66 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
67 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
68 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
69 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
70 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
77 {0x4800, "Chelsio T440-dbg VF"},
78 {0x4801, "Chelsio T420-CR VF"},
79 {0x4802, "Chelsio T422-CR VF"},
80 {0x4803, "Chelsio T440-CR VF"},
81 {0x4804, "Chelsio T420-BCH VF"},
82 {0x4805, "Chelsio T440-BCH VF"},
83 {0x4806, "Chelsio T440-CH VF"},
84 {0x4807, "Chelsio T420-SO VF"},
85 {0x4808, "Chelsio T420-CX VF"},
86 {0x4809, "Chelsio T420-BT VF"},
87 {0x480a, "Chelsio T404-BT VF"},
88 {0x480e, "Chelsio T440-LP-CR VF"},
90 {0x5800, "Chelsio T580-dbg VF"},
91 {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */
92 {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */
93 {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */
94 {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */
95 {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */
96 {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */
97 {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */
98 {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */
99 {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */
100 {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */
101 {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */
102 {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */
103 {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */
105 {0x5804, "Chelsio T520-BCH VF"},
106 {0x5805, "Chelsio T540-BCH VF"},
107 {0x5806, "Chelsio T540-CH VF"},
108 {0x5808, "Chelsio T520-CX VF"},
109 {0x580b, "Chelsio B520-SR VF"},
110 {0x580c, "Chelsio B504-BT VF"},
111 {0x580f, "Chelsio Amsterdam VF"},
112 {0x5813, "Chelsio T580-CHR VF"},
115 {0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */
116 {0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */
117 {0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */
118 {0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */
119 {0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */
122 static d_ioctl_t t4vf_ioctl;
124 static struct cdevsw t4vf_cdevsw = {
125 .d_version = D_VERSION,
126 .d_ioctl = t4vf_ioctl,
131 t4vf_probe(device_t dev)
136 d = pci_get_device(dev);
137 for (i = 0; i < nitems(t4vf_pciids); i++) {
138 if (d == t4vf_pciids[i].device) {
139 device_set_desc(dev, t4vf_pciids[i].desc);
140 return (BUS_PROBE_DEFAULT);
147 t5vf_probe(device_t dev)
152 d = pci_get_device(dev);
153 for (i = 0; i < nitems(t5vf_pciids); i++) {
154 if (d == t5vf_pciids[i].device) {
155 device_set_desc(dev, t5vf_pciids[i].desc);
156 return (BUS_PROBE_DEFAULT);
163 t6vf_probe(device_t dev)
168 d = pci_get_device(dev);
169 for (i = 0; i < nitems(t6vf_pciids); i++) {
170 if (d == t6vf_pciids[i].device) {
171 device_set_desc(dev, t6vf_pciids[i].desc);
172 return (BUS_PROBE_DEFAULT);
178 #define FW_PARAM_DEV(param) \
179 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
180 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
181 #define FW_PARAM_PFVF(param) \
182 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
183 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
186 get_params__pre_init(struct adapter *sc)
189 uint32_t param[3], val[3];
191 param[0] = FW_PARAM_DEV(FWREV);
192 param[1] = FW_PARAM_DEV(TPREV);
193 param[2] = FW_PARAM_DEV(CCLK);
194 rc = -t4vf_query_params(sc, nitems(param), param, val);
196 device_printf(sc->dev,
197 "failed to query parameters (pre_init): %d.\n", rc);
201 sc->params.fw_vers = val[0];
202 sc->params.tp_vers = val[1];
203 sc->params.vpd.cclk = val[2];
205 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
206 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
207 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
208 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
209 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
211 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
212 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
213 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
214 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
215 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
221 get_params__post_init(struct adapter *sc)
225 rc = -t4vf_get_sge_params(sc);
227 device_printf(sc->dev,
228 "unable to retrieve adapter SGE parameters: %d\n", rc);
232 rc = -t4vf_get_rss_glb_config(sc);
234 device_printf(sc->dev,
235 "unable to retrieve adapter RSS parameters: %d\n", rc);
238 if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
239 device_printf(sc->dev,
240 "unable to operate with global RSS mode %d\n",
241 sc->params.rss.mode);
245 rc = t4_read_chip_settings(sc);
250 * Grab our Virtual Interface resource allocation, extract the
251 * features that we're interested in and do a bit of sanity testing on
254 rc = -t4vf_get_vfres(sc);
256 device_printf(sc->dev,
257 "unable to get virtual interface resources: %d\n", rc);
262 * Check for various parameter sanity issues.
264 if (sc->params.vfres.pmask == 0) {
265 device_printf(sc->dev, "no port access configured/usable!\n");
268 if (sc->params.vfres.nvi == 0) {
269 device_printf(sc->dev,
270 "no virtual interfaces configured/usable!\n");
273 sc->params.portvec = sc->params.vfres.pmask;
279 set_params__post_init(struct adapter *sc)
283 /* ask for encapsulated CPLs */
284 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
286 (void)t4vf_set_params(sc, 1, ¶m, &val);
295 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
296 struct intrs_and_queues *iaq)
298 struct vf_resources *vfres;
299 int nrxq10g, nrxq1g, nrxq;
300 int ntxq10g, ntxq1g, ntxq;
301 int itype, iq_avail, navail, rc;
304 * Figure out the layout of queues across our VIs and ensure
305 * we can allocate enough interrupts for our layout.
307 vfres = &sc->params.vfres;
308 bzero(iaq, sizeof(*iaq));
310 for (itype = INTR_MSIX; itype != 0; itype >>= 1) {
311 if (itype == INTR_INTX)
314 if (itype == INTR_MSIX)
315 navail = pci_msix_count(sc->dev);
317 navail = pci_msi_count(sc->dev);
322 iaq->intr_type = itype;
323 iaq->intr_flags_10g = 0;
324 iaq->intr_flags_1g = 0;
327 * XXX: The Linux driver reserves an Ingress Queue for
328 * forwarded interrupts when using MSI (but not MSI-X).
329 * It seems it just always asks for 2 interrupts and
330 * forwards all rxqs to the forwarded interrupt.
332 * We must reserve one IRQ for the for the firmware
335 * Every rxq requires an ingress queue with a free
336 * list and interrupts and an egress queue. Every txq
337 * requires an ETH egress queue.
339 iaq->nirq = T4VF_EXTRA_INTR;
342 * First, determine how many queues we can allocate.
343 * Start by finding the upper bound on rxqs from the
344 * limit on ingress queues.
346 iq_avail = vfres->niqflint - iaq->nirq;
347 if (iq_avail < n10g + n1g) {
348 device_printf(sc->dev,
349 "Not enough ingress queues (%d) for %d ports\n",
350 vfres->niqflint, n10g + n1g);
355 * Try to honor the cap on interrupts. If there aren't
356 * enough interrupts for at least one interrupt per
357 * port, then don't bother, we will just forward all
358 * interrupts to one interrupt in that case.
360 if (iaq->nirq + n10g + n1g <= navail) {
361 if (iq_avail > navail - iaq->nirq)
362 iq_avail = navail - iaq->nirq;
365 nrxq10g = t4_nrxq10g;
367 nrxq = n10g * nrxq10g + n1g * nrxq1g;
368 if (nrxq > iq_avail && nrxq1g > 1) {
369 /* Too many ingress queues. Try just 1 for 1G. */
371 nrxq = n10g * nrxq10g + n1g * nrxq1g;
373 if (nrxq > iq_avail) {
375 * Still too many ingress queues. Use what we
376 * can for each 10G port.
378 nrxq10g = (iq_avail - n1g) / n10g;
379 nrxq = n10g * nrxq10g + n1g * nrxq1g;
381 KASSERT(nrxq <= iq_avail, ("too many ingress queues"));
384 * Next, determine the upper bound on txqs from the limit
387 if (vfres->nethctrl < n10g + n1g) {
388 device_printf(sc->dev,
389 "Not enough ETH queues (%d) for %d ports\n",
390 vfres->nethctrl, n10g + n1g);
394 ntxq10g = t4_ntxq10g;
396 ntxq = n10g * ntxq10g + n1g * ntxq1g;
397 if (ntxq > vfres->nethctrl) {
398 /* Too many ETH queues. Try just 1 for 1G. */
400 ntxq = n10g * ntxq10g + n1g * ntxq1g;
402 if (ntxq > vfres->nethctrl) {
404 * Still too many ETH queues. Use what we
405 * can for each 10G port.
407 ntxq10g = (vfres->nethctrl - n1g) / n10g;
408 ntxq = n10g * ntxq10g + n1g * ntxq1g;
410 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
413 * Finally, ensure we have enough egress queues.
415 if (vfres->neq < (n10g + n1g) * 2) {
416 device_printf(sc->dev,
417 "Not enough egress queues (%d) for %d ports\n",
418 vfres->neq, n10g + n1g);
421 if (nrxq + ntxq > vfres->neq) {
422 /* Just punt and use 1 for everything. */
423 nrxq1g = ntxq1g = nrxq10g = ntxq10g = 1;
424 nrxq = n10g * nrxq10g + n1g * nrxq1g;
425 ntxq = n10g * ntxq10g + n1g * ntxq1g;
427 KASSERT(nrxq <= iq_avail, ("too many ingress queues"));
428 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
429 KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues"));
432 * Do we have enough interrupts? For MSI the interrupts
433 * have to be a power of 2 as well.
436 iaq->ntxq10g = ntxq10g;
437 iaq->ntxq1g = ntxq1g;
438 iaq->nrxq10g = nrxq10g;
439 iaq->nrxq1g = nrxq1g;
440 if (iaq->nirq <= navail &&
441 (itype != INTR_MSI || powerof2(iaq->nirq))) {
443 if (itype == INTR_MSIX)
444 rc = pci_alloc_msix(sc->dev, &navail);
446 rc = pci_alloc_msi(sc->dev, &navail);
448 device_printf(sc->dev,
449 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
450 itype, rc, iaq->nirq, navail);
453 if (navail == iaq->nirq) {
454 iaq->intr_flags_10g = INTR_RXQ;
455 iaq->intr_flags_1g = INTR_RXQ;
458 pci_release_msi(sc->dev);
461 /* Fall back to a single interrupt. */
464 if (itype == INTR_MSIX)
465 rc = pci_alloc_msix(sc->dev, &navail);
467 rc = pci_alloc_msi(sc->dev, &navail);
469 device_printf(sc->dev,
470 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
471 itype, rc, iaq->nirq, navail);
472 iaq->intr_flags_10g = 0;
473 iaq->intr_flags_1g = 0;
477 device_printf(sc->dev,
478 "failed to find a usable interrupt type. "
479 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
480 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
486 t4vf_attach(device_t dev)
489 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
490 struct make_dev_args mda;
491 struct intrs_and_queues iaq;
494 sc = device_get_softc(dev);
496 pci_enable_busmaster(dev);
497 pci_set_max_read_req(dev, 4096);
498 sc->params.pci.mps = pci_get_max_payload(dev);
502 sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS);
503 sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL);
504 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
505 device_get_nameunit(dev));
506 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
509 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
510 TAILQ_INIT(&sc->sfl);
511 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
513 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
515 rc = t4_map_bars_0_and_4(sc);
517 goto done; /* error message displayed already */
519 rc = -t4vf_prep_adapter(sc);
523 t4_init_devnames(sc);
524 if (sc->names == NULL) {
526 goto done; /* error message displayed already */
530 * Leave the 'pf' and 'mbox' values as zero. This ensures
531 * that various firmware messages do not set the fields which
532 * is the correct thing to do for a VF.
535 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
537 make_dev_args_init(&mda);
538 mda.mda_devsw = &t4vf_cdevsw;
539 mda.mda_uid = UID_ROOT;
540 mda.mda_gid = GID_WHEEL;
542 mda.mda_si_drv1 = sc;
543 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
545 device_printf(dev, "failed to create nexus char device: %d.\n",
548 #if defined(__i386__)
549 if ((cpu_feature & CPUID_CX8) == 0) {
550 device_printf(dev, "64 bit atomics not available.\n");
557 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux
558 * 2.6.31 and later we can't call pci_reset_function() in order to
559 * issue an FLR because of a self- deadlock on the device semaphore.
560 * Meanwhile, the OS infrastructure doesn't issue FLRs in all the
561 * cases where they're needed -- for instance, some versions of KVM
562 * fail to reset "Assigned Devices" when the VM reboots. Therefore we
563 * use the firmware based reset in order to reset any per function
566 rc = -t4vf_fw_reset(sc);
568 device_printf(dev, "FW reset failed: %d\n", rc);
574 * Grab basic operational parameters. These will predominantly have
575 * been set up by the Physical Function Driver or will be hard coded
576 * into the adapter. We just have to live with them ... Note that
577 * we _must_ get our VPD parameters before our SGE parameters because
578 * we need to know the adapter's core clock from the VPD in order to
579 * properly decode the SGE Timer Values.
581 rc = get_params__pre_init(sc);
583 goto done; /* error message displayed already */
584 rc = get_params__post_init(sc);
586 goto done; /* error message displayed already */
588 rc = set_params__post_init(sc);
590 goto done; /* error message displayed already */
592 rc = t4_map_bar_2(sc);
594 goto done; /* error message displayed already */
596 rc = t4_create_dma_tag(sc);
598 goto done; /* error message displayed already */
601 * The number of "ports" which we support is equal to the number of
602 * Virtual Interfaces with which we've been provisioned.
604 sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS);
607 * We may have been provisioned with more VIs than the number of
608 * ports we're allowed to access (our Port Access Rights Mask).
609 * Just use a single VI for each port.
611 sc->params.nports = imin(sc->params.nports,
612 bitcount32(sc->params.vfres.pmask));
616 * XXX: The Linux VF driver will lower nports if it thinks there
617 * are too few resources in vfres (niqflint, nethctrl, neq).
622 * First pass over all the ports - allocate VIs and initialize some
623 * basic parameters like mac address, port type, etc. We also figure
624 * out whether a port is 10G or 1G and use that information when
625 * calculating how many interrupts to attempt to allocate.
628 for_each_port(sc, i) {
629 struct port_info *pi;
631 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
634 /* These must be set before t4_port_init */
638 pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE,
642 * Allocate the "main" VI and initialize parameters
645 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
647 device_printf(dev, "unable to initialize port %d: %d\n",
649 free(pi->vi, M_CXGBE);
655 /* No t4_link_start. */
657 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
658 device_get_nameunit(dev), i);
659 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
660 sc->chan_map[pi->tx_chan] = i;
662 pi->tc = malloc(sizeof(struct tx_sched_class) *
663 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
665 if (port_top_speed(pi) >= 10) {
671 pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, -1);
672 if (pi->dev == NULL) {
674 "failed to add device for port %d.\n", i);
678 pi->vi[0].dev = pi->dev;
679 device_set_softc(pi->dev, pi);
683 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
685 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq);
687 goto done; /* error message displayed already */
689 sc->intr_type = iaq.intr_type;
690 sc->intr_count = iaq.nirq;
693 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
694 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
695 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
696 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
697 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
699 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
701 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
703 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
705 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
708 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
712 * Second pass over the ports. This time we know the number of rx and
713 * tx queues that each port should get.
716 for_each_port(sc, i) {
717 struct port_info *pi = sc->port[i];
723 for_each_vi(pi, j, vi) {
725 vi->qsize_rxq = t4_qsize_rxq;
726 vi->qsize_txq = t4_qsize_txq;
728 vi->first_rxq = rqidx;
729 vi->first_txq = tqidx;
730 if (port_top_speed(pi) >= 10) {
731 vi->tmr_idx = t4_tmr_idx_10g;
732 vi->pktc_idx = t4_pktc_idx_10g;
733 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
734 vi->nrxq = j == 0 ? iaq.nrxq10g : 1;
735 vi->ntxq = j == 0 ? iaq.ntxq10g : 1;
737 vi->tmr_idx = t4_tmr_idx_1g;
738 vi->pktc_idx = t4_pktc_idx_1g;
739 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
740 vi->nrxq = j == 0 ? iaq.nrxq1g : 1;
741 vi->ntxq = j == 0 ? iaq.ntxq1g : 1;
746 vi->rsrv_noflowq = 0;
750 rc = t4_setup_intr_handlers(sc);
753 "failed to setup interrupt handlers: %d\n", rc);
757 rc = bus_generic_attach(dev);
760 "failed to attach all child ports: %d\n", rc);
765 "%d ports, %d %s interrupt%s, %d eq, %d iq\n",
766 sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ?
767 "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq,
772 t4_detach_common(dev);
780 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
783 /* 0x3f is used as the revision for VFs. */
784 regs->version = chip_id(sc) | (0x3f << 10);
785 t4_get_regs(sc, buf, regs->len);
789 t4_clr_vi_stats(struct adapter *sc)
793 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
794 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
795 t4_write_reg(sc, VF_MPS_REG(reg), 0);
799 t4vf_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
803 struct adapter *sc = dev->si_drv1;
805 rc = priv_check(td, PRIV_DRIVER);
810 case CHELSIO_T4_GETREG: {
811 struct t4_reg *edata = (struct t4_reg *)data;
813 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
816 if (edata->size == 4)
817 edata->val = t4_read_reg(sc, edata->addr);
818 else if (edata->size == 8)
819 edata->val = t4_read_reg64(sc, edata->addr);
825 case CHELSIO_T4_SETREG: {
826 struct t4_reg *edata = (struct t4_reg *)data;
828 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
831 if (edata->size == 4) {
832 if (edata->val & 0xffffffff00000000)
834 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
835 } else if (edata->size == 8)
836 t4_write_reg64(sc, edata->addr, edata->val);
841 case CHELSIO_T4_REGDUMP: {
842 struct t4_regdump *regs = (struct t4_regdump *)data;
843 int reglen = t4_get_regs_len(sc);
846 if (regs->len < reglen) {
847 regs->len = reglen; /* hint to the caller */
852 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
853 get_regs(sc, regs, buf);
854 rc = copyout(buf, regs->data, reglen);
858 case CHELSIO_T4_CLEAR_STATS: {
860 u_int port_id = *(uint32_t *)data;
861 struct port_info *pi;
864 if (port_id >= sc->params.nports)
866 pi = sc->port[port_id];
869 pi->tx_parse_error = 0;
873 * Since this command accepts a port, clear stats for
874 * all VIs on this port.
876 for_each_vi(pi, v, vi) {
877 if (vi->flags & VI_INIT_DONE) {
881 for_each_rxq(vi, i, rxq) {
882 #if defined(INET) || defined(INET6)
883 rxq->lro.lro_queued = 0;
884 rxq->lro.lro_flushed = 0;
887 rxq->vlan_extraction = 0;
890 for_each_txq(vi, i, txq) {
893 txq->vlan_insertion = 0;
897 txq->txpkts0_wrs = 0;
898 txq->txpkts1_wrs = 0;
899 txq->txpkts0_pkts = 0;
900 txq->txpkts1_pkts = 0;
901 mp_ring_reset_stats(txq->r);
907 case CHELSIO_T4_SCHED_CLASS:
908 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
910 case CHELSIO_T4_SCHED_QUEUE:
911 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
920 static device_method_t t4vf_methods[] = {
921 DEVMETHOD(device_probe, t4vf_probe),
922 DEVMETHOD(device_attach, t4vf_attach),
923 DEVMETHOD(device_detach, t4_detach_common),
928 static driver_t t4vf_driver = {
931 sizeof(struct adapter)
934 static device_method_t t5vf_methods[] = {
935 DEVMETHOD(device_probe, t5vf_probe),
936 DEVMETHOD(device_attach, t4vf_attach),
937 DEVMETHOD(device_detach, t4_detach_common),
942 static driver_t t5vf_driver = {
945 sizeof(struct adapter)
948 static device_method_t t6vf_methods[] = {
949 DEVMETHOD(device_probe, t6vf_probe),
950 DEVMETHOD(device_attach, t4vf_attach),
951 DEVMETHOD(device_detach, t4_detach_common),
956 static driver_t t6vf_driver = {
959 sizeof(struct adapter)
962 static driver_t cxgbev_driver = {
965 sizeof(struct port_info)
968 static driver_t cxlv_driver = {
971 sizeof(struct port_info)
974 static driver_t ccv_driver = {
977 sizeof(struct port_info)
980 static devclass_t t4vf_devclass, t5vf_devclass, t6vf_devclass;
981 static devclass_t cxgbev_devclass, cxlv_devclass, ccv_devclass;
983 DRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0);
984 MODULE_VERSION(t4vf, 1);
985 MODULE_DEPEND(t4vf, t4nex, 1, 1, 1);
987 DRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0);
988 MODULE_VERSION(t5vf, 1);
989 MODULE_DEPEND(t5vf, t5nex, 1, 1, 1);
991 DRIVER_MODULE(t6vf, pci, t6vf_driver, t6vf_devclass, 0, 0);
992 MODULE_VERSION(t6vf, 1);
993 MODULE_DEPEND(t6vf, t6nex, 1, 1, 1);
995 DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0);
996 MODULE_VERSION(cxgbev, 1);
998 DRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0);
999 MODULE_VERSION(cxlv, 1);
1001 DRIVER_MODULE(ccv, t6vf, ccv_driver, ccv_devclass, 0, 0);
1002 MODULE_VERSION(ccv, 1);