2 * Copyright (c) 2012, 2015 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include "tom/t4_tls.h"
36 #define LISTEN_HASH_SIZE 32
39 * Min receive window. We want it to be large enough to accommodate receive
40 * coalescing, handle jumbo frames, and not trigger sender SWS avoidance.
42 #define MIN_RCV_WND (24 * 1024U)
45 * Max receive window supported by HW in bytes. Only a small part of it can
46 * be set through option0, the rest needs to be set through RX_DATA_ACK.
48 #define MAX_RCV_WND ((1U << 27) - 1)
50 #define DDP_RSVD_WIN (16 * 1024U)
51 #define SB_DDP_INDICATE SB_IN_TOE /* soreceive must respond to indicate */
53 #define USE_DDP_RX_FLOW_CONTROL
55 #define PPOD_SZ(n) ((n) * sizeof(struct pagepod))
56 #define PPOD_SIZE (PPOD_SZ(1))
60 TPF_ATTACHED = (1 << 0), /* a tcpcb refers to this toepcb */
61 TPF_FLOWC_WR_SENT = (1 << 1), /* firmware flow context WR sent */
62 TPF_TX_DATA_SENT = (1 << 2), /* some data sent */
63 TPF_TX_SUSPENDED = (1 << 3), /* tx suspended for lack of resources */
64 TPF_SEND_FIN = (1 << 4), /* send FIN after all pending data */
65 TPF_FIN_SENT = (1 << 5), /* FIN has been sent */
66 TPF_ABORT_SHUTDOWN = (1 << 6), /* connection abort is in progress */
67 TPF_CPL_PENDING = (1 << 7), /* haven't received the last CPL */
68 TPF_SYNQE = (1 << 8), /* synq_entry, not really a toepcb */
69 TPF_SYNQE_NEEDFREE = (1 << 9), /* synq_entry was malloc'd separately */
70 TPF_SYNQE_TCPDDP = (1 << 10), /* ulp_mode TCPDDP in toepcb */
71 TPF_SYNQE_EXPANDED = (1 << 11), /* toepcb ready, tid context updated */
72 TPF_SYNQE_HAS_L2TE = (1 << 12), /* we've replied to PASS_ACCEPT_REQ */
73 TPF_SYNQE_TLS = (1 << 13), /* ulp_mode TLS in toepcb */
74 TPF_FORCE_CREDITS = (1 << 14), /* always send credits */
78 DDP_OK = (1 << 0), /* OK to turn on DDP */
79 DDP_SC_REQ = (1 << 1), /* state change (on/off) requested */
80 DDP_ON = (1 << 2), /* DDP is turned on */
81 DDP_BUF0_ACTIVE = (1 << 3), /* buffer 0 in use (not invalidated) */
82 DDP_BUF1_ACTIVE = (1 << 4), /* buffer 1 in use (not invalidated) */
83 DDP_TASK_ACTIVE = (1 << 5), /* requeue task is queued / running */
84 DDP_DEAD = (1 << 6), /* toepcb is shutting down */
88 struct offload_settings;
90 struct ofld_tx_sdesc {
91 uint32_t plen; /* payload length */
92 uint8_t tx_credits; /* firmware tx credits (unit is 16B) */
93 void *iv_buffer; /* optional buffer holding IVs for TLS */
99 u_int pr_page_shift[4];
100 uint32_t pr_tag_mask; /* hardware tagmask for this region. */
101 uint32_t pr_invalid_bit; /* OR with this to invalidate tag. */
102 uint32_t pr_alias_mask; /* AND with tag to get alias bits. */
103 u_int pr_alias_shift; /* shift this much for first alias bit. */
107 struct ppod_reservation {
108 struct ppod_region *prsv_pr;
109 uint32_t prsv_tag; /* Full tag: pgsz, alias, tag, color */
114 TAILQ_ENTRY(pageset) link;
118 int offset; /* offset in first page */
120 struct ppod_reservation prsv;
126 TAILQ_HEAD(pagesetq, pageset);
128 #define PS_WIRED 0x0001 /* Pages wired rather than held. */
129 #define PS_PPODS_WRITTEN 0x0002 /* Page pods written to the card. */
131 #define EXT_FLAG_AIOTX EXT_FLAG_VENDOR1
133 #define IS_AIOTX_MBUF(m) \
134 ((m)->m_flags & M_EXT && (m)->m_ext.ext_flags & EXT_FLAG_AIOTX)
145 struct ddp_buffer db[2];
146 TAILQ_HEAD(, pageset) cached_pagesets;
147 TAILQ_HEAD(, kaiocb) aiojobq;
151 int active_id; /* the currently active DDP buffer */
152 struct task requeue_task;
153 struct kaiocb *queueing;
157 struct aiotx_buffer {
164 TAILQ_ENTRY(toepcb) link; /* toep_list */
165 u_int flags; /* miscellaneous flags */
168 struct inpcb *inp; /* backpointer to host stack's PCB */
170 struct vi_info *vi; /* virtual interface */
171 struct sge_wrq *ofld_txq;
172 struct sge_ofld_rxq *ofld_rxq;
173 struct sge_wrq *ctrlq;
174 struct l2t_entry *l2te; /* L2 table entry used by this connection */
175 struct clip_entry *ce; /* CLIP table entry used by this tid */
176 int tid; /* Connection identifier */
177 int tc_idx; /* traffic class that this tid is bound to */
179 /* tx credit handling */
180 u_int tx_total; /* total tx WR credits (in 16B units) */
181 u_int tx_credits; /* tx WR credits (in 16B units) available */
182 u_int tx_nocompl; /* tx WR credits since last compl request */
183 u_int plen_nocompl; /* payload since last compl request */
185 /* rx credit handling */
186 u_int sb_cc; /* last noted value of so_rcv->sb_cc */
187 int rx_credits; /* rx credits (in bytes) to be returned to hw */
189 u_int ulp_mode; /* ULP mode */
192 struct mbufq ulp_pduq; /* PDUs waiting to be sent out. */
193 struct mbufq ulp_pdu_reclaimq;
196 struct tls_ofld_info tls;
198 TAILQ_HEAD(, kaiocb) aiotx_jobq;
199 struct task aiotx_task;
200 bool aiotx_task_active;
202 /* Tx software descriptor */
207 struct ofld_tx_sdesc txsd[];
210 #define DDP_LOCK(toep) mtx_lock(&(toep)->ddp.lock)
211 #define DDP_UNLOCK(toep) mtx_unlock(&(toep)->ddp.lock)
212 #define DDP_ASSERT_LOCKED(toep) mtx_assert(&(toep)->ddp.lock, MA_OWNED)
214 struct flowc_tx_params {
217 unsigned int snd_space;
221 #define DDP_RETRY_WAIT 5 /* seconds to wait before re-enabling DDP */
222 #define DDP_LOW_SCORE 1
223 #define DDP_HIGH_SCORE 3
226 * Compressed state for embryonic connections for a listener. Barely fits in
227 * 64B, try not to grow it further.
230 TAILQ_ENTRY(synq_entry) link; /* listen_ctx's synq link */
231 int flags; /* same as toepcb's tp_flags */
233 struct listen_ctx *lctx; /* backpointer to listen ctx */
237 volatile uintptr_t wr;
238 volatile u_int refcnt;
240 uint16_t rcv_bufsize;
243 /* listen_ctx flags */
244 #define LCTX_RPL_PENDING 1 /* waiting for a CPL_PASS_OPEN_RPL */
247 LIST_ENTRY(listen_ctx) link; /* listen hash linkage */
248 volatile int refcount;
250 struct stid_region stid_region;
252 struct inpcb *inp; /* listening socket's inp */
254 struct sge_wrq *ctrlq;
255 struct sge_ofld_rxq *ofld_rxq;
256 struct clip_entry *ce;
257 TAILQ_HEAD(, synq_entry) synq;
261 TAILQ_ENTRY(clip_entry) link;
262 struct in6_addr lip; /* local IPv6 address */
266 TAILQ_HEAD(clip_head, clip_entry);
270 /* toepcb's associated with this TOE device */
271 struct mtx toep_list_lock;
272 TAILQ_HEAD(, toepcb) toep_list;
274 struct mtx lctx_hash_lock;
275 LIST_HEAD(, listen_ctx) *listen_hash;
277 int lctx_count; /* # of lctx in the hash table */
279 struct ppod_region pr;
281 struct mtx clip_table_lock;
282 struct clip_head clip_table;
285 /* WRs that will not be sent to the chip because L2 resolution failed */
286 struct mtx unsent_wr_lock;
287 STAILQ_HEAD(, wrqe) unsent_wr_list;
288 struct task reclaim_wr_resources;
291 static inline struct tom_data *
292 tod_td(struct toedev *tod)
295 return (__containerof(tod, struct tom_data, tod));
298 static inline struct adapter *
299 td_adapter(struct tom_data *td)
302 return (td->tod.tod_softc);
306 set_mbuf_ulp_submode(struct mbuf *m, uint8_t ulp_submode)
310 m->m_pkthdr.PH_per.eight[0] = ulp_submode;
313 static inline uint8_t
314 mbuf_ulp_submode(struct mbuf *m)
318 return (m->m_pkthdr.PH_per.eight[0]);
322 struct toepcb *alloc_toepcb(struct vi_info *, int, int, int);
323 struct toepcb *hold_toepcb(struct toepcb *);
324 void free_toepcb(struct toepcb *);
325 void offload_socket(struct socket *, struct toepcb *);
326 void undo_offload_socket(struct socket *);
327 void final_cpl_received(struct toepcb *);
328 void insert_tid(struct adapter *, int, void *, int);
329 void *lookup_tid(struct adapter *, int);
330 void update_tid(struct adapter *, int, void *);
331 void remove_tid(struct adapter *, int, int);
332 int find_best_mtu_idx(struct adapter *, struct in_conninfo *,
333 struct offload_settings *);
334 u_long select_rcv_wnd(struct socket *);
335 int select_rcv_wscale(void);
336 uint64_t calc_opt0(struct socket *, struct vi_info *, struct l2t_entry *,
337 int, int, int, int, struct offload_settings *);
338 uint64_t select_ntuple(struct vi_info *, struct l2t_entry *);
339 int select_ulp_mode(struct socket *, struct adapter *,
340 struct offload_settings *);
341 void set_ulp_mode(struct toepcb *, int);
342 int negative_advice(int);
343 struct clip_entry *hold_lip(struct tom_data *, struct in6_addr *,
344 struct clip_entry *);
345 void release_lip(struct tom_data *, struct clip_entry *);
348 void t4_init_connect_cpl_handlers(void);
349 void t4_uninit_connect_cpl_handlers(void);
350 int t4_connect(struct toedev *, struct socket *, struct rtentry *,
352 void act_open_failure_cleanup(struct adapter *, u_int, u_int);
355 void t4_init_listen_cpl_handlers(void);
356 void t4_uninit_listen_cpl_handlers(void);
357 int t4_listen_start(struct toedev *, struct tcpcb *);
358 int t4_listen_stop(struct toedev *, struct tcpcb *);
359 void t4_syncache_added(struct toedev *, void *);
360 void t4_syncache_removed(struct toedev *, void *);
361 int t4_syncache_respond(struct toedev *, void *, struct mbuf *);
362 int do_abort_req_synqe(struct sge_iq *, const struct rss_header *,
364 int do_abort_rpl_synqe(struct sge_iq *, const struct rss_header *,
366 void t4_offload_socket(struct toedev *, void *, struct socket *);
369 void aiotx_init_toep(struct toepcb *);
370 int t4_aio_queue_aiotx(struct socket *, struct kaiocb *);
371 void t4_init_cpl_io_handlers(void);
372 void t4_uninit_cpl_io_handlers(void);
373 void send_abort_rpl(struct adapter *, struct sge_wrq *, int , int);
374 void send_flowc_wr(struct toepcb *, struct flowc_tx_params *);
375 void send_reset(struct adapter *, struct toepcb *, uint32_t);
376 int send_rx_credits(struct adapter *, struct toepcb *, int);
377 void send_rx_modulate(struct adapter *, struct toepcb *);
378 void make_established(struct toepcb *, uint32_t, uint32_t, uint16_t);
379 int t4_close_conn(struct adapter *, struct toepcb *);
380 void t4_rcvd(struct toedev *, struct tcpcb *);
381 void t4_rcvd_locked(struct toedev *, struct tcpcb *);
382 int t4_tod_output(struct toedev *, struct tcpcb *);
383 int t4_send_fin(struct toedev *, struct tcpcb *);
384 int t4_send_rst(struct toedev *, struct tcpcb *);
385 void t4_set_tcb_field(struct adapter *, struct sge_wrq *, struct toepcb *,
386 uint16_t, uint64_t, uint64_t, int, int);
387 void t4_push_frames(struct adapter *sc, struct toepcb *toep, int drop);
388 void t4_push_pdus(struct adapter *sc, struct toepcb *toep, int drop);
389 int do_set_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
392 int t4_init_ppod_region(struct ppod_region *, struct t4_range *, u_int,
394 void t4_free_ppod_region(struct ppod_region *);
395 int t4_alloc_page_pods_for_ps(struct ppod_region *, struct pageset *);
396 int t4_alloc_page_pods_for_buf(struct ppod_region *, vm_offset_t, int,
397 struct ppod_reservation *);
398 int t4_write_page_pods_for_ps(struct adapter *, struct sge_wrq *, int,
400 int t4_write_page_pods_for_buf(struct adapter *, struct sge_wrq *, int tid,
401 struct ppod_reservation *, vm_offset_t, int);
402 void t4_free_page_pods(struct ppod_reservation *);
403 int t4_soreceive_ddp(struct socket *, struct sockaddr **, struct uio *,
404 struct mbuf **, struct mbuf **, int *);
405 int t4_aio_queue_ddp(struct socket *, struct kaiocb *);
406 void t4_ddp_mod_load(void);
407 void t4_ddp_mod_unload(void);
408 void ddp_assert_empty(struct toepcb *);
409 void ddp_init_toep(struct toepcb *);
410 void ddp_uninit_toep(struct toepcb *);
411 void ddp_queue_toep(struct toepcb *);
412 void release_ddp_resources(struct toepcb *toep);
413 void handle_ddp_close(struct toepcb *, struct tcpcb *, uint32_t);
414 void handle_ddp_indicate(struct toepcb *);
415 void handle_ddp_tcb_rpl(struct toepcb *, const struct cpl_set_tcb_rpl *);
416 void insert_ddp_data(struct toepcb *, uint32_t);
417 const struct offload_settings *lookup_offload_policy(struct adapter *, int,
418 struct mbuf *, uint16_t, struct inpcb *);
421 bool can_tls_offload(struct adapter *);
422 int t4_ctloutput_tls(struct socket *, struct sockopt *);
423 void t4_push_tls_records(struct adapter *, struct toepcb *, int);
424 void t4_tls_mod_load(void);
425 void t4_tls_mod_unload(void);
426 void tls_establish(struct toepcb *);
427 void tls_init_toep(struct toepcb *);
428 int tls_rx_key(struct toepcb *);
429 void tls_stop_handshake_timer(struct toepcb *);
430 int tls_tx_key(struct toepcb *);
431 void tls_uninit_toep(struct toepcb *);