2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
40 * series chips and several workalikes including the following:
42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
44 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
45 * ASIX Electronics AX88140A (www.asix.com.tw)
46 * ASIX Electronics AX88141 (www.asix.com.tw)
47 * ADMtek AL981 (www.admtek.com.tw)
48 * ADMtek AN983 (www.admtek.com.tw)
49 * ADMtek CardBus AN985 (www.admtek.com.tw)
50 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
51 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
52 * Accton EN1217 (www.accton.com)
53 * Xircom X3201 (www.xircom.com)
55 * Conexant LANfinity (www.conexant.com)
56 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
58 * Datasheets for the 21143 are available at developer.intel.com.
59 * Datasheets for the clone parts can be found at their respective sites.
60 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
61 * The PNIC II is essentially a Macronix 98715A chip; the only difference
62 * worth noting is that its multicast hash table is only 128 bits wide
65 * Written by Bill Paul <wpaul@ee.columbia.edu>
66 * Electrical Engineering Department
67 * Columbia University, New York City
70 * The Intel 21143 is the successor to the DEC 21140. It is basically
71 * the same as the 21140 but with a few new features. The 21143 supports
72 * three kinds of media attachments:
74 * o MII port, for 10Mbps and 100Mbps support and NWAY
75 * autonegotiation provided by an external PHY.
76 * o SYM port, for symbol mode 100Mbps support.
80 * The 100Mbps SYM port and 10baseT port can be used together in
81 * combination with the internal NWAY support to create a 10/100
82 * autosensing configuration.
84 * Note that not all tulip workalikes are handled in this driver: we only
85 * deal with those which are relatively well behaved. The Winbond is
86 * handled separately due to its different register offsets and the
87 * special handling needed for its various bugs. The PNIC is handled
88 * here, but I'm not thrilled about it.
90 * All of the workalike chips use some form of MII transceiver support
91 * with the exception of the Macronix chips, which also have a SYM port.
92 * The ASIX AX88140A is also documented to have a SYM port, but all
93 * the cards I've seen use an MII transceiver, probably because the
94 * AX88140A doesn't support internal NWAY.
97 #ifdef HAVE_KERNEL_OPTION_HEADERS
98 #include "opt_device_polling.h"
101 #include <sys/param.h>
102 #include <sys/endian.h>
103 #include <sys/systm.h>
104 #include <sys/sockio.h>
105 #include <sys/mbuf.h>
106 #include <sys/malloc.h>
107 #include <sys/kernel.h>
108 #include <sys/module.h>
109 #include <sys/socket.h>
112 #include <net/if_var.h>
113 #include <net/if_arp.h>
114 #include <net/ethernet.h>
115 #include <net/if_dl.h>
116 #include <net/if_media.h>
117 #include <net/if_types.h>
118 #include <net/if_vlan_var.h>
122 #include <machine/bus.h>
123 #include <machine/resource.h>
125 #include <sys/rman.h>
127 #include <dev/mii/mii.h>
128 #include <dev/mii/mii_bitbang.h>
129 #include <dev/mii/miivar.h>
131 #include <dev/pci/pcireg.h>
132 #include <dev/pci/pcivar.h>
134 #define DC_USEIOSPACE
136 #include <dev/dc/if_dcreg.h>
139 #include <dev/ofw/openfirm.h>
140 #include <machine/ofw_machdep.h>
143 MODULE_DEPEND(dc, pci, 1, 1, 1);
144 MODULE_DEPEND(dc, ether, 1, 1, 1);
145 MODULE_DEPEND(dc, miibus, 1, 1, 1);
148 * "device miibus" is required in kernel config. See GENERIC if you get
151 #include "miibus_if.h"
154 * Various supported device vendors/types and their names.
156 static const struct dc_type dc_devs[] = {
157 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
158 "Intel 21143 10/100BaseTX" },
159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
160 "Davicom DM9009 10/100BaseTX" },
161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
162 "Davicom DM9100 10/100BaseTX" },
163 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
164 "Davicom DM9102A 10/100BaseTX" },
165 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
166 "Davicom DM9102 10/100BaseTX" },
167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
168 "ADMtek AL981 10/100BaseTX" },
169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
170 "ADMtek AN983 10/100BaseTX" },
171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
172 "ADMtek AN985 CardBus 10/100BaseTX or clone" },
173 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
174 "ADMtek ADM9511 10/100BaseTX" },
175 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
176 "ADMtek ADM9513 10/100BaseTX" },
177 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
178 "ASIX AX88141 10/100BaseTX" },
179 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
180 "ASIX AX88140A 10/100BaseTX" },
181 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
182 "Macronix 98713A 10/100BaseTX" },
183 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
184 "Macronix 98713 10/100BaseTX" },
185 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
186 "Compex RL100-TX 10/100BaseTX" },
187 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
188 "Compex RL100-TX 10/100BaseTX" },
189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
190 "Macronix 98725 10/100BaseTX" },
191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
192 "Macronix 98715AEC-C 10/100BaseTX" },
193 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
194 "Macronix 98715/98715A 10/100BaseTX" },
195 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
196 "Macronix 98727/98732 10/100BaseTX" },
197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
198 "LC82C115 PNIC II 10/100BaseTX" },
199 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
200 "82c169 PNIC 10/100BaseTX" },
201 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
202 "82c168 PNIC 10/100BaseTX" },
203 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
204 "Accton EN1217 10/100BaseTX" },
205 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
206 "Accton EN2242 MiniPCI 10/100BaseTX" },
207 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
208 "Xircom X3201 10/100BaseTX" },
209 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
210 "Neteasy DRP-32TXD Cardbus 10/100" },
211 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
212 "Abocom FE2500 10/100BaseTX" },
213 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
214 "Abocom FE2500MX 10/100BaseTX" },
215 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
216 "Conexant LANfinity MiniPCI 10/100BaseTX" },
217 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
218 "Hawking CB102 CardBus 10/100" },
219 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
220 "PlaneX FNW-3602-T CardBus 10/100" },
221 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
222 "3Com OfficeConnect 10/100B" },
223 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
224 "Microsoft MN-120 CardBus 10/100" },
225 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
226 "Microsoft MN-130 10/100" },
227 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
228 "Linksys PCMPC200 CardBus 10/100" },
229 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
230 "Linksys PCMPC200 CardBus 10/100" },
231 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0,
232 "ULi M5261 FastEthernet" },
233 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0,
234 "ULi M5263 FastEthernet" },
238 static int dc_probe(device_t);
239 static int dc_attach(device_t);
240 static int dc_detach(device_t);
241 static int dc_suspend(device_t);
242 static int dc_resume(device_t);
243 static const struct dc_type *dc_devtype(device_t);
244 static void dc_discard_rxbuf(struct dc_softc *, int);
245 static int dc_newbuf(struct dc_softc *, int);
246 static int dc_encap(struct dc_softc *, struct mbuf **);
247 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
248 static int dc_rx_resync(struct dc_softc *);
249 static int dc_rxeof(struct dc_softc *);
250 static void dc_txeof(struct dc_softc *);
251 static void dc_tick(void *);
252 static void dc_tx_underrun(struct dc_softc *);
253 static void dc_intr(void *);
254 static void dc_start(struct ifnet *);
255 static void dc_start_locked(struct ifnet *);
256 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
257 static void dc_init(void *);
258 static void dc_init_locked(struct dc_softc *);
259 static void dc_stop(struct dc_softc *);
260 static void dc_watchdog(void *);
261 static int dc_shutdown(device_t);
262 static int dc_ifmedia_upd(struct ifnet *);
263 static int dc_ifmedia_upd_locked(struct dc_softc *);
264 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
266 static int dc_dma_alloc(struct dc_softc *);
267 static void dc_dma_free(struct dc_softc *);
268 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
270 static void dc_delay(struct dc_softc *);
271 static void dc_eeprom_idle(struct dc_softc *);
272 static void dc_eeprom_putbyte(struct dc_softc *, int);
273 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
274 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
275 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
276 static void dc_eeprom_width(struct dc_softc *);
277 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
279 static int dc_miibus_readreg(device_t, int, int);
280 static int dc_miibus_writereg(device_t, int, int, int);
281 static void dc_miibus_statchg(device_t);
282 static void dc_miibus_mediainit(device_t);
284 static void dc_setcfg(struct dc_softc *, int);
285 static void dc_netcfg_wait(struct dc_softc *);
286 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
287 static uint32_t dc_mchash_be(const uint8_t *);
288 static void dc_setfilt_21143(struct dc_softc *);
289 static void dc_setfilt_asix(struct dc_softc *);
290 static void dc_setfilt_admtek(struct dc_softc *);
291 static void dc_setfilt_uli(struct dc_softc *);
292 static void dc_setfilt_xircom(struct dc_softc *);
294 static void dc_setfilt(struct dc_softc *);
296 static void dc_reset(struct dc_softc *);
297 static int dc_list_rx_init(struct dc_softc *);
298 static int dc_list_tx_init(struct dc_softc *);
300 static int dc_read_srom(struct dc_softc *, int);
301 static int dc_parse_21143_srom(struct dc_softc *);
302 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
303 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
304 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
305 static void dc_apply_fixup(struct dc_softc *, int);
306 static int dc_check_multiport(struct dc_softc *);
311 static uint32_t dc_mii_bitbang_read(device_t);
312 static void dc_mii_bitbang_write(device_t, uint32_t);
314 static const struct mii_bitbang_ops dc_mii_bitbang_ops = {
316 dc_mii_bitbang_write,
318 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */
319 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */
320 DC_SIO_MII_CLK, /* MII_BIT_MDC */
321 0, /* MII_BIT_DIR_HOST_PHY */
322 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */
327 #define DC_RES SYS_RES_IOPORT
328 #define DC_RID DC_PCI_CFBIO
330 #define DC_RES SYS_RES_MEMORY
331 #define DC_RID DC_PCI_CFBMA
334 static device_method_t dc_methods[] = {
335 /* Device interface */
336 DEVMETHOD(device_probe, dc_probe),
337 DEVMETHOD(device_attach, dc_attach),
338 DEVMETHOD(device_detach, dc_detach),
339 DEVMETHOD(device_suspend, dc_suspend),
340 DEVMETHOD(device_resume, dc_resume),
341 DEVMETHOD(device_shutdown, dc_shutdown),
344 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
345 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
346 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
347 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
352 static driver_t dc_driver = {
355 sizeof(struct dc_softc)
358 static devclass_t dc_devclass;
360 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL,
362 MODULE_PNP_INFO("W32:vendor/device;U8:revision;D:#", pci, dc, dc_devs,
363 nitems(dc_devs) - 1);
364 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
366 #define DC_SETBIT(sc, reg, x) \
367 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
369 #define DC_CLRBIT(sc, reg, x) \
370 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
372 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
373 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
376 dc_delay(struct dc_softc *sc)
380 for (idx = (300 / 33) + 1; idx > 0; idx--)
381 CSR_READ_4(sc, DC_BUSCTL);
385 dc_eeprom_width(struct dc_softc *sc)
389 /* Force EEPROM to idle state. */
392 /* Enter EEPROM access mode. */
393 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
395 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
399 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
408 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
414 for (i = 1; i <= 12; i++) {
415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
417 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
426 /* Turn off EEPROM access mode. */
434 /* Enter EEPROM access mode. */
435 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
437 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
439 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
441 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
444 /* Turn off EEPROM access mode. */
449 dc_eeprom_idle(struct dc_softc *sc)
453 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
455 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
457 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
459 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
462 for (i = 0; i < 25; i++) {
463 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
465 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
471 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
473 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
477 * Send a read command and address to the EEPROM, check for ACK.
480 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
484 d = DC_EECMD_READ >> 6;
487 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
489 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
491 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
493 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
498 * Feed in each bit and strobe the clock.
500 for (i = sc->dc_romwidth; i--;) {
501 if (addr & (1 << i)) {
502 SIO_SET(DC_SIO_EE_DATAIN);
504 SIO_CLR(DC_SIO_EE_DATAIN);
507 SIO_SET(DC_SIO_EE_CLK);
509 SIO_CLR(DC_SIO_EE_CLK);
515 * Read a word of data stored in the EEPROM at address 'addr.'
516 * The PNIC 82c168/82c169 has its own non-standard way to read
520 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
525 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
527 for (i = 0; i < DC_TIMEOUT; i++) {
529 r = CSR_READ_4(sc, DC_SIO);
530 if (!(r & DC_PN_SIOCTL_BUSY)) {
531 *dest = (uint16_t)(r & 0xFFFF);
538 * Read a word of data stored in the EEPROM at address 'addr.'
539 * The Xircom X3201 has its own non-standard way to read
543 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
546 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
549 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
550 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
552 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
553 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
555 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
559 * Read a word of data stored in the EEPROM at address 'addr.'
562 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
567 /* Force EEPROM to idle state. */
570 /* Enter EEPROM access mode. */
571 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
573 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
575 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
577 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
581 * Send address of word we want to read.
583 dc_eeprom_putbyte(sc, addr);
586 * Start reading bits from EEPROM.
588 for (i = 0x8000; i; i >>= 1) {
589 SIO_SET(DC_SIO_EE_CLK);
591 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
594 SIO_CLR(DC_SIO_EE_CLK);
598 /* Turn off EEPROM access mode. */
605 * Read a sequence of words from the EEPROM.
608 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
611 uint16_t word = 0, *ptr;
613 for (i = 0; i < cnt; i++) {
615 dc_eeprom_getword_pnic(sc, off + i, &word);
616 else if (DC_IS_XIRCOM(sc))
617 dc_eeprom_getword_xircom(sc, off + i, &word);
619 dc_eeprom_getword(sc, off + i, &word);
620 ptr = (uint16_t *)(dest + (i * 2));
622 *ptr = be16toh(word);
624 *ptr = le16toh(word);
629 * Write the MII serial port for the MII bit-bang module.
632 dc_mii_bitbang_write(device_t dev, uint32_t val)
636 sc = device_get_softc(dev);
638 CSR_WRITE_4(sc, DC_SIO, val);
639 CSR_BARRIER_4(sc, DC_SIO,
640 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
644 * Read the MII serial port for the MII bit-bang module.
647 dc_mii_bitbang_read(device_t dev)
652 sc = device_get_softc(dev);
654 val = CSR_READ_4(sc, DC_SIO);
655 CSR_BARRIER_4(sc, DC_SIO,
656 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
662 dc_miibus_readreg(device_t dev, int phy, int reg)
665 int i, rval, phy_reg = 0;
667 sc = device_get_softc(dev);
669 if (sc->dc_pmode != DC_PMODE_MII) {
670 if (phy == (MII_NPHY - 1)) {
674 * Fake something to make the probe
675 * code think there's a PHY here.
677 return (BMSR_MEDIAMASK);
680 return (DC_VENDORID_LO);
681 return (DC_VENDORID_DEC);
684 return (DC_DEVICEID_82C168);
685 return (DC_DEVICEID_21143);
693 if (DC_IS_PNIC(sc)) {
694 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
695 (phy << 23) | (reg << 18));
696 for (i = 0; i < DC_TIMEOUT; i++) {
698 rval = CSR_READ_4(sc, DC_PN_MII);
699 if (!(rval & DC_PN_MII_BUSY)) {
701 return (rval == 0xFFFF ? 0 : rval);
707 if (sc->dc_type == DC_TYPE_ULI_M5263) {
708 CSR_WRITE_4(sc, DC_ROM,
709 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
710 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
712 for (i = 0; i < DC_TIMEOUT; i++) {
714 rval = CSR_READ_4(sc, DC_ROM);
715 if ((rval & DC_ULI_PHY_OP_DONE) != 0) {
716 return (rval & DC_ULI_PHY_DATA_MASK);
720 device_printf(dev, "phy read timed out\n");
724 if (DC_IS_COMET(sc)) {
727 phy_reg = DC_AL_BMCR;
730 phy_reg = DC_AL_BMSR;
733 phy_reg = DC_AL_VENID;
736 phy_reg = DC_AL_DEVID;
739 phy_reg = DC_AL_ANAR;
742 phy_reg = DC_AL_LPAR;
745 phy_reg = DC_AL_ANER;
748 device_printf(dev, "phy_read: bad phy register %x\n",
753 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
759 if (sc->dc_type == DC_TYPE_98713) {
760 phy_reg = CSR_READ_4(sc, DC_NETCFG);
761 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
763 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
764 if (sc->dc_type == DC_TYPE_98713)
765 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
771 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
776 sc = device_get_softc(dev);
778 if (DC_IS_PNIC(sc)) {
779 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
780 (phy << 23) | (reg << 10) | data);
781 for (i = 0; i < DC_TIMEOUT; i++) {
782 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
788 if (sc->dc_type == DC_TYPE_ULI_M5263) {
789 CSR_WRITE_4(sc, DC_ROM,
790 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
791 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
792 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) |
793 DC_ULI_PHY_OP_WRITE);
798 if (DC_IS_COMET(sc)) {
801 phy_reg = DC_AL_BMCR;
804 phy_reg = DC_AL_BMSR;
807 phy_reg = DC_AL_VENID;
810 phy_reg = DC_AL_DEVID;
813 phy_reg = DC_AL_ANAR;
816 phy_reg = DC_AL_LPAR;
819 phy_reg = DC_AL_ANER;
822 device_printf(dev, "phy_write: bad phy register %x\n",
828 CSR_WRITE_4(sc, phy_reg, data);
832 if (sc->dc_type == DC_TYPE_98713) {
833 phy_reg = CSR_READ_4(sc, DC_NETCFG);
834 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
836 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);
837 if (sc->dc_type == DC_TYPE_98713)
838 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
844 dc_miibus_statchg(device_t dev)
848 struct mii_data *mii;
851 sc = device_get_softc(dev);
853 mii = device_get_softc(sc->dc_miibus);
855 if (mii == NULL || ifp == NULL ||
856 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
859 ifm = &mii->mii_media;
860 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
861 dc_setcfg(sc, ifm->ifm_media);
863 } else if (!DC_IS_ADMTEK(sc))
864 dc_setcfg(sc, mii->mii_media_active);
867 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
868 (IFM_ACTIVE | IFM_AVALID)) {
869 switch (IFM_SUBTYPE(mii->mii_media_active)) {
879 * Special support for DM9102A cards with HomePNA PHYs. Note:
880 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
881 * to be impossible to talk to the management interface of the DM9801
882 * PHY (its MDIO pin is not connected to anything). Consequently,
883 * the driver has to just 'know' about the additional mode and deal
884 * with it itself. *sigh*
887 dc_miibus_mediainit(device_t dev)
890 struct mii_data *mii;
894 rev = pci_get_revid(dev);
896 sc = device_get_softc(dev);
897 mii = device_get_softc(sc->dc_miibus);
898 ifm = &mii->mii_media;
900 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
901 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
904 #define DC_BITS_512 9
905 #define DC_BITS_128 7
909 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
913 /* Compute CRC for the address value. */
914 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
917 * The hash table on the PNIC II and the MX98715AEC-C/D/E
918 * chips is only 128 bits wide.
920 if (sc->dc_flags & DC_128BIT_HASH)
921 return (crc & ((1 << DC_BITS_128) - 1));
923 /* The hash table on the MX98715BEC is only 64 bits wide. */
924 if (sc->dc_flags & DC_64BIT_HASH)
925 return (crc & ((1 << DC_BITS_64) - 1));
927 /* Xircom's hash filtering table is different (read: weird) */
928 /* Xircom uses the LEAST significant bits */
929 if (DC_IS_XIRCOM(sc)) {
930 if ((crc & 0x180) == 0x180)
931 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
933 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
937 return (crc & ((1 << DC_BITS_512) - 1));
941 * Calculate CRC of a multicast group address, return the lower 6 bits.
944 dc_mchash_be(const uint8_t *addr)
948 /* Compute CRC for the address value. */
949 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
951 /* Return the filter bit position. */
952 return ((crc >> 26) & 0x0000003F);
956 * 21143-style RX filter setup routine. Filter programming is done by
957 * downloading a special setup frame into the TX engine. 21143, Macronix,
958 * PNIC, PNIC II and Davicom chips are programmed this way.
960 * We always program the chip using 'hash perfect' mode, i.e. one perfect
961 * address (our node address) and a 512-bit hash filter for multicast
962 * frames. We also sneak the broadcast address into the hash filter since
966 dc_hash_maddr_21143(void *arg, struct sockaddr_dl *sdl, u_int cnt)
968 struct dc_softc *sc = arg;
971 h = dc_mchash_le(sc, LLADDR(sdl));
972 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF));
978 dc_setfilt_21143(struct dc_softc *sc)
980 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
981 struct dc_desc *sframe;
988 i = sc->dc_cdata.dc_tx_prod;
989 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
990 sc->dc_cdata.dc_tx_cnt++;
991 sframe = &sc->dc_ldata.dc_tx_list[i];
992 sp = sc->dc_cdata.dc_sbuf;
993 bzero(sp, DC_SFRAME_LEN);
995 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
996 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
997 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
999 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1001 /* If we want promiscuous mode, set the allframes bit. */
1002 if (ifp->if_flags & IFF_PROMISC)
1003 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1005 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1007 if (ifp->if_flags & IFF_ALLMULTI)
1008 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1010 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1012 if_foreach_llmaddr(ifp, dc_hash_maddr_21143, sp);
1014 if (ifp->if_flags & IFF_BROADCAST) {
1015 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1016 sp[h >> 4] |= htole32(1 << (h & 0xF));
1019 /* Set our MAC address. */
1020 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1021 sp[39] = DC_SP_MAC(eaddr[0]);
1022 sp[40] = DC_SP_MAC(eaddr[1]);
1023 sp[41] = DC_SP_MAC(eaddr[2]);
1025 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1026 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1027 BUS_DMASYNC_PREWRITE);
1028 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1029 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1032 * The PNIC takes an exceedingly long time to process its
1033 * setup frame; wait 10ms after posting the setup frame
1034 * before proceeding, just so it has time to swallow its
1039 sc->dc_wdog_timer = 5;
1043 dc_hash_maddr_admtek_be(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1045 uint32_t *hashes = arg;
1048 h = dc_mchash_be(LLADDR(sdl));
1050 hashes[0] |= (1 << h);
1052 hashes[1] |= (1 << (h - 32));
1057 struct dc_hash_maddr_admtek_le_ctx {
1058 struct dc_softc *sc;
1063 dc_hash_maddr_admtek_le(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1065 struct dc_hash_maddr_admtek_le_ctx *ctx = arg;
1068 h = dc_mchash_le(ctx->sc, LLADDR(sdl));
1070 ctx->hashes[0] |= (1 << h);
1072 ctx->hashes[1] |= (1 << (h - 32));
1078 dc_setfilt_admtek(struct dc_softc *sc)
1080 uint8_t eaddr[ETHER_ADDR_LEN];
1082 struct dc_hash_maddr_admtek_le_ctx ctx = { sc, { 0, 0 }};
1086 /* Init our MAC address. */
1087 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1088 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1089 eaddr[1] << 8 | eaddr[0]);
1090 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1092 /* If we want promiscuous mode, set the allframes bit. */
1093 if (ifp->if_flags & IFF_PROMISC)
1094 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1096 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1098 if (ifp->if_flags & IFF_ALLMULTI)
1099 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1101 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1103 /* First, zot all the existing hash bits. */
1104 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1105 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1108 * If we're already in promisc or allmulti mode, we
1109 * don't have to bother programming the multicast filter.
1111 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1114 /* Now program new ones. */
1115 if (DC_IS_CENTAUR(sc))
1116 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_le, &ctx);
1118 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, &ctx.hashes);
1120 CSR_WRITE_4(sc, DC_AL_MAR0, ctx.hashes[0]);
1121 CSR_WRITE_4(sc, DC_AL_MAR1, ctx.hashes[1]);
1125 dc_setfilt_asix(struct dc_softc *sc)
1127 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1129 uint32_t hashes[2] = { 0, 0 };
1133 /* Init our MAC address. */
1134 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1135 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1136 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1137 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1138 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1140 /* If we want promiscuous mode, set the allframes bit. */
1141 if (ifp->if_flags & IFF_PROMISC)
1142 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1144 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1146 if (ifp->if_flags & IFF_ALLMULTI)
1147 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1149 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1152 * The ASIX chip has a special bit to enable reception
1153 * of broadcast frames.
1155 if (ifp->if_flags & IFF_BROADCAST)
1156 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1158 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1160 /* first, zot all the existing hash bits */
1161 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1162 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1163 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1164 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1167 * If we're already in promisc or allmulti mode, we
1168 * don't have to bother programming the multicast filter.
1170 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1173 /* now program new ones */
1174 if_foreach_llmaddr(ifp, dc_hash_maddr_admtek_be, hashes);
1176 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1177 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1178 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1179 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1183 dc_hash_maddr_uli(void *arg, struct sockaddr_dl *sdl, u_int mcnt)
1185 uint32_t **sp = arg;
1188 if (mcnt == DC_ULI_FILTER_NPERF)
1191 *(*sp)++ = DC_SP_MAC(ma[1] << 8 | ma[0]);
1192 *(*sp)++ = DC_SP_MAC(ma[3] << 8 | ma[2]);
1193 *(*sp)++ = DC_SP_MAC(ma[5] << 8 | ma[4]);
1199 dc_setfilt_uli(struct dc_softc *sc)
1201 uint8_t eaddr[ETHER_ADDR_LEN];
1203 struct dc_desc *sframe;
1204 uint32_t filter, *sp;
1209 i = sc->dc_cdata.dc_tx_prod;
1210 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1211 sc->dc_cdata.dc_tx_cnt++;
1212 sframe = &sc->dc_ldata.dc_tx_list[i];
1213 sp = sc->dc_cdata.dc_sbuf;
1214 bzero(sp, DC_SFRAME_LEN);
1216 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1217 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1218 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT);
1220 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1222 /* Set station address. */
1223 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1224 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]);
1225 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]);
1226 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]);
1228 /* Set broadcast address. */
1229 *sp++ = DC_SP_MAC(0xFFFF);
1230 *sp++ = DC_SP_MAC(0xFFFF);
1231 *sp++ = DC_SP_MAC(0xFFFF);
1233 /* Extract current filter configuration. */
1234 filter = CSR_READ_4(sc, DC_NETCFG);
1235 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI);
1237 /* Now build perfect filters. */
1238 mcnt = if_foreach_llmaddr(ifp, dc_hash_maddr_uli, &sp);
1240 if (mcnt == DC_ULI_FILTER_NPERF)
1241 filter |= DC_NETCFG_RX_ALLMULTI;
1243 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) {
1244 *sp++ = DC_SP_MAC(0xFFFF);
1245 *sp++ = DC_SP_MAC(0xFFFF);
1246 *sp++ = DC_SP_MAC(0xFFFF);
1249 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1250 CSR_WRITE_4(sc, DC_NETCFG,
1251 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1252 if (ifp->if_flags & IFF_PROMISC)
1253 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI;
1254 if (ifp->if_flags & IFF_ALLMULTI)
1255 filter |= DC_NETCFG_RX_ALLMULTI;
1256 CSR_WRITE_4(sc, DC_NETCFG,
1257 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1258 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1259 CSR_WRITE_4(sc, DC_NETCFG, filter);
1261 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1262 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1263 BUS_DMASYNC_PREWRITE);
1264 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1265 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1272 sc->dc_wdog_timer = 5;
1276 dc_hash_maddr_xircom(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1278 struct dc_softc *sc = arg;
1281 h = dc_mchash_le(sc, LLADDR(sdl));
1282 sc->dc_cdata.dc_sbuf[h >> 4] |= htole32(1 << (h & 0xF));
1287 dc_setfilt_xircom(struct dc_softc *sc)
1289 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1291 struct dc_desc *sframe;
1296 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1298 i = sc->dc_cdata.dc_tx_prod;
1299 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1300 sc->dc_cdata.dc_tx_cnt++;
1301 sframe = &sc->dc_ldata.dc_tx_list[i];
1302 sp = sc->dc_cdata.dc_sbuf;
1303 bzero(sp, DC_SFRAME_LEN);
1305 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1306 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1307 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1309 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1311 /* If we want promiscuous mode, set the allframes bit. */
1312 if (ifp->if_flags & IFF_PROMISC)
1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1315 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1317 if (ifp->if_flags & IFF_ALLMULTI)
1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1320 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1322 if_foreach_llmaddr(ifp, dc_hash_maddr_xircom, &sp);
1324 if (ifp->if_flags & IFF_BROADCAST) {
1325 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1326 sp[h >> 4] |= htole32(1 << (h & 0xF));
1329 /* Set our MAC address. */
1330 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1331 sp[0] = DC_SP_MAC(eaddr[0]);
1332 sp[1] = DC_SP_MAC(eaddr[1]);
1333 sp[2] = DC_SP_MAC(eaddr[2]);
1335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1336 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1337 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1338 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1339 BUS_DMASYNC_PREWRITE);
1340 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1341 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1348 sc->dc_wdog_timer = 5;
1352 dc_setfilt(struct dc_softc *sc)
1355 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1356 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1357 dc_setfilt_21143(sc);
1360 dc_setfilt_asix(sc);
1362 if (DC_IS_ADMTEK(sc))
1363 dc_setfilt_admtek(sc);
1368 if (DC_IS_XIRCOM(sc))
1369 dc_setfilt_xircom(sc);
1373 dc_netcfg_wait(struct dc_softc *sc)
1378 for (i = 0; i < DC_TIMEOUT; i++) {
1379 isr = CSR_READ_4(sc, DC_ISR);
1380 if (isr & DC_ISR_TX_IDLE &&
1381 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1382 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1386 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) {
1387 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1388 device_printf(sc->dc_dev,
1389 "%s: failed to force tx to idle state\n", __func__);
1390 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1391 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1392 !DC_HAS_BROKEN_RXSTATE(sc))
1393 device_printf(sc->dc_dev,
1394 "%s: failed to force rx to idle state\n", __func__);
1399 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1400 * the netconfig register, we first have to put the transmit and/or
1401 * receive logic in the idle state.
1404 dc_setcfg(struct dc_softc *sc, int media)
1406 int restart = 0, watchdogreg;
1408 if (IFM_SUBTYPE(media) == IFM_NONE)
1411 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1413 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1417 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1420 if (sc->dc_pmode == DC_PMODE_MII) {
1421 if (DC_IS_INTEL(sc)) {
1422 /* There's a write enable bit here that reads as 1. */
1423 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1424 watchdogreg &= ~DC_WDOG_CTLWREN;
1425 watchdogreg |= DC_WDOG_JABBERDIS;
1426 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1428 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1430 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1431 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1432 if (sc->dc_type == DC_TYPE_98713)
1433 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1434 DC_NETCFG_SCRAMBLER));
1435 if (!DC_IS_DAVICOM(sc))
1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1437 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1439 if (DC_IS_PNIC(sc)) {
1440 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1441 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1442 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1450 if (IFM_SUBTYPE(media) == IFM_10_T) {
1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1453 if (sc->dc_pmode == DC_PMODE_MII) {
1454 /* There's a write enable bit here that reads as 1. */
1455 if (DC_IS_INTEL(sc)) {
1456 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1457 watchdogreg &= ~DC_WDOG_CTLWREN;
1458 watchdogreg |= DC_WDOG_JABBERDIS;
1459 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1461 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1463 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1464 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1465 if (sc->dc_type == DC_TYPE_98713)
1466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1467 if (!DC_IS_DAVICOM(sc))
1468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1469 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1471 if (DC_IS_PNIC(sc)) {
1472 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1473 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1474 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1479 if (DC_IS_INTEL(sc)) {
1480 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1481 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1482 if ((media & IFM_GMASK) == IFM_FDX)
1483 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1485 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1486 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1487 DC_CLRBIT(sc, DC_10BTCTRL,
1488 DC_TCTL_AUTONEGENBL);
1495 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1496 * PHY and we want HomePNA mode, set the portsel bit to turn
1497 * on the external MII port.
1499 if (DC_IS_DAVICOM(sc)) {
1500 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1504 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1508 if ((media & IFM_GMASK) == IFM_FDX) {
1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1510 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1511 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1513 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1514 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1515 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1519 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1523 dc_reset(struct dc_softc *sc)
1527 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1529 for (i = 0; i < DC_TIMEOUT; i++) {
1531 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1535 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1536 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) {
1538 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1542 if (i == DC_TIMEOUT)
1543 device_printf(sc->dc_dev, "reset never completed!\n");
1545 /* Wait a little while for the chip to get its brains in order. */
1548 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1549 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1550 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1553 * Bring the SIA out of reset. In some cases, it looks
1554 * like failing to unreset the SIA soon enough gets it
1555 * into a state where it will never come out of reset
1556 * until we reset the whole chip again.
1558 if (DC_IS_INTEL(sc)) {
1559 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1560 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF);
1561 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1565 static const struct dc_type *
1566 dc_devtype(device_t dev)
1568 const struct dc_type *t;
1573 devid = pci_get_devid(dev);
1574 rev = pci_get_revid(dev);
1576 while (t->dc_name != NULL) {
1577 if (devid == t->dc_devid && rev >= t->dc_minrev)
1586 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1587 * IDs against our list and return a device name if we find a match.
1588 * We do a little bit of extra work to identify the exact type of
1589 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1590 * but different revision IDs. The same is true for 98715/98715A
1591 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1592 * cases, the exact chip revision affects driver behavior.
1595 dc_probe(device_t dev)
1597 const struct dc_type *t;
1599 t = dc_devtype(dev);
1602 device_set_desc(dev, t->dc_name);
1603 return (BUS_PROBE_DEFAULT);
1610 dc_apply_fixup(struct dc_softc *sc, int media)
1612 struct dc_mediainfo *m;
1620 if (m->dc_media == media)
1628 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1629 reg = (p[0] | (p[1] << 8)) << 16;
1630 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1633 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1634 reg = (p[0] | (p[1] << 8)) << 16;
1635 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1640 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1642 struct dc_mediainfo *m;
1644 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1646 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1649 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1650 case DC_SIA_CODE_10BT:
1651 m->dc_media = IFM_10_T;
1653 case DC_SIA_CODE_10BT_FDX:
1654 m->dc_media = IFM_10_T | IFM_FDX;
1656 case DC_SIA_CODE_10B2:
1657 m->dc_media = IFM_10_2;
1659 case DC_SIA_CODE_10B5:
1660 m->dc_media = IFM_10_5;
1667 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1668 * Things apparently already work for cards that do
1669 * supply Media Specific Data.
1671 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1674 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1678 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1681 m->dc_next = sc->dc_mi;
1684 sc->dc_pmode = DC_PMODE_SIA;
1689 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1691 struct dc_mediainfo *m;
1693 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1695 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1698 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1699 m->dc_media = IFM_100_TX;
1701 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1702 m->dc_media = IFM_100_TX | IFM_FDX;
1705 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
1707 m->dc_next = sc->dc_mi;
1710 sc->dc_pmode = DC_PMODE_SYM;
1715 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1717 struct dc_mediainfo *m;
1720 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1722 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1725 /* We abuse IFM_AUTO to represent MII. */
1726 m->dc_media = IFM_AUTO;
1727 m->dc_gp_len = l->dc_gpr_len;
1730 p += sizeof(struct dc_eblock_mii);
1732 p += 2 * l->dc_gpr_len;
1733 m->dc_reset_len = *p;
1735 m->dc_reset_ptr = p;
1737 m->dc_next = sc->dc_mi;
1743 dc_read_srom(struct dc_softc *sc, int bits)
1747 size = DC_ROM_SIZE(bits);
1748 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
1749 if (sc->dc_srom == NULL) {
1750 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n");
1753 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1758 dc_parse_21143_srom(struct dc_softc *sc)
1760 struct dc_leaf_hdr *lhdr;
1761 struct dc_eblock_hdr *hdr;
1762 int error, have_mii, i, loff;
1766 loff = sc->dc_srom[27];
1767 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1770 ptr += sizeof(struct dc_leaf_hdr) - 1;
1772 * Look if we got a MII media block.
1774 for (i = 0; i < lhdr->dc_mcnt; i++) {
1775 hdr = (struct dc_eblock_hdr *)ptr;
1776 if (hdr->dc_type == DC_EBLOCK_MII)
1779 ptr += (hdr->dc_len & 0x7F);
1784 * Do the same thing again. Only use SIA and SYM media
1785 * blocks if no MII media block is available.
1788 ptr += sizeof(struct dc_leaf_hdr) - 1;
1790 for (i = 0; i < lhdr->dc_mcnt; i++) {
1791 hdr = (struct dc_eblock_hdr *)ptr;
1792 switch (hdr->dc_type) {
1794 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1798 error = dc_decode_leaf_sia(sc,
1799 (struct dc_eblock_sia *)hdr);
1803 error = dc_decode_leaf_sym(sc,
1804 (struct dc_eblock_sym *)hdr);
1807 /* Don't care. Yet. */
1810 ptr += (hdr->dc_len & 0x7F);
1817 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1822 ("%s: wrong number of segments (%d)", __func__, nseg));
1824 *paddr = segs->ds_addr;
1828 dc_dma_alloc(struct dc_softc *sc)
1832 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0,
1833 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1834 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1835 NULL, NULL, &sc->dc_ptag);
1837 device_printf(sc->dc_dev,
1838 "failed to allocate parent DMA tag\n");
1842 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1843 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1844 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1,
1845 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag);
1847 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n");
1851 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1852 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1,
1853 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag);
1855 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n");
1859 /* RX descriptor list. */
1860 error = bus_dmamem_alloc(sc->dc_rx_ltag,
1861 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT |
1862 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap);
1864 device_printf(sc->dc_dev,
1865 "failed to allocate DMA'able memory for RX list\n");
1868 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap,
1869 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr,
1870 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT);
1872 device_printf(sc->dc_dev,
1873 "failed to load DMA'able memory for RX list\n");
1876 /* TX descriptor list. */
1877 error = bus_dmamem_alloc(sc->dc_tx_ltag,
1878 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT |
1879 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap);
1881 device_printf(sc->dc_dev,
1882 "failed to allocate DMA'able memory for TX list\n");
1885 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap,
1886 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr,
1887 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT);
1889 device_printf(sc->dc_dev,
1890 "cannot load DMA'able memory for TX list\n");
1895 * Allocate a busdma tag and DMA safe memory for the multicast
1898 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1899 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1900 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
1901 0, NULL, NULL, &sc->dc_stag);
1903 device_printf(sc->dc_dev,
1904 "failed to create DMA tag for setup frame\n");
1907 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
1908 BUS_DMA_NOWAIT, &sc->dc_smap);
1910 device_printf(sc->dc_dev,
1911 "failed to allocate DMA'able memory for setup frame\n");
1914 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
1915 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
1917 device_printf(sc->dc_dev,
1918 "cannot load DMA'able memory for setup frame\n");
1922 /* Allocate a busdma tag for RX mbufs. */
1923 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0,
1924 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1925 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag);
1927 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n");
1931 /* Allocate a busdma tag for TX mbufs. */
1932 error = bus_dma_tag_create(sc->dc_ptag, 1, 0,
1933 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1934 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
1935 0, NULL, NULL, &sc->dc_tx_mtag);
1937 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n");
1941 /* Create the TX/RX busdma maps. */
1942 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1943 error = bus_dmamap_create(sc->dc_tx_mtag, 0,
1944 &sc->dc_cdata.dc_tx_map[i]);
1946 device_printf(sc->dc_dev,
1947 "failed to create TX mbuf dmamap\n");
1951 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1952 error = bus_dmamap_create(sc->dc_rx_mtag, 0,
1953 &sc->dc_cdata.dc_rx_map[i]);
1955 device_printf(sc->dc_dev,
1956 "failed to create RX mbuf dmamap\n");
1960 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap);
1962 device_printf(sc->dc_dev,
1963 "failed to create spare RX mbuf dmamap\n");
1972 dc_dma_free(struct dc_softc *sc)
1977 if (sc->dc_rx_mtag != NULL) {
1978 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1979 if (sc->dc_cdata.dc_rx_map[i] != NULL)
1980 bus_dmamap_destroy(sc->dc_rx_mtag,
1981 sc->dc_cdata.dc_rx_map[i]);
1983 if (sc->dc_sparemap != NULL)
1984 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap);
1985 bus_dma_tag_destroy(sc->dc_rx_mtag);
1989 if (sc->dc_rx_mtag != NULL) {
1990 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1991 if (sc->dc_cdata.dc_tx_map[i] != NULL)
1992 bus_dmamap_destroy(sc->dc_tx_mtag,
1993 sc->dc_cdata.dc_tx_map[i]);
1995 bus_dma_tag_destroy(sc->dc_tx_mtag);
1998 /* RX descriptor list. */
1999 if (sc->dc_rx_ltag) {
2000 if (sc->dc_ldata.dc_rx_list_paddr != 0)
2001 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap);
2002 if (sc->dc_ldata.dc_rx_list != NULL)
2003 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list,
2005 bus_dma_tag_destroy(sc->dc_rx_ltag);
2008 /* TX descriptor list. */
2009 if (sc->dc_tx_ltag) {
2010 if (sc->dc_ldata.dc_tx_list_paddr != 0)
2011 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap);
2012 if (sc->dc_ldata.dc_tx_list != NULL)
2013 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list,
2015 bus_dma_tag_destroy(sc->dc_tx_ltag);
2018 /* multicast setup frame. */
2020 if (sc->dc_saddr != 0)
2021 bus_dmamap_unload(sc->dc_stag, sc->dc_smap);
2022 if (sc->dc_cdata.dc_sbuf != NULL)
2023 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf,
2025 bus_dma_tag_destroy(sc->dc_stag);
2030 * Attach the interface. Allocate softc structures, do ifmedia
2031 * setup and ethernet/BPF attach.
2034 dc_attach(device_t dev)
2036 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
2038 struct dc_softc *sc;
2040 struct dc_mediainfo *m;
2041 uint32_t reg, revision;
2043 int error, mac_offset, n, phy, rid, tmp;
2046 sc = device_get_softc(dev);
2049 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2053 * Map control/status registers.
2055 pci_enable_busmaster(dev);
2058 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
2060 if (sc->dc_res == NULL) {
2061 device_printf(dev, "couldn't map ports/memory\n");
2066 sc->dc_btag = rman_get_bustag(sc->dc_res);
2067 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2069 /* Allocate interrupt. */
2071 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2072 RF_SHAREABLE | RF_ACTIVE);
2074 if (sc->dc_irq == NULL) {
2075 device_printf(dev, "couldn't map interrupt\n");
2080 /* Need this info to decide on a chip type. */
2081 sc->dc_info = dc_devtype(dev);
2082 revision = pci_get_revid(dev);
2085 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
2086 if (sc->dc_info->dc_devid !=
2087 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
2088 sc->dc_info->dc_devid !=
2089 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
2090 dc_eeprom_width(sc);
2092 switch (sc->dc_info->dc_devid) {
2093 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
2094 sc->dc_type = DC_TYPE_21143;
2095 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2096 sc->dc_flags |= DC_REDUCED_MII_POLL;
2097 /* Save EEPROM contents so we can parse them later. */
2098 error = dc_read_srom(sc, sc->dc_romwidth);
2102 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
2103 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
2104 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
2105 sc->dc_type = DC_TYPE_DM9102;
2106 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
2107 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
2108 sc->dc_flags |= DC_TX_ALIGN;
2109 sc->dc_pmode = DC_PMODE_MII;
2111 /* Increase the latency timer value. */
2112 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
2114 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
2115 sc->dc_type = DC_TYPE_AL981;
2116 sc->dc_flags |= DC_TX_USE_TX_INTR;
2117 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2118 sc->dc_pmode = DC_PMODE_MII;
2119 error = dc_read_srom(sc, sc->dc_romwidth);
2123 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983):
2124 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
2125 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
2126 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
2127 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
2128 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
2129 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
2130 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
2131 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
2132 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
2133 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
2134 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
2135 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
2136 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
2137 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
2138 sc->dc_type = DC_TYPE_AN983;
2139 sc->dc_flags |= DC_64BIT_HASH;
2140 sc->dc_flags |= DC_TX_USE_TX_INTR;
2141 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2142 sc->dc_pmode = DC_PMODE_MII;
2143 /* Don't read SROM for - auto-loaded on reset */
2145 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
2146 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
2147 if (revision < DC_REVISION_98713A) {
2148 sc->dc_type = DC_TYPE_98713;
2150 if (revision >= DC_REVISION_98713A) {
2151 sc->dc_type = DC_TYPE_98713A;
2152 sc->dc_flags |= DC_21143_NWAY;
2154 sc->dc_flags |= DC_REDUCED_MII_POLL;
2155 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2157 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
2158 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
2160 * Macronix MX98715AEC-C/D/E parts have only a
2161 * 128-bit hash table. We need to deal with these
2162 * in the same manner as the PNIC II so that we
2163 * get the right number of bits out of the
2166 if (revision >= DC_REVISION_98715AEC_C &&
2167 revision < DC_REVISION_98725)
2168 sc->dc_flags |= DC_128BIT_HASH;
2169 sc->dc_type = DC_TYPE_987x5;
2170 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2171 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2173 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
2174 sc->dc_type = DC_TYPE_987x5;
2175 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2176 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2178 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
2179 sc->dc_type = DC_TYPE_PNICII;
2180 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
2181 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2183 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
2184 sc->dc_type = DC_TYPE_PNIC;
2185 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
2186 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
2187 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2188 if (sc->dc_pnic_rx_buf == NULL) {
2189 device_printf(sc->dc_dev,
2190 "Could not allocate PNIC RX buffer\n");
2194 if (revision < DC_REVISION_82C169)
2195 sc->dc_pmode = DC_PMODE_SYM;
2197 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
2198 sc->dc_type = DC_TYPE_ASIX;
2199 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
2200 sc->dc_flags |= DC_REDUCED_MII_POLL;
2201 sc->dc_pmode = DC_PMODE_MII;
2203 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
2204 sc->dc_type = DC_TYPE_XIRCOM;
2205 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2208 * We don't actually need to coalesce, but we're doing
2209 * it to obtain a double word aligned buffer.
2210 * The DC_TX_COALESCE flag is required.
2212 sc->dc_pmode = DC_PMODE_MII;
2214 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
2215 sc->dc_type = DC_TYPE_CONEXANT;
2216 sc->dc_flags |= DC_TX_INTR_ALWAYS;
2217 sc->dc_flags |= DC_REDUCED_MII_POLL;
2218 sc->dc_pmode = DC_PMODE_MII;
2219 error = dc_read_srom(sc, sc->dc_romwidth);
2223 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261):
2224 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263):
2225 if (sc->dc_info->dc_devid ==
2226 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261))
2227 sc->dc_type = DC_TYPE_ULI_M5261;
2229 sc->dc_type = DC_TYPE_ULI_M5263;
2230 /* TX buffers should be aligned on 4 byte boundary. */
2231 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2233 sc->dc_pmode = DC_PMODE_MII;
2234 error = dc_read_srom(sc, sc->dc_romwidth);
2239 device_printf(dev, "unknown device: %x\n",
2240 sc->dc_info->dc_devid);
2244 /* Save the cache line size. */
2245 if (DC_IS_DAVICOM(sc))
2246 sc->dc_cachesize = 0;
2248 sc->dc_cachesize = pci_get_cachelnsz(dev);
2250 /* Reset the adapter. */
2253 /* Take 21143 out of snooze mode */
2254 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2255 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2256 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2257 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2261 * Try to learn something about the supported media.
2262 * We know that ASIX and ADMtek and Davicom devices
2263 * will *always* be using MII media, so that's a no-brainer.
2264 * The tricky ones are the Macronix/PNIC II and the
2267 if (DC_IS_INTEL(sc)) {
2268 error = dc_parse_21143_srom(sc);
2271 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2272 if (sc->dc_type == DC_TYPE_98713)
2273 sc->dc_pmode = DC_PMODE_MII;
2275 sc->dc_pmode = DC_PMODE_SYM;
2276 } else if (!sc->dc_pmode)
2277 sc->dc_pmode = DC_PMODE_MII;
2280 * Get station address from the EEPROM.
2282 switch(sc->dc_type) {
2284 case DC_TYPE_98713A:
2286 case DC_TYPE_PNICII:
2287 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2288 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2289 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2292 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2294 case DC_TYPE_DM9102:
2295 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2298 * If this is an onboard dc(4) the station address read from
2299 * the EEPROM is all zero and we have to get it from the FCode.
2301 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2302 OF_getetheraddr(dev, (caddr_t)&eaddr);
2307 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2311 reg = CSR_READ_4(sc, DC_AL_PAR0);
2312 mac = (uint8_t *)&eaddr[0];
2313 mac[0] = (reg >> 0) & 0xff;
2314 mac[1] = (reg >> 8) & 0xff;
2315 mac[2] = (reg >> 16) & 0xff;
2316 mac[3] = (reg >> 24) & 0xff;
2317 reg = CSR_READ_4(sc, DC_AL_PAR1);
2318 mac[4] = (reg >> 0) & 0xff;
2319 mac[5] = (reg >> 8) & 0xff;
2321 case DC_TYPE_CONEXANT:
2322 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2325 case DC_TYPE_XIRCOM:
2326 /* The MAC comes from the CIS. */
2327 mac = pci_get_ether(dev);
2329 device_printf(dev, "No station address in CIS!\n");
2333 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2335 case DC_TYPE_ULI_M5261:
2336 case DC_TYPE_ULI_M5263:
2337 srom = (uint16_t *)sc->dc_srom;
2338 if (srom == NULL || *srom == 0xFFFF || *srom == 0) {
2340 * No valid SROM present, read station address
2344 "Reading station address from ID Table.\n");
2345 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000);
2346 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0);
2347 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2348 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010);
2349 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2350 CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2351 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0);
2352 mac = (uint8_t *)eaddr;
2353 for (n = 0; n < ETHER_ADDR_LEN; n++)
2354 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);
2355 CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2356 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000);
2359 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3,
2363 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2367 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr));
2369 * If we still have invalid station address, see whether we can
2370 * find station address for chip 0. Some multi-port controllers
2371 * just store station address for chip 0 if they have a shared
2374 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) ||
2375 (sc->dc_eaddr[0] == 0xffffffff &&
2376 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) {
2377 error = dc_check_multiport(sc);
2379 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr));
2380 /* Extract media information. */
2381 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) {
2382 while (sc->dc_mi != NULL) {
2383 m = sc->dc_mi->dc_next;
2384 free(sc->dc_mi, M_DEVBUF);
2387 error = dc_parse_21143_srom(sc);
2391 } else if (error == ENOMEM)
2397 if ((error = dc_dma_alloc(sc)) != 0)
2400 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2402 device_printf(dev, "can not if_alloc()\n");
2407 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2408 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2409 ifp->if_ioctl = dc_ioctl;
2410 ifp->if_start = dc_start;
2411 ifp->if_init = dc_init;
2412 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2413 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2414 IFQ_SET_READY(&ifp->if_snd);
2417 * Do MII setup. If this is a 21143, check for a PHY on the
2418 * MII bus after applying any necessary fixups to twiddle the
2419 * GPIO bits. If we don't end up finding a PHY, restore the
2420 * old selection (SIA only or SIA/SYM) and attach the dcphy
2424 if (DC_IS_INTEL(sc)) {
2425 dc_apply_fixup(sc, IFM_AUTO);
2427 sc->dc_pmode = DC_PMODE_MII;
2431 * Setup General Purpose port mode and data so the tulip can talk
2432 * to the MII. This needs to be done before mii_attach so that
2433 * we can actually see them.
2435 if (DC_IS_XIRCOM(sc)) {
2436 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2437 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2439 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2440 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2446 * Note: both the AL981 and AN983 have internal PHYs, however the
2447 * AL981 provides direct access to the PHY registers while the AN983
2448 * uses a serial MII interface. The AN983's MII interface is also
2449 * buggy in that you can read from any MII address (0 to 31), but
2450 * only address 1 behaves normally. To deal with both cases, we
2451 * pretend that the PHY is at MII address 1.
2453 if (DC_IS_ADMTEK(sc))
2454 phy = DC_ADMTEK_PHYADDR;
2457 * Note: the ukphy probes of the RS7112 report a PHY at MII address
2458 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the
2461 if (DC_IS_CONEXANT(sc))
2462 phy = DC_CONEXANT_PHYADDR;
2464 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2465 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
2467 if (error && DC_IS_INTEL(sc)) {
2469 if (sc->dc_pmode != DC_PMODE_SIA)
2470 sc->dc_pmode = DC_PMODE_SYM;
2471 sc->dc_flags |= DC_21143_NWAY;
2473 * For non-MII cards, we need to have the 21143
2474 * drive the LEDs. Except there are some systems
2475 * like the NEC VersaPro NoteBook PC which have no
2476 * LEDs, and twiddling these bits has adverse effects
2477 * on them. (I.e. you suddenly can't get a link.)
2479 if (!(pci_get_subvendor(dev) == 0x1033 &&
2480 pci_get_subdevice(dev) == 0x8028))
2481 sc->dc_flags |= DC_TULIP_LEDS;
2482 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2483 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
2488 device_printf(dev, "attaching PHYs failed\n");
2492 if (DC_IS_ADMTEK(sc)) {
2494 * Set automatic TX underrun recovery for the ADMtek chips
2496 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2500 * Tell the upper layer(s) we support long frames.
2502 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2503 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2504 ifp->if_capenable = ifp->if_capabilities;
2505 #ifdef DEVICE_POLLING
2506 ifp->if_capabilities |= IFCAP_POLLING;
2509 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2510 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2513 * Call MI attach routine.
2515 ether_ifattach(ifp, (caddr_t)eaddr);
2517 /* Hook interrupt last to avoid having to lock softc */
2518 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2519 NULL, dc_intr, sc, &sc->dc_intrhand);
2522 device_printf(dev, "couldn't set up irq\n");
2523 ether_ifdetach(ifp);
2534 * Shutdown hardware and free up resources. This can be called any
2535 * time after the mutex has been initialized. It is called in both
2536 * the error case in attach and the normal detach case so it needs
2537 * to be careful about only freeing resources that have actually been
2541 dc_detach(device_t dev)
2543 struct dc_softc *sc;
2545 struct dc_mediainfo *m;
2547 sc = device_get_softc(dev);
2548 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2552 #ifdef DEVICE_POLLING
2553 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
2554 ether_poll_deregister(ifp);
2557 /* These should only be active if attach succeeded */
2558 if (device_is_attached(dev)) {
2562 callout_drain(&sc->dc_stat_ch);
2563 callout_drain(&sc->dc_wdog_ch);
2564 ether_ifdetach(ifp);
2567 device_delete_child(dev, sc->dc_miibus);
2568 bus_generic_detach(dev);
2570 if (sc->dc_intrhand)
2571 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2573 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2575 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2582 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2584 while (sc->dc_mi != NULL) {
2585 m = sc->dc_mi->dc_next;
2586 free(sc->dc_mi, M_DEVBUF);
2589 free(sc->dc_srom, M_DEVBUF);
2591 mtx_destroy(&sc->dc_mtx);
2597 * Initialize the transmit descriptors.
2600 dc_list_tx_init(struct dc_softc *sc)
2602 struct dc_chain_data *cd;
2603 struct dc_list_data *ld;
2608 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2609 if (i == DC_TX_LIST_CNT - 1)
2613 ld->dc_tx_list[i].dc_status = 0;
2614 ld->dc_tx_list[i].dc_ctl = 0;
2615 ld->dc_tx_list[i].dc_data = 0;
2616 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2617 cd->dc_tx_chain[i] = NULL;
2620 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2622 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
2623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2628 * Initialize the RX descriptors and allocate mbufs for them. Note that
2629 * we arrange the descriptors in a closed ring, so that the last descriptor
2630 * points back to the first.
2633 dc_list_rx_init(struct dc_softc *sc)
2635 struct dc_chain_data *cd;
2636 struct dc_list_data *ld;
2642 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2643 if (dc_newbuf(sc, i) != 0)
2645 if (i == DC_RX_LIST_CNT - 1)
2649 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2653 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2654 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2659 * Initialize an RX descriptor and attach an MBUF cluster.
2662 dc_newbuf(struct dc_softc *sc, int i)
2666 bus_dma_segment_t segs[1];
2669 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2672 m->m_len = m->m_pkthdr.len = MCLBYTES;
2673 m_adj(m, sizeof(u_int64_t));
2676 * If this is a PNIC chip, zero the buffer. This is part
2677 * of the workaround for the receive bug in the 82c168 and
2680 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2681 bzero(mtod(m, char *), m->m_len);
2683 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap,
2689 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__,
2691 if (sc->dc_cdata.dc_rx_chain[i] != NULL)
2692 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]);
2694 map = sc->dc_cdata.dc_rx_map[i];
2695 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2696 sc->dc_sparemap = map;
2697 sc->dc_cdata.dc_rx_chain[i] = m;
2698 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2699 BUS_DMASYNC_PREREAD);
2701 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2702 sc->dc_ldata.dc_rx_list[i].dc_data =
2703 htole32(DC_ADDR_LO(segs[0].ds_addr));
2704 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2705 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2712 * The PNIC chip has a terrible bug in it that manifests itself during
2713 * periods of heavy activity. The exact mode of failure if difficult to
2714 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2715 * will happen on slow machines. The bug is that sometimes instead of
2716 * uploading one complete frame during reception, it uploads what looks
2717 * like the entire contents of its FIFO memory. The frame we want is at
2718 * the end of the whole mess, but we never know exactly how much data has
2719 * been uploaded, so salvaging the frame is hard.
2721 * There is only one way to do it reliably, and it's disgusting.
2722 * Here's what we know:
2724 * - We know there will always be somewhere between one and three extra
2725 * descriptors uploaded.
2727 * - We know the desired received frame will always be at the end of the
2728 * total data upload.
2730 * - We know the size of the desired received frame because it will be
2731 * provided in the length field of the status word in the last descriptor.
2733 * Here's what we do:
2735 * - When we allocate buffers for the receive ring, we bzero() them.
2736 * This means that we know that the buffer contents should be all
2737 * zeros, except for data uploaded by the chip.
2739 * - We also force the PNIC chip to upload frames that include the
2740 * ethernet CRC at the end.
2742 * - We gather all of the bogus frame data into a single buffer.
2744 * - We then position a pointer at the end of this buffer and scan
2745 * backwards until we encounter the first non-zero byte of data.
2746 * This is the end of the received frame. We know we will encounter
2747 * some data at the end of the frame because the CRC will always be
2748 * there, so even if the sender transmits a packet of all zeros,
2749 * we won't be fooled.
2751 * - We know the size of the actual received frame, so we subtract
2752 * that value from the current pointer location. This brings us
2753 * to the start of the actual received packet.
2755 * - We copy this into an mbuf and pass it on, along with the actual
2758 * The performance hit is tremendous, but it beats dropping frames all
2762 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2764 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2766 struct dc_desc *cur_rx;
2767 struct dc_desc *c = NULL;
2768 struct mbuf *m = NULL;
2771 uint32_t rxstat = 0;
2773 i = sc->dc_pnic_rx_bug_save;
2774 cur_rx = &sc->dc_ldata.dc_rx_list[idx];
2775 ptr = sc->dc_pnic_rx_buf;
2776 bzero(ptr, DC_RXLEN * 5);
2778 /* Copy all the bytes from the bogus buffers. */
2780 c = &sc->dc_ldata.dc_rx_list[i];
2781 rxstat = le32toh(c->dc_status);
2782 m = sc->dc_cdata.dc_rx_chain[i];
2783 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2785 /* If this is the last buffer, break out. */
2786 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2788 dc_discard_rxbuf(sc, i);
2789 DC_INC(i, DC_RX_LIST_CNT);
2792 /* Find the length of the actual receive frame. */
2793 total_len = DC_RXBYTES(rxstat);
2795 /* Scan backwards until we hit a non-zero byte. */
2796 while (*ptr == 0x00)
2800 if ((uintptr_t)(ptr) & 0x3)
2803 /* Now find the start of the frame. */
2805 if (ptr < sc->dc_pnic_rx_buf)
2806 ptr = sc->dc_pnic_rx_buf;
2809 * Now copy the salvaged frame to the last mbuf and fake up
2810 * the status word to make it look like a successful
2813 bcopy(ptr, mtod(m, char *), total_len);
2814 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2818 * This routine searches the RX ring for dirty descriptors in the
2819 * event that the rxeof routine falls out of sync with the chip's
2820 * current descriptor pointer. This may happen sometimes as a result
2821 * of a "no RX buffer available" condition that happens when the chip
2822 * consumes all of the RX buffers before the driver has a chance to
2823 * process the RX ring. This routine may need to be called more than
2824 * once to bring the driver back in sync with the chip, however we
2825 * should still be getting RX DONE interrupts to drive the search
2826 * for new packets in the RX ring, so we should catch up eventually.
2829 dc_rx_resync(struct dc_softc *sc)
2831 struct dc_desc *cur_rx;
2834 pos = sc->dc_cdata.dc_rx_prod;
2836 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2837 cur_rx = &sc->dc_ldata.dc_rx_list[pos];
2838 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2840 DC_INC(pos, DC_RX_LIST_CNT);
2843 /* If the ring really is empty, then just return. */
2844 if (i == DC_RX_LIST_CNT)
2847 /* We've fallen behing the chip: catch it. */
2848 sc->dc_cdata.dc_rx_prod = pos;
2854 dc_discard_rxbuf(struct dc_softc *sc, int i)
2858 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2859 m = sc->dc_cdata.dc_rx_chain[i];
2860 bzero(mtod(m, char *), m->m_len);
2863 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2864 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2865 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD |
2866 BUS_DMASYNC_PREWRITE);
2870 * A frame has been uploaded: pass the resulting mbuf chain up to
2871 * the higher level protocols.
2874 dc_rxeof(struct dc_softc *sc)
2878 struct dc_desc *cur_rx;
2879 int i, total_len, rx_npkts;
2887 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD |
2888 BUS_DMASYNC_POSTWRITE);
2889 for (i = sc->dc_cdata.dc_rx_prod;
2890 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
2891 DC_INC(i, DC_RX_LIST_CNT)) {
2892 #ifdef DEVICE_POLLING
2893 if (ifp->if_capenable & IFCAP_POLLING) {
2894 if (sc->rxcycles <= 0)
2899 cur_rx = &sc->dc_ldata.dc_rx_list[i];
2900 rxstat = le32toh(cur_rx->dc_status);
2901 if ((rxstat & DC_RXSTAT_OWN) != 0)
2903 m = sc->dc_cdata.dc_rx_chain[i];
2904 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2905 BUS_DMASYNC_POSTREAD);
2906 total_len = DC_RXBYTES(rxstat);
2909 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2910 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2911 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2912 sc->dc_pnic_rx_bug_save = i;
2913 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0)
2915 dc_pnic_rx_bug_war(sc, i);
2916 rxstat = le32toh(cur_rx->dc_status);
2917 total_len = DC_RXBYTES(rxstat);
2922 * If an error occurs, update stats, clear the
2923 * status word and leave the mbuf cluster in place:
2924 * it should simply get re-used next time this descriptor
2925 * comes up in the ring. However, don't report long
2926 * frames as errors since they could be vlans.
2928 if ((rxstat & DC_RXSTAT_RXERR)) {
2929 if (!(rxstat & DC_RXSTAT_GIANT) ||
2930 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2931 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2932 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2933 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2934 if (rxstat & DC_RXSTAT_COLLSEEN)
2935 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
2936 dc_discard_rxbuf(sc, i);
2937 if (rxstat & DC_RXSTAT_CRCERR)
2940 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2947 /* No errors; receive the packet. */
2948 total_len -= ETHER_CRC_LEN;
2949 #ifdef __NO_STRICT_ALIGNMENT
2951 * On architectures without alignment problems we try to
2952 * allocate a new buffer for the receive ring, and pass up
2953 * the one where the packet is already, saving the expensive
2954 * copy done in m_devget().
2955 * If we are on an architecture with alignment problems, or
2956 * if the allocation fails, then use m_devget and leave the
2957 * existing buffer in the receive ring.
2959 if (dc_newbuf(sc, i) != 0) {
2960 dc_discard_rxbuf(sc, i);
2961 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2964 m->m_pkthdr.rcvif = ifp;
2965 m->m_pkthdr.len = m->m_len = total_len;
2970 m0 = m_devget(mtod(m, char *), total_len,
2971 ETHER_ALIGN, ifp, NULL);
2972 dc_discard_rxbuf(sc, i);
2974 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2981 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2983 (*ifp->if_input)(ifp, m);
2987 sc->dc_cdata.dc_rx_prod = i;
2992 * A frame was downloaded to the chip. It's safe for us to clean up
2996 dc_txeof(struct dc_softc *sc)
2998 struct dc_desc *cur_tx;
3001 uint32_t ctl, txstat;
3003 if (sc->dc_cdata.dc_tx_cnt == 0)
3009 * Go through our tx list and free mbufs for those
3010 * frames that have been transmitted.
3012 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD |
3013 BUS_DMASYNC_POSTWRITE);
3015 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod;
3016 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) {
3017 cur_tx = &sc->dc_ldata.dc_tx_list[idx];
3018 txstat = le32toh(cur_tx->dc_status);
3019 ctl = le32toh(cur_tx->dc_ctl);
3021 if (txstat & DC_TXSTAT_OWN)
3024 if (sc->dc_cdata.dc_tx_chain[idx] == NULL)
3027 if (ctl & DC_TXCTL_SETUP) {
3028 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP);
3030 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
3031 BUS_DMASYNC_POSTWRITE);
3033 * Yes, the PNIC is so brain damaged
3034 * that it will sometimes generate a TX
3035 * underrun error while DMAing the RX
3036 * filter setup frame. If we detect this,
3037 * we have to send the setup frame again,
3038 * or else the filter won't be programmed
3041 if (DC_IS_PNIC(sc)) {
3042 if (txstat & DC_TXSTAT_ERRSUM)
3045 sc->dc_cdata.dc_tx_chain[idx] = NULL;
3049 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
3051 * XXX: Why does my Xircom taunt me so?
3052 * For some reason it likes setting the CARRLOST flag
3053 * even when the carrier is there. wtf?!?
3054 * Who knows, but Conexant chips have the
3055 * same problem. Maybe they took lessons
3058 if (/*sc->dc_type == DC_TYPE_21143 &&*/
3059 sc->dc_pmode == DC_PMODE_MII &&
3060 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3061 DC_TXSTAT_NOCARRIER)))
3062 txstat &= ~DC_TXSTAT_ERRSUM;
3064 if (/*sc->dc_type == DC_TYPE_21143 &&*/
3065 sc->dc_pmode == DC_PMODE_MII &&
3066 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3067 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
3068 txstat &= ~DC_TXSTAT_ERRSUM;
3071 if (txstat & DC_TXSTAT_ERRSUM) {
3072 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3073 if (txstat & DC_TXSTAT_EXCESSCOLL)
3074 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
3075 if (txstat & DC_TXSTAT_LATECOLL)
3076 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
3077 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
3078 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3083 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3084 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3);
3086 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3087 BUS_DMASYNC_POSTWRITE);
3088 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3089 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
3090 sc->dc_cdata.dc_tx_chain[idx] = NULL;
3092 sc->dc_cdata.dc_tx_cons = idx;
3094 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3095 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3096 if (sc->dc_cdata.dc_tx_cnt == 0)
3097 sc->dc_wdog_timer = 0;
3100 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3101 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3107 struct dc_softc *sc;
3108 struct mii_data *mii;
3115 mii = device_get_softc(sc->dc_miibus);
3118 * Reclaim transmitted frames for controllers that do
3119 * not generate TX completion interrupt for every frame.
3121 if (sc->dc_flags & DC_TX_USE_TX_INTR)
3124 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
3125 if (sc->dc_flags & DC_21143_NWAY) {
3126 r = CSR_READ_4(sc, DC_10BTSTAT);
3127 if (IFM_SUBTYPE(mii->mii_media_active) ==
3128 IFM_100_TX && (r & DC_TSTAT_LS100)) {
3132 if (IFM_SUBTYPE(mii->mii_media_active) ==
3133 IFM_10_T && (r & DC_TSTAT_LS10)) {
3137 if (sc->dc_link == 0)
3141 * For NICs which never report DC_RXSTATE_WAIT, we
3142 * have to bite the bullet...
3144 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
3145 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
3146 sc->dc_cdata.dc_tx_cnt == 0)
3153 * When the init routine completes, we expect to be able to send
3154 * packets right away, and in fact the network code will send a
3155 * gratuitous ARP the moment the init routine marks the interface
3156 * as running. However, even though the MAC may have been initialized,
3157 * there may be a delay of a few seconds before the PHY completes
3158 * autonegotiation and the link is brought up. Any transmissions
3159 * made during that delay will be lost. Dealing with this is tricky:
3160 * we can't just pause in the init routine while waiting for the
3161 * PHY to come ready since that would bring the whole system to
3162 * a screeching halt for several seconds.
3164 * What we do here is prevent the TX start routine from sending
3165 * any packets until a link has been established. After the
3166 * interface has been initialized, the tick routine will poll
3167 * the state of the PHY until the IFM_ACTIVE flag is set. Until
3168 * that time, packets will stay in the send queue, and once the
3169 * link comes up, they will be flushed out to the wire.
3171 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3172 dc_start_locked(ifp);
3174 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3175 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3177 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3181 * A transmit underrun has occurred. Back off the transmit threshold,
3182 * or switch to store and forward mode if we have to.
3185 dc_tx_underrun(struct dc_softc *sc)
3187 uint32_t netcfg, isr;
3191 netcfg = CSR_READ_4(sc, DC_NETCFG);
3192 device_printf(sc->dc_dev, "TX underrun -- ");
3193 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) {
3194 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) {
3195 printf("using store and forward mode\n");
3196 netcfg |= DC_NETCFG_STORENFWD;
3198 printf("increasing TX threshold\n");
3199 sc->dc_txthresh += DC_TXTHRESH_INC;
3200 netcfg &= ~DC_NETCFG_TX_THRESH;
3201 netcfg |= sc->dc_txthresh;
3204 if (DC_IS_INTEL(sc)) {
3206 * The real 21143 requires that the transmitter be idle
3207 * in order to change the transmit threshold or store
3208 * and forward state.
3210 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON);
3212 for (i = 0; i < DC_TIMEOUT; i++) {
3213 isr = CSR_READ_4(sc, DC_ISR);
3214 if (isr & DC_ISR_TX_IDLE)
3218 if (i == DC_TIMEOUT) {
3219 device_printf(sc->dc_dev,
3220 "%s: failed to force tx to idle state\n",
3226 printf("resetting\n");
3231 CSR_WRITE_4(sc, DC_NETCFG, netcfg);
3232 if (DC_IS_INTEL(sc))
3233 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON);
3235 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3240 #ifdef DEVICE_POLLING
3241 static poll_handler_t dc_poll;
3244 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3246 struct dc_softc *sc = ifp->if_softc;
3251 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3256 sc->rxcycles = count;
3257 rx_npkts = dc_rxeof(sc);
3259 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3260 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3261 dc_start_locked(ifp);
3263 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3266 status = CSR_READ_4(sc, DC_ISR);
3267 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3268 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3274 /* ack what we have */
3275 CSR_WRITE_4(sc, DC_ISR, status);
3277 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3278 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3279 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff));
3281 if (dc_rx_resync(sc))
3284 /* restart transmit unit if necessary */
3285 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3286 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3288 if (status & DC_ISR_TX_UNDERRUN)
3291 if (status & DC_ISR_BUS_ERR) {
3292 if_printf(ifp, "%s: bus error\n", __func__);
3293 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3300 #endif /* DEVICE_POLLING */
3305 struct dc_softc *sc;
3316 status = CSR_READ_4(sc, DC_ISR);
3317 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) {
3322 #ifdef DEVICE_POLLING
3323 if (ifp->if_capenable & IFCAP_POLLING) {
3328 /* Disable interrupts. */
3329 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3331 for (n = 16; n > 0; n--) {
3332 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3334 /* Ack interrupts. */
3335 CSR_WRITE_4(sc, DC_ISR, status);
3337 if (status & DC_ISR_RX_OK) {
3338 if (dc_rxeof(sc) == 0) {
3339 while (dc_rx_resync(sc))
3344 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3347 if (status & DC_ISR_TX_IDLE) {
3349 if (sc->dc_cdata.dc_tx_cnt) {
3350 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3351 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3355 if (status & DC_ISR_TX_UNDERRUN)
3358 if ((status & DC_ISR_RX_WATDOGTIMEO)
3359 || (status & DC_ISR_RX_NOBUF)) {
3360 r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3361 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff));
3362 if (dc_rxeof(sc) == 0) {
3363 while (dc_rx_resync(sc))
3368 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3369 dc_start_locked(ifp);
3371 if (status & DC_ISR_BUS_ERR) {
3372 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3377 status = CSR_READ_4(sc, DC_ISR);
3378 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0)
3382 /* Re-enable interrupts. */
3383 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3384 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3390 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3391 * pointers to the fragment pointers.
3394 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3396 bus_dma_segment_t segs[DC_MAXFRAGS];
3400 int cur, defragged, error, first, frag, i, idx, nseg;
3404 if (sc->dc_flags & DC_TX_COALESCE &&
3405 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3406 m = m_defrag(*m_head, M_NOWAIT);
3410 * Count the number of frags in this chain to see if we
3411 * need to m_collapse. Since the descriptor list is shared
3412 * by all packets, we'll m_collapse long chains so that they
3413 * do not use up the entire list, even if they would fit.
3416 for (m = *m_head; m != NULL; m = m->m_next)
3418 if (i > DC_TX_LIST_CNT / 4 ||
3419 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3421 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS);
3425 if (defragged != 0) {
3434 idx = sc->dc_cdata.dc_tx_prod;
3435 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3436 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3437 if (error == EFBIG) {
3438 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT,
3439 DC_MAXFRAGS)) == NULL) {
3442 return (defragged != 0 ? error : ENOBUFS);
3445 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3446 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3452 } else if (error != 0)
3454 KASSERT(nseg <= DC_MAXFRAGS,
3455 ("%s: wrong number of segments (%d)", __func__, nseg));
3462 /* Check descriptor overruns. */
3463 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3464 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3467 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3468 BUS_DMASYNC_PREWRITE);
3470 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3471 for (i = 0; i < nseg; i++) {
3472 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3473 (frag == (DC_TX_LIST_CNT - 1)) &&
3474 (first != sc->dc_cdata.dc_tx_first)) {
3475 bus_dmamap_unload(sc->dc_tx_mtag,
3476 sc->dc_cdata.dc_tx_map[first]);
3482 f = &sc->dc_ldata.dc_tx_list[frag];
3483 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3486 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3488 f->dc_status = htole32(DC_TXSTAT_OWN);
3489 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr));
3491 DC_INC(frag, DC_TX_LIST_CNT);
3494 sc->dc_cdata.dc_tx_prod = frag;
3495 sc->dc_cdata.dc_tx_cnt += nseg;
3496 sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3497 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3498 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3499 sc->dc_ldata.dc_tx_list[first].dc_ctl |=
3500 htole32(DC_TXCTL_FINT);
3501 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3502 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3503 if (sc->dc_flags & DC_TX_USE_TX_INTR &&
3504 ++sc->dc_cdata.dc_tx_pkts >= 8) {
3505 sc->dc_cdata.dc_tx_pkts = 0;
3506 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3508 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3510 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3514 * Swap the last and the first dmamaps to ensure the map for
3515 * this transmission is placed at the last descriptor.
3517 map = sc->dc_cdata.dc_tx_map[cur];
3518 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first];
3519 sc->dc_cdata.dc_tx_map[first] = map;
3525 dc_start(struct ifnet *ifp)
3527 struct dc_softc *sc;
3531 dc_start_locked(ifp);
3536 * Main transmit routine
3537 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3538 * regions directly in the transmit lists. We also save a copy of the
3539 * pointers since the transmit list fragment pointers are physical
3543 dc_start_locked(struct ifnet *ifp)
3545 struct dc_softc *sc;
3546 struct mbuf *m_head;
3553 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
3554 IFF_DRV_RUNNING || sc->dc_link == 0)
3557 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3559 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
3561 * If there's no way we can send any packets, return now.
3563 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3564 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3567 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3571 if (dc_encap(sc, &m_head)) {
3574 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3575 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3581 * If there's a BPF listener, bounce a copy of this frame
3584 BPF_MTAP(ifp, m_head);
3589 if (!(sc->dc_flags & DC_TX_POLL))
3590 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3593 * Set a timeout in case the chip goes out to lunch.
3595 sc->dc_wdog_timer = 5;
3602 struct dc_softc *sc = xsc;
3610 dc_init_locked(struct dc_softc *sc)
3612 struct ifnet *ifp = sc->dc_ifp;
3613 struct mii_data *mii;
3614 struct ifmedia *ifm;
3618 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3621 mii = device_get_softc(sc->dc_miibus);
3624 * Cancel pending I/O and free all RX/TX buffers.
3628 if (DC_IS_INTEL(sc)) {
3629 ifm = &mii->mii_media;
3630 dc_apply_fixup(sc, ifm->ifm_media);
3634 * Set cache alignment and burst length.
3636 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc))
3637 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3639 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3641 * Evenly share the bus between receive and transmit process.
3643 if (DC_IS_INTEL(sc))
3644 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3645 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3646 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3648 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3650 if (sc->dc_flags & DC_TX_POLL)
3651 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3652 switch(sc->dc_cachesize) {
3654 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3657 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3660 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3664 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3668 if (sc->dc_flags & DC_TX_STORENFWD)
3669 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3671 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3672 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3674 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3675 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3679 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3680 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3682 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3684 * The app notes for the 98713 and 98715A say that
3685 * in order to have the chips operate properly, a magic
3686 * number must be written to CSR16. Macronix does not
3687 * document the meaning of these bits so there's no way
3688 * to know exactly what they do. The 98713 has a magic
3689 * number all its own; the rest all use a different one.
3691 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3692 if (sc->dc_type == DC_TYPE_98713)
3693 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3695 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3698 if (DC_IS_XIRCOM(sc)) {
3700 * setup General Purpose Port mode and data so the tulip
3701 * can talk to the MII.
3703 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3704 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3706 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3707 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3711 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3712 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3714 /* Init circular RX list. */
3715 if (dc_list_rx_init(sc) == ENOBUFS) {
3716 device_printf(sc->dc_dev,
3717 "initialization failed: no memory for rx buffers\n");
3723 * Init TX descriptors.
3725 dc_list_tx_init(sc);
3728 * Load the address of the RX list.
3730 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3731 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3734 * Enable interrupts.
3736 #ifdef DEVICE_POLLING
3738 * ... but only if we are not polling, and make sure they are off in
3739 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3742 if (ifp->if_capenable & IFCAP_POLLING)
3743 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3746 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3747 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3749 /* Initialize TX jabber and RX watchdog timer. */
3751 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK |
3754 /* Enable transmitter. */
3755 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3758 * If this is an Intel 21143 and we're not using the
3759 * MII port, program the LED control pins so we get
3760 * link and activity indications.
3762 if (sc->dc_flags & DC_TULIP_LEDS) {
3763 CSR_WRITE_4(sc, DC_WATCHDOG,
3764 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3765 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3769 * Load the RX/multicast filter. We do this sort of late
3770 * because the filter programming scheme on the 21143 and
3771 * some clones requires DMAing a setup frame via the TX
3772 * engine, and we need the transmitter enabled for that.
3776 /* Enable receiver. */
3777 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3778 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3780 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3781 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3783 dc_ifmedia_upd_locked(sc);
3785 /* Clear missed frames and overflow counter. */
3786 CSR_READ_4(sc, DC_FRAMESDISCARDED);
3788 /* Don't start the ticker if this is a homePNA link. */
3789 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3792 if (sc->dc_flags & DC_21143_NWAY)
3793 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3795 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3798 sc->dc_wdog_timer = 0;
3799 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3803 * Set media options.
3806 dc_ifmedia_upd(struct ifnet *ifp)
3808 struct dc_softc *sc;
3813 error = dc_ifmedia_upd_locked(sc);
3819 dc_ifmedia_upd_locked(struct dc_softc *sc)
3821 struct mii_data *mii;
3822 struct ifmedia *ifm;
3828 mii = device_get_softc(sc->dc_miibus);
3829 error = mii_mediachg(mii);
3831 ifm = &mii->mii_media;
3832 if (DC_IS_INTEL(sc))
3833 dc_setcfg(sc, ifm->ifm_media);
3834 else if (DC_IS_DAVICOM(sc) &&
3835 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3836 dc_setcfg(sc, ifm->ifm_media);
3843 * Report current media status.
3846 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3848 struct dc_softc *sc;
3849 struct mii_data *mii;
3850 struct ifmedia *ifm;
3853 mii = device_get_softc(sc->dc_miibus);
3856 ifm = &mii->mii_media;
3857 if (DC_IS_DAVICOM(sc)) {
3858 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3859 ifmr->ifm_active = ifm->ifm_media;
3860 ifmr->ifm_status = 0;
3865 ifmr->ifm_active = mii->mii_media_active;
3866 ifmr->ifm_status = mii->mii_media_status;
3871 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3873 struct dc_softc *sc = ifp->if_softc;
3874 struct ifreq *ifr = (struct ifreq *)data;
3875 struct mii_data *mii;
3881 if (ifp->if_flags & IFF_UP) {
3882 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3883 (IFF_PROMISC | IFF_ALLMULTI);
3885 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3889 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3893 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3896 sc->dc_if_flags = ifp->if_flags;
3902 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3908 mii = device_get_softc(sc->dc_miibus);
3909 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3912 #ifdef DEVICE_POLLING
3913 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3914 !(ifp->if_capenable & IFCAP_POLLING)) {
3915 error = ether_poll_register(dc_poll, ifp);
3919 /* Disable interrupts */
3920 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3921 ifp->if_capenable |= IFCAP_POLLING;
3925 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3926 ifp->if_capenable & IFCAP_POLLING) {
3927 error = ether_poll_deregister(ifp);
3928 /* Enable interrupts. */
3930 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3931 ifp->if_capenable &= ~IFCAP_POLLING;
3935 #endif /* DEVICE_POLLING */
3938 error = ether_ioctl(ifp, command, data);
3946 dc_watchdog(void *xsc)
3948 struct dc_softc *sc = xsc;
3953 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3954 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3959 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3960 device_printf(sc->dc_dev, "watchdog timeout\n");
3962 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3965 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3966 dc_start_locked(ifp);
3970 * Stop the adapter and free any mbufs allocated to the
3974 dc_stop(struct dc_softc *sc)
3977 struct dc_list_data *ld;
3978 struct dc_chain_data *cd;
3980 uint32_t ctl, netcfg;
3988 callout_stop(&sc->dc_stat_ch);
3989 callout_stop(&sc->dc_wdog_ch);
3990 sc->dc_wdog_timer = 0;
3993 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3995 netcfg = CSR_READ_4(sc, DC_NETCFG);
3996 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3997 CSR_WRITE_4(sc, DC_NETCFG,
3998 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3999 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
4000 /* Wait the completion of TX/RX SM. */
4001 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
4004 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
4005 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
4008 * Free data in the RX lists.
4010 for (i = 0; i < DC_RX_LIST_CNT; i++) {
4011 if (cd->dc_rx_chain[i] != NULL) {
4012 bus_dmamap_sync(sc->dc_rx_mtag,
4013 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD);
4014 bus_dmamap_unload(sc->dc_rx_mtag,
4016 m_freem(cd->dc_rx_chain[i]);
4017 cd->dc_rx_chain[i] = NULL;
4020 bzero(ld->dc_rx_list, DC_RX_LIST_SZ);
4021 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
4022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4025 * Free the TX list buffers.
4027 for (i = 0; i < DC_TX_LIST_CNT; i++) {
4028 if (cd->dc_tx_chain[i] != NULL) {
4029 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
4030 if (ctl & DC_TXCTL_SETUP) {
4031 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
4032 BUS_DMASYNC_POSTWRITE);
4034 bus_dmamap_sync(sc->dc_tx_mtag,
4035 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE);
4036 bus_dmamap_unload(sc->dc_tx_mtag,
4038 m_freem(cd->dc_tx_chain[i]);
4040 cd->dc_tx_chain[i] = NULL;
4043 bzero(ld->dc_tx_list, DC_TX_LIST_SZ);
4044 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
4045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4049 * Device suspend routine. Stop the interface and save some PCI
4050 * settings in case the BIOS doesn't restore them properly on
4054 dc_suspend(device_t dev)
4056 struct dc_softc *sc;
4058 sc = device_get_softc(dev);
4068 * Device resume routine. Restore some PCI settings in case the BIOS
4069 * doesn't, re-enable busmastering, and restart the interface if
4073 dc_resume(device_t dev)
4075 struct dc_softc *sc;
4078 sc = device_get_softc(dev);
4081 /* reinitialize interface if necessary */
4083 if (ifp->if_flags & IFF_UP)
4093 * Stop all chip I/O so that the kernel's probe routines don't
4094 * get confused by errant DMAs when rebooting.
4097 dc_shutdown(device_t dev)
4099 struct dc_softc *sc;
4101 sc = device_get_softc(dev);
4111 dc_check_multiport(struct dc_softc *sc)
4113 struct dc_softc *dsc;
4119 dc = devclass_find("dc");
4120 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {
4121 child = devclass_get_device(dc, unit);
4124 if (child == sc->dc_dev)
4126 if (device_get_parent(child) != device_get_parent(sc->dc_dev))
4128 if (unit > device_get_unit(sc->dc_dev))
4130 if (device_is_attached(child) == 0)
4132 dsc = device_get_softc(child);
4133 device_printf(sc->dc_dev,
4134 "Using station address of %s as base\n",
4135 device_get_nameunit(child));
4136 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN);
4137 eaddr = (uint8_t *)sc->dc_eaddr;
4139 /* Prepare SROM to parse again. */
4140 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL &&
4141 sc->dc_romwidth != 0) {
4142 free(sc->dc_srom, M_DEVBUF);
4143 sc->dc_romwidth = dsc->dc_romwidth;
4144 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth),
4145 M_DEVBUF, M_NOWAIT);
4146 if (sc->dc_srom == NULL) {
4147 device_printf(sc->dc_dev,
4148 "Could not allocate SROM buffer\n");
4151 bcopy(dsc->dc_srom, sc->dc_srom,
4152 DC_ROM_SIZE(sc->dc_romwidth));