2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN983 (www.admtek.com.tw)
47 * ADMtek CardBus AN985 (www.admtek.com.tw)
48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
50 * Accton EN1217 (www.accton.com)
51 * Xircom X3201 (www.xircom.com)
53 * Conexant LANfinity (www.conexant.com)
54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
56 * Datasheets for the 21143 are available at developer.intel.com.
57 * Datasheets for the clone parts can be found at their respective sites.
58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
59 * The PNIC II is essentially a Macronix 98715A chip; the only difference
60 * worth noting is that its multicast hash table is only 128 bits wide
63 * Written by Bill Paul <wpaul@ee.columbia.edu>
64 * Electrical Engineering Department
65 * Columbia University, New York City
68 * The Intel 21143 is the successor to the DEC 21140. It is basically
69 * the same as the 21140 but with a few new features. The 21143 supports
70 * three kinds of media attachments:
72 * o MII port, for 10Mbps and 100Mbps support and NWAY
73 * autonegotiation provided by an external PHY.
74 * o SYM port, for symbol mode 100Mbps support.
78 * The 100Mbps SYM port and 10baseT port can be used together in
79 * combination with the internal NWAY support to create a 10/100
80 * autosensing configuration.
82 * Note that not all tulip workalikes are handled in this driver: we only
83 * deal with those which are relatively well behaved. The Winbond is
84 * handled separately due to its different register offsets and the
85 * special handling needed for its various bugs. The PNIC is handled
86 * here, but I'm not thrilled about it.
88 * All of the workalike chips use some form of MII transceiver support
89 * with the exception of the Macronix chips, which also have a SYM port.
90 * The ASIX AX88140A is also documented to have a SYM port, but all
91 * the cards I've seen use an MII transceiver, probably because the
92 * AX88140A doesn't support internal NWAY.
95 #ifdef HAVE_KERNEL_OPTION_HEADERS
96 #include "opt_device_polling.h"
99 #include <sys/param.h>
100 #include <sys/endian.h>
101 #include <sys/systm.h>
102 #include <sys/sockio.h>
103 #include <sys/mbuf.h>
104 #include <sys/malloc.h>
105 #include <sys/kernel.h>
106 #include <sys/module.h>
107 #include <sys/socket.h>
110 #include <net/if_var.h>
111 #include <net/if_arp.h>
112 #include <net/ethernet.h>
113 #include <net/if_dl.h>
114 #include <net/if_media.h>
115 #include <net/if_types.h>
116 #include <net/if_vlan_var.h>
120 #include <machine/bus.h>
121 #include <machine/resource.h>
123 #include <sys/rman.h>
125 #include <dev/mii/mii.h>
126 #include <dev/mii/mii_bitbang.h>
127 #include <dev/mii/miivar.h>
129 #include <dev/pci/pcireg.h>
130 #include <dev/pci/pcivar.h>
132 #define DC_USEIOSPACE
134 #include <dev/dc/if_dcreg.h>
137 #include <dev/ofw/openfirm.h>
138 #include <machine/ofw_machdep.h>
141 MODULE_DEPEND(dc, pci, 1, 1, 1);
142 MODULE_DEPEND(dc, ether, 1, 1, 1);
143 MODULE_DEPEND(dc, miibus, 1, 1, 1);
146 * "device miibus" is required in kernel config. See GENERIC if you get
149 #include "miibus_if.h"
152 * Various supported device vendors/types and their names.
154 static const struct dc_type dc_devs[] = {
155 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
156 "Intel 21143 10/100BaseTX" },
157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
158 "Davicom DM9009 10/100BaseTX" },
159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
160 "Davicom DM9100 10/100BaseTX" },
161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
162 "Davicom DM9102A 10/100BaseTX" },
163 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
164 "Davicom DM9102 10/100BaseTX" },
165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
166 "ADMtek AL981 10/100BaseTX" },
167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
168 "ADMtek AN983 10/100BaseTX" },
169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
170 "ADMtek AN985 CardBus 10/100BaseTX or clone" },
171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
172 "ADMtek ADM9511 10/100BaseTX" },
173 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
174 "ADMtek ADM9513 10/100BaseTX" },
175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
176 "ASIX AX88141 10/100BaseTX" },
177 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
178 "ASIX AX88140A 10/100BaseTX" },
179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
180 "Macronix 98713A 10/100BaseTX" },
181 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
182 "Macronix 98713 10/100BaseTX" },
183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
184 "Compex RL100-TX 10/100BaseTX" },
185 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
186 "Compex RL100-TX 10/100BaseTX" },
187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
188 "Macronix 98725 10/100BaseTX" },
189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
190 "Macronix 98715AEC-C 10/100BaseTX" },
191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
192 "Macronix 98715/98715A 10/100BaseTX" },
193 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
194 "Macronix 98727/98732 10/100BaseTX" },
195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
196 "LC82C115 PNIC II 10/100BaseTX" },
197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
198 "82c169 PNIC 10/100BaseTX" },
199 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
200 "82c168 PNIC 10/100BaseTX" },
201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
202 "Accton EN1217 10/100BaseTX" },
203 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
204 "Accton EN2242 MiniPCI 10/100BaseTX" },
205 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
206 "Xircom X3201 10/100BaseTX" },
207 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
208 "Neteasy DRP-32TXD Cardbus 10/100" },
209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
210 "Abocom FE2500 10/100BaseTX" },
211 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
212 "Abocom FE2500MX 10/100BaseTX" },
213 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
214 "Conexant LANfinity MiniPCI 10/100BaseTX" },
215 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
216 "Hawking CB102 CardBus 10/100" },
217 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
218 "PlaneX FNW-3602-T CardBus 10/100" },
219 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
220 "3Com OfficeConnect 10/100B" },
221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
222 "Microsoft MN-120 CardBus 10/100" },
223 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
224 "Microsoft MN-130 10/100" },
225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
226 "Linksys PCMPC200 CardBus 10/100" },
227 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
228 "Linksys PCMPC200 CardBus 10/100" },
229 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0,
230 "ULi M5261 FastEthernet" },
231 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0,
232 "ULi M5263 FastEthernet" },
236 static int dc_probe(device_t);
237 static int dc_attach(device_t);
238 static int dc_detach(device_t);
239 static int dc_suspend(device_t);
240 static int dc_resume(device_t);
241 static const struct dc_type *dc_devtype(device_t);
242 static void dc_discard_rxbuf(struct dc_softc *, int);
243 static int dc_newbuf(struct dc_softc *, int);
244 static int dc_encap(struct dc_softc *, struct mbuf **);
245 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
246 static int dc_rx_resync(struct dc_softc *);
247 static int dc_rxeof(struct dc_softc *);
248 static void dc_txeof(struct dc_softc *);
249 static void dc_tick(void *);
250 static void dc_tx_underrun(struct dc_softc *);
251 static void dc_intr(void *);
252 static void dc_start(struct ifnet *);
253 static void dc_start_locked(struct ifnet *);
254 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
255 static void dc_init(void *);
256 static void dc_init_locked(struct dc_softc *);
257 static void dc_stop(struct dc_softc *);
258 static void dc_watchdog(void *);
259 static int dc_shutdown(device_t);
260 static int dc_ifmedia_upd(struct ifnet *);
261 static int dc_ifmedia_upd_locked(struct dc_softc *);
262 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
264 static int dc_dma_alloc(struct dc_softc *);
265 static void dc_dma_free(struct dc_softc *);
266 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
268 static void dc_delay(struct dc_softc *);
269 static void dc_eeprom_idle(struct dc_softc *);
270 static void dc_eeprom_putbyte(struct dc_softc *, int);
271 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
272 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
273 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
274 static void dc_eeprom_width(struct dc_softc *);
275 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
277 static int dc_miibus_readreg(device_t, int, int);
278 static int dc_miibus_writereg(device_t, int, int, int);
279 static void dc_miibus_statchg(device_t);
280 static void dc_miibus_mediainit(device_t);
282 static void dc_setcfg(struct dc_softc *, int);
283 static void dc_netcfg_wait(struct dc_softc *);
284 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
285 static uint32_t dc_mchash_be(const uint8_t *);
286 static void dc_setfilt_21143(struct dc_softc *);
287 static void dc_setfilt_asix(struct dc_softc *);
288 static void dc_setfilt_admtek(struct dc_softc *);
289 static void dc_setfilt_uli(struct dc_softc *);
290 static void dc_setfilt_xircom(struct dc_softc *);
292 static void dc_setfilt(struct dc_softc *);
294 static void dc_reset(struct dc_softc *);
295 static int dc_list_rx_init(struct dc_softc *);
296 static int dc_list_tx_init(struct dc_softc *);
298 static int dc_read_srom(struct dc_softc *, int);
299 static int dc_parse_21143_srom(struct dc_softc *);
300 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
301 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
302 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
303 static void dc_apply_fixup(struct dc_softc *, int);
304 static int dc_check_multiport(struct dc_softc *);
309 static uint32_t dc_mii_bitbang_read(device_t);
310 static void dc_mii_bitbang_write(device_t, uint32_t);
312 static const struct mii_bitbang_ops dc_mii_bitbang_ops = {
314 dc_mii_bitbang_write,
316 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */
317 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */
318 DC_SIO_MII_CLK, /* MII_BIT_MDC */
319 0, /* MII_BIT_DIR_HOST_PHY */
320 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */
325 #define DC_RES SYS_RES_IOPORT
326 #define DC_RID DC_PCI_CFBIO
328 #define DC_RES SYS_RES_MEMORY
329 #define DC_RID DC_PCI_CFBMA
332 static device_method_t dc_methods[] = {
333 /* Device interface */
334 DEVMETHOD(device_probe, dc_probe),
335 DEVMETHOD(device_attach, dc_attach),
336 DEVMETHOD(device_detach, dc_detach),
337 DEVMETHOD(device_suspend, dc_suspend),
338 DEVMETHOD(device_resume, dc_resume),
339 DEVMETHOD(device_shutdown, dc_shutdown),
342 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
343 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
344 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
345 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
350 static driver_t dc_driver = {
353 sizeof(struct dc_softc)
356 static devclass_t dc_devclass;
358 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL,
360 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
362 #define DC_SETBIT(sc, reg, x) \
363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
365 #define DC_CLRBIT(sc, reg, x) \
366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
368 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
369 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
372 dc_delay(struct dc_softc *sc)
376 for (idx = (300 / 33) + 1; idx > 0; idx--)
377 CSR_READ_4(sc, DC_BUSCTL);
381 dc_eeprom_width(struct dc_softc *sc)
385 /* Force EEPROM to idle state. */
388 /* Enter EEPROM access mode. */
389 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
391 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
395 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
400 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
404 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
406 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
410 for (i = 1; i <= 12; i++) {
411 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
413 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
422 /* Turn off EEPROM access mode. */
430 /* Enter EEPROM access mode. */
431 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
433 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
435 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
437 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
440 /* Turn off EEPROM access mode. */
445 dc_eeprom_idle(struct dc_softc *sc)
449 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
451 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
455 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
458 for (i = 0; i < 25; i++) {
459 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
461 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
465 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
469 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
473 * Send a read command and address to the EEPROM, check for ACK.
476 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
480 d = DC_EECMD_READ >> 6;
483 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
485 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
487 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
489 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
494 * Feed in each bit and strobe the clock.
496 for (i = sc->dc_romwidth; i--;) {
497 if (addr & (1 << i)) {
498 SIO_SET(DC_SIO_EE_DATAIN);
500 SIO_CLR(DC_SIO_EE_DATAIN);
503 SIO_SET(DC_SIO_EE_CLK);
505 SIO_CLR(DC_SIO_EE_CLK);
511 * Read a word of data stored in the EEPROM at address 'addr.'
512 * The PNIC 82c168/82c169 has its own non-standard way to read
516 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
521 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
523 for (i = 0; i < DC_TIMEOUT; i++) {
525 r = CSR_READ_4(sc, DC_SIO);
526 if (!(r & DC_PN_SIOCTL_BUSY)) {
527 *dest = (uint16_t)(r & 0xFFFF);
534 * Read a word of data stored in the EEPROM at address 'addr.'
535 * The Xircom X3201 has its own non-standard way to read
539 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
542 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
545 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
546 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
548 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
549 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
551 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
555 * Read a word of data stored in the EEPROM at address 'addr.'
558 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
563 /* Force EEPROM to idle state. */
566 /* Enter EEPROM access mode. */
567 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
569 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
571 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
573 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
577 * Send address of word we want to read.
579 dc_eeprom_putbyte(sc, addr);
582 * Start reading bits from EEPROM.
584 for (i = 0x8000; i; i >>= 1) {
585 SIO_SET(DC_SIO_EE_CLK);
587 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
590 SIO_CLR(DC_SIO_EE_CLK);
594 /* Turn off EEPROM access mode. */
601 * Read a sequence of words from the EEPROM.
604 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
607 uint16_t word = 0, *ptr;
609 for (i = 0; i < cnt; i++) {
611 dc_eeprom_getword_pnic(sc, off + i, &word);
612 else if (DC_IS_XIRCOM(sc))
613 dc_eeprom_getword_xircom(sc, off + i, &word);
615 dc_eeprom_getword(sc, off + i, &word);
616 ptr = (uint16_t *)(dest + (i * 2));
618 *ptr = be16toh(word);
620 *ptr = le16toh(word);
625 * Write the MII serial port for the MII bit-bang module.
628 dc_mii_bitbang_write(device_t dev, uint32_t val)
632 sc = device_get_softc(dev);
634 CSR_WRITE_4(sc, DC_SIO, val);
635 CSR_BARRIER_4(sc, DC_SIO,
636 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
640 * Read the MII serial port for the MII bit-bang module.
643 dc_mii_bitbang_read(device_t dev)
648 sc = device_get_softc(dev);
650 val = CSR_READ_4(sc, DC_SIO);
651 CSR_BARRIER_4(sc, DC_SIO,
652 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
658 dc_miibus_readreg(device_t dev, int phy, int reg)
661 int i, rval, phy_reg = 0;
663 sc = device_get_softc(dev);
665 if (sc->dc_pmode != DC_PMODE_MII) {
666 if (phy == (MII_NPHY - 1)) {
670 * Fake something to make the probe
671 * code think there's a PHY here.
673 return (BMSR_MEDIAMASK);
676 return (DC_VENDORID_LO);
677 return (DC_VENDORID_DEC);
680 return (DC_DEVICEID_82C168);
681 return (DC_DEVICEID_21143);
689 if (DC_IS_PNIC(sc)) {
690 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
691 (phy << 23) | (reg << 18));
692 for (i = 0; i < DC_TIMEOUT; i++) {
694 rval = CSR_READ_4(sc, DC_PN_MII);
695 if (!(rval & DC_PN_MII_BUSY)) {
697 return (rval == 0xFFFF ? 0 : rval);
703 if (sc->dc_type == DC_TYPE_ULI_M5263) {
704 CSR_WRITE_4(sc, DC_ROM,
705 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
706 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
708 for (i = 0; i < DC_TIMEOUT; i++) {
710 rval = CSR_READ_4(sc, DC_ROM);
711 if ((rval & DC_ULI_PHY_OP_DONE) != 0) {
712 return (rval & DC_ULI_PHY_DATA_MASK);
716 device_printf(dev, "phy read timed out\n");
720 if (DC_IS_COMET(sc)) {
723 phy_reg = DC_AL_BMCR;
726 phy_reg = DC_AL_BMSR;
729 phy_reg = DC_AL_VENID;
732 phy_reg = DC_AL_DEVID;
735 phy_reg = DC_AL_ANAR;
738 phy_reg = DC_AL_LPAR;
741 phy_reg = DC_AL_ANER;
744 device_printf(dev, "phy_read: bad phy register %x\n",
749 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
755 if (sc->dc_type == DC_TYPE_98713) {
756 phy_reg = CSR_READ_4(sc, DC_NETCFG);
757 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
759 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
760 if (sc->dc_type == DC_TYPE_98713)
761 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
767 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
772 sc = device_get_softc(dev);
774 if (DC_IS_PNIC(sc)) {
775 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
776 (phy << 23) | (reg << 10) | data);
777 for (i = 0; i < DC_TIMEOUT; i++) {
778 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
784 if (sc->dc_type == DC_TYPE_ULI_M5263) {
785 CSR_WRITE_4(sc, DC_ROM,
786 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
787 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
788 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) |
789 DC_ULI_PHY_OP_WRITE);
794 if (DC_IS_COMET(sc)) {
797 phy_reg = DC_AL_BMCR;
800 phy_reg = DC_AL_BMSR;
803 phy_reg = DC_AL_VENID;
806 phy_reg = DC_AL_DEVID;
809 phy_reg = DC_AL_ANAR;
812 phy_reg = DC_AL_LPAR;
815 phy_reg = DC_AL_ANER;
818 device_printf(dev, "phy_write: bad phy register %x\n",
824 CSR_WRITE_4(sc, phy_reg, data);
828 if (sc->dc_type == DC_TYPE_98713) {
829 phy_reg = CSR_READ_4(sc, DC_NETCFG);
830 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
832 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);
833 if (sc->dc_type == DC_TYPE_98713)
834 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
840 dc_miibus_statchg(device_t dev)
844 struct mii_data *mii;
847 sc = device_get_softc(dev);
849 mii = device_get_softc(sc->dc_miibus);
851 if (mii == NULL || ifp == NULL ||
852 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
855 ifm = &mii->mii_media;
856 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
857 dc_setcfg(sc, ifm->ifm_media);
859 } else if (!DC_IS_ADMTEK(sc))
860 dc_setcfg(sc, mii->mii_media_active);
863 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
864 (IFM_ACTIVE | IFM_AVALID)) {
865 switch (IFM_SUBTYPE(mii->mii_media_active)) {
875 * Special support for DM9102A cards with HomePNA PHYs. Note:
876 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
877 * to be impossible to talk to the management interface of the DM9801
878 * PHY (its MDIO pin is not connected to anything). Consequently,
879 * the driver has to just 'know' about the additional mode and deal
880 * with it itself. *sigh*
883 dc_miibus_mediainit(device_t dev)
886 struct mii_data *mii;
890 rev = pci_get_revid(dev);
892 sc = device_get_softc(dev);
893 mii = device_get_softc(sc->dc_miibus);
894 ifm = &mii->mii_media;
896 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
897 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
900 #define DC_BITS_512 9
901 #define DC_BITS_128 7
905 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
909 /* Compute CRC for the address value. */
910 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
913 * The hash table on the PNIC II and the MX98715AEC-C/D/E
914 * chips is only 128 bits wide.
916 if (sc->dc_flags & DC_128BIT_HASH)
917 return (crc & ((1 << DC_BITS_128) - 1));
919 /* The hash table on the MX98715BEC is only 64 bits wide. */
920 if (sc->dc_flags & DC_64BIT_HASH)
921 return (crc & ((1 << DC_BITS_64) - 1));
923 /* Xircom's hash filtering table is different (read: weird) */
924 /* Xircom uses the LEAST significant bits */
925 if (DC_IS_XIRCOM(sc)) {
926 if ((crc & 0x180) == 0x180)
927 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
929 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
933 return (crc & ((1 << DC_BITS_512) - 1));
937 * Calculate CRC of a multicast group address, return the lower 6 bits.
940 dc_mchash_be(const uint8_t *addr)
944 /* Compute CRC for the address value. */
945 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
947 /* Return the filter bit position. */
948 return ((crc >> 26) & 0x0000003F);
952 * 21143-style RX filter setup routine. Filter programming is done by
953 * downloading a special setup frame into the TX engine. 21143, Macronix,
954 * PNIC, PNIC II and Davicom chips are programmed this way.
956 * We always program the chip using 'hash perfect' mode, i.e. one perfect
957 * address (our node address) and a 512-bit hash filter for multicast
958 * frames. We also sneak the broadcast address into the hash filter since
962 dc_setfilt_21143(struct dc_softc *sc)
964 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
965 struct dc_desc *sframe;
967 struct ifmultiaddr *ifma;
973 i = sc->dc_cdata.dc_tx_prod;
974 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
975 sc->dc_cdata.dc_tx_cnt++;
976 sframe = &sc->dc_ldata.dc_tx_list[i];
977 sp = sc->dc_cdata.dc_sbuf;
978 bzero(sp, DC_SFRAME_LEN);
980 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
981 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
982 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
984 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
986 /* If we want promiscuous mode, set the allframes bit. */
987 if (ifp->if_flags & IFF_PROMISC)
988 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
990 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
992 if (ifp->if_flags & IFF_ALLMULTI)
993 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
995 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
998 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
999 if (ifma->ifma_addr->sa_family != AF_LINK)
1001 h = dc_mchash_le(sc,
1002 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1003 sp[h >> 4] |= htole32(1 << (h & 0xF));
1005 if_maddr_runlock(ifp);
1007 if (ifp->if_flags & IFF_BROADCAST) {
1008 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1009 sp[h >> 4] |= htole32(1 << (h & 0xF));
1012 /* Set our MAC address. */
1013 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1014 sp[39] = DC_SP_MAC(eaddr[0]);
1015 sp[40] = DC_SP_MAC(eaddr[1]);
1016 sp[41] = DC_SP_MAC(eaddr[2]);
1018 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1019 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1020 BUS_DMASYNC_PREWRITE);
1021 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1022 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1025 * The PNIC takes an exceedingly long time to process its
1026 * setup frame; wait 10ms after posting the setup frame
1027 * before proceeding, just so it has time to swallow its
1032 sc->dc_wdog_timer = 5;
1036 dc_setfilt_admtek(struct dc_softc *sc)
1038 uint8_t eaddr[ETHER_ADDR_LEN];
1040 struct ifmultiaddr *ifma;
1042 uint32_t hashes[2] = { 0, 0 };
1046 /* Init our MAC address. */
1047 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1048 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1049 eaddr[1] << 8 | eaddr[0]);
1050 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1052 /* If we want promiscuous mode, set the allframes bit. */
1053 if (ifp->if_flags & IFF_PROMISC)
1054 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1056 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1058 if (ifp->if_flags & IFF_ALLMULTI)
1059 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1061 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1063 /* First, zot all the existing hash bits. */
1064 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1065 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1068 * If we're already in promisc or allmulti mode, we
1069 * don't have to bother programming the multicast filter.
1071 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1074 /* Now program new ones. */
1075 if_maddr_rlock(ifp);
1076 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1077 if (ifma->ifma_addr->sa_family != AF_LINK)
1079 if (DC_IS_CENTAUR(sc))
1080 h = dc_mchash_le(sc,
1081 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1084 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1086 hashes[0] |= (1 << h);
1088 hashes[1] |= (1 << (h - 32));
1090 if_maddr_runlock(ifp);
1092 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1093 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1097 dc_setfilt_asix(struct dc_softc *sc)
1099 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1101 struct ifmultiaddr *ifma;
1103 uint32_t hashes[2] = { 0, 0 };
1107 /* Init our MAC address. */
1108 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1109 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1110 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1111 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1112 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1114 /* If we want promiscuous mode, set the allframes bit. */
1115 if (ifp->if_flags & IFF_PROMISC)
1116 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1118 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1120 if (ifp->if_flags & IFF_ALLMULTI)
1121 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1123 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1126 * The ASIX chip has a special bit to enable reception
1127 * of broadcast frames.
1129 if (ifp->if_flags & IFF_BROADCAST)
1130 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1132 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1134 /* first, zot all the existing hash bits */
1135 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1136 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1137 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1138 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1141 * If we're already in promisc or allmulti mode, we
1142 * don't have to bother programming the multicast filter.
1144 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1147 /* now program new ones */
1148 if_maddr_rlock(ifp);
1149 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1150 if (ifma->ifma_addr->sa_family != AF_LINK)
1152 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1154 hashes[0] |= (1 << h);
1156 hashes[1] |= (1 << (h - 32));
1158 if_maddr_runlock(ifp);
1160 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1161 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1162 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1163 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1167 dc_setfilt_uli(struct dc_softc *sc)
1169 uint8_t eaddr[ETHER_ADDR_LEN];
1171 struct ifmultiaddr *ifma;
1172 struct dc_desc *sframe;
1173 uint32_t filter, *sp;
1179 i = sc->dc_cdata.dc_tx_prod;
1180 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1181 sc->dc_cdata.dc_tx_cnt++;
1182 sframe = &sc->dc_ldata.dc_tx_list[i];
1183 sp = sc->dc_cdata.dc_sbuf;
1184 bzero(sp, DC_SFRAME_LEN);
1186 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1187 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1188 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT);
1190 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1192 /* Set station address. */
1193 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1194 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]);
1195 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]);
1196 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]);
1198 /* Set broadcast address. */
1199 *sp++ = DC_SP_MAC(0xFFFF);
1200 *sp++ = DC_SP_MAC(0xFFFF);
1201 *sp++ = DC_SP_MAC(0xFFFF);
1203 /* Extract current filter configuration. */
1204 filter = CSR_READ_4(sc, DC_NETCFG);
1205 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI);
1207 /* Now build perfect filters. */
1209 if_maddr_rlock(ifp);
1210 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1211 if (ifma->ifma_addr->sa_family != AF_LINK)
1213 if (mcnt >= DC_ULI_FILTER_NPERF) {
1214 filter |= DC_NETCFG_RX_ALLMULTI;
1217 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1218 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]);
1219 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]);
1220 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]);
1223 if_maddr_runlock(ifp);
1225 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) {
1226 *sp++ = DC_SP_MAC(0xFFFF);
1227 *sp++ = DC_SP_MAC(0xFFFF);
1228 *sp++ = DC_SP_MAC(0xFFFF);
1231 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1232 CSR_WRITE_4(sc, DC_NETCFG,
1233 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1234 if (ifp->if_flags & IFF_PROMISC)
1235 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI;
1236 if (ifp->if_flags & IFF_ALLMULTI)
1237 filter |= DC_NETCFG_RX_ALLMULTI;
1238 CSR_WRITE_4(sc, DC_NETCFG,
1239 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1240 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1241 CSR_WRITE_4(sc, DC_NETCFG, filter);
1243 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1244 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1245 BUS_DMASYNC_PREWRITE);
1246 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1247 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1254 sc->dc_wdog_timer = 5;
1258 dc_setfilt_xircom(struct dc_softc *sc)
1260 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1262 struct ifmultiaddr *ifma;
1263 struct dc_desc *sframe;
1268 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1270 i = sc->dc_cdata.dc_tx_prod;
1271 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1272 sc->dc_cdata.dc_tx_cnt++;
1273 sframe = &sc->dc_ldata.dc_tx_list[i];
1274 sp = sc->dc_cdata.dc_sbuf;
1275 bzero(sp, DC_SFRAME_LEN);
1277 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1278 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1279 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1281 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1283 /* If we want promiscuous mode, set the allframes bit. */
1284 if (ifp->if_flags & IFF_PROMISC)
1285 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1287 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1289 if (ifp->if_flags & IFF_ALLMULTI)
1290 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1292 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1294 if_maddr_rlock(ifp);
1295 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1296 if (ifma->ifma_addr->sa_family != AF_LINK)
1298 h = dc_mchash_le(sc,
1299 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1300 sp[h >> 4] |= htole32(1 << (h & 0xF));
1302 if_maddr_runlock(ifp);
1304 if (ifp->if_flags & IFF_BROADCAST) {
1305 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1306 sp[h >> 4] |= htole32(1 << (h & 0xF));
1309 /* Set our MAC address. */
1310 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1311 sp[0] = DC_SP_MAC(eaddr[0]);
1312 sp[1] = DC_SP_MAC(eaddr[1]);
1313 sp[2] = DC_SP_MAC(eaddr[2]);
1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1317 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1318 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1319 BUS_DMASYNC_PREWRITE);
1320 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1321 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1328 sc->dc_wdog_timer = 5;
1332 dc_setfilt(struct dc_softc *sc)
1335 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1336 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1337 dc_setfilt_21143(sc);
1340 dc_setfilt_asix(sc);
1342 if (DC_IS_ADMTEK(sc))
1343 dc_setfilt_admtek(sc);
1348 if (DC_IS_XIRCOM(sc))
1349 dc_setfilt_xircom(sc);
1353 dc_netcfg_wait(struct dc_softc *sc)
1358 for (i = 0; i < DC_TIMEOUT; i++) {
1359 isr = CSR_READ_4(sc, DC_ISR);
1360 if (isr & DC_ISR_TX_IDLE &&
1361 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1362 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1366 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) {
1367 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1368 device_printf(sc->dc_dev,
1369 "%s: failed to force tx to idle state\n", __func__);
1370 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1371 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1372 !DC_HAS_BROKEN_RXSTATE(sc))
1373 device_printf(sc->dc_dev,
1374 "%s: failed to force rx to idle state\n", __func__);
1379 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1380 * the netconfig register, we first have to put the transmit and/or
1381 * receive logic in the idle state.
1384 dc_setcfg(struct dc_softc *sc, int media)
1386 int restart = 0, watchdogreg;
1388 if (IFM_SUBTYPE(media) == IFM_NONE)
1391 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1393 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1397 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1398 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1399 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1400 if (sc->dc_pmode == DC_PMODE_MII) {
1401 if (DC_IS_INTEL(sc)) {
1402 /* There's a write enable bit here that reads as 1. */
1403 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1404 watchdogreg &= ~DC_WDOG_CTLWREN;
1405 watchdogreg |= DC_WDOG_JABBERDIS;
1406 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1408 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1410 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1411 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1412 if (sc->dc_type == DC_TYPE_98713)
1413 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1414 DC_NETCFG_SCRAMBLER));
1415 if (!DC_IS_DAVICOM(sc))
1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1417 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1419 if (DC_IS_PNIC(sc)) {
1420 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1422 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1430 if (IFM_SUBTYPE(media) == IFM_10_T) {
1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1432 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1433 if (sc->dc_pmode == DC_PMODE_MII) {
1434 /* There's a write enable bit here that reads as 1. */
1435 if (DC_IS_INTEL(sc)) {
1436 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1437 watchdogreg &= ~DC_WDOG_CTLWREN;
1438 watchdogreg |= DC_WDOG_JABBERDIS;
1439 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1441 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1443 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1444 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1445 if (sc->dc_type == DC_TYPE_98713)
1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1447 if (!DC_IS_DAVICOM(sc))
1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1449 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1451 if (DC_IS_PNIC(sc)) {
1452 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1453 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1454 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1457 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1459 if (DC_IS_INTEL(sc)) {
1460 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1461 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1462 if ((media & IFM_GMASK) == IFM_FDX)
1463 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1466 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1467 DC_CLRBIT(sc, DC_10BTCTRL,
1468 DC_TCTL_AUTONEGENBL);
1475 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1476 * PHY and we want HomePNA mode, set the portsel bit to turn
1477 * on the external MII port.
1479 if (DC_IS_DAVICOM(sc)) {
1480 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1481 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1484 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1488 if ((media & IFM_GMASK) == IFM_FDX) {
1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1490 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1491 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1494 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1495 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1503 dc_reset(struct dc_softc *sc)
1507 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1509 for (i = 0; i < DC_TIMEOUT; i++) {
1511 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1515 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1516 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) {
1518 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1522 if (i == DC_TIMEOUT)
1523 device_printf(sc->dc_dev, "reset never completed!\n");
1525 /* Wait a little while for the chip to get its brains in order. */
1528 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1529 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1530 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1533 * Bring the SIA out of reset. In some cases, it looks
1534 * like failing to unreset the SIA soon enough gets it
1535 * into a state where it will never come out of reset
1536 * until we reset the whole chip again.
1538 if (DC_IS_INTEL(sc)) {
1539 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1540 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF);
1541 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1545 static const struct dc_type *
1546 dc_devtype(device_t dev)
1548 const struct dc_type *t;
1553 devid = pci_get_devid(dev);
1554 rev = pci_get_revid(dev);
1556 while (t->dc_name != NULL) {
1557 if (devid == t->dc_devid && rev >= t->dc_minrev)
1566 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1567 * IDs against our list and return a device name if we find a match.
1568 * We do a little bit of extra work to identify the exact type of
1569 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1570 * but different revision IDs. The same is true for 98715/98715A
1571 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1572 * cases, the exact chip revision affects driver behavior.
1575 dc_probe(device_t dev)
1577 const struct dc_type *t;
1579 t = dc_devtype(dev);
1582 device_set_desc(dev, t->dc_name);
1583 return (BUS_PROBE_DEFAULT);
1590 dc_apply_fixup(struct dc_softc *sc, int media)
1592 struct dc_mediainfo *m;
1600 if (m->dc_media == media)
1608 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1609 reg = (p[0] | (p[1] << 8)) << 16;
1610 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1613 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1614 reg = (p[0] | (p[1] << 8)) << 16;
1615 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1620 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1622 struct dc_mediainfo *m;
1624 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1626 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1629 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1630 case DC_SIA_CODE_10BT:
1631 m->dc_media = IFM_10_T;
1633 case DC_SIA_CODE_10BT_FDX:
1634 m->dc_media = IFM_10_T | IFM_FDX;
1636 case DC_SIA_CODE_10B2:
1637 m->dc_media = IFM_10_2;
1639 case DC_SIA_CODE_10B5:
1640 m->dc_media = IFM_10_5;
1647 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1648 * Things apparently already work for cards that do
1649 * supply Media Specific Data.
1651 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1654 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1658 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1661 m->dc_next = sc->dc_mi;
1664 sc->dc_pmode = DC_PMODE_SIA;
1669 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1671 struct dc_mediainfo *m;
1673 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1675 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1678 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1679 m->dc_media = IFM_100_TX;
1681 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1682 m->dc_media = IFM_100_TX | IFM_FDX;
1685 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
1687 m->dc_next = sc->dc_mi;
1690 sc->dc_pmode = DC_PMODE_SYM;
1695 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1697 struct dc_mediainfo *m;
1700 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1702 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1705 /* We abuse IFM_AUTO to represent MII. */
1706 m->dc_media = IFM_AUTO;
1707 m->dc_gp_len = l->dc_gpr_len;
1710 p += sizeof(struct dc_eblock_mii);
1712 p += 2 * l->dc_gpr_len;
1713 m->dc_reset_len = *p;
1715 m->dc_reset_ptr = p;
1717 m->dc_next = sc->dc_mi;
1723 dc_read_srom(struct dc_softc *sc, int bits)
1727 size = DC_ROM_SIZE(bits);
1728 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
1729 if (sc->dc_srom == NULL) {
1730 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n");
1733 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1738 dc_parse_21143_srom(struct dc_softc *sc)
1740 struct dc_leaf_hdr *lhdr;
1741 struct dc_eblock_hdr *hdr;
1742 int error, have_mii, i, loff;
1746 loff = sc->dc_srom[27];
1747 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1750 ptr += sizeof(struct dc_leaf_hdr) - 1;
1752 * Look if we got a MII media block.
1754 for (i = 0; i < lhdr->dc_mcnt; i++) {
1755 hdr = (struct dc_eblock_hdr *)ptr;
1756 if (hdr->dc_type == DC_EBLOCK_MII)
1759 ptr += (hdr->dc_len & 0x7F);
1764 * Do the same thing again. Only use SIA and SYM media
1765 * blocks if no MII media block is available.
1768 ptr += sizeof(struct dc_leaf_hdr) - 1;
1770 for (i = 0; i < lhdr->dc_mcnt; i++) {
1771 hdr = (struct dc_eblock_hdr *)ptr;
1772 switch (hdr->dc_type) {
1774 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1778 error = dc_decode_leaf_sia(sc,
1779 (struct dc_eblock_sia *)hdr);
1783 error = dc_decode_leaf_sym(sc,
1784 (struct dc_eblock_sym *)hdr);
1787 /* Don't care. Yet. */
1790 ptr += (hdr->dc_len & 0x7F);
1797 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1802 ("%s: wrong number of segments (%d)", __func__, nseg));
1804 *paddr = segs->ds_addr;
1808 dc_dma_alloc(struct dc_softc *sc)
1812 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0,
1813 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1814 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1815 NULL, NULL, &sc->dc_ptag);
1817 device_printf(sc->dc_dev,
1818 "failed to allocate parent DMA tag\n");
1822 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1823 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1824 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1,
1825 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag);
1827 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n");
1831 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1832 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1,
1833 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag);
1835 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n");
1839 /* RX descriptor list. */
1840 error = bus_dmamem_alloc(sc->dc_rx_ltag,
1841 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT |
1842 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap);
1844 device_printf(sc->dc_dev,
1845 "failed to allocate DMA'able memory for RX list\n");
1848 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap,
1849 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr,
1850 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT);
1852 device_printf(sc->dc_dev,
1853 "failed to load DMA'able memory for RX list\n");
1856 /* TX descriptor list. */
1857 error = bus_dmamem_alloc(sc->dc_tx_ltag,
1858 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT |
1859 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap);
1861 device_printf(sc->dc_dev,
1862 "failed to allocate DMA'able memory for TX list\n");
1865 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap,
1866 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr,
1867 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT);
1869 device_printf(sc->dc_dev,
1870 "cannot load DMA'able memory for TX list\n");
1875 * Allocate a busdma tag and DMA safe memory for the multicast
1878 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1879 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1880 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
1881 0, NULL, NULL, &sc->dc_stag);
1883 device_printf(sc->dc_dev,
1884 "failed to create DMA tag for setup frame\n");
1887 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
1888 BUS_DMA_NOWAIT, &sc->dc_smap);
1890 device_printf(sc->dc_dev,
1891 "failed to allocate DMA'able memory for setup frame\n");
1894 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
1895 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
1897 device_printf(sc->dc_dev,
1898 "cannot load DMA'able memory for setup frame\n");
1902 /* Allocate a busdma tag for RX mbufs. */
1903 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0,
1904 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1905 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag);
1907 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n");
1911 /* Allocate a busdma tag for TX mbufs. */
1912 error = bus_dma_tag_create(sc->dc_ptag, 1, 0,
1913 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1914 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
1915 0, NULL, NULL, &sc->dc_tx_mtag);
1917 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n");
1921 /* Create the TX/RX busdma maps. */
1922 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1923 error = bus_dmamap_create(sc->dc_tx_mtag, 0,
1924 &sc->dc_cdata.dc_tx_map[i]);
1926 device_printf(sc->dc_dev,
1927 "failed to create TX mbuf dmamap\n");
1931 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1932 error = bus_dmamap_create(sc->dc_rx_mtag, 0,
1933 &sc->dc_cdata.dc_rx_map[i]);
1935 device_printf(sc->dc_dev,
1936 "failed to create RX mbuf dmamap\n");
1940 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap);
1942 device_printf(sc->dc_dev,
1943 "failed to create spare RX mbuf dmamap\n");
1952 dc_dma_free(struct dc_softc *sc)
1957 if (sc->dc_rx_mtag != NULL) {
1958 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1959 if (sc->dc_cdata.dc_rx_map[i] != NULL)
1960 bus_dmamap_destroy(sc->dc_rx_mtag,
1961 sc->dc_cdata.dc_rx_map[i]);
1963 if (sc->dc_sparemap != NULL)
1964 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap);
1965 bus_dma_tag_destroy(sc->dc_rx_mtag);
1969 if (sc->dc_rx_mtag != NULL) {
1970 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1971 if (sc->dc_cdata.dc_tx_map[i] != NULL)
1972 bus_dmamap_destroy(sc->dc_tx_mtag,
1973 sc->dc_cdata.dc_tx_map[i]);
1975 bus_dma_tag_destroy(sc->dc_tx_mtag);
1978 /* RX descriptor list. */
1979 if (sc->dc_rx_ltag) {
1980 if (sc->dc_ldata.dc_rx_list_paddr != 0)
1981 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap);
1982 if (sc->dc_ldata.dc_rx_list != NULL)
1983 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list,
1985 bus_dma_tag_destroy(sc->dc_rx_ltag);
1988 /* TX descriptor list. */
1989 if (sc->dc_tx_ltag) {
1990 if (sc->dc_ldata.dc_tx_list_paddr != 0)
1991 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap);
1992 if (sc->dc_ldata.dc_tx_list != NULL)
1993 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list,
1995 bus_dma_tag_destroy(sc->dc_tx_ltag);
1998 /* multicast setup frame. */
2000 if (sc->dc_saddr != 0)
2001 bus_dmamap_unload(sc->dc_stag, sc->dc_smap);
2002 if (sc->dc_cdata.dc_sbuf != NULL)
2003 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf,
2005 bus_dma_tag_destroy(sc->dc_stag);
2010 * Attach the interface. Allocate softc structures, do ifmedia
2011 * setup and ethernet/BPF attach.
2014 dc_attach(device_t dev)
2016 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
2018 struct dc_softc *sc;
2020 struct dc_mediainfo *m;
2021 uint32_t reg, revision;
2023 int error, mac_offset, n, phy, rid, tmp;
2026 sc = device_get_softc(dev);
2029 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2033 * Map control/status registers.
2035 pci_enable_busmaster(dev);
2038 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
2040 if (sc->dc_res == NULL) {
2041 device_printf(dev, "couldn't map ports/memory\n");
2046 sc->dc_btag = rman_get_bustag(sc->dc_res);
2047 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2049 /* Allocate interrupt. */
2051 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2052 RF_SHAREABLE | RF_ACTIVE);
2054 if (sc->dc_irq == NULL) {
2055 device_printf(dev, "couldn't map interrupt\n");
2060 /* Need this info to decide on a chip type. */
2061 sc->dc_info = dc_devtype(dev);
2062 revision = pci_get_revid(dev);
2065 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
2066 if (sc->dc_info->dc_devid !=
2067 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
2068 sc->dc_info->dc_devid !=
2069 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
2070 dc_eeprom_width(sc);
2072 switch (sc->dc_info->dc_devid) {
2073 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
2074 sc->dc_type = DC_TYPE_21143;
2075 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2076 sc->dc_flags |= DC_REDUCED_MII_POLL;
2077 /* Save EEPROM contents so we can parse them later. */
2078 error = dc_read_srom(sc, sc->dc_romwidth);
2082 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
2083 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
2084 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
2085 sc->dc_type = DC_TYPE_DM9102;
2086 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
2087 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
2088 sc->dc_flags |= DC_TX_ALIGN;
2089 sc->dc_pmode = DC_PMODE_MII;
2091 /* Increase the latency timer value. */
2092 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
2094 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
2095 sc->dc_type = DC_TYPE_AL981;
2096 sc->dc_flags |= DC_TX_USE_TX_INTR;
2097 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2098 sc->dc_pmode = DC_PMODE_MII;
2099 error = dc_read_srom(sc, sc->dc_romwidth);
2103 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983):
2104 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
2105 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
2106 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
2107 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
2108 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
2109 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
2110 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
2111 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
2112 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
2113 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
2114 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
2115 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
2116 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
2117 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
2118 sc->dc_type = DC_TYPE_AN983;
2119 sc->dc_flags |= DC_64BIT_HASH;
2120 sc->dc_flags |= DC_TX_USE_TX_INTR;
2121 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2122 sc->dc_pmode = DC_PMODE_MII;
2123 /* Don't read SROM for - auto-loaded on reset */
2125 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
2126 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
2127 if (revision < DC_REVISION_98713A) {
2128 sc->dc_type = DC_TYPE_98713;
2130 if (revision >= DC_REVISION_98713A) {
2131 sc->dc_type = DC_TYPE_98713A;
2132 sc->dc_flags |= DC_21143_NWAY;
2134 sc->dc_flags |= DC_REDUCED_MII_POLL;
2135 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2137 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
2138 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
2140 * Macronix MX98715AEC-C/D/E parts have only a
2141 * 128-bit hash table. We need to deal with these
2142 * in the same manner as the PNIC II so that we
2143 * get the right number of bits out of the
2146 if (revision >= DC_REVISION_98715AEC_C &&
2147 revision < DC_REVISION_98725)
2148 sc->dc_flags |= DC_128BIT_HASH;
2149 sc->dc_type = DC_TYPE_987x5;
2150 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2151 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2153 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
2154 sc->dc_type = DC_TYPE_987x5;
2155 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2156 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2158 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
2159 sc->dc_type = DC_TYPE_PNICII;
2160 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
2161 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2163 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
2164 sc->dc_type = DC_TYPE_PNIC;
2165 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
2166 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
2167 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2168 if (sc->dc_pnic_rx_buf == NULL) {
2169 device_printf(sc->dc_dev,
2170 "Could not allocate PNIC RX buffer\n");
2174 if (revision < DC_REVISION_82C169)
2175 sc->dc_pmode = DC_PMODE_SYM;
2177 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
2178 sc->dc_type = DC_TYPE_ASIX;
2179 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
2180 sc->dc_flags |= DC_REDUCED_MII_POLL;
2181 sc->dc_pmode = DC_PMODE_MII;
2183 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
2184 sc->dc_type = DC_TYPE_XIRCOM;
2185 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2188 * We don't actually need to coalesce, but we're doing
2189 * it to obtain a double word aligned buffer.
2190 * The DC_TX_COALESCE flag is required.
2192 sc->dc_pmode = DC_PMODE_MII;
2194 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
2195 sc->dc_type = DC_TYPE_CONEXANT;
2196 sc->dc_flags |= DC_TX_INTR_ALWAYS;
2197 sc->dc_flags |= DC_REDUCED_MII_POLL;
2198 sc->dc_pmode = DC_PMODE_MII;
2199 error = dc_read_srom(sc, sc->dc_romwidth);
2203 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261):
2204 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263):
2205 if (sc->dc_info->dc_devid ==
2206 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261))
2207 sc->dc_type = DC_TYPE_ULI_M5261;
2209 sc->dc_type = DC_TYPE_ULI_M5263;
2210 /* TX buffers should be aligned on 4 byte boundary. */
2211 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2213 sc->dc_pmode = DC_PMODE_MII;
2214 error = dc_read_srom(sc, sc->dc_romwidth);
2219 device_printf(dev, "unknown device: %x\n",
2220 sc->dc_info->dc_devid);
2224 /* Save the cache line size. */
2225 if (DC_IS_DAVICOM(sc))
2226 sc->dc_cachesize = 0;
2228 sc->dc_cachesize = pci_get_cachelnsz(dev);
2230 /* Reset the adapter. */
2233 /* Take 21143 out of snooze mode */
2234 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2235 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2236 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2237 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2241 * Try to learn something about the supported media.
2242 * We know that ASIX and ADMtek and Davicom devices
2243 * will *always* be using MII media, so that's a no-brainer.
2244 * The tricky ones are the Macronix/PNIC II and the
2247 if (DC_IS_INTEL(sc)) {
2248 error = dc_parse_21143_srom(sc);
2251 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2252 if (sc->dc_type == DC_TYPE_98713)
2253 sc->dc_pmode = DC_PMODE_MII;
2255 sc->dc_pmode = DC_PMODE_SYM;
2256 } else if (!sc->dc_pmode)
2257 sc->dc_pmode = DC_PMODE_MII;
2260 * Get station address from the EEPROM.
2262 switch(sc->dc_type) {
2264 case DC_TYPE_98713A:
2266 case DC_TYPE_PNICII:
2267 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2268 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2269 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2272 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2274 case DC_TYPE_DM9102:
2275 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2278 * If this is an onboard dc(4) the station address read from
2279 * the EEPROM is all zero and we have to get it from the FCode.
2281 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2282 OF_getetheraddr(dev, (caddr_t)&eaddr);
2287 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2291 reg = CSR_READ_4(sc, DC_AL_PAR0);
2292 mac = (uint8_t *)&eaddr[0];
2293 mac[0] = (reg >> 0) & 0xff;
2294 mac[1] = (reg >> 8) & 0xff;
2295 mac[2] = (reg >> 16) & 0xff;
2296 mac[3] = (reg >> 24) & 0xff;
2297 reg = CSR_READ_4(sc, DC_AL_PAR1);
2298 mac[4] = (reg >> 0) & 0xff;
2299 mac[5] = (reg >> 8) & 0xff;
2301 case DC_TYPE_CONEXANT:
2302 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2305 case DC_TYPE_XIRCOM:
2306 /* The MAC comes from the CIS. */
2307 mac = pci_get_ether(dev);
2309 device_printf(dev, "No station address in CIS!\n");
2313 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2315 case DC_TYPE_ULI_M5261:
2316 case DC_TYPE_ULI_M5263:
2317 srom = (uint16_t *)sc->dc_srom;
2318 if (srom == NULL || *srom == 0xFFFF || *srom == 0) {
2320 * No valid SROM present, read station address
2324 "Reading station address from ID Table.\n");
2325 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000);
2326 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0);
2327 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2328 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010);
2329 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2330 CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2331 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0);
2332 mac = (uint8_t *)eaddr;
2333 for (n = 0; n < ETHER_ADDR_LEN; n++)
2334 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);
2335 CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2336 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000);
2339 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3,
2343 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2347 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr));
2349 * If we still have invalid station address, see whether we can
2350 * find station address for chip 0. Some multi-port controllers
2351 * just store station address for chip 0 if they have a shared
2354 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) ||
2355 (sc->dc_eaddr[0] == 0xffffffff &&
2356 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) {
2357 error = dc_check_multiport(sc);
2359 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr));
2360 /* Extract media information. */
2361 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) {
2362 while (sc->dc_mi != NULL) {
2363 m = sc->dc_mi->dc_next;
2364 free(sc->dc_mi, M_DEVBUF);
2367 error = dc_parse_21143_srom(sc);
2371 } else if (error == ENOMEM)
2377 if ((error = dc_dma_alloc(sc)) != 0)
2380 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2382 device_printf(dev, "can not if_alloc()\n");
2387 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2389 ifp->if_ioctl = dc_ioctl;
2390 ifp->if_start = dc_start;
2391 ifp->if_init = dc_init;
2392 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2393 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2394 IFQ_SET_READY(&ifp->if_snd);
2397 * Do MII setup. If this is a 21143, check for a PHY on the
2398 * MII bus after applying any necessary fixups to twiddle the
2399 * GPIO bits. If we don't end up finding a PHY, restore the
2400 * old selection (SIA only or SIA/SYM) and attach the dcphy
2404 if (DC_IS_INTEL(sc)) {
2405 dc_apply_fixup(sc, IFM_AUTO);
2407 sc->dc_pmode = DC_PMODE_MII;
2411 * Setup General Purpose port mode and data so the tulip can talk
2412 * to the MII. This needs to be done before mii_attach so that
2413 * we can actually see them.
2415 if (DC_IS_XIRCOM(sc)) {
2416 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2417 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2419 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2420 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2426 * Note: both the AL981 and AN983 have internal PHYs, however the
2427 * AL981 provides direct access to the PHY registers while the AN983
2428 * uses a serial MII interface. The AN983's MII interface is also
2429 * buggy in that you can read from any MII address (0 to 31), but
2430 * only address 1 behaves normally. To deal with both cases, we
2431 * pretend that the PHY is at MII address 1.
2433 if (DC_IS_ADMTEK(sc))
2434 phy = DC_ADMTEK_PHYADDR;
2437 * Note: the ukphy probes of the RS7112 report a PHY at MII address
2438 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the
2441 if (DC_IS_CONEXANT(sc))
2442 phy = DC_CONEXANT_PHYADDR;
2444 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2445 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
2447 if (error && DC_IS_INTEL(sc)) {
2449 if (sc->dc_pmode != DC_PMODE_SIA)
2450 sc->dc_pmode = DC_PMODE_SYM;
2451 sc->dc_flags |= DC_21143_NWAY;
2453 * For non-MII cards, we need to have the 21143
2454 * drive the LEDs. Except there are some systems
2455 * like the NEC VersaPro NoteBook PC which have no
2456 * LEDs, and twiddling these bits has adverse effects
2457 * on them. (I.e. you suddenly can't get a link.)
2459 if (!(pci_get_subvendor(dev) == 0x1033 &&
2460 pci_get_subdevice(dev) == 0x8028))
2461 sc->dc_flags |= DC_TULIP_LEDS;
2462 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2463 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
2468 device_printf(dev, "attaching PHYs failed\n");
2472 if (DC_IS_ADMTEK(sc)) {
2474 * Set automatic TX underrun recovery for the ADMtek chips
2476 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2480 * Tell the upper layer(s) we support long frames.
2482 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2483 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2484 ifp->if_capenable = ifp->if_capabilities;
2485 #ifdef DEVICE_POLLING
2486 ifp->if_capabilities |= IFCAP_POLLING;
2489 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2490 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2493 * Call MI attach routine.
2495 ether_ifattach(ifp, (caddr_t)eaddr);
2497 /* Hook interrupt last to avoid having to lock softc */
2498 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2499 NULL, dc_intr, sc, &sc->dc_intrhand);
2502 device_printf(dev, "couldn't set up irq\n");
2503 ether_ifdetach(ifp);
2514 * Shutdown hardware and free up resources. This can be called any
2515 * time after the mutex has been initialized. It is called in both
2516 * the error case in attach and the normal detach case so it needs
2517 * to be careful about only freeing resources that have actually been
2521 dc_detach(device_t dev)
2523 struct dc_softc *sc;
2525 struct dc_mediainfo *m;
2527 sc = device_get_softc(dev);
2528 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2532 #ifdef DEVICE_POLLING
2533 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
2534 ether_poll_deregister(ifp);
2537 /* These should only be active if attach succeeded */
2538 if (device_is_attached(dev)) {
2542 callout_drain(&sc->dc_stat_ch);
2543 callout_drain(&sc->dc_wdog_ch);
2544 ether_ifdetach(ifp);
2547 device_delete_child(dev, sc->dc_miibus);
2548 bus_generic_detach(dev);
2550 if (sc->dc_intrhand)
2551 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2553 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2555 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2562 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2564 while (sc->dc_mi != NULL) {
2565 m = sc->dc_mi->dc_next;
2566 free(sc->dc_mi, M_DEVBUF);
2569 free(sc->dc_srom, M_DEVBUF);
2571 mtx_destroy(&sc->dc_mtx);
2577 * Initialize the transmit descriptors.
2580 dc_list_tx_init(struct dc_softc *sc)
2582 struct dc_chain_data *cd;
2583 struct dc_list_data *ld;
2588 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2589 if (i == DC_TX_LIST_CNT - 1)
2593 ld->dc_tx_list[i].dc_status = 0;
2594 ld->dc_tx_list[i].dc_ctl = 0;
2595 ld->dc_tx_list[i].dc_data = 0;
2596 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2597 cd->dc_tx_chain[i] = NULL;
2600 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2602 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
2603 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2608 * Initialize the RX descriptors and allocate mbufs for them. Note that
2609 * we arrange the descriptors in a closed ring, so that the last descriptor
2610 * points back to the first.
2613 dc_list_rx_init(struct dc_softc *sc)
2615 struct dc_chain_data *cd;
2616 struct dc_list_data *ld;
2622 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2623 if (dc_newbuf(sc, i) != 0)
2625 if (i == DC_RX_LIST_CNT - 1)
2629 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2633 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2634 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2639 * Initialize an RX descriptor and attach an MBUF cluster.
2642 dc_newbuf(struct dc_softc *sc, int i)
2646 bus_dma_segment_t segs[1];
2649 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2652 m->m_len = m->m_pkthdr.len = MCLBYTES;
2653 m_adj(m, sizeof(u_int64_t));
2656 * If this is a PNIC chip, zero the buffer. This is part
2657 * of the workaround for the receive bug in the 82c168 and
2660 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2661 bzero(mtod(m, char *), m->m_len);
2663 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap,
2669 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__,
2671 if (sc->dc_cdata.dc_rx_chain[i] != NULL)
2672 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]);
2674 map = sc->dc_cdata.dc_rx_map[i];
2675 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2676 sc->dc_sparemap = map;
2677 sc->dc_cdata.dc_rx_chain[i] = m;
2678 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2679 BUS_DMASYNC_PREREAD);
2681 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2682 sc->dc_ldata.dc_rx_list[i].dc_data =
2683 htole32(DC_ADDR_LO(segs[0].ds_addr));
2684 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2685 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2686 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2692 * The PNIC chip has a terrible bug in it that manifests itself during
2693 * periods of heavy activity. The exact mode of failure if difficult to
2694 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2695 * will happen on slow machines. The bug is that sometimes instead of
2696 * uploading one complete frame during reception, it uploads what looks
2697 * like the entire contents of its FIFO memory. The frame we want is at
2698 * the end of the whole mess, but we never know exactly how much data has
2699 * been uploaded, so salvaging the frame is hard.
2701 * There is only one way to do it reliably, and it's disgusting.
2702 * Here's what we know:
2704 * - We know there will always be somewhere between one and three extra
2705 * descriptors uploaded.
2707 * - We know the desired received frame will always be at the end of the
2708 * total data upload.
2710 * - We know the size of the desired received frame because it will be
2711 * provided in the length field of the status word in the last descriptor.
2713 * Here's what we do:
2715 * - When we allocate buffers for the receive ring, we bzero() them.
2716 * This means that we know that the buffer contents should be all
2717 * zeros, except for data uploaded by the chip.
2719 * - We also force the PNIC chip to upload frames that include the
2720 * ethernet CRC at the end.
2722 * - We gather all of the bogus frame data into a single buffer.
2724 * - We then position a pointer at the end of this buffer and scan
2725 * backwards until we encounter the first non-zero byte of data.
2726 * This is the end of the received frame. We know we will encounter
2727 * some data at the end of the frame because the CRC will always be
2728 * there, so even if the sender transmits a packet of all zeros,
2729 * we won't be fooled.
2731 * - We know the size of the actual received frame, so we subtract
2732 * that value from the current pointer location. This brings us
2733 * to the start of the actual received packet.
2735 * - We copy this into an mbuf and pass it on, along with the actual
2738 * The performance hit is tremendous, but it beats dropping frames all
2742 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2744 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2746 struct dc_desc *cur_rx;
2747 struct dc_desc *c = NULL;
2748 struct mbuf *m = NULL;
2751 uint32_t rxstat = 0;
2753 i = sc->dc_pnic_rx_bug_save;
2754 cur_rx = &sc->dc_ldata.dc_rx_list[idx];
2755 ptr = sc->dc_pnic_rx_buf;
2756 bzero(ptr, DC_RXLEN * 5);
2758 /* Copy all the bytes from the bogus buffers. */
2760 c = &sc->dc_ldata.dc_rx_list[i];
2761 rxstat = le32toh(c->dc_status);
2762 m = sc->dc_cdata.dc_rx_chain[i];
2763 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2765 /* If this is the last buffer, break out. */
2766 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2768 dc_discard_rxbuf(sc, i);
2769 DC_INC(i, DC_RX_LIST_CNT);
2772 /* Find the length of the actual receive frame. */
2773 total_len = DC_RXBYTES(rxstat);
2775 /* Scan backwards until we hit a non-zero byte. */
2776 while (*ptr == 0x00)
2780 if ((uintptr_t)(ptr) & 0x3)
2783 /* Now find the start of the frame. */
2785 if (ptr < sc->dc_pnic_rx_buf)
2786 ptr = sc->dc_pnic_rx_buf;
2789 * Now copy the salvaged frame to the last mbuf and fake up
2790 * the status word to make it look like a successful
2793 bcopy(ptr, mtod(m, char *), total_len);
2794 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2798 * This routine searches the RX ring for dirty descriptors in the
2799 * event that the rxeof routine falls out of sync with the chip's
2800 * current descriptor pointer. This may happen sometimes as a result
2801 * of a "no RX buffer available" condition that happens when the chip
2802 * consumes all of the RX buffers before the driver has a chance to
2803 * process the RX ring. This routine may need to be called more than
2804 * once to bring the driver back in sync with the chip, however we
2805 * should still be getting RX DONE interrupts to drive the search
2806 * for new packets in the RX ring, so we should catch up eventually.
2809 dc_rx_resync(struct dc_softc *sc)
2811 struct dc_desc *cur_rx;
2814 pos = sc->dc_cdata.dc_rx_prod;
2816 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2817 cur_rx = &sc->dc_ldata.dc_rx_list[pos];
2818 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2820 DC_INC(pos, DC_RX_LIST_CNT);
2823 /* If the ring really is empty, then just return. */
2824 if (i == DC_RX_LIST_CNT)
2827 /* We've fallen behing the chip: catch it. */
2828 sc->dc_cdata.dc_rx_prod = pos;
2834 dc_discard_rxbuf(struct dc_softc *sc, int i)
2838 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2839 m = sc->dc_cdata.dc_rx_chain[i];
2840 bzero(mtod(m, char *), m->m_len);
2843 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2844 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2845 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD |
2846 BUS_DMASYNC_PREWRITE);
2850 * A frame has been uploaded: pass the resulting mbuf chain up to
2851 * the higher level protocols.
2854 dc_rxeof(struct dc_softc *sc)
2858 struct dc_desc *cur_rx;
2859 int i, total_len, rx_npkts;
2867 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD |
2868 BUS_DMASYNC_POSTWRITE);
2869 for (i = sc->dc_cdata.dc_rx_prod;
2870 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
2871 DC_INC(i, DC_RX_LIST_CNT)) {
2872 #ifdef DEVICE_POLLING
2873 if (ifp->if_capenable & IFCAP_POLLING) {
2874 if (sc->rxcycles <= 0)
2879 cur_rx = &sc->dc_ldata.dc_rx_list[i];
2880 rxstat = le32toh(cur_rx->dc_status);
2881 if ((rxstat & DC_RXSTAT_OWN) != 0)
2883 m = sc->dc_cdata.dc_rx_chain[i];
2884 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2885 BUS_DMASYNC_POSTREAD);
2886 total_len = DC_RXBYTES(rxstat);
2889 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2890 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2891 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2892 sc->dc_pnic_rx_bug_save = i;
2893 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0)
2895 dc_pnic_rx_bug_war(sc, i);
2896 rxstat = le32toh(cur_rx->dc_status);
2897 total_len = DC_RXBYTES(rxstat);
2902 * If an error occurs, update stats, clear the
2903 * status word and leave the mbuf cluster in place:
2904 * it should simply get re-used next time this descriptor
2905 * comes up in the ring. However, don't report long
2906 * frames as errors since they could be vlans.
2908 if ((rxstat & DC_RXSTAT_RXERR)) {
2909 if (!(rxstat & DC_RXSTAT_GIANT) ||
2910 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2911 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2912 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2913 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2914 if (rxstat & DC_RXSTAT_COLLSEEN)
2915 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
2916 dc_discard_rxbuf(sc, i);
2917 if (rxstat & DC_RXSTAT_CRCERR)
2920 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2927 /* No errors; receive the packet. */
2928 total_len -= ETHER_CRC_LEN;
2929 #ifdef __NO_STRICT_ALIGNMENT
2931 * On architectures without alignment problems we try to
2932 * allocate a new buffer for the receive ring, and pass up
2933 * the one where the packet is already, saving the expensive
2934 * copy done in m_devget().
2935 * If we are on an architecture with alignment problems, or
2936 * if the allocation fails, then use m_devget and leave the
2937 * existing buffer in the receive ring.
2939 if (dc_newbuf(sc, i) != 0) {
2940 dc_discard_rxbuf(sc, i);
2941 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2944 m->m_pkthdr.rcvif = ifp;
2945 m->m_pkthdr.len = m->m_len = total_len;
2950 m0 = m_devget(mtod(m, char *), total_len,
2951 ETHER_ALIGN, ifp, NULL);
2952 dc_discard_rxbuf(sc, i);
2954 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2961 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2963 (*ifp->if_input)(ifp, m);
2967 sc->dc_cdata.dc_rx_prod = i;
2972 * A frame was downloaded to the chip. It's safe for us to clean up
2976 dc_txeof(struct dc_softc *sc)
2978 struct dc_desc *cur_tx;
2981 uint32_t ctl, txstat;
2983 if (sc->dc_cdata.dc_tx_cnt == 0)
2989 * Go through our tx list and free mbufs for those
2990 * frames that have been transmitted.
2992 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD |
2993 BUS_DMASYNC_POSTWRITE);
2995 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod;
2996 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) {
2997 cur_tx = &sc->dc_ldata.dc_tx_list[idx];
2998 txstat = le32toh(cur_tx->dc_status);
2999 ctl = le32toh(cur_tx->dc_ctl);
3001 if (txstat & DC_TXSTAT_OWN)
3004 if (sc->dc_cdata.dc_tx_chain[idx] == NULL)
3007 if (ctl & DC_TXCTL_SETUP) {
3008 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP);
3010 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
3011 BUS_DMASYNC_POSTWRITE);
3013 * Yes, the PNIC is so brain damaged
3014 * that it will sometimes generate a TX
3015 * underrun error while DMAing the RX
3016 * filter setup frame. If we detect this,
3017 * we have to send the setup frame again,
3018 * or else the filter won't be programmed
3021 if (DC_IS_PNIC(sc)) {
3022 if (txstat & DC_TXSTAT_ERRSUM)
3025 sc->dc_cdata.dc_tx_chain[idx] = NULL;
3029 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
3031 * XXX: Why does my Xircom taunt me so?
3032 * For some reason it likes setting the CARRLOST flag
3033 * even when the carrier is there. wtf?!?
3034 * Who knows, but Conexant chips have the
3035 * same problem. Maybe they took lessons
3038 if (/*sc->dc_type == DC_TYPE_21143 &&*/
3039 sc->dc_pmode == DC_PMODE_MII &&
3040 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3041 DC_TXSTAT_NOCARRIER)))
3042 txstat &= ~DC_TXSTAT_ERRSUM;
3044 if (/*sc->dc_type == DC_TYPE_21143 &&*/
3045 sc->dc_pmode == DC_PMODE_MII &&
3046 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3047 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
3048 txstat &= ~DC_TXSTAT_ERRSUM;
3051 if (txstat & DC_TXSTAT_ERRSUM) {
3052 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3053 if (txstat & DC_TXSTAT_EXCESSCOLL)
3054 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
3055 if (txstat & DC_TXSTAT_LATECOLL)
3056 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
3057 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
3058 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3063 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3064 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3);
3066 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3067 BUS_DMASYNC_POSTWRITE);
3068 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3069 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
3070 sc->dc_cdata.dc_tx_chain[idx] = NULL;
3072 sc->dc_cdata.dc_tx_cons = idx;
3074 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3075 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3076 if (sc->dc_cdata.dc_tx_cnt == 0)
3077 sc->dc_wdog_timer = 0;
3080 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3081 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3087 struct dc_softc *sc;
3088 struct mii_data *mii;
3095 mii = device_get_softc(sc->dc_miibus);
3098 * Reclaim transmitted frames for controllers that do
3099 * not generate TX completion interrupt for every frame.
3101 if (sc->dc_flags & DC_TX_USE_TX_INTR)
3104 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
3105 if (sc->dc_flags & DC_21143_NWAY) {
3106 r = CSR_READ_4(sc, DC_10BTSTAT);
3107 if (IFM_SUBTYPE(mii->mii_media_active) ==
3108 IFM_100_TX && (r & DC_TSTAT_LS100)) {
3112 if (IFM_SUBTYPE(mii->mii_media_active) ==
3113 IFM_10_T && (r & DC_TSTAT_LS10)) {
3117 if (sc->dc_link == 0)
3121 * For NICs which never report DC_RXSTATE_WAIT, we
3122 * have to bite the bullet...
3124 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
3125 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
3126 sc->dc_cdata.dc_tx_cnt == 0)
3133 * When the init routine completes, we expect to be able to send
3134 * packets right away, and in fact the network code will send a
3135 * gratuitous ARP the moment the init routine marks the interface
3136 * as running. However, even though the MAC may have been initialized,
3137 * there may be a delay of a few seconds before the PHY completes
3138 * autonegotiation and the link is brought up. Any transmissions
3139 * made during that delay will be lost. Dealing with this is tricky:
3140 * we can't just pause in the init routine while waiting for the
3141 * PHY to come ready since that would bring the whole system to
3142 * a screeching halt for several seconds.
3144 * What we do here is prevent the TX start routine from sending
3145 * any packets until a link has been established. After the
3146 * interface has been initialized, the tick routine will poll
3147 * the state of the PHY until the IFM_ACTIVE flag is set. Until
3148 * that time, packets will stay in the send queue, and once the
3149 * link comes up, they will be flushed out to the wire.
3151 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3152 dc_start_locked(ifp);
3154 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3155 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3157 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3161 * A transmit underrun has occurred. Back off the transmit threshold,
3162 * or switch to store and forward mode if we have to.
3165 dc_tx_underrun(struct dc_softc *sc)
3167 uint32_t netcfg, isr;
3171 netcfg = CSR_READ_4(sc, DC_NETCFG);
3172 device_printf(sc->dc_dev, "TX underrun -- ");
3173 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) {
3174 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) {
3175 printf("using store and forward mode\n");
3176 netcfg |= DC_NETCFG_STORENFWD;
3178 printf("increasing TX threshold\n");
3179 sc->dc_txthresh += DC_TXTHRESH_INC;
3180 netcfg &= ~DC_NETCFG_TX_THRESH;
3181 netcfg |= sc->dc_txthresh;
3184 if (DC_IS_INTEL(sc)) {
3186 * The real 21143 requires that the transmitter be idle
3187 * in order to change the transmit threshold or store
3188 * and forward state.
3190 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON);
3192 for (i = 0; i < DC_TIMEOUT; i++) {
3193 isr = CSR_READ_4(sc, DC_ISR);
3194 if (isr & DC_ISR_TX_IDLE)
3198 if (i == DC_TIMEOUT) {
3199 device_printf(sc->dc_dev,
3200 "%s: failed to force tx to idle state\n",
3206 printf("resetting\n");
3211 CSR_WRITE_4(sc, DC_NETCFG, netcfg);
3212 if (DC_IS_INTEL(sc))
3213 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON);
3215 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3220 #ifdef DEVICE_POLLING
3221 static poll_handler_t dc_poll;
3224 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3226 struct dc_softc *sc = ifp->if_softc;
3231 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3236 sc->rxcycles = count;
3237 rx_npkts = dc_rxeof(sc);
3239 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3240 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3241 dc_start_locked(ifp);
3243 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3246 status = CSR_READ_4(sc, DC_ISR);
3247 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3248 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3254 /* ack what we have */
3255 CSR_WRITE_4(sc, DC_ISR, status);
3257 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3258 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3259 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff));
3261 if (dc_rx_resync(sc))
3264 /* restart transmit unit if necessary */
3265 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3266 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3268 if (status & DC_ISR_TX_UNDERRUN)
3271 if (status & DC_ISR_BUS_ERR) {
3272 if_printf(ifp, "%s: bus error\n", __func__);
3273 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3280 #endif /* DEVICE_POLLING */
3285 struct dc_softc *sc;
3296 status = CSR_READ_4(sc, DC_ISR);
3297 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) {
3302 #ifdef DEVICE_POLLING
3303 if (ifp->if_capenable & IFCAP_POLLING) {
3308 /* Disable interrupts. */
3309 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3311 for (n = 16; n > 0; n--) {
3312 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3314 /* Ack interrupts. */
3315 CSR_WRITE_4(sc, DC_ISR, status);
3317 if (status & DC_ISR_RX_OK) {
3318 if (dc_rxeof(sc) == 0) {
3319 while (dc_rx_resync(sc))
3324 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3327 if (status & DC_ISR_TX_IDLE) {
3329 if (sc->dc_cdata.dc_tx_cnt) {
3330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3331 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3335 if (status & DC_ISR_TX_UNDERRUN)
3338 if ((status & DC_ISR_RX_WATDOGTIMEO)
3339 || (status & DC_ISR_RX_NOBUF)) {
3340 r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3341 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff));
3342 if (dc_rxeof(sc) == 0) {
3343 while (dc_rx_resync(sc))
3348 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3349 dc_start_locked(ifp);
3351 if (status & DC_ISR_BUS_ERR) {
3352 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3357 status = CSR_READ_4(sc, DC_ISR);
3358 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0)
3362 /* Re-enable interrupts. */
3363 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3364 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3370 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3371 * pointers to the fragment pointers.
3374 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3376 bus_dma_segment_t segs[DC_MAXFRAGS];
3380 int cur, defragged, error, first, frag, i, idx, nseg;
3384 if (sc->dc_flags & DC_TX_COALESCE &&
3385 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3386 m = m_defrag(*m_head, M_NOWAIT);
3390 * Count the number of frags in this chain to see if we
3391 * need to m_collapse. Since the descriptor list is shared
3392 * by all packets, we'll m_collapse long chains so that they
3393 * do not use up the entire list, even if they would fit.
3396 for (m = *m_head; m != NULL; m = m->m_next)
3398 if (i > DC_TX_LIST_CNT / 4 ||
3399 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3401 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS);
3405 if (defragged != 0) {
3414 idx = sc->dc_cdata.dc_tx_prod;
3415 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3416 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3417 if (error == EFBIG) {
3418 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT,
3419 DC_MAXFRAGS)) == NULL) {
3422 return (defragged != 0 ? error : ENOBUFS);
3425 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3426 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3432 } else if (error != 0)
3434 KASSERT(nseg <= DC_MAXFRAGS,
3435 ("%s: wrong number of segments (%d)", __func__, nseg));
3442 /* Check descriptor overruns. */
3443 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3444 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3447 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3448 BUS_DMASYNC_PREWRITE);
3450 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3451 for (i = 0; i < nseg; i++) {
3452 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3453 (frag == (DC_TX_LIST_CNT - 1)) &&
3454 (first != sc->dc_cdata.dc_tx_first)) {
3455 bus_dmamap_unload(sc->dc_tx_mtag,
3456 sc->dc_cdata.dc_tx_map[first]);
3462 f = &sc->dc_ldata.dc_tx_list[frag];
3463 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3466 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3468 f->dc_status = htole32(DC_TXSTAT_OWN);
3469 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr));
3471 DC_INC(frag, DC_TX_LIST_CNT);
3474 sc->dc_cdata.dc_tx_prod = frag;
3475 sc->dc_cdata.dc_tx_cnt += nseg;
3476 sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3477 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3478 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3479 sc->dc_ldata.dc_tx_list[first].dc_ctl |=
3480 htole32(DC_TXCTL_FINT);
3481 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3482 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3483 if (sc->dc_flags & DC_TX_USE_TX_INTR &&
3484 ++sc->dc_cdata.dc_tx_pkts >= 8) {
3485 sc->dc_cdata.dc_tx_pkts = 0;
3486 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3488 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3490 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3491 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3494 * Swap the last and the first dmamaps to ensure the map for
3495 * this transmission is placed at the last descriptor.
3497 map = sc->dc_cdata.dc_tx_map[cur];
3498 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first];
3499 sc->dc_cdata.dc_tx_map[first] = map;
3505 dc_start(struct ifnet *ifp)
3507 struct dc_softc *sc;
3511 dc_start_locked(ifp);
3516 * Main transmit routine
3517 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3518 * regions directly in the transmit lists. We also save a copy of the
3519 * pointers since the transmit list fragment pointers are physical
3523 dc_start_locked(struct ifnet *ifp)
3525 struct dc_softc *sc;
3526 struct mbuf *m_head;
3533 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
3534 IFF_DRV_RUNNING || sc->dc_link == 0)
3537 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3539 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
3541 * If there's no way we can send any packets, return now.
3543 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3544 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3547 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3551 if (dc_encap(sc, &m_head)) {
3554 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3555 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3561 * If there's a BPF listener, bounce a copy of this frame
3564 BPF_MTAP(ifp, m_head);
3569 if (!(sc->dc_flags & DC_TX_POLL))
3570 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3573 * Set a timeout in case the chip goes out to lunch.
3575 sc->dc_wdog_timer = 5;
3582 struct dc_softc *sc = xsc;
3590 dc_init_locked(struct dc_softc *sc)
3592 struct ifnet *ifp = sc->dc_ifp;
3593 struct mii_data *mii;
3594 struct ifmedia *ifm;
3598 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3601 mii = device_get_softc(sc->dc_miibus);
3604 * Cancel pending I/O and free all RX/TX buffers.
3608 if (DC_IS_INTEL(sc)) {
3609 ifm = &mii->mii_media;
3610 dc_apply_fixup(sc, ifm->ifm_media);
3614 * Set cache alignment and burst length.
3616 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc))
3617 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3619 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3621 * Evenly share the bus between receive and transmit process.
3623 if (DC_IS_INTEL(sc))
3624 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3625 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3626 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3628 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3630 if (sc->dc_flags & DC_TX_POLL)
3631 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3632 switch(sc->dc_cachesize) {
3634 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3637 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3640 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3644 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3648 if (sc->dc_flags & DC_TX_STORENFWD)
3649 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3651 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3652 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3654 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3655 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3659 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3660 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3662 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3664 * The app notes for the 98713 and 98715A say that
3665 * in order to have the chips operate properly, a magic
3666 * number must be written to CSR16. Macronix does not
3667 * document the meaning of these bits so there's no way
3668 * to know exactly what they do. The 98713 has a magic
3669 * number all its own; the rest all use a different one.
3671 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3672 if (sc->dc_type == DC_TYPE_98713)
3673 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3675 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3678 if (DC_IS_XIRCOM(sc)) {
3680 * setup General Purpose Port mode and data so the tulip
3681 * can talk to the MII.
3683 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3684 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3686 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3687 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3691 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3692 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3694 /* Init circular RX list. */
3695 if (dc_list_rx_init(sc) == ENOBUFS) {
3696 device_printf(sc->dc_dev,
3697 "initialization failed: no memory for rx buffers\n");
3703 * Init TX descriptors.
3705 dc_list_tx_init(sc);
3708 * Load the address of the RX list.
3710 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3711 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3714 * Enable interrupts.
3716 #ifdef DEVICE_POLLING
3718 * ... but only if we are not polling, and make sure they are off in
3719 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3722 if (ifp->if_capenable & IFCAP_POLLING)
3723 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3726 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3727 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3729 /* Initialize TX jabber and RX watchdog timer. */
3731 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK |
3734 /* Enable transmitter. */
3735 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3738 * If this is an Intel 21143 and we're not using the
3739 * MII port, program the LED control pins so we get
3740 * link and activity indications.
3742 if (sc->dc_flags & DC_TULIP_LEDS) {
3743 CSR_WRITE_4(sc, DC_WATCHDOG,
3744 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3745 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3749 * Load the RX/multicast filter. We do this sort of late
3750 * because the filter programming scheme on the 21143 and
3751 * some clones requires DMAing a setup frame via the TX
3752 * engine, and we need the transmitter enabled for that.
3756 /* Enable receiver. */
3757 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3758 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3760 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3761 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3763 dc_ifmedia_upd_locked(sc);
3765 /* Clear missed frames and overflow counter. */
3766 CSR_READ_4(sc, DC_FRAMESDISCARDED);
3768 /* Don't start the ticker if this is a homePNA link. */
3769 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3772 if (sc->dc_flags & DC_21143_NWAY)
3773 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3775 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3778 sc->dc_wdog_timer = 0;
3779 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3783 * Set media options.
3786 dc_ifmedia_upd(struct ifnet *ifp)
3788 struct dc_softc *sc;
3793 error = dc_ifmedia_upd_locked(sc);
3799 dc_ifmedia_upd_locked(struct dc_softc *sc)
3801 struct mii_data *mii;
3802 struct ifmedia *ifm;
3808 mii = device_get_softc(sc->dc_miibus);
3809 error = mii_mediachg(mii);
3811 ifm = &mii->mii_media;
3812 if (DC_IS_INTEL(sc))
3813 dc_setcfg(sc, ifm->ifm_media);
3814 else if (DC_IS_DAVICOM(sc) &&
3815 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3816 dc_setcfg(sc, ifm->ifm_media);
3823 * Report current media status.
3826 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3828 struct dc_softc *sc;
3829 struct mii_data *mii;
3830 struct ifmedia *ifm;
3833 mii = device_get_softc(sc->dc_miibus);
3836 ifm = &mii->mii_media;
3837 if (DC_IS_DAVICOM(sc)) {
3838 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3839 ifmr->ifm_active = ifm->ifm_media;
3840 ifmr->ifm_status = 0;
3845 ifmr->ifm_active = mii->mii_media_active;
3846 ifmr->ifm_status = mii->mii_media_status;
3851 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3853 struct dc_softc *sc = ifp->if_softc;
3854 struct ifreq *ifr = (struct ifreq *)data;
3855 struct mii_data *mii;
3861 if (ifp->if_flags & IFF_UP) {
3862 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3863 (IFF_PROMISC | IFF_ALLMULTI);
3865 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3869 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3873 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3876 sc->dc_if_flags = ifp->if_flags;
3882 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3888 mii = device_get_softc(sc->dc_miibus);
3889 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3892 #ifdef DEVICE_POLLING
3893 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3894 !(ifp->if_capenable & IFCAP_POLLING)) {
3895 error = ether_poll_register(dc_poll, ifp);
3899 /* Disable interrupts */
3900 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3901 ifp->if_capenable |= IFCAP_POLLING;
3905 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3906 ifp->if_capenable & IFCAP_POLLING) {
3907 error = ether_poll_deregister(ifp);
3908 /* Enable interrupts. */
3910 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3911 ifp->if_capenable &= ~IFCAP_POLLING;
3915 #endif /* DEVICE_POLLING */
3918 error = ether_ioctl(ifp, command, data);
3926 dc_watchdog(void *xsc)
3928 struct dc_softc *sc = xsc;
3933 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3934 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3939 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3940 device_printf(sc->dc_dev, "watchdog timeout\n");
3942 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3945 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3946 dc_start_locked(ifp);
3950 * Stop the adapter and free any mbufs allocated to the
3954 dc_stop(struct dc_softc *sc)
3957 struct dc_list_data *ld;
3958 struct dc_chain_data *cd;
3960 uint32_t ctl, netcfg;
3968 callout_stop(&sc->dc_stat_ch);
3969 callout_stop(&sc->dc_wdog_ch);
3970 sc->dc_wdog_timer = 0;
3973 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3975 netcfg = CSR_READ_4(sc, DC_NETCFG);
3976 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3977 CSR_WRITE_4(sc, DC_NETCFG,
3978 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3979 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3980 /* Wait the completion of TX/RX SM. */
3981 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3984 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3985 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3988 * Free data in the RX lists.
3990 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3991 if (cd->dc_rx_chain[i] != NULL) {
3992 bus_dmamap_sync(sc->dc_rx_mtag,
3993 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD);
3994 bus_dmamap_unload(sc->dc_rx_mtag,
3996 m_freem(cd->dc_rx_chain[i]);
3997 cd->dc_rx_chain[i] = NULL;
4000 bzero(ld->dc_rx_list, DC_RX_LIST_SZ);
4001 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
4002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4005 * Free the TX list buffers.
4007 for (i = 0; i < DC_TX_LIST_CNT; i++) {
4008 if (cd->dc_tx_chain[i] != NULL) {
4009 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
4010 if (ctl & DC_TXCTL_SETUP) {
4011 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
4012 BUS_DMASYNC_POSTWRITE);
4014 bus_dmamap_sync(sc->dc_tx_mtag,
4015 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE);
4016 bus_dmamap_unload(sc->dc_tx_mtag,
4018 m_freem(cd->dc_tx_chain[i]);
4020 cd->dc_tx_chain[i] = NULL;
4023 bzero(ld->dc_tx_list, DC_TX_LIST_SZ);
4024 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
4025 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4029 * Device suspend routine. Stop the interface and save some PCI
4030 * settings in case the BIOS doesn't restore them properly on
4034 dc_suspend(device_t dev)
4036 struct dc_softc *sc;
4038 sc = device_get_softc(dev);
4048 * Device resume routine. Restore some PCI settings in case the BIOS
4049 * doesn't, re-enable busmastering, and restart the interface if
4053 dc_resume(device_t dev)
4055 struct dc_softc *sc;
4058 sc = device_get_softc(dev);
4061 /* reinitialize interface if necessary */
4063 if (ifp->if_flags & IFF_UP)
4073 * Stop all chip I/O so that the kernel's probe routines don't
4074 * get confused by errant DMAs when rebooting.
4077 dc_shutdown(device_t dev)
4079 struct dc_softc *sc;
4081 sc = device_get_softc(dev);
4091 dc_check_multiport(struct dc_softc *sc)
4093 struct dc_softc *dsc;
4099 dc = devclass_find("dc");
4100 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {
4101 child = devclass_get_device(dc, unit);
4104 if (child == sc->dc_dev)
4106 if (device_get_parent(child) != device_get_parent(sc->dc_dev))
4108 if (unit > device_get_unit(sc->dc_dev))
4110 if (device_is_attached(child) == 0)
4112 dsc = device_get_softc(child);
4113 device_printf(sc->dc_dev,
4114 "Using station address of %s as base\n",
4115 device_get_nameunit(child));
4116 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN);
4117 eaddr = (uint8_t *)sc->dc_eaddr;
4119 /* Prepare SROM to parse again. */
4120 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL &&
4121 sc->dc_romwidth != 0) {
4122 free(sc->dc_srom, M_DEVBUF);
4123 sc->dc_romwidth = dsc->dc_romwidth;
4124 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth),
4125 M_DEVBUF, M_NOWAIT);
4126 if (sc->dc_srom == NULL) {
4127 device_printf(sc->dc_dev,
4128 "Could not allocate SROM buffer\n");
4131 bcopy(dsc->dc_srom, sc->dc_srom,
4132 DC_ROM_SIZE(sc->dc_romwidth));