2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
52 * Conexant LANfinity (www.conexant.com)
53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
55 * Datasheets for the 21143 are available at developer.intel.com.
56 * Datasheets for the clone parts can be found at their respective sites.
57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
58 * The PNIC II is essentially a Macronix 98715A chip; the only difference
59 * worth noting is that its multicast hash table is only 128 bits wide
62 * Written by Bill Paul <wpaul@ee.columbia.edu>
63 * Electrical Engineering Department
64 * Columbia University, New York City
67 * The Intel 21143 is the successor to the DEC 21140. It is basically
68 * the same as the 21140 but with a few new features. The 21143 supports
69 * three kinds of media attachments:
71 * o MII port, for 10Mbps and 100Mbps support and NWAY
72 * autonegotiation provided by an external PHY.
73 * o SYM port, for symbol mode 100Mbps support.
77 * The 100Mbps SYM port and 10baseT port can be used together in
78 * combination with the internal NWAY support to create a 10/100
79 * autosensing configuration.
81 * Note that not all tulip workalikes are handled in this driver: we only
82 * deal with those which are relatively well behaved. The Winbond is
83 * handled separately due to its different register offsets and the
84 * special handling needed for its various bugs. The PNIC is handled
85 * here, but I'm not thrilled about it.
87 * All of the workalike chips use some form of MII transceiver support
88 * with the exception of the Macronix chips, which also have a SYM port.
89 * The ASIX AX88140A is also documented to have a SYM port, but all
90 * the cards I've seen use an MII transceiver, probably because the
91 * AX88140A doesn't support internal NWAY.
94 #ifdef HAVE_KERNEL_OPTION_HEADERS
95 #include "opt_device_polling.h"
98 #include <sys/param.h>
99 #include <sys/endian.h>
100 #include <sys/systm.h>
101 #include <sys/sockio.h>
102 #include <sys/mbuf.h>
103 #include <sys/malloc.h>
104 #include <sys/kernel.h>
105 #include <sys/module.h>
106 #include <sys/socket.h>
107 #include <sys/sysctl.h>
110 #include <net/if_arp.h>
111 #include <net/ethernet.h>
112 #include <net/if_dl.h>
113 #include <net/if_media.h>
114 #include <net/if_types.h>
115 #include <net/if_vlan_var.h>
119 #include <machine/bus.h>
120 #include <machine/resource.h>
122 #include <sys/rman.h>
124 #include <dev/mii/mii.h>
125 #include <dev/mii/miivar.h>
127 #include <dev/pci/pcireg.h>
128 #include <dev/pci/pcivar.h>
130 #define DC_USEIOSPACE
135 #include <dev/dc/if_dcreg.h>
138 #include <dev/ofw/openfirm.h>
139 #include <machine/ofw_machdep.h>
142 MODULE_DEPEND(dc, pci, 1, 1, 1);
143 MODULE_DEPEND(dc, ether, 1, 1, 1);
144 MODULE_DEPEND(dc, miibus, 1, 1, 1);
147 * "device miibus" is required in kernel config. See GENERIC if you get
150 #include "miibus_if.h"
153 * Various supported device vendors/types and their names.
155 static struct dc_type dc_devs[] = {
156 { DC_VENDORID_DEC, DC_DEVICEID_21143,
157 "Intel 21143 10/100BaseTX" },
158 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
159 "Davicom DM9009 10/100BaseTX" },
160 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
161 "Davicom DM9100 10/100BaseTX" },
162 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
163 "Davicom DM9102 10/100BaseTX" },
164 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
165 "Davicom DM9102A 10/100BaseTX" },
166 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
167 "ADMtek AL981 10/100BaseTX" },
168 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
169 "ADMtek AN985 10/100BaseTX" },
170 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
171 "ADMtek ADM9511 10/100BaseTX" },
172 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
173 "ADMtek ADM9513 10/100BaseTX" },
174 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
175 "Netgear FA511 10/100BaseTX" },
176 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
177 "ASIX AX88140A 10/100BaseTX" },
178 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
179 "ASIX AX88141 10/100BaseTX" },
180 { DC_VENDORID_MX, DC_DEVICEID_98713,
181 "Macronix 98713 10/100BaseTX" },
182 { DC_VENDORID_MX, DC_DEVICEID_98713,
183 "Macronix 98713A 10/100BaseTX" },
184 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
185 "Compex RL100-TX 10/100BaseTX" },
186 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
187 "Compex RL100-TX 10/100BaseTX" },
188 { DC_VENDORID_MX, DC_DEVICEID_987x5,
189 "Macronix 98715/98715A 10/100BaseTX" },
190 { DC_VENDORID_MX, DC_DEVICEID_987x5,
191 "Macronix 98715AEC-C 10/100BaseTX" },
192 { DC_VENDORID_MX, DC_DEVICEID_987x5,
193 "Macronix 98725 10/100BaseTX" },
194 { DC_VENDORID_MX, DC_DEVICEID_98727,
195 "Macronix 98727/98732 10/100BaseTX" },
196 { DC_VENDORID_LO, DC_DEVICEID_82C115,
197 "LC82C115 PNIC II 10/100BaseTX" },
198 { DC_VENDORID_LO, DC_DEVICEID_82C168,
199 "82c168 PNIC 10/100BaseTX" },
200 { DC_VENDORID_LO, DC_DEVICEID_82C168,
201 "82c169 PNIC 10/100BaseTX" },
202 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
203 "Accton EN1217 10/100BaseTX" },
204 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
205 "Accton EN2242 MiniPCI 10/100BaseTX" },
206 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
207 "Xircom X3201 10/100BaseTX" },
208 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
209 "Abocom FE2500 10/100BaseTX" },
210 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX,
211 "Abocom FE2500MX 10/100BaseTX" },
212 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
213 "Conexant LANfinity MiniPCI 10/100BaseTX" },
214 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX,
215 "Hawking CB102 CardBus 10/100" },
216 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T,
217 "PlaneX FNW-3602-T CardBus 10/100" },
218 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
219 "3Com OfficeConnect 10/100B" },
220 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120,
221 "Microsoft MN-120 CardBus 10/100" },
222 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130,
223 "Microsoft MN-130 10/100" },
224 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE,
225 "Microsoft MN-130 10/100" },
229 static int dc_probe(device_t);
230 static int dc_attach(device_t);
231 static int dc_detach(device_t);
232 static int dc_suspend(device_t);
233 static int dc_resume(device_t);
234 static struct dc_type *dc_devtype(device_t);
235 static int dc_newbuf(struct dc_softc *, int, int);
236 static int dc_encap(struct dc_softc *, struct mbuf **);
237 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
238 static int dc_rx_resync(struct dc_softc *);
239 static void dc_rxeof(struct dc_softc *);
240 static void dc_txeof(struct dc_softc *);
241 static void dc_tick(void *);
242 static void dc_tx_underrun(struct dc_softc *);
243 static void dc_intr(void *);
244 static void dc_start(struct ifnet *);
245 static void dc_start_locked(struct ifnet *);
246 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
247 static void dc_init(void *);
248 static void dc_init_locked(struct dc_softc *);
249 static void dc_stop(struct dc_softc *);
250 static void dc_watchdog(struct ifnet *);
251 static void dc_shutdown(device_t);
252 static int dc_ifmedia_upd(struct ifnet *);
253 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
255 static void dc_delay(struct dc_softc *);
256 static void dc_eeprom_idle(struct dc_softc *);
257 static void dc_eeprom_putbyte(struct dc_softc *, int);
258 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
259 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
260 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
261 static void dc_eeprom_width(struct dc_softc *);
262 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
264 static void dc_mii_writebit(struct dc_softc *, int);
265 static int dc_mii_readbit(struct dc_softc *);
266 static void dc_mii_sync(struct dc_softc *);
267 static void dc_mii_send(struct dc_softc *, u_int32_t, int);
268 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
269 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
270 static int dc_miibus_readreg(device_t, int, int);
271 static int dc_miibus_writereg(device_t, int, int, int);
272 static void dc_miibus_statchg(device_t);
273 static void dc_miibus_mediainit(device_t);
275 static void dc_setcfg(struct dc_softc *, int);
276 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
277 static uint32_t dc_mchash_be(const uint8_t *);
278 static void dc_setfilt_21143(struct dc_softc *);
279 static void dc_setfilt_asix(struct dc_softc *);
280 static void dc_setfilt_admtek(struct dc_softc *);
281 static void dc_setfilt_xircom(struct dc_softc *);
283 static void dc_setfilt(struct dc_softc *);
285 static void dc_reset(struct dc_softc *);
286 static int dc_list_rx_init(struct dc_softc *);
287 static int dc_list_tx_init(struct dc_softc *);
289 static void dc_read_srom(struct dc_softc *, int);
290 static void dc_parse_21143_srom(struct dc_softc *);
291 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
292 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
293 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
294 static void dc_apply_fixup(struct dc_softc *, int);
296 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
297 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
300 #define DC_RES SYS_RES_IOPORT
301 #define DC_RID DC_PCI_CFBIO
303 #define DC_RES SYS_RES_MEMORY
304 #define DC_RID DC_PCI_CFBMA
307 static device_method_t dc_methods[] = {
308 /* Device interface */
309 DEVMETHOD(device_probe, dc_probe),
310 DEVMETHOD(device_attach, dc_attach),
311 DEVMETHOD(device_detach, dc_detach),
312 DEVMETHOD(device_suspend, dc_suspend),
313 DEVMETHOD(device_resume, dc_resume),
314 DEVMETHOD(device_shutdown, dc_shutdown),
317 DEVMETHOD(bus_print_child, bus_generic_print_child),
318 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
321 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
322 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
323 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
324 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
329 static driver_t dc_driver = {
332 sizeof(struct dc_softc)
335 static devclass_t dc_devclass;
337 static int dc_quick = 1;
338 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0,
339 "do not m_devget() in dc driver");
342 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
343 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
344 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
346 #define DC_SETBIT(sc, reg, x) \
347 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
349 #define DC_CLRBIT(sc, reg, x) \
350 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
352 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
353 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
356 dc_delay(struct dc_softc *sc)
360 for (idx = (300 / 33) + 1; idx > 0; idx--)
361 CSR_READ_4(sc, DC_BUSCTL);
365 dc_eeprom_width(struct dc_softc *sc)
369 /* Force EEPROM to idle state. */
372 /* Enter EEPROM access mode. */
373 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
375 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
384 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
386 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
394 for (i = 1; i <= 12; i++) {
395 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
397 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
398 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
402 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
406 /* Turn off EEPROM access mode. */
414 /* Enter EEPROM access mode. */
415 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
417 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
424 /* Turn off EEPROM access mode. */
429 dc_eeprom_idle(struct dc_softc *sc)
433 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
435 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
442 for (i = 0; i < 25; i++) {
443 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
445 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
453 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
457 * Send a read command and address to the EEPROM, check for ACK.
460 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
464 d = DC_EECMD_READ >> 6;
467 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
471 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
473 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
478 * Feed in each bit and strobe the clock.
480 for (i = sc->dc_romwidth; i--;) {
481 if (addr & (1 << i)) {
482 SIO_SET(DC_SIO_EE_DATAIN);
484 SIO_CLR(DC_SIO_EE_DATAIN);
487 SIO_SET(DC_SIO_EE_CLK);
489 SIO_CLR(DC_SIO_EE_CLK);
495 * Read a word of data stored in the EEPROM at address 'addr.'
496 * The PNIC 82c168/82c169 has its own non-standard way to read
500 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
505 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
507 for (i = 0; i < DC_TIMEOUT; i++) {
509 r = CSR_READ_4(sc, DC_SIO);
510 if (!(r & DC_PN_SIOCTL_BUSY)) {
511 *dest = (u_int16_t)(r & 0xFFFF);
518 * Read a word of data stored in the EEPROM at address 'addr.'
519 * The Xircom X3201 has its own non-standard way to read
523 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
526 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
529 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
530 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
532 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
533 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
535 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
539 * Read a word of data stored in the EEPROM at address 'addr.'
542 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
547 /* Force EEPROM to idle state. */
550 /* Enter EEPROM access mode. */
551 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
553 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
555 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
557 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
561 * Send address of word we want to read.
563 dc_eeprom_putbyte(sc, addr);
566 * Start reading bits from EEPROM.
568 for (i = 0x8000; i; i >>= 1) {
569 SIO_SET(DC_SIO_EE_CLK);
571 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
574 SIO_CLR(DC_SIO_EE_CLK);
578 /* Turn off EEPROM access mode. */
585 * Read a sequence of words from the EEPROM.
588 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
591 u_int16_t word = 0, *ptr;
593 for (i = 0; i < cnt; i++) {
595 dc_eeprom_getword_pnic(sc, off + i, &word);
596 else if (DC_IS_XIRCOM(sc))
597 dc_eeprom_getword_xircom(sc, off + i, &word);
599 dc_eeprom_getword(sc, off + i, &word);
600 ptr = (u_int16_t *)(dest + (i * 2));
602 *ptr = be16toh(word);
604 *ptr = le16toh(word);
609 * The following two routines are taken from the Macronix 98713
610 * Application Notes pp.19-21.
613 * Write a bit to the MII bus.
616 dc_mii_writebit(struct dc_softc *sc, int bit)
620 CSR_WRITE_4(sc, DC_SIO,
621 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT);
623 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
625 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
626 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
630 * Read a bit from the MII bus.
633 dc_mii_readbit(struct dc_softc *sc)
636 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR);
637 CSR_READ_4(sc, DC_SIO);
638 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
639 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
640 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
647 * Sync the PHYs by setting data bit and strobing the clock 32 times.
650 dc_mii_sync(struct dc_softc *sc)
654 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
656 for (i = 0; i < 32; i++)
657 dc_mii_writebit(sc, 1);
661 * Clock a series of bits through the MII.
664 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
668 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
669 dc_mii_writebit(sc, bits & i);
673 * Read an PHY register through the MII.
676 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
681 * Set up frame for RX.
683 frame->mii_stdelim = DC_MII_STARTDELIM;
684 frame->mii_opcode = DC_MII_READOP;
685 frame->mii_turnaround = 0;
694 * Send command/address info.
696 dc_mii_send(sc, frame->mii_stdelim, 2);
697 dc_mii_send(sc, frame->mii_opcode, 2);
698 dc_mii_send(sc, frame->mii_phyaddr, 5);
699 dc_mii_send(sc, frame->mii_regaddr, 5);
703 dc_mii_writebit(sc, 1);
704 dc_mii_writebit(sc, 0);
708 ack = dc_mii_readbit(sc);
711 * Now try reading data bits. If the ack failed, we still
712 * need to clock through 16 cycles to keep the PHY(s) in sync.
715 for (i = 0; i < 16; i++)
720 for (i = 0x8000; i; i >>= 1) {
722 if (dc_mii_readbit(sc))
723 frame->mii_data |= i;
729 dc_mii_writebit(sc, 0);
730 dc_mii_writebit(sc, 0);
738 * Write to a PHY register through the MII.
741 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
745 * Set up frame for TX.
748 frame->mii_stdelim = DC_MII_STARTDELIM;
749 frame->mii_opcode = DC_MII_WRITEOP;
750 frame->mii_turnaround = DC_MII_TURNAROUND;
757 dc_mii_send(sc, frame->mii_stdelim, 2);
758 dc_mii_send(sc, frame->mii_opcode, 2);
759 dc_mii_send(sc, frame->mii_phyaddr, 5);
760 dc_mii_send(sc, frame->mii_regaddr, 5);
761 dc_mii_send(sc, frame->mii_turnaround, 2);
762 dc_mii_send(sc, frame->mii_data, 16);
765 dc_mii_writebit(sc, 0);
766 dc_mii_writebit(sc, 0);
772 dc_miibus_readreg(device_t dev, int phy, int reg)
774 struct dc_mii_frame frame;
776 int i, rval, phy_reg = 0;
778 sc = device_get_softc(dev);
779 bzero(&frame, sizeof(frame));
782 * Note: both the AL981 and AN985 have internal PHYs,
783 * however the AL981 provides direct access to the PHY
784 * registers while the AN985 uses a serial MII interface.
785 * The AN985's MII interface is also buggy in that you
786 * can read from any MII address (0 to 31), but only address 1
787 * behaves normally. To deal with both cases, we pretend
788 * that the PHY is at MII address 1.
790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
794 * Note: the ukphy probes of the RS7112 report a PHY at
795 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
796 * so we only respond to correct one.
798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
801 if (sc->dc_pmode != DC_PMODE_MII) {
802 if (phy == (MII_NPHY - 1)) {
806 * Fake something to make the probe
807 * code think there's a PHY here.
809 return (BMSR_MEDIAMASK);
813 return (DC_VENDORID_LO);
814 return (DC_VENDORID_DEC);
818 return (DC_DEVICEID_82C168);
819 return (DC_DEVICEID_21143);
829 if (DC_IS_PNIC(sc)) {
830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
831 (phy << 23) | (reg << 18));
832 for (i = 0; i < DC_TIMEOUT; i++) {
834 rval = CSR_READ_4(sc, DC_PN_MII);
835 if (!(rval & DC_PN_MII_BUSY)) {
837 return (rval == 0xFFFF ? 0 : rval);
843 if (DC_IS_COMET(sc)) {
846 phy_reg = DC_AL_BMCR;
849 phy_reg = DC_AL_BMSR;
852 phy_reg = DC_AL_VENID;
855 phy_reg = DC_AL_DEVID;
858 phy_reg = DC_AL_ANAR;
861 phy_reg = DC_AL_LPAR;
864 phy_reg = DC_AL_ANER;
867 device_printf(dev, "phy_read: bad phy register %x\n",
873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
880 frame.mii_phyaddr = phy;
881 frame.mii_regaddr = reg;
882 if (sc->dc_type == DC_TYPE_98713) {
883 phy_reg = CSR_READ_4(sc, DC_NETCFG);
884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
886 dc_mii_readreg(sc, &frame);
887 if (sc->dc_type == DC_TYPE_98713)
888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
890 return (frame.mii_data);
894 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
897 struct dc_mii_frame frame;
900 sc = device_get_softc(dev);
901 bzero(&frame, sizeof(frame));
903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
909 if (DC_IS_PNIC(sc)) {
910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
911 (phy << 23) | (reg << 10) | data);
912 for (i = 0; i < DC_TIMEOUT; i++) {
913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
919 if (DC_IS_COMET(sc)) {
922 phy_reg = DC_AL_BMCR;
925 phy_reg = DC_AL_BMSR;
928 phy_reg = DC_AL_VENID;
931 phy_reg = DC_AL_DEVID;
934 phy_reg = DC_AL_ANAR;
937 phy_reg = DC_AL_LPAR;
940 phy_reg = DC_AL_ANER;
943 device_printf(dev, "phy_write: bad phy register %x\n",
949 CSR_WRITE_4(sc, phy_reg, data);
953 frame.mii_phyaddr = phy;
954 frame.mii_regaddr = reg;
955 frame.mii_data = data;
957 if (sc->dc_type == DC_TYPE_98713) {
958 phy_reg = CSR_READ_4(sc, DC_NETCFG);
959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
961 dc_mii_writereg(sc, &frame);
962 if (sc->dc_type == DC_TYPE_98713)
963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
969 dc_miibus_statchg(device_t dev)
972 struct mii_data *mii;
975 sc = device_get_softc(dev);
976 if (DC_IS_ADMTEK(sc))
979 mii = device_get_softc(sc->dc_miibus);
980 ifm = &mii->mii_media;
981 if (DC_IS_DAVICOM(sc) &&
982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
983 dc_setcfg(sc, ifm->ifm_media);
984 sc->dc_if_media = ifm->ifm_media;
986 dc_setcfg(sc, mii->mii_media_active);
987 sc->dc_if_media = mii->mii_media_active;
992 * Special support for DM9102A cards with HomePNA PHYs. Note:
993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
994 * to be impossible to talk to the management interface of the DM9801
995 * PHY (its MDIO pin is not connected to anything). Consequently,
996 * the driver has to just 'know' about the additional mode and deal
997 * with it itself. *sigh*
1000 dc_miibus_mediainit(device_t dev)
1002 struct dc_softc *sc;
1003 struct mii_data *mii;
1004 struct ifmedia *ifm;
1007 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1009 sc = device_get_softc(dev);
1010 mii = device_get_softc(sc->dc_miibus);
1011 ifm = &mii->mii_media;
1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1017 #define DC_BITS_512 9
1018 #define DC_BITS_128 7
1019 #define DC_BITS_64 6
1022 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1026 /* Compute CRC for the address value. */
1027 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1030 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1031 * chips is only 128 bits wide.
1033 if (sc->dc_flags & DC_128BIT_HASH)
1034 return (crc & ((1 << DC_BITS_128) - 1));
1036 /* The hash table on the MX98715BEC is only 64 bits wide. */
1037 if (sc->dc_flags & DC_64BIT_HASH)
1038 return (crc & ((1 << DC_BITS_64) - 1));
1040 /* Xircom's hash filtering table is different (read: weird) */
1041 /* Xircom uses the LEAST significant bits */
1042 if (DC_IS_XIRCOM(sc)) {
1043 if ((crc & 0x180) == 0x180)
1044 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1046 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1050 return (crc & ((1 << DC_BITS_512) - 1));
1054 * Calculate CRC of a multicast group address, return the lower 6 bits.
1057 dc_mchash_be(const uint8_t *addr)
1061 /* Compute CRC for the address value. */
1062 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1064 /* Return the filter bit position. */
1065 return ((crc >> 26) & 0x0000003F);
1069 * 21143-style RX filter setup routine. Filter programming is done by
1070 * downloading a special setup frame into the TX engine. 21143, Macronix,
1071 * PNIC, PNIC II and Davicom chips are programmed this way.
1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1074 * address (our node address) and a 512-bit hash filter for multicast
1075 * frames. We also sneak the broadcast address into the hash filter since
1079 dc_setfilt_21143(struct dc_softc *sc)
1081 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1082 struct dc_desc *sframe;
1084 struct ifmultiaddr *ifma;
1090 i = sc->dc_cdata.dc_tx_prod;
1091 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1092 sc->dc_cdata.dc_tx_cnt++;
1093 sframe = &sc->dc_ldata->dc_tx_list[i];
1094 sp = sc->dc_cdata.dc_sbuf;
1095 bzero(sp, DC_SFRAME_LEN);
1097 sframe->dc_data = htole32(sc->dc_saddr);
1098 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1099 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1101 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1103 /* If we want promiscuous mode, set the allframes bit. */
1104 if (ifp->if_flags & IFF_PROMISC)
1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1109 if (ifp->if_flags & IFF_ALLMULTI)
1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1116 if (ifma->ifma_addr->sa_family != AF_LINK)
1118 h = dc_mchash_le(sc,
1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1120 sp[h >> 4] |= htole32(1 << (h & 0xF));
1122 IF_ADDR_UNLOCK(ifp);
1124 if (ifp->if_flags & IFF_BROADCAST) {
1125 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1126 sp[h >> 4] |= htole32(1 << (h & 0xF));
1129 /* Set our MAC address. */
1130 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1131 sp[39] = DC_SP_MAC(eaddr[0]);
1132 sp[40] = DC_SP_MAC(eaddr[1]);
1133 sp[41] = DC_SP_MAC(eaddr[2]);
1135 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1136 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1139 * The PNIC takes an exceedingly long time to process its
1140 * setup frame; wait 10ms after posting the setup frame
1141 * before proceeding, just so it has time to swallow its
1150 dc_setfilt_admtek(struct dc_softc *sc)
1152 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1154 struct ifmultiaddr *ifma;
1156 u_int32_t hashes[2] = { 0, 0 };
1160 /* Init our MAC address. */
1161 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1162 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[0]);
1163 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[1]);
1165 /* If we want promiscuous mode, set the allframes bit. */
1166 if (ifp->if_flags & IFF_PROMISC)
1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1171 if (ifp->if_flags & IFF_ALLMULTI)
1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1176 /* First, zot all the existing hash bits. */
1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1181 * If we're already in promisc or allmulti mode, we
1182 * don't have to bother programming the multicast filter.
1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1187 /* Now program new ones. */
1189 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1190 if (ifma->ifma_addr->sa_family != AF_LINK)
1192 if (DC_IS_CENTAUR(sc))
1193 h = dc_mchash_le(sc,
1194 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1197 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1199 hashes[0] |= (1 << h);
1201 hashes[1] |= (1 << (h - 32));
1203 IF_ADDR_UNLOCK(ifp);
1205 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1206 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1210 dc_setfilt_asix(struct dc_softc *sc)
1212 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1214 struct ifmultiaddr *ifma;
1216 u_int32_t hashes[2] = { 0, 0 };
1220 /* Init our MAC address. */
1221 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1227 /* If we want promiscuous mode, set the allframes bit. */
1228 if (ifp->if_flags & IFF_PROMISC)
1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1233 if (ifp->if_flags & IFF_ALLMULTI)
1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1239 * The ASIX chip has a special bit to enable reception
1240 * of broadcast frames.
1242 if (ifp->if_flags & IFF_BROADCAST)
1243 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1245 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1247 /* first, zot all the existing hash bits */
1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1254 * If we're already in promisc or allmulti mode, we
1255 * don't have to bother programming the multicast filter.
1257 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1260 /* now program new ones */
1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1263 if (ifma->ifma_addr->sa_family != AF_LINK)
1265 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1267 hashes[0] |= (1 << h);
1269 hashes[1] |= (1 << (h - 32));
1271 IF_ADDR_UNLOCK(ifp);
1273 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1274 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1280 dc_setfilt_xircom(struct dc_softc *sc)
1282 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1284 struct ifmultiaddr *ifma;
1285 struct dc_desc *sframe;
1290 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1292 i = sc->dc_cdata.dc_tx_prod;
1293 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1294 sc->dc_cdata.dc_tx_cnt++;
1295 sframe = &sc->dc_ldata->dc_tx_list[i];
1296 sp = sc->dc_cdata.dc_sbuf;
1297 bzero(sp, DC_SFRAME_LEN);
1299 sframe->dc_data = htole32(sc->dc_saddr);
1300 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1301 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1303 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1305 /* If we want promiscuous mode, set the allframes bit. */
1306 if (ifp->if_flags & IFF_PROMISC)
1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1311 if (ifp->if_flags & IFF_ALLMULTI)
1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1317 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1318 if (ifma->ifma_addr->sa_family != AF_LINK)
1320 h = dc_mchash_le(sc,
1321 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1322 sp[h >> 4] |= htole32(1 << (h & 0xF));
1324 IF_ADDR_UNLOCK(ifp);
1326 if (ifp->if_flags & IFF_BROADCAST) {
1327 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1328 sp[h >> 4] |= htole32(1 << (h & 0xF));
1331 /* Set our MAC address. */
1332 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1333 sp[0] = DC_SP_MAC(eaddr[0]);
1334 sp[1] = DC_SP_MAC(eaddr[1]);
1335 sp[2] = DC_SP_MAC(eaddr[2]);
1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1339 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1340 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1341 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1352 dc_setfilt(struct dc_softc *sc)
1355 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1356 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1357 dc_setfilt_21143(sc);
1360 dc_setfilt_asix(sc);
1362 if (DC_IS_ADMTEK(sc))
1363 dc_setfilt_admtek(sc);
1365 if (DC_IS_XIRCOM(sc))
1366 dc_setfilt_xircom(sc);
1370 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1371 * the netconfig register, we first have to put the transmit and/or
1372 * receive logic in the idle state.
1375 dc_setcfg(struct dc_softc *sc, int media)
1377 int i, restart = 0, watchdogreg;
1380 if (IFM_SUBTYPE(media) == IFM_NONE)
1383 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1385 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1387 for (i = 0; i < DC_TIMEOUT; i++) {
1388 isr = CSR_READ_4(sc, DC_ISR);
1389 if (isr & DC_ISR_TX_IDLE &&
1390 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1391 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1396 if (i == DC_TIMEOUT)
1397 if_printf(sc->dc_ifp,
1398 "failed to force tx and rx to idle state\n");
1401 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1402 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1404 if (sc->dc_pmode == DC_PMODE_MII) {
1405 if (DC_IS_INTEL(sc)) {
1406 /* There's a write enable bit here that reads as 1. */
1407 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1408 watchdogreg &= ~DC_WDOG_CTLWREN;
1409 watchdogreg |= DC_WDOG_JABBERDIS;
1410 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1412 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1414 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1415 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1416 if (sc->dc_type == DC_TYPE_98713)
1417 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1418 DC_NETCFG_SCRAMBLER));
1419 if (!DC_IS_DAVICOM(sc))
1420 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1421 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1422 if (DC_IS_INTEL(sc))
1423 dc_apply_fixup(sc, IFM_AUTO);
1425 if (DC_IS_PNIC(sc)) {
1426 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1427 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1428 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1430 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1433 if (DC_IS_INTEL(sc))
1435 (media & IFM_GMASK) == IFM_FDX ?
1436 IFM_100_TX | IFM_FDX : IFM_100_TX);
1440 if (IFM_SUBTYPE(media) == IFM_10_T) {
1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1443 if (sc->dc_pmode == DC_PMODE_MII) {
1444 /* There's a write enable bit here that reads as 1. */
1445 if (DC_IS_INTEL(sc)) {
1446 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1447 watchdogreg &= ~DC_WDOG_CTLWREN;
1448 watchdogreg |= DC_WDOG_JABBERDIS;
1449 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1451 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1453 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1454 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1455 if (sc->dc_type == DC_TYPE_98713)
1456 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1457 if (!DC_IS_DAVICOM(sc))
1458 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1459 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1460 if (DC_IS_INTEL(sc))
1461 dc_apply_fixup(sc, IFM_AUTO);
1463 if (DC_IS_PNIC(sc)) {
1464 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1465 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1466 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1468 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1469 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1470 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1471 if (DC_IS_INTEL(sc)) {
1472 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1473 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1474 if ((media & IFM_GMASK) == IFM_FDX)
1475 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1477 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1478 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1479 DC_CLRBIT(sc, DC_10BTCTRL,
1480 DC_TCTL_AUTONEGENBL);
1482 (media & IFM_GMASK) == IFM_FDX ?
1483 IFM_10_T | IFM_FDX : IFM_10_T);
1490 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1491 * PHY and we want HomePNA mode, set the portsel bit to turn
1492 * on the external MII port.
1494 if (DC_IS_DAVICOM(sc)) {
1495 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1499 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1503 if ((media & IFM_GMASK) == IFM_FDX) {
1504 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1505 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1506 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1508 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1509 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1510 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1514 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1518 dc_reset(struct dc_softc *sc)
1522 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1524 for (i = 0; i < DC_TIMEOUT; i++) {
1526 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1530 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1531 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1533 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1537 if (i == DC_TIMEOUT)
1538 if_printf(sc->dc_ifp, "reset never completed!\n");
1540 /* Wait a little while for the chip to get its brains in order. */
1543 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1544 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1545 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1548 * Bring the SIA out of reset. In some cases, it looks
1549 * like failing to unreset the SIA soon enough gets it
1550 * into a state where it will never come out of reset
1551 * until we reset the whole chip again.
1553 if (DC_IS_INTEL(sc)) {
1554 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1555 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1556 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1560 static struct dc_type *
1561 dc_devtype(device_t dev)
1568 while (t->dc_name != NULL) {
1569 if ((pci_get_vendor(dev) == t->dc_vid) &&
1570 (pci_get_device(dev) == t->dc_did)) {
1571 /* Check the PCI revision */
1572 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1573 if (t->dc_did == DC_DEVICEID_98713 &&
1574 rev >= DC_REVISION_98713A)
1576 if (t->dc_did == DC_DEVICEID_98713_CP &&
1577 rev >= DC_REVISION_98713A)
1579 if (t->dc_did == DC_DEVICEID_987x5 &&
1580 rev >= DC_REVISION_98715AEC_C)
1582 if (t->dc_did == DC_DEVICEID_987x5 &&
1583 rev >= DC_REVISION_98725)
1585 if (t->dc_did == DC_DEVICEID_AX88140A &&
1586 rev >= DC_REVISION_88141)
1588 if (t->dc_did == DC_DEVICEID_82C168 &&
1589 rev >= DC_REVISION_82C169)
1591 if (t->dc_did == DC_DEVICEID_DM9102 &&
1592 rev >= DC_REVISION_DM9102A)
1595 * The Microsoft MN-130 has a device ID of 0x0002,
1596 * which happens to be the same as the PNIC 82c168.
1597 * To keep dc_attach() from getting confused, we
1598 * pretend its ID is something different.
1599 * XXX: ideally, dc_attach() should be checking
1600 * vendorid+deviceid together to avoid such
1603 if (t->dc_vid == DC_VENDORID_MICROSOFT &&
1604 t->dc_did == DC_DEVICEID_MSMN130)
1615 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1616 * IDs against our list and return a device name if we find a match.
1617 * We do a little bit of extra work to identify the exact type of
1618 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1619 * but different revision IDs. The same is true for 98715/98715A
1620 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1621 * cases, the exact chip revision affects driver behavior.
1624 dc_probe(device_t dev)
1628 t = dc_devtype(dev);
1631 device_set_desc(dev, t->dc_name);
1632 return (BUS_PROBE_DEFAULT);
1639 dc_apply_fixup(struct dc_softc *sc, int media)
1641 struct dc_mediainfo *m;
1649 if (m->dc_media == media)
1657 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1658 reg = (p[0] | (p[1] << 8)) << 16;
1659 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1662 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1663 reg = (p[0] | (p[1] << 8)) << 16;
1664 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1669 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1671 struct dc_mediainfo *m;
1673 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1674 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1675 case DC_SIA_CODE_10BT:
1676 m->dc_media = IFM_10_T;
1678 case DC_SIA_CODE_10BT_FDX:
1679 m->dc_media = IFM_10_T | IFM_FDX;
1681 case DC_SIA_CODE_10B2:
1682 m->dc_media = IFM_10_2;
1684 case DC_SIA_CODE_10B5:
1685 m->dc_media = IFM_10_5;
1692 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1693 * Things apparently already work for cards that do
1694 * supply Media Specific Data.
1696 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1699 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1703 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1706 m->dc_next = sc->dc_mi;
1709 sc->dc_pmode = DC_PMODE_SIA;
1713 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1715 struct dc_mediainfo *m;
1717 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1718 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1719 m->dc_media = IFM_100_TX;
1721 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1722 m->dc_media = IFM_100_TX | IFM_FDX;
1725 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1727 m->dc_next = sc->dc_mi;
1730 sc->dc_pmode = DC_PMODE_SYM;
1734 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1736 struct dc_mediainfo *m;
1739 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1740 /* We abuse IFM_AUTO to represent MII. */
1741 m->dc_media = IFM_AUTO;
1742 m->dc_gp_len = l->dc_gpr_len;
1745 p += sizeof(struct dc_eblock_mii);
1747 p += 2 * l->dc_gpr_len;
1748 m->dc_reset_len = *p;
1750 m->dc_reset_ptr = p;
1752 m->dc_next = sc->dc_mi;
1757 dc_read_srom(struct dc_softc *sc, int bits)
1762 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1763 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1767 dc_parse_21143_srom(struct dc_softc *sc)
1769 struct dc_leaf_hdr *lhdr;
1770 struct dc_eblock_hdr *hdr;
1771 int have_mii, i, loff;
1775 loff = sc->dc_srom[27];
1776 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1779 ptr += sizeof(struct dc_leaf_hdr) - 1;
1781 * Look if we got a MII media block.
1783 for (i = 0; i < lhdr->dc_mcnt; i++) {
1784 hdr = (struct dc_eblock_hdr *)ptr;
1785 if (hdr->dc_type == DC_EBLOCK_MII)
1788 ptr += (hdr->dc_len & 0x7F);
1793 * Do the same thing again. Only use SIA and SYM media
1794 * blocks if no MII media block is available.
1797 ptr += sizeof(struct dc_leaf_hdr) - 1;
1798 for (i = 0; i < lhdr->dc_mcnt; i++) {
1799 hdr = (struct dc_eblock_hdr *)ptr;
1800 switch (hdr->dc_type) {
1802 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1806 dc_decode_leaf_sia(sc,
1807 (struct dc_eblock_sia *)hdr);
1811 dc_decode_leaf_sym(sc,
1812 (struct dc_eblock_sym *)hdr);
1815 /* Don't care. Yet. */
1818 ptr += (hdr->dc_len & 0x7F);
1824 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1828 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1830 *paddr = segs->ds_addr;
1834 * Attach the interface. Allocate softc structures, do ifmedia
1835 * setup and ethernet/BPF attach.
1838 dc_attach(device_t dev)
1841 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1843 struct dc_softc *sc;
1846 int error = 0, rid, mac_offset;
1850 sc = device_get_softc(dev);
1852 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1856 * Map control/status registers.
1858 pci_enable_busmaster(dev);
1861 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1863 if (sc->dc_res == NULL) {
1864 device_printf(dev, "couldn't map ports/memory\n");
1869 sc->dc_btag = rman_get_bustag(sc->dc_res);
1870 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1872 /* Allocate interrupt. */
1874 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1875 RF_SHAREABLE | RF_ACTIVE);
1877 if (sc->dc_irq == NULL) {
1878 device_printf(dev, "couldn't map interrupt\n");
1883 /* Need this info to decide on a chip type. */
1884 sc->dc_info = dc_devtype(dev);
1885 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1887 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1888 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1889 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1890 dc_eeprom_width(sc);
1892 switch (sc->dc_info->dc_did) {
1893 case DC_DEVICEID_21143:
1894 sc->dc_type = DC_TYPE_21143;
1895 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1896 sc->dc_flags |= DC_REDUCED_MII_POLL;
1897 /* Save EEPROM contents so we can parse them later. */
1898 dc_read_srom(sc, sc->dc_romwidth);
1900 case DC_DEVICEID_DM9009:
1901 case DC_DEVICEID_DM9100:
1902 case DC_DEVICEID_DM9102:
1903 sc->dc_type = DC_TYPE_DM9102;
1904 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1905 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1906 sc->dc_flags |= DC_TX_ALIGN;
1907 sc->dc_pmode = DC_PMODE_MII;
1908 /* Increase the latency timer value. */
1909 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1910 command &= 0xFFFF00FF;
1911 command |= 0x00008000;
1912 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1914 case DC_DEVICEID_AL981:
1915 sc->dc_type = DC_TYPE_AL981;
1916 sc->dc_flags |= DC_TX_USE_TX_INTR;
1917 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1918 sc->dc_pmode = DC_PMODE_MII;
1919 dc_read_srom(sc, sc->dc_romwidth);
1921 case DC_DEVICEID_AN985:
1922 case DC_DEVICEID_ADM9511:
1923 case DC_DEVICEID_ADM9513:
1924 case DC_DEVICEID_FA511:
1925 case DC_DEVICEID_FE2500:
1926 case DC_DEVICEID_EN2242:
1927 case DC_DEVICEID_HAWKING_PN672TX:
1928 case DC_DEVICEID_3CSOHOB:
1929 case DC_DEVICEID_MSMN120:
1930 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/
1931 sc->dc_type = DC_TYPE_AN985;
1932 sc->dc_flags |= DC_64BIT_HASH;
1933 sc->dc_flags |= DC_TX_USE_TX_INTR;
1934 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1935 sc->dc_pmode = DC_PMODE_MII;
1936 /* Don't read SROM for - auto-loaded on reset */
1938 case DC_DEVICEID_98713:
1939 case DC_DEVICEID_98713_CP:
1940 if (revision < DC_REVISION_98713A) {
1941 sc->dc_type = DC_TYPE_98713;
1943 if (revision >= DC_REVISION_98713A) {
1944 sc->dc_type = DC_TYPE_98713A;
1945 sc->dc_flags |= DC_21143_NWAY;
1947 sc->dc_flags |= DC_REDUCED_MII_POLL;
1948 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1950 case DC_DEVICEID_987x5:
1951 case DC_DEVICEID_EN1217:
1953 * Macronix MX98715AEC-C/D/E parts have only a
1954 * 128-bit hash table. We need to deal with these
1955 * in the same manner as the PNIC II so that we
1956 * get the right number of bits out of the
1959 if (revision >= DC_REVISION_98715AEC_C &&
1960 revision < DC_REVISION_98725)
1961 sc->dc_flags |= DC_128BIT_HASH;
1962 sc->dc_type = DC_TYPE_987x5;
1963 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1964 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1966 case DC_DEVICEID_98727:
1967 sc->dc_type = DC_TYPE_987x5;
1968 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1969 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1971 case DC_DEVICEID_82C115:
1972 sc->dc_type = DC_TYPE_PNICII;
1973 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1974 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1976 case DC_DEVICEID_82C168:
1977 sc->dc_type = DC_TYPE_PNIC;
1978 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
1979 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1980 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1981 if (revision < DC_REVISION_82C169)
1982 sc->dc_pmode = DC_PMODE_SYM;
1984 case DC_DEVICEID_AX88140A:
1985 sc->dc_type = DC_TYPE_ASIX;
1986 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
1987 sc->dc_flags |= DC_REDUCED_MII_POLL;
1988 sc->dc_pmode = DC_PMODE_MII;
1990 case DC_DEVICEID_X3201:
1991 sc->dc_type = DC_TYPE_XIRCOM;
1992 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1995 * We don't actually need to coalesce, but we're doing
1996 * it to obtain a double word aligned buffer.
1997 * The DC_TX_COALESCE flag is required.
1999 sc->dc_pmode = DC_PMODE_MII;
2001 case DC_DEVICEID_RS7112:
2002 sc->dc_type = DC_TYPE_CONEXANT;
2003 sc->dc_flags |= DC_TX_INTR_ALWAYS;
2004 sc->dc_flags |= DC_REDUCED_MII_POLL;
2005 sc->dc_pmode = DC_PMODE_MII;
2006 dc_read_srom(sc, sc->dc_romwidth);
2009 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
2013 /* Save the cache line size. */
2014 if (DC_IS_DAVICOM(sc))
2015 sc->dc_cachesize = 0;
2017 sc->dc_cachesize = pci_read_config(dev,
2018 DC_PCI_CFLT, 4) & 0xFF;
2020 /* Reset the adapter. */
2023 /* Take 21143 out of snooze mode */
2024 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2025 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2026 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2027 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2031 * Try to learn something about the supported media.
2032 * We know that ASIX and ADMtek and Davicom devices
2033 * will *always* be using MII media, so that's a no-brainer.
2034 * The tricky ones are the Macronix/PNIC II and the
2037 if (DC_IS_INTEL(sc))
2038 dc_parse_21143_srom(sc);
2039 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2040 if (sc->dc_type == DC_TYPE_98713)
2041 sc->dc_pmode = DC_PMODE_MII;
2043 sc->dc_pmode = DC_PMODE_SYM;
2044 } else if (!sc->dc_pmode)
2045 sc->dc_pmode = DC_PMODE_MII;
2048 * Get station address from the EEPROM.
2050 switch(sc->dc_type) {
2052 case DC_TYPE_98713A:
2054 case DC_TYPE_PNICII:
2055 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2056 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2057 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2060 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2062 case DC_TYPE_DM9102:
2063 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2066 * If this is an onboard dc(4) the station address read from
2067 * the EEPROM is all zero and we have to get it from the FCode.
2069 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2070 OF_getetheraddr(dev, (caddr_t)&eaddr);
2075 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2079 eaddr[0] = CSR_READ_4(sc, DC_AL_PAR0);
2080 eaddr[1] = CSR_READ_4(sc, DC_AL_PAR1);
2082 case DC_TYPE_CONEXANT:
2083 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2086 case DC_TYPE_XIRCOM:
2087 /* The MAC comes from the CIS. */
2088 mac = pci_get_ether(dev);
2090 device_printf(dev, "No station address in CIS!\n");
2094 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2097 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2101 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2102 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2103 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1,
2104 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag);
2106 device_printf(dev, "failed to allocate busdma tag\n");
2110 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2111 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
2113 device_printf(dev, "failed to allocate DMA safe memory\n");
2117 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
2118 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
2121 device_printf(dev, "cannot get address of the descriptors\n");
2127 * Allocate a busdma tag and DMA safe memory for the multicast
2130 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2131 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1,
2132 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag);
2134 device_printf(dev, "failed to allocate busdma tag\n");
2138 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2139 BUS_DMA_NOWAIT, &sc->dc_smap);
2141 device_printf(dev, "failed to allocate DMA safe memory\n");
2145 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2146 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2148 device_printf(dev, "cannot get address of the descriptors\n");
2153 /* Allocate a busdma tag for mbufs. */
2154 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
2155 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES,
2156 0, NULL, NULL, &sc->dc_mtag);
2158 device_printf(dev, "failed to allocate busdma tag\n");
2163 /* Create the TX/RX busdma maps. */
2164 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2165 error = bus_dmamap_create(sc->dc_mtag, 0,
2166 &sc->dc_cdata.dc_tx_map[i]);
2168 device_printf(dev, "failed to init TX ring\n");
2173 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2174 error = bus_dmamap_create(sc->dc_mtag, 0,
2175 &sc->dc_cdata.dc_rx_map[i]);
2177 device_printf(dev, "failed to init RX ring\n");
2182 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
2184 device_printf(dev, "failed to init RX ring\n");
2189 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2191 device_printf(dev, "can not if_alloc()\n");
2196 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2197 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */
2198 ifp->if_mtu = ETHERMTU;
2199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2200 ifp->if_ioctl = dc_ioctl;
2201 ifp->if_start = dc_start;
2202 ifp->if_watchdog = dc_watchdog;
2203 ifp->if_init = dc_init;
2204 ifp->if_baudrate = 10000000;
2205 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2206 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2207 IFQ_SET_READY(&ifp->if_snd);
2210 * Do MII setup. If this is a 21143, check for a PHY on the
2211 * MII bus after applying any necessary fixups to twiddle the
2212 * GPIO bits. If we don't end up finding a PHY, restore the
2213 * old selection (SIA only or SIA/SYM) and attach the dcphy
2216 if (DC_IS_INTEL(sc)) {
2217 dc_apply_fixup(sc, IFM_AUTO);
2219 sc->dc_pmode = DC_PMODE_MII;
2223 * Setup General Purpose port mode and data so the tulip can talk
2224 * to the MII. This needs to be done before mii_phy_probe so that
2225 * we can actually see them.
2227 if (DC_IS_XIRCOM(sc)) {
2228 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2229 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2231 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2232 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2236 error = mii_phy_probe(dev, &sc->dc_miibus,
2237 dc_ifmedia_upd, dc_ifmedia_sts);
2239 if (error && DC_IS_INTEL(sc)) {
2241 if (sc->dc_pmode != DC_PMODE_SIA)
2242 sc->dc_pmode = DC_PMODE_SYM;
2243 sc->dc_flags |= DC_21143_NWAY;
2244 mii_phy_probe(dev, &sc->dc_miibus,
2245 dc_ifmedia_upd, dc_ifmedia_sts);
2247 * For non-MII cards, we need to have the 21143
2248 * drive the LEDs. Except there are some systems
2249 * like the NEC VersaPro NoteBook PC which have no
2250 * LEDs, and twiddling these bits has adverse effects
2251 * on them. (I.e. you suddenly can't get a link.)
2253 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2254 sc->dc_flags |= DC_TULIP_LEDS;
2259 device_printf(dev, "MII without any PHY!\n");
2263 if (DC_IS_ADMTEK(sc)) {
2265 * Set automatic TX underrun recovery for the ADMtek chips
2267 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2271 * Tell the upper layer(s) we support long frames.
2273 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2274 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2275 ifp->if_capenable = ifp->if_capabilities;
2276 #ifdef DEVICE_POLLING
2277 ifp->if_capabilities |= IFCAP_POLLING;
2280 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2283 sc->dc_srm_media = 0;
2285 /* Remember the SRM console media setting */
2286 if (DC_IS_INTEL(sc)) {
2287 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2288 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2289 switch ((command >> 8) & 0xff) {
2291 sc->dc_srm_media = IFM_10_T;
2294 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2297 sc->dc_srm_media = IFM_100_TX;
2300 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2303 if (sc->dc_srm_media)
2304 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2309 * Call MI attach routine.
2311 ether_ifattach(ifp, (caddr_t)eaddr);
2313 /* Hook interrupt last to avoid having to lock softc */
2314 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2315 dc_intr, sc, &sc->dc_intrhand);
2318 device_printf(dev, "couldn't set up irq\n");
2319 ether_ifdetach(ifp);
2330 * Shutdown hardware and free up resources. This can be called any
2331 * time after the mutex has been initialized. It is called in both
2332 * the error case in attach and the normal detach case so it needs
2333 * to be careful about only freeing resources that have actually been
2337 dc_detach(device_t dev)
2339 struct dc_softc *sc;
2341 struct dc_mediainfo *m;
2344 sc = device_get_softc(dev);
2345 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2349 #ifdef DEVICE_POLLING
2350 if (ifp->if_capenable & IFCAP_POLLING)
2351 ether_poll_deregister(ifp);
2354 /* These should only be active if attach succeeded */
2355 if (device_is_attached(dev)) {
2359 callout_drain(&sc->dc_stat_ch);
2360 ether_ifdetach(ifp);
2363 device_delete_child(dev, sc->dc_miibus);
2364 bus_generic_detach(dev);
2366 if (sc->dc_intrhand)
2367 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2369 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2371 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2376 if (sc->dc_cdata.dc_sbuf != NULL)
2377 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
2378 if (sc->dc_ldata != NULL)
2379 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
2381 for (i = 0; i < DC_TX_LIST_CNT; i++)
2382 if (sc->dc_cdata.dc_tx_map[i] != NULL)
2383 bus_dmamap_destroy(sc->dc_mtag,
2384 sc->dc_cdata.dc_tx_map[i]);
2385 for (i = 0; i < DC_RX_LIST_CNT; i++)
2386 if (sc->dc_cdata.dc_rx_map[i] != NULL)
2387 bus_dmamap_destroy(sc->dc_mtag,
2388 sc->dc_cdata.dc_rx_map[i]);
2389 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
2392 bus_dma_tag_destroy(sc->dc_stag);
2394 bus_dma_tag_destroy(sc->dc_mtag);
2396 bus_dma_tag_destroy(sc->dc_ltag);
2398 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2400 while (sc->dc_mi != NULL) {
2401 m = sc->dc_mi->dc_next;
2402 free(sc->dc_mi, M_DEVBUF);
2405 free(sc->dc_srom, M_DEVBUF);
2407 mtx_destroy(&sc->dc_mtx);
2413 * Initialize the transmit descriptors.
2416 dc_list_tx_init(struct dc_softc *sc)
2418 struct dc_chain_data *cd;
2419 struct dc_list_data *ld;
2424 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2425 if (i == DC_TX_LIST_CNT - 1)
2429 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2430 cd->dc_tx_chain[i] = NULL;
2431 ld->dc_tx_list[i].dc_data = 0;
2432 ld->dc_tx_list[i].dc_ctl = 0;
2435 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2436 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2437 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2443 * Initialize the RX descriptors and allocate mbufs for them. Note that
2444 * we arrange the descriptors in a closed ring, so that the last descriptor
2445 * points back to the first.
2448 dc_list_rx_init(struct dc_softc *sc)
2450 struct dc_chain_data *cd;
2451 struct dc_list_data *ld;
2457 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2458 if (dc_newbuf(sc, i, 1) != 0)
2460 if (i == DC_RX_LIST_CNT - 1)
2464 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2468 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2474 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
2476 bus_dma_segment_t *segs;
2481 struct dc_softc *sc;
2485 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur];
2487 sc->dc_cdata.dc_rx_err = error;
2491 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
2492 sc->dc_cdata.dc_rx_err = 0;
2493 c->dc_data = htole32(segs->ds_addr);
2497 * Initialize an RX descriptor and attach an MBUF cluster.
2500 dc_newbuf(struct dc_softc *sc, int i, int alloc)
2507 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2511 m_new = sc->dc_cdata.dc_rx_chain[i];
2512 m_new->m_data = m_new->m_ext.ext_buf;
2514 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2515 m_adj(m_new, sizeof(u_int64_t));
2518 * If this is a PNIC chip, zero the buffer. This is part
2519 * of the workaround for the receive bug in the 82c168 and
2522 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2523 bzero(mtod(m_new, char *), m_new->m_len);
2525 /* No need to remap the mbuf if we're reusing it. */
2527 sc->dc_cdata.dc_rx_cur = i;
2528 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap,
2529 m_new, dc_dma_map_rxbuf, sc, 0);
2534 if (sc->dc_cdata.dc_rx_err != 0) {
2536 return (sc->dc_cdata.dc_rx_err);
2538 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2539 tmp = sc->dc_cdata.dc_rx_map[i];
2540 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2541 sc->dc_sparemap = tmp;
2542 sc->dc_cdata.dc_rx_chain[i] = m_new;
2545 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2546 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2547 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2548 BUS_DMASYNC_PREREAD);
2549 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2556 * The PNIC chip has a terrible bug in it that manifests itself during
2557 * periods of heavy activity. The exact mode of failure if difficult to
2558 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2559 * will happen on slow machines. The bug is that sometimes instead of
2560 * uploading one complete frame during reception, it uploads what looks
2561 * like the entire contents of its FIFO memory. The frame we want is at
2562 * the end of the whole mess, but we never know exactly how much data has
2563 * been uploaded, so salvaging the frame is hard.
2565 * There is only one way to do it reliably, and it's disgusting.
2566 * Here's what we know:
2568 * - We know there will always be somewhere between one and three extra
2569 * descriptors uploaded.
2571 * - We know the desired received frame will always be at the end of the
2572 * total data upload.
2574 * - We know the size of the desired received frame because it will be
2575 * provided in the length field of the status word in the last descriptor.
2577 * Here's what we do:
2579 * - When we allocate buffers for the receive ring, we bzero() them.
2580 * This means that we know that the buffer contents should be all
2581 * zeros, except for data uploaded by the chip.
2583 * - We also force the PNIC chip to upload frames that include the
2584 * ethernet CRC at the end.
2586 * - We gather all of the bogus frame data into a single buffer.
2588 * - We then position a pointer at the end of this buffer and scan
2589 * backwards until we encounter the first non-zero byte of data.
2590 * This is the end of the received frame. We know we will encounter
2591 * some data at the end of the frame because the CRC will always be
2592 * there, so even if the sender transmits a packet of all zeros,
2593 * we won't be fooled.
2595 * - We know the size of the actual received frame, so we subtract
2596 * that value from the current pointer location. This brings us
2597 * to the start of the actual received packet.
2599 * - We copy this into an mbuf and pass it on, along with the actual
2602 * The performance hit is tremendous, but it beats dropping frames all
2606 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2608 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2610 struct dc_desc *cur_rx;
2611 struct dc_desc *c = NULL;
2612 struct mbuf *m = NULL;
2615 u_int32_t rxstat = 0;
2617 i = sc->dc_pnic_rx_bug_save;
2618 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2619 ptr = sc->dc_pnic_rx_buf;
2620 bzero(ptr, DC_RXLEN * 5);
2622 /* Copy all the bytes from the bogus buffers. */
2624 c = &sc->dc_ldata->dc_rx_list[i];
2625 rxstat = le32toh(c->dc_status);
2626 m = sc->dc_cdata.dc_rx_chain[i];
2627 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2629 /* If this is the last buffer, break out. */
2630 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2632 dc_newbuf(sc, i, 0);
2633 DC_INC(i, DC_RX_LIST_CNT);
2636 /* Find the length of the actual receive frame. */
2637 total_len = DC_RXBYTES(rxstat);
2639 /* Scan backwards until we hit a non-zero byte. */
2640 while (*ptr == 0x00)
2644 if ((uintptr_t)(ptr) & 0x3)
2647 /* Now find the start of the frame. */
2649 if (ptr < sc->dc_pnic_rx_buf)
2650 ptr = sc->dc_pnic_rx_buf;
2653 * Now copy the salvaged frame to the last mbuf and fake up
2654 * the status word to make it look like a successful
2657 dc_newbuf(sc, i, 0);
2658 bcopy(ptr, mtod(m, char *), total_len);
2659 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2663 * This routine searches the RX ring for dirty descriptors in the
2664 * event that the rxeof routine falls out of sync with the chip's
2665 * current descriptor pointer. This may happen sometimes as a result
2666 * of a "no RX buffer available" condition that happens when the chip
2667 * consumes all of the RX buffers before the driver has a chance to
2668 * process the RX ring. This routine may need to be called more than
2669 * once to bring the driver back in sync with the chip, however we
2670 * should still be getting RX DONE interrupts to drive the search
2671 * for new packets in the RX ring, so we should catch up eventually.
2674 dc_rx_resync(struct dc_softc *sc)
2676 struct dc_desc *cur_rx;
2679 pos = sc->dc_cdata.dc_rx_prod;
2681 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2682 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2683 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2685 DC_INC(pos, DC_RX_LIST_CNT);
2688 /* If the ring really is empty, then just return. */
2689 if (i == DC_RX_LIST_CNT)
2692 /* We've fallen behing the chip: catch it. */
2693 sc->dc_cdata.dc_rx_prod = pos;
2699 * A frame has been uploaded: pass the resulting mbuf chain up to
2700 * the higher level protocols.
2703 dc_rxeof(struct dc_softc *sc)
2707 struct dc_desc *cur_rx;
2708 int i, total_len = 0;
2714 i = sc->dc_cdata.dc_rx_prod;
2716 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2717 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2719 #ifdef DEVICE_POLLING
2720 if (ifp->if_capenable & IFCAP_POLLING) {
2721 if (sc->rxcycles <= 0)
2726 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2727 rxstat = le32toh(cur_rx->dc_status);
2728 m = sc->dc_cdata.dc_rx_chain[i];
2729 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2730 BUS_DMASYNC_POSTREAD);
2731 total_len = DC_RXBYTES(rxstat);
2733 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2734 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2735 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2736 sc->dc_pnic_rx_bug_save = i;
2737 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2738 DC_INC(i, DC_RX_LIST_CNT);
2741 dc_pnic_rx_bug_war(sc, i);
2742 rxstat = le32toh(cur_rx->dc_status);
2743 total_len = DC_RXBYTES(rxstat);
2748 * If an error occurs, update stats, clear the
2749 * status word and leave the mbuf cluster in place:
2750 * it should simply get re-used next time this descriptor
2751 * comes up in the ring. However, don't report long
2752 * frames as errors since they could be vlans.
2754 if ((rxstat & DC_RXSTAT_RXERR)) {
2755 if (!(rxstat & DC_RXSTAT_GIANT) ||
2756 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2757 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2758 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2760 if (rxstat & DC_RXSTAT_COLLSEEN)
2761 ifp->if_collisions++;
2762 dc_newbuf(sc, i, 0);
2763 if (rxstat & DC_RXSTAT_CRCERR) {
2764 DC_INC(i, DC_RX_LIST_CNT);
2773 /* No errors; receive the packet. */
2774 total_len -= ETHER_CRC_LEN;
2777 * On the x86 we do not have alignment problems, so try to
2778 * allocate a new buffer for the receive ring, and pass up
2779 * the one where the packet is already, saving the expensive
2780 * copy done in m_devget().
2781 * If we are on an architecture with alignment problems, or
2782 * if the allocation fails, then use m_devget and leave the
2783 * existing buffer in the receive ring.
2785 if (dc_quick && dc_newbuf(sc, i, 1) == 0) {
2786 m->m_pkthdr.rcvif = ifp;
2787 m->m_pkthdr.len = m->m_len = total_len;
2788 DC_INC(i, DC_RX_LIST_CNT);
2794 m0 = m_devget(mtod(m, char *), total_len,
2795 ETHER_ALIGN, ifp, NULL);
2796 dc_newbuf(sc, i, 0);
2797 DC_INC(i, DC_RX_LIST_CNT);
2807 (*ifp->if_input)(ifp, m);
2811 sc->dc_cdata.dc_rx_prod = i;
2815 * A frame was downloaded to the chip. It's safe for us to clean up
2820 dc_txeof(struct dc_softc *sc)
2822 struct dc_desc *cur_tx = NULL;
2825 u_int32_t ctl, txstat;
2830 * Go through our tx list and free mbufs for those
2831 * frames that have been transmitted.
2833 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2834 idx = sc->dc_cdata.dc_tx_cons;
2835 while (idx != sc->dc_cdata.dc_tx_prod) {
2837 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2838 txstat = le32toh(cur_tx->dc_status);
2839 ctl = le32toh(cur_tx->dc_ctl);
2841 if (txstat & DC_TXSTAT_OWN)
2844 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2845 if (ctl & DC_TXCTL_SETUP) {
2847 * Yes, the PNIC is so brain damaged
2848 * that it will sometimes generate a TX
2849 * underrun error while DMAing the RX
2850 * filter setup frame. If we detect this,
2851 * we have to send the setup frame again,
2852 * or else the filter won't be programmed
2855 if (DC_IS_PNIC(sc)) {
2856 if (txstat & DC_TXSTAT_ERRSUM)
2859 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2861 sc->dc_cdata.dc_tx_cnt--;
2862 DC_INC(idx, DC_TX_LIST_CNT);
2866 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2868 * XXX: Why does my Xircom taunt me so?
2869 * For some reason it likes setting the CARRLOST flag
2870 * even when the carrier is there. wtf?!?
2871 * Who knows, but Conexant chips have the
2872 * same problem. Maybe they took lessons
2875 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2876 sc->dc_pmode == DC_PMODE_MII &&
2877 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2878 DC_TXSTAT_NOCARRIER)))
2879 txstat &= ~DC_TXSTAT_ERRSUM;
2881 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2882 sc->dc_pmode == DC_PMODE_MII &&
2883 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2884 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2885 txstat &= ~DC_TXSTAT_ERRSUM;
2888 if (txstat & DC_TXSTAT_ERRSUM) {
2890 if (txstat & DC_TXSTAT_EXCESSCOLL)
2891 ifp->if_collisions++;
2892 if (txstat & DC_TXSTAT_LATECOLL)
2893 ifp->if_collisions++;
2894 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2900 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2903 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2904 bus_dmamap_sync(sc->dc_mtag,
2905 sc->dc_cdata.dc_tx_map[idx],
2906 BUS_DMASYNC_POSTWRITE);
2907 bus_dmamap_unload(sc->dc_mtag,
2908 sc->dc_cdata.dc_tx_map[idx]);
2909 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2910 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2913 sc->dc_cdata.dc_tx_cnt--;
2914 DC_INC(idx, DC_TX_LIST_CNT);
2917 if (idx != sc->dc_cdata.dc_tx_cons) {
2918 /* Some buffers have been freed. */
2919 sc->dc_cdata.dc_tx_cons = idx;
2920 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2922 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2928 struct dc_softc *sc;
2929 struct mii_data *mii;
2936 mii = device_get_softc(sc->dc_miibus);
2938 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2939 if (sc->dc_flags & DC_21143_NWAY) {
2940 r = CSR_READ_4(sc, DC_10BTSTAT);
2941 if (IFM_SUBTYPE(mii->mii_media_active) ==
2942 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2946 if (IFM_SUBTYPE(mii->mii_media_active) ==
2947 IFM_10_T && (r & DC_TSTAT_LS10)) {
2951 if (sc->dc_link == 0)
2954 r = CSR_READ_4(sc, DC_ISR);
2955 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2956 sc->dc_cdata.dc_tx_cnt == 0) {
2958 if (!(mii->mii_media_status & IFM_ACTIVE))
2966 * When the init routine completes, we expect to be able to send
2967 * packets right away, and in fact the network code will send a
2968 * gratuitous ARP the moment the init routine marks the interface
2969 * as running. However, even though the MAC may have been initialized,
2970 * there may be a delay of a few seconds before the PHY completes
2971 * autonegotiation and the link is brought up. Any transmissions
2972 * made during that delay will be lost. Dealing with this is tricky:
2973 * we can't just pause in the init routine while waiting for the
2974 * PHY to come ready since that would bring the whole system to
2975 * a screeching halt for several seconds.
2977 * What we do here is prevent the TX start routine from sending
2978 * any packets until a link has been established. After the
2979 * interface has been initialized, the tick routine will poll
2980 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2981 * that time, packets will stay in the send queue, and once the
2982 * link comes up, they will be flushed out to the wire.
2984 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2985 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2987 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2988 dc_start_locked(ifp);
2991 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2992 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2994 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2998 * A transmit underrun has occurred. Back off the transmit threshold,
2999 * or switch to store and forward mode if we have to.
3002 dc_tx_underrun(struct dc_softc *sc)
3007 if (DC_IS_DAVICOM(sc))
3010 if (DC_IS_INTEL(sc)) {
3012 * The real 21143 requires that the transmitter be idle
3013 * in order to change the transmit threshold or store
3014 * and forward state.
3016 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3018 for (i = 0; i < DC_TIMEOUT; i++) {
3019 isr = CSR_READ_4(sc, DC_ISR);
3020 if (isr & DC_ISR_TX_IDLE)
3024 if (i == DC_TIMEOUT) {
3025 if_printf(sc->dc_ifp,
3026 "failed to force tx to idle state\n");
3031 if_printf(sc->dc_ifp, "TX underrun -- ");
3032 sc->dc_txthresh += DC_TXTHRESH_INC;
3033 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3034 printf("using store and forward mode\n");
3035 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3037 printf("increasing TX threshold\n");
3038 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3039 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3042 if (DC_IS_INTEL(sc))
3043 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3046 #ifdef DEVICE_POLLING
3047 static poll_handler_t dc_poll;
3050 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3052 struct dc_softc *sc = ifp->if_softc;
3056 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3061 sc->rxcycles = count;
3064 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3065 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3066 dc_start_locked(ifp);
3068 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3071 status = CSR_READ_4(sc, DC_ISR);
3072 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3073 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3079 /* ack what we have */
3080 CSR_WRITE_4(sc, DC_ISR, status);
3082 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3083 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3084 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3086 if (dc_rx_resync(sc))
3089 /* restart transmit unit if necessary */
3090 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3091 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3093 if (status & DC_ISR_TX_UNDERRUN)
3096 if (status & DC_ISR_BUS_ERR) {
3097 if_printf(ifp, "dc_poll: bus error\n");
3104 #endif /* DEVICE_POLLING */
3109 struct dc_softc *sc;
3118 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3123 #ifdef DEVICE_POLLING
3124 if (ifp->if_capenable & IFCAP_POLLING) {
3130 /* Suppress unwanted interrupts */
3131 if (!(ifp->if_flags & IFF_UP)) {
3132 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3138 /* Disable interrupts. */
3139 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3141 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
3142 status != 0xFFFFFFFF &&
3143 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3145 CSR_WRITE_4(sc, DC_ISR, status);
3147 if (status & DC_ISR_RX_OK) {
3149 curpkts = ifp->if_ipackets;
3151 if (curpkts == ifp->if_ipackets) {
3152 while (dc_rx_resync(sc))
3157 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3160 if (status & DC_ISR_TX_IDLE) {
3162 if (sc->dc_cdata.dc_tx_cnt) {
3163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3164 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3168 if (status & DC_ISR_TX_UNDERRUN)
3171 if ((status & DC_ISR_RX_WATDOGTIMEO)
3172 || (status & DC_ISR_RX_NOBUF)) {
3174 curpkts = ifp->if_ipackets;
3176 if (curpkts == ifp->if_ipackets) {
3177 while (dc_rx_resync(sc))
3182 if (status & DC_ISR_BUS_ERR) {
3188 /* Re-enable interrupts. */
3189 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3191 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3192 dc_start_locked(ifp);
3198 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error)
3200 bus_dma_segment_t *segs;
3205 struct dc_softc *sc;
3207 int cur, first, frag, i;
3211 sc->dc_cdata.dc_tx_err = error;
3215 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3216 for (i = 0; i < nseg; i++) {
3217 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3218 (frag == (DC_TX_LIST_CNT - 1)) &&
3219 (first != sc->dc_cdata.dc_tx_first)) {
3220 bus_dmamap_unload(sc->dc_mtag,
3221 sc->dc_cdata.dc_tx_map[first]);
3222 sc->dc_cdata.dc_tx_err = ENOBUFS;
3226 f = &sc->dc_ldata->dc_tx_list[frag];
3227 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3230 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3232 f->dc_status = htole32(DC_TXSTAT_OWN);
3233 f->dc_data = htole32(segs[i].ds_addr);
3235 DC_INC(frag, DC_TX_LIST_CNT);
3238 sc->dc_cdata.dc_tx_err = 0;
3239 sc->dc_cdata.dc_tx_prod = frag;
3240 sc->dc_cdata.dc_tx_cnt += nseg;
3241 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3242 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping;
3243 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3244 sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3245 htole32(DC_TXCTL_FINT);
3246 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3247 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3248 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3249 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3250 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3254 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3255 * pointers to the fragment pointers.
3258 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3261 int error, idx, chainlen = 0;
3264 * If there's no way we can send any packets, return now.
3266 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6)
3270 * Count the number of frags in this chain to see if
3271 * we need to m_defrag. Since the descriptor list is shared
3272 * by all packets, we'll m_defrag long chains so that they
3273 * do not use up the entire list, even if they would fit.
3275 for (m = *m_head; m != NULL; m = m->m_next)
3278 if ((chainlen > DC_TX_LIST_CNT / 4) ||
3279 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) {
3280 m = m_defrag(*m_head, M_DONTWAIT);
3287 * Start packing the mbufs in this chain into
3288 * the fragment pointers. Stop when we run out
3289 * of fragments or hit the end of the mbuf chain.
3291 idx = sc->dc_cdata.dc_tx_prod;
3292 sc->dc_cdata.dc_tx_mapping = *m_head;
3293 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3294 *m_head, dc_dma_map_txbuf, sc, 0);
3297 if (sc->dc_cdata.dc_tx_err != 0)
3298 return (sc->dc_cdata.dc_tx_err);
3299 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3300 BUS_DMASYNC_PREWRITE);
3301 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
3302 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3307 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3308 * to the mbuf data regions directly in the transmit lists. We also save a
3309 * copy of the pointers since the transmit list fragment pointers are
3310 * physical addresses.
3314 dc_start(struct ifnet *ifp)
3316 struct dc_softc *sc;
3320 dc_start_locked(ifp);
3325 dc_start_locked(struct ifnet *ifp)
3327 struct dc_softc *sc;
3328 struct mbuf *m_head = NULL, *m;
3329 unsigned int queued = 0;
3336 if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3339 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
3342 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3344 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3345 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3349 if (sc->dc_flags & DC_TX_COALESCE &&
3350 (m_head->m_next != NULL ||
3351 sc->dc_flags & DC_TX_ALIGN)) {
3352 m = m_defrag(m_head, M_DONTWAIT);
3354 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3355 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3362 if (dc_encap(sc, &m_head)) {
3363 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3364 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3367 idx = sc->dc_cdata.dc_tx_prod;
3371 * If there's a BPF listener, bounce a copy of this frame
3374 BPF_MTAP(ifp, m_head);
3376 if (sc->dc_flags & DC_TX_ONE) {
3377 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3384 if (!(sc->dc_flags & DC_TX_POLL))
3385 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3388 * Set a timeout in case the chip goes out to lunch.
3397 struct dc_softc *sc = xsc;
3402 if(sc->dc_srm_media) {
3404 struct mii_data *mii;
3406 ifr.ifr_media = sc->dc_srm_media;
3407 sc->dc_srm_media = 0;
3409 mii = device_get_softc(sc->dc_miibus);
3410 ifmedia_ioctl(sc->dc_ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3417 dc_init_locked(struct dc_softc *sc)
3419 struct ifnet *ifp = sc->dc_ifp;
3420 struct mii_data *mii;
3424 mii = device_get_softc(sc->dc_miibus);
3427 * Cancel pending I/O and free all RX/TX buffers.
3433 * Set cache alignment and burst length.
3435 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3436 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3438 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3440 * Evenly share the bus between receive and transmit process.
3442 if (DC_IS_INTEL(sc))
3443 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3444 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3445 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3447 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3449 if (sc->dc_flags & DC_TX_POLL)
3450 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3451 switch(sc->dc_cachesize) {
3453 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3456 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3459 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3463 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3467 if (sc->dc_flags & DC_TX_STORENFWD)
3468 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3470 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3471 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3474 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3478 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3481 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3483 * The app notes for the 98713 and 98715A say that
3484 * in order to have the chips operate properly, a magic
3485 * number must be written to CSR16. Macronix does not
3486 * document the meaning of these bits so there's no way
3487 * to know exactly what they do. The 98713 has a magic
3488 * number all its own; the rest all use a different one.
3490 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3491 if (sc->dc_type == DC_TYPE_98713)
3492 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3494 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3497 if (DC_IS_XIRCOM(sc)) {
3499 * setup General Purpose Port mode and data so the tulip
3500 * can talk to the MII.
3502 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3503 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3505 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3506 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3510 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3511 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3513 /* Init circular RX list. */
3514 if (dc_list_rx_init(sc) == ENOBUFS) {
3516 "initialization failed: no memory for rx buffers\n");
3522 * Init TX descriptors.
3524 dc_list_tx_init(sc);
3527 * Load the address of the RX list.
3529 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3530 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3533 * Enable interrupts.
3535 #ifdef DEVICE_POLLING
3537 * ... but only if we are not polling, and make sure they are off in
3538 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3541 if (ifp->if_capenable & IFCAP_POLLING)
3542 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3545 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3546 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3548 /* Enable transmitter. */
3549 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3552 * If this is an Intel 21143 and we're not using the
3553 * MII port, program the LED control pins so we get
3554 * link and activity indications.
3556 if (sc->dc_flags & DC_TULIP_LEDS) {
3557 CSR_WRITE_4(sc, DC_WATCHDOG,
3558 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3559 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3563 * Load the RX/multicast filter. We do this sort of late
3564 * because the filter programming scheme on the 21143 and
3565 * some clones requires DMAing a setup frame via the TX
3566 * engine, and we need the transmitter enabled for that.
3570 /* Enable receiver. */
3571 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3572 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3575 dc_setcfg(sc, sc->dc_if_media);
3577 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3578 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3580 /* Don't start the ticker if this is a homePNA link. */
3581 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3584 if (sc->dc_flags & DC_21143_NWAY)
3585 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3587 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3592 * Set media options.
3595 dc_ifmedia_upd(struct ifnet *ifp)
3597 struct dc_softc *sc;
3598 struct mii_data *mii;
3599 struct ifmedia *ifm;
3602 mii = device_get_softc(sc->dc_miibus);
3605 ifm = &mii->mii_media;
3607 if (DC_IS_DAVICOM(sc) &&
3608 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3609 dc_setcfg(sc, ifm->ifm_media);
3618 * Report current media status.
3621 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3623 struct dc_softc *sc;
3624 struct mii_data *mii;
3625 struct ifmedia *ifm;
3628 mii = device_get_softc(sc->dc_miibus);
3631 ifm = &mii->mii_media;
3632 if (DC_IS_DAVICOM(sc)) {
3633 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3634 ifmr->ifm_active = ifm->ifm_media;
3635 ifmr->ifm_status = 0;
3639 ifmr->ifm_active = mii->mii_media_active;
3640 ifmr->ifm_status = mii->mii_media_status;
3645 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3647 struct dc_softc *sc = ifp->if_softc;
3648 struct ifreq *ifr = (struct ifreq *)data;
3649 struct mii_data *mii;
3655 if (ifp->if_flags & IFF_UP) {
3656 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3657 (IFF_PROMISC | IFF_ALLMULTI);
3659 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3663 sc->dc_txthresh = 0;
3667 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3670 sc->dc_if_flags = ifp->if_flags;
3683 mii = device_get_softc(sc->dc_miibus);
3684 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3687 if (sc->dc_srm_media)
3688 sc->dc_srm_media = 0;
3693 #ifdef DEVICE_POLLING
3694 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3695 !(ifp->if_capenable & IFCAP_POLLING)) {
3696 error = ether_poll_register(dc_poll, ifp);
3700 /* Disable interrupts */
3701 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3702 ifp->if_capenable |= IFCAP_POLLING;
3707 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3708 ifp->if_capenable & IFCAP_POLLING) {
3709 error = ether_poll_deregister(ifp);
3710 /* Enable interrupts. */
3712 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3713 ifp->if_capenable &= ~IFCAP_POLLING;
3717 #endif /* DEVICE_POLLING */
3720 error = ether_ioctl(ifp, command, data);
3728 dc_watchdog(struct ifnet *ifp)
3730 struct dc_softc *sc;
3737 if_printf(ifp, "watchdog timeout\n");
3743 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3744 dc_start_locked(ifp);
3750 * Stop the adapter and free any mbufs allocated to the
3754 dc_stop(struct dc_softc *sc)
3757 struct dc_list_data *ld;
3758 struct dc_chain_data *cd;
3769 callout_stop(&sc->dc_stat_ch);
3771 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3773 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3774 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3775 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3776 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3780 * Free data in the RX lists.
3782 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3783 if (cd->dc_rx_chain[i] != NULL) {
3784 m_freem(cd->dc_rx_chain[i]);
3785 cd->dc_rx_chain[i] = NULL;
3788 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
3791 * Free the TX list buffers.
3793 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3794 if (cd->dc_tx_chain[i] != NULL) {
3795 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3796 if ((ctl & DC_TXCTL_SETUP) ||
3797 !(ctl & DC_TXCTL_LASTFRAG)) {
3798 cd->dc_tx_chain[i] = NULL;
3801 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
3802 m_freem(cd->dc_tx_chain[i]);
3803 cd->dc_tx_chain[i] = NULL;
3806 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
3810 * Device suspend routine. Stop the interface and save some PCI
3811 * settings in case the BIOS doesn't restore them properly on
3815 dc_suspend(device_t dev)
3817 struct dc_softc *sc;
3819 sc = device_get_softc(dev);
3829 * Device resume routine. Restore some PCI settings in case the BIOS
3830 * doesn't, re-enable busmastering, and restart the interface if
3834 dc_resume(device_t dev)
3836 struct dc_softc *sc;
3839 sc = device_get_softc(dev);
3842 /* reinitialize interface if necessary */
3844 if (ifp->if_flags & IFF_UP)
3854 * Stop all chip I/O so that the kernel's probe routines don't
3855 * get confused by errant DMAs when rebooting.
3858 dc_shutdown(device_t dev)
3860 struct dc_softc *sc;
3862 sc = device_get_softc(dev);
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