2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
49 * Accton EN1217 (www.accton.com)
50 * Xircom X3201 (www.xircom.com)
52 * Conexant LANfinity (www.conexant.com)
53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
55 * Datasheets for the 21143 are available at developer.intel.com.
56 * Datasheets for the clone parts can be found at their respective sites.
57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
58 * The PNIC II is essentially a Macronix 98715A chip; the only difference
59 * worth noting is that its multicast hash table is only 128 bits wide
62 * Written by Bill Paul <wpaul@ee.columbia.edu>
63 * Electrical Engineering Department
64 * Columbia University, New York City
67 * The Intel 21143 is the successor to the DEC 21140. It is basically
68 * the same as the 21140 but with a few new features. The 21143 supports
69 * three kinds of media attachments:
71 * o MII port, for 10Mbps and 100Mbps support and NWAY
72 * autonegotiation provided by an external PHY.
73 * o SYM port, for symbol mode 100Mbps support.
77 * The 100Mbps SYM port and 10baseT port can be used together in
78 * combination with the internal NWAY support to create a 10/100
79 * autosensing configuration.
81 * Note that not all tulip workalikes are handled in this driver: we only
82 * deal with those which are relatively well behaved. The Winbond is
83 * handled separately due to its different register offsets and the
84 * special handling needed for its various bugs. The PNIC is handled
85 * here, but I'm not thrilled about it.
87 * All of the workalike chips use some form of MII transceiver support
88 * with the exception of the Macronix chips, which also have a SYM port.
89 * The ASIX AX88140A is also documented to have a SYM port, but all
90 * the cards I've seen use an MII transceiver, probably because the
91 * AX88140A doesn't support internal NWAY.
94 #include <sys/param.h>
95 #include <sys/endian.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
99 #include <sys/malloc.h>
100 #include <sys/kernel.h>
101 #include <sys/module.h>
102 #include <sys/socket.h>
103 #include <sys/sysctl.h>
106 #include <net/if_arp.h>
107 #include <net/ethernet.h>
108 #include <net/if_dl.h>
109 #include <net/if_media.h>
110 #include <net/if_types.h>
111 #include <net/if_vlan_var.h>
115 #include <machine/bus.h>
116 #include <machine/resource.h>
118 #include <sys/rman.h>
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
126 #define DC_USEIOSPACE
131 #include <pci/if_dcreg.h>
134 #include <dev/ofw/openfirm.h>
135 #include <machine/ofw_machdep.h>
138 MODULE_DEPEND(dc, pci, 1, 1, 1);
139 MODULE_DEPEND(dc, ether, 1, 1, 1);
140 MODULE_DEPEND(dc, miibus, 1, 1, 1);
142 /* "controller miibus0" required. See GENERIC if you get errors here. */
143 #include "miibus_if.h"
146 * Various supported device vendors/types and their names.
148 static struct dc_type dc_devs[] = {
149 { DC_VENDORID_DEC, DC_DEVICEID_21143,
150 "Intel 21143 10/100BaseTX" },
151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
152 "Davicom DM9009 10/100BaseTX" },
153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
154 "Davicom DM9100 10/100BaseTX" },
155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
156 "Davicom DM9102 10/100BaseTX" },
157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
158 "Davicom DM9102A 10/100BaseTX" },
159 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
160 "ADMtek AL981 10/100BaseTX" },
161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
162 "ADMtek AN985 10/100BaseTX" },
163 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
164 "ADMtek ADM9511 10/100BaseTX" },
165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
166 "ADMtek ADM9513 10/100BaseTX" },
167 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
168 "Netgear FA511 10/100BaseTX" },
169 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
170 "ASIX AX88140A 10/100BaseTX" },
171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
172 "ASIX AX88141 10/100BaseTX" },
173 { DC_VENDORID_MX, DC_DEVICEID_98713,
174 "Macronix 98713 10/100BaseTX" },
175 { DC_VENDORID_MX, DC_DEVICEID_98713,
176 "Macronix 98713A 10/100BaseTX" },
177 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
178 "Compex RL100-TX 10/100BaseTX" },
179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
180 "Compex RL100-TX 10/100BaseTX" },
181 { DC_VENDORID_MX, DC_DEVICEID_987x5,
182 "Macronix 98715/98715A 10/100BaseTX" },
183 { DC_VENDORID_MX, DC_DEVICEID_987x5,
184 "Macronix 98715AEC-C 10/100BaseTX" },
185 { DC_VENDORID_MX, DC_DEVICEID_987x5,
186 "Macronix 98725 10/100BaseTX" },
187 { DC_VENDORID_MX, DC_DEVICEID_98727,
188 "Macronix 98727/98732 10/100BaseTX" },
189 { DC_VENDORID_LO, DC_DEVICEID_82C115,
190 "LC82C115 PNIC II 10/100BaseTX" },
191 { DC_VENDORID_LO, DC_DEVICEID_82C168,
192 "82c168 PNIC 10/100BaseTX" },
193 { DC_VENDORID_LO, DC_DEVICEID_82C168,
194 "82c169 PNIC 10/100BaseTX" },
195 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
196 "Accton EN1217 10/100BaseTX" },
197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
198 "Accton EN2242 MiniPCI 10/100BaseTX" },
199 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
200 "Xircom X3201 10/100BaseTX" },
201 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
202 "Abocom FE2500 10/100BaseTX" },
203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX,
204 "Abocom FE2500MX 10/100BaseTX" },
205 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
206 "Conexant LANfinity MiniPCI 10/100BaseTX" },
207 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX,
208 "Hawking CB102 CardBus 10/100" },
209 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T,
210 "PlaneX FNW-3602-T CardBus 10/100" },
211 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
212 "3Com OfficeConnect 10/100B" },
213 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120,
214 "Microsoft MN-120 CardBus 10/100" },
215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130,
216 "Microsoft MN-130 10/100" },
217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE,
218 "Microsoft MN-130 10/100" },
222 static int dc_probe(device_t);
223 static int dc_attach(device_t);
224 static int dc_detach(device_t);
225 static int dc_suspend(device_t);
226 static int dc_resume(device_t);
227 static struct dc_type *dc_devtype(device_t);
228 static int dc_newbuf(struct dc_softc *, int, int);
229 static int dc_encap(struct dc_softc *, struct mbuf **);
230 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
231 static int dc_rx_resync(struct dc_softc *);
232 static void dc_rxeof(struct dc_softc *);
233 static void dc_txeof(struct dc_softc *);
234 static void dc_tick(void *);
235 static void dc_tx_underrun(struct dc_softc *);
236 static void dc_intr(void *);
237 static void dc_start(struct ifnet *);
238 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
239 static void dc_init(void *);
240 static void dc_stop(struct dc_softc *);
241 static void dc_watchdog(struct ifnet *);
242 static void dc_shutdown(device_t);
243 static int dc_ifmedia_upd(struct ifnet *);
244 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
246 static void dc_delay(struct dc_softc *);
247 static void dc_eeprom_idle(struct dc_softc *);
248 static void dc_eeprom_putbyte(struct dc_softc *, int);
249 static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
250 static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
251 static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
252 static void dc_eeprom_width(struct dc_softc *);
253 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
255 static void dc_mii_writebit(struct dc_softc *, int);
256 static int dc_mii_readbit(struct dc_softc *);
257 static void dc_mii_sync(struct dc_softc *);
258 static void dc_mii_send(struct dc_softc *, u_int32_t, int);
259 static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
260 static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
261 static int dc_miibus_readreg(device_t, int, int);
262 static int dc_miibus_writereg(device_t, int, int, int);
263 static void dc_miibus_statchg(device_t);
264 static void dc_miibus_mediainit(device_t);
266 static void dc_setcfg(struct dc_softc *, int);
267 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
268 static uint32_t dc_mchash_be(const uint8_t *);
269 static void dc_setfilt_21143(struct dc_softc *);
270 static void dc_setfilt_asix(struct dc_softc *);
271 static void dc_setfilt_admtek(struct dc_softc *);
272 static void dc_setfilt_xircom(struct dc_softc *);
274 static void dc_setfilt(struct dc_softc *);
276 static void dc_reset(struct dc_softc *);
277 static int dc_list_rx_init(struct dc_softc *);
278 static int dc_list_tx_init(struct dc_softc *);
280 static void dc_read_srom(struct dc_softc *, int);
281 static void dc_parse_21143_srom(struct dc_softc *);
282 static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
283 static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
284 static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
285 static void dc_apply_fixup(struct dc_softc *, int);
287 static void dc_dma_map_txbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
288 static void dc_dma_map_rxbuf(void *, bus_dma_segment_t *, int, bus_size_t, int);
291 #define DC_RES SYS_RES_IOPORT
292 #define DC_RID DC_PCI_CFBIO
294 #define DC_RES SYS_RES_MEMORY
295 #define DC_RID DC_PCI_CFBMA
298 static device_method_t dc_methods[] = {
299 /* Device interface */
300 DEVMETHOD(device_probe, dc_probe),
301 DEVMETHOD(device_attach, dc_attach),
302 DEVMETHOD(device_detach, dc_detach),
303 DEVMETHOD(device_suspend, dc_suspend),
304 DEVMETHOD(device_resume, dc_resume),
305 DEVMETHOD(device_shutdown, dc_shutdown),
308 DEVMETHOD(bus_print_child, bus_generic_print_child),
309 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
312 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
313 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
314 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
315 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
320 static driver_t dc_driver = {
323 sizeof(struct dc_softc)
326 static devclass_t dc_devclass;
328 static int dc_quick = 1;
329 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0,
330 "do not m_devget() in dc driver");
333 DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0);
334 DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
335 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
337 #define DC_SETBIT(sc, reg, x) \
338 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
340 #define DC_CLRBIT(sc, reg, x) \
341 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
343 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
344 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
349 dc_delay(struct dc_softc *sc)
353 for (idx = (300 / 33) + 1; idx > 0; idx--)
354 CSR_READ_4(sc, DC_BUSCTL);
358 dc_eeprom_width(struct dc_softc *sc)
362 /* Force EEPROM to idle state. */
365 /* Enter EEPROM access mode. */
366 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
368 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
370 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
372 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
387 for (i = 1; i <= 12; i++) {
388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
390 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
399 /* Turn off EEPROM access mode. */
407 /* Enter EEPROM access mode. */
408 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
410 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
414 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
417 /* Turn off EEPROM access mode. */
422 dc_eeprom_idle(struct dc_softc *sc)
426 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
428 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
432 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
435 for (i = 0; i < 25; i++) {
436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
446 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
450 * Send a read command and address to the EEPROM, check for ACK.
453 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
457 d = DC_EECMD_READ >> 6;
460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
462 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
464 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
466 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
471 * Feed in each bit and strobe the clock.
473 for (i = sc->dc_romwidth; i--;) {
474 if (addr & (1 << i)) {
475 SIO_SET(DC_SIO_EE_DATAIN);
477 SIO_CLR(DC_SIO_EE_DATAIN);
480 SIO_SET(DC_SIO_EE_CLK);
482 SIO_CLR(DC_SIO_EE_CLK);
488 * Read a word of data stored in the EEPROM at address 'addr.'
489 * The PNIC 82c168/82c169 has its own non-standard way to read
493 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
498 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
500 for (i = 0; i < DC_TIMEOUT; i++) {
502 r = CSR_READ_4(sc, DC_SIO);
503 if (!(r & DC_PN_SIOCTL_BUSY)) {
504 *dest = (u_int16_t)(r & 0xFFFF);
511 * Read a word of data stored in the EEPROM at address 'addr.'
512 * The Xircom X3201 has its own non-standard way to read
516 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
519 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
522 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
523 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
525 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
526 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
528 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
532 * Read a word of data stored in the EEPROM at address 'addr.'
535 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
540 /* Force EEPROM to idle state. */
543 /* Enter EEPROM access mode. */
544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
554 * Send address of word we want to read.
556 dc_eeprom_putbyte(sc, addr);
559 * Start reading bits from EEPROM.
561 for (i = 0x8000; i; i >>= 1) {
562 SIO_SET(DC_SIO_EE_CLK);
564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
567 SIO_CLR(DC_SIO_EE_CLK);
571 /* Turn off EEPROM access mode. */
578 * Read a sequence of words from the EEPROM.
581 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
584 u_int16_t word = 0, *ptr;
586 for (i = 0; i < cnt; i++) {
588 dc_eeprom_getword_pnic(sc, off + i, &word);
589 else if (DC_IS_XIRCOM(sc))
590 dc_eeprom_getword_xircom(sc, off + i, &word);
592 dc_eeprom_getword(sc, off + i, &word);
593 ptr = (u_int16_t *)(dest + (i * 2));
595 *ptr = be16toh(word);
597 *ptr = le16toh(word);
602 * The following two routines are taken from the Macronix 98713
603 * Application Notes pp.19-21.
606 * Write a bit to the MII bus.
609 dc_mii_writebit(struct dc_softc *sc, int bit)
613 CSR_WRITE_4(sc, DC_SIO,
614 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT);
616 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
618 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
619 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
623 * Read a bit from the MII bus.
626 dc_mii_readbit(struct dc_softc *sc)
629 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR);
630 CSR_READ_4(sc, DC_SIO);
631 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
632 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
633 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
640 * Sync the PHYs by setting data bit and strobing the clock 32 times.
643 dc_mii_sync(struct dc_softc *sc)
647 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
649 for (i = 0; i < 32; i++)
650 dc_mii_writebit(sc, 1);
654 * Clock a series of bits through the MII.
657 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
661 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
662 dc_mii_writebit(sc, bits & i);
666 * Read an PHY register through the MII.
669 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
676 * Set up frame for RX.
678 frame->mii_stdelim = DC_MII_STARTDELIM;
679 frame->mii_opcode = DC_MII_READOP;
680 frame->mii_turnaround = 0;
689 * Send command/address info.
691 dc_mii_send(sc, frame->mii_stdelim, 2);
692 dc_mii_send(sc, frame->mii_opcode, 2);
693 dc_mii_send(sc, frame->mii_phyaddr, 5);
694 dc_mii_send(sc, frame->mii_regaddr, 5);
698 dc_mii_writebit(sc, 1);
699 dc_mii_writebit(sc, 0);
703 ack = dc_mii_readbit(sc);
706 * Now try reading data bits. If the ack failed, we still
707 * need to clock through 16 cycles to keep the PHY(s) in sync.
710 for (i = 0; i < 16; i++)
715 for (i = 0x8000; i; i >>= 1) {
717 if (dc_mii_readbit(sc))
718 frame->mii_data |= i;
724 dc_mii_writebit(sc, 0);
725 dc_mii_writebit(sc, 0);
735 * Write to a PHY register through the MII.
738 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
743 * Set up frame for TX.
746 frame->mii_stdelim = DC_MII_STARTDELIM;
747 frame->mii_opcode = DC_MII_WRITEOP;
748 frame->mii_turnaround = DC_MII_TURNAROUND;
755 dc_mii_send(sc, frame->mii_stdelim, 2);
756 dc_mii_send(sc, frame->mii_opcode, 2);
757 dc_mii_send(sc, frame->mii_phyaddr, 5);
758 dc_mii_send(sc, frame->mii_regaddr, 5);
759 dc_mii_send(sc, frame->mii_turnaround, 2);
760 dc_mii_send(sc, frame->mii_data, 16);
763 dc_mii_writebit(sc, 0);
764 dc_mii_writebit(sc, 0);
772 dc_miibus_readreg(device_t dev, int phy, int reg)
774 struct dc_mii_frame frame;
776 int i, rval, phy_reg = 0;
778 sc = device_get_softc(dev);
779 bzero(&frame, sizeof(frame));
782 * Note: both the AL981 and AN985 have internal PHYs,
783 * however the AL981 provides direct access to the PHY
784 * registers while the AN985 uses a serial MII interface.
785 * The AN985's MII interface is also buggy in that you
786 * can read from any MII address (0 to 31), but only address 1
787 * behaves normally. To deal with both cases, we pretend
788 * that the PHY is at MII address 1.
790 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
794 * Note: the ukphy probes of the RS7112 report a PHY at
795 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
796 * so we only respond to correct one.
798 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
801 if (sc->dc_pmode != DC_PMODE_MII) {
802 if (phy == (MII_NPHY - 1)) {
806 * Fake something to make the probe
807 * code think there's a PHY here.
809 return (BMSR_MEDIAMASK);
813 return (DC_VENDORID_LO);
814 return (DC_VENDORID_DEC);
818 return (DC_DEVICEID_82C168);
819 return (DC_DEVICEID_21143);
829 if (DC_IS_PNIC(sc)) {
830 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
831 (phy << 23) | (reg << 18));
832 for (i = 0; i < DC_TIMEOUT; i++) {
834 rval = CSR_READ_4(sc, DC_PN_MII);
835 if (!(rval & DC_PN_MII_BUSY)) {
837 return (rval == 0xFFFF ? 0 : rval);
843 if (DC_IS_COMET(sc)) {
846 phy_reg = DC_AL_BMCR;
849 phy_reg = DC_AL_BMSR;
852 phy_reg = DC_AL_VENID;
855 phy_reg = DC_AL_DEVID;
858 phy_reg = DC_AL_ANAR;
861 phy_reg = DC_AL_LPAR;
864 phy_reg = DC_AL_ANER;
867 printf("dc%d: phy_read: bad phy register %x\n",
873 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
880 frame.mii_phyaddr = phy;
881 frame.mii_regaddr = reg;
882 if (sc->dc_type == DC_TYPE_98713) {
883 phy_reg = CSR_READ_4(sc, DC_NETCFG);
884 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
886 dc_mii_readreg(sc, &frame);
887 if (sc->dc_type == DC_TYPE_98713)
888 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
890 return (frame.mii_data);
894 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
897 struct dc_mii_frame frame;
900 sc = device_get_softc(dev);
901 bzero(&frame, sizeof(frame));
903 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
906 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
909 if (DC_IS_PNIC(sc)) {
910 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
911 (phy << 23) | (reg << 10) | data);
912 for (i = 0; i < DC_TIMEOUT; i++) {
913 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
919 if (DC_IS_COMET(sc)) {
922 phy_reg = DC_AL_BMCR;
925 phy_reg = DC_AL_BMSR;
928 phy_reg = DC_AL_VENID;
931 phy_reg = DC_AL_DEVID;
934 phy_reg = DC_AL_ANAR;
937 phy_reg = DC_AL_LPAR;
940 phy_reg = DC_AL_ANER;
943 printf("dc%d: phy_write: bad phy register %x\n",
949 CSR_WRITE_4(sc, phy_reg, data);
953 frame.mii_phyaddr = phy;
954 frame.mii_regaddr = reg;
955 frame.mii_data = data;
957 if (sc->dc_type == DC_TYPE_98713) {
958 phy_reg = CSR_READ_4(sc, DC_NETCFG);
959 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
961 dc_mii_writereg(sc, &frame);
962 if (sc->dc_type == DC_TYPE_98713)
963 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
969 dc_miibus_statchg(device_t dev)
972 struct mii_data *mii;
975 sc = device_get_softc(dev);
976 if (DC_IS_ADMTEK(sc))
979 mii = device_get_softc(sc->dc_miibus);
980 ifm = &mii->mii_media;
981 if (DC_IS_DAVICOM(sc) &&
982 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
983 dc_setcfg(sc, ifm->ifm_media);
984 sc->dc_if_media = ifm->ifm_media;
986 dc_setcfg(sc, mii->mii_media_active);
987 sc->dc_if_media = mii->mii_media_active;
992 * Special support for DM9102A cards with HomePNA PHYs. Note:
993 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
994 * to be impossible to talk to the management interface of the DM9801
995 * PHY (its MDIO pin is not connected to anything). Consequently,
996 * the driver has to just 'know' about the additional mode and deal
997 * with it itself. *sigh*
1000 dc_miibus_mediainit(device_t dev)
1002 struct dc_softc *sc;
1003 struct mii_data *mii;
1004 struct ifmedia *ifm;
1007 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1009 sc = device_get_softc(dev);
1010 mii = device_get_softc(sc->dc_miibus);
1011 ifm = &mii->mii_media;
1013 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1014 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1017 #define DC_BITS_512 9
1018 #define DC_BITS_128 7
1019 #define DC_BITS_64 6
1022 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1026 /* Compute CRC for the address value. */
1027 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1030 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1031 * chips is only 128 bits wide.
1033 if (sc->dc_flags & DC_128BIT_HASH)
1034 return (crc & ((1 << DC_BITS_128) - 1));
1036 /* The hash table on the MX98715BEC is only 64 bits wide. */
1037 if (sc->dc_flags & DC_64BIT_HASH)
1038 return (crc & ((1 << DC_BITS_64) - 1));
1040 /* Xircom's hash filtering table is different (read: weird) */
1041 /* Xircom uses the LEAST significant bits */
1042 if (DC_IS_XIRCOM(sc)) {
1043 if ((crc & 0x180) == 0x180)
1044 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1046 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1050 return (crc & ((1 << DC_BITS_512) - 1));
1054 * Calculate CRC of a multicast group address, return the lower 6 bits.
1057 dc_mchash_be(const uint8_t *addr)
1061 /* Compute CRC for the address value. */
1062 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1064 /* Return the filter bit position. */
1065 return ((crc >> 26) & 0x0000003F);
1069 * 21143-style RX filter setup routine. Filter programming is done by
1070 * downloading a special setup frame into the TX engine. 21143, Macronix,
1071 * PNIC, PNIC II and Davicom chips are programmed this way.
1073 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1074 * address (our node address) and a 512-bit hash filter for multicast
1075 * frames. We also sneak the broadcast address into the hash filter since
1079 dc_setfilt_21143(struct dc_softc *sc)
1081 struct dc_desc *sframe;
1083 struct ifmultiaddr *ifma;
1089 i = sc->dc_cdata.dc_tx_prod;
1090 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1091 sc->dc_cdata.dc_tx_cnt++;
1092 sframe = &sc->dc_ldata->dc_tx_list[i];
1093 sp = sc->dc_cdata.dc_sbuf;
1094 bzero(sp, DC_SFRAME_LEN);
1096 sframe->dc_data = htole32(sc->dc_saddr);
1097 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1098 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1100 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1102 /* If we want promiscuous mode, set the allframes bit. */
1103 if (ifp->if_flags & IFF_PROMISC)
1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1108 if (ifp->if_flags & IFF_ALLMULTI)
1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1113 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1114 if (ifma->ifma_addr->sa_family != AF_LINK)
1116 h = dc_mchash_le(sc,
1117 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1118 sp[h >> 4] |= htole32(1 << (h & 0xF));
1121 if (ifp->if_flags & IFF_BROADCAST) {
1122 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1123 sp[h >> 4] |= htole32(1 << (h & 0xF));
1126 /* Set our MAC address */
1127 sp[39] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]);
1128 sp[40] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]);
1129 sp[41] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]);
1131 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1132 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1135 * The PNIC takes an exceedingly long time to process its
1136 * setup frame; wait 10ms after posting the setup frame
1137 * before proceeding, just so it has time to swallow its
1146 dc_setfilt_admtek(struct dc_softc *sc)
1149 struct ifmultiaddr *ifma;
1151 u_int32_t hashes[2] = { 0, 0 };
1155 /* Init our MAC address. */
1156 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0]));
1157 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4]));
1159 /* If we want promiscuous mode, set the allframes bit. */
1160 if (ifp->if_flags & IFF_PROMISC)
1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1165 if (ifp->if_flags & IFF_ALLMULTI)
1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1170 /* First, zot all the existing hash bits. */
1171 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1172 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1175 * If we're already in promisc or allmulti mode, we
1176 * don't have to bother programming the multicast filter.
1178 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1181 /* Now program new ones. */
1182 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1183 if (ifma->ifma_addr->sa_family != AF_LINK)
1185 if (DC_IS_CENTAUR(sc))
1186 h = dc_mchash_le(sc,
1187 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1190 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1192 hashes[0] |= (1 << h);
1194 hashes[1] |= (1 << (h - 32));
1197 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1198 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1202 dc_setfilt_asix(struct dc_softc *sc)
1205 struct ifmultiaddr *ifma;
1207 u_int32_t hashes[2] = { 0, 0 };
1211 /* Init our MAC address */
1212 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1213 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1214 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[0]));
1215 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1216 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1217 *(u_int32_t *)(&IFP2ENADDR(sc->dc_ifp)[4]));
1219 /* If we want promiscuous mode, set the allframes bit. */
1220 if (ifp->if_flags & IFF_PROMISC)
1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1225 if (ifp->if_flags & IFF_ALLMULTI)
1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1228 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1231 * The ASIX chip has a special bit to enable reception
1232 * of broadcast frames.
1234 if (ifp->if_flags & IFF_BROADCAST)
1235 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1237 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1239 /* first, zot all the existing hash bits */
1240 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1241 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1242 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1243 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1246 * If we're already in promisc or allmulti mode, we
1247 * don't have to bother programming the multicast filter.
1249 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1252 /* now program new ones */
1253 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1254 if (ifma->ifma_addr->sa_family != AF_LINK)
1256 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1258 hashes[0] |= (1 << h);
1260 hashes[1] |= (1 << (h - 32));
1263 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1264 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1270 dc_setfilt_xircom(struct dc_softc *sc)
1273 struct ifmultiaddr *ifma;
1274 struct dc_desc *sframe;
1279 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1281 i = sc->dc_cdata.dc_tx_prod;
1282 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1283 sc->dc_cdata.dc_tx_cnt++;
1284 sframe = &sc->dc_ldata->dc_tx_list[i];
1285 sp = sc->dc_cdata.dc_sbuf;
1286 bzero(sp, DC_SFRAME_LEN);
1288 sframe->dc_data = htole32(sc->dc_saddr);
1289 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1290 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1292 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1294 /* If we want promiscuous mode, set the allframes bit. */
1295 if (ifp->if_flags & IFF_PROMISC)
1296 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1298 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1300 if (ifp->if_flags & IFF_ALLMULTI)
1301 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1303 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1305 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1306 if (ifma->ifma_addr->sa_family != AF_LINK)
1308 h = dc_mchash_le(sc,
1309 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1310 sp[h >> 4] |= htole32(1 << (h & 0xF));
1313 if (ifp->if_flags & IFF_BROADCAST) {
1314 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1315 sp[h >> 4] |= htole32(1 << (h & 0xF));
1318 /* Set our MAC address */
1319 sp[0] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[0]);
1320 sp[1] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[1]);
1321 sp[2] = DC_SP_MAC(((u_int16_t *)IFP2ENADDR(sc->dc_ifp))[2]);
1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1325 ifp->if_flags |= IFF_RUNNING;
1326 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1327 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1338 dc_setfilt(struct dc_softc *sc)
1341 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1342 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1343 dc_setfilt_21143(sc);
1346 dc_setfilt_asix(sc);
1348 if (DC_IS_ADMTEK(sc))
1349 dc_setfilt_admtek(sc);
1351 if (DC_IS_XIRCOM(sc))
1352 dc_setfilt_xircom(sc);
1356 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1357 * the netconfig register, we first have to put the transmit and/or
1358 * receive logic in the idle state.
1361 dc_setcfg(struct dc_softc *sc, int media)
1363 int i, restart = 0, watchdogreg;
1366 if (IFM_SUBTYPE(media) == IFM_NONE)
1369 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1371 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1373 for (i = 0; i < DC_TIMEOUT; i++) {
1374 isr = CSR_READ_4(sc, DC_ISR);
1375 if (isr & DC_ISR_TX_IDLE &&
1376 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1377 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1382 if (i == DC_TIMEOUT)
1383 printf("dc%d: failed to force tx and "
1384 "rx to idle state\n", sc->dc_unit);
1387 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1388 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1389 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1390 if (sc->dc_pmode == DC_PMODE_MII) {
1391 if (DC_IS_INTEL(sc)) {
1392 /* There's a write enable bit here that reads as 1. */
1393 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1394 watchdogreg &= ~DC_WDOG_CTLWREN;
1395 watchdogreg |= DC_WDOG_JABBERDIS;
1396 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1398 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1400 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1401 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1402 if (sc->dc_type == DC_TYPE_98713)
1403 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1404 DC_NETCFG_SCRAMBLER));
1405 if (!DC_IS_DAVICOM(sc))
1406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1407 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1408 if (DC_IS_INTEL(sc))
1409 dc_apply_fixup(sc, IFM_AUTO);
1411 if (DC_IS_PNIC(sc)) {
1412 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1413 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1414 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1419 if (DC_IS_INTEL(sc))
1421 (media & IFM_GMASK) == IFM_FDX ?
1422 IFM_100_TX | IFM_FDX : IFM_100_TX);
1426 if (IFM_SUBTYPE(media) == IFM_10_T) {
1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1428 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1429 if (sc->dc_pmode == DC_PMODE_MII) {
1430 /* There's a write enable bit here that reads as 1. */
1431 if (DC_IS_INTEL(sc)) {
1432 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1433 watchdogreg &= ~DC_WDOG_CTLWREN;
1434 watchdogreg |= DC_WDOG_JABBERDIS;
1435 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1437 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1439 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1440 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1441 if (sc->dc_type == DC_TYPE_98713)
1442 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1443 if (!DC_IS_DAVICOM(sc))
1444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1445 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1446 if (DC_IS_INTEL(sc))
1447 dc_apply_fixup(sc, IFM_AUTO);
1449 if (DC_IS_PNIC(sc)) {
1450 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1451 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1452 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1455 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1456 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1457 if (DC_IS_INTEL(sc)) {
1458 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1459 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1460 if ((media & IFM_GMASK) == IFM_FDX)
1461 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1463 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1464 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1465 DC_CLRBIT(sc, DC_10BTCTRL,
1466 DC_TCTL_AUTONEGENBL);
1468 (media & IFM_GMASK) == IFM_FDX ?
1469 IFM_10_T | IFM_FDX : IFM_10_T);
1476 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1477 * PHY and we want HomePNA mode, set the portsel bit to turn
1478 * on the external MII port.
1480 if (DC_IS_DAVICOM(sc)) {
1481 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1485 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1489 if ((media & IFM_GMASK) == IFM_FDX) {
1490 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1491 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1492 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1495 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1496 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1500 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1504 dc_reset(struct dc_softc *sc)
1508 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1510 for (i = 0; i < DC_TIMEOUT; i++) {
1512 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1516 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1517 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
1519 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1523 if (i == DC_TIMEOUT)
1524 printf("dc%d: reset never completed!\n", sc->dc_unit);
1526 /* Wait a little while for the chip to get its brains in order. */
1529 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1530 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1531 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1534 * Bring the SIA out of reset. In some cases, it looks
1535 * like failing to unreset the SIA soon enough gets it
1536 * into a state where it will never come out of reset
1537 * until we reset the whole chip again.
1539 if (DC_IS_INTEL(sc)) {
1540 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1541 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1542 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1546 static struct dc_type *
1547 dc_devtype(device_t dev)
1554 while (t->dc_name != NULL) {
1555 if ((pci_get_vendor(dev) == t->dc_vid) &&
1556 (pci_get_device(dev) == t->dc_did)) {
1557 /* Check the PCI revision */
1558 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1559 if (t->dc_did == DC_DEVICEID_98713 &&
1560 rev >= DC_REVISION_98713A)
1562 if (t->dc_did == DC_DEVICEID_98713_CP &&
1563 rev >= DC_REVISION_98713A)
1565 if (t->dc_did == DC_DEVICEID_987x5 &&
1566 rev >= DC_REVISION_98715AEC_C)
1568 if (t->dc_did == DC_DEVICEID_987x5 &&
1569 rev >= DC_REVISION_98725)
1571 if (t->dc_did == DC_DEVICEID_AX88140A &&
1572 rev >= DC_REVISION_88141)
1574 if (t->dc_did == DC_DEVICEID_82C168 &&
1575 rev >= DC_REVISION_82C169)
1577 if (t->dc_did == DC_DEVICEID_DM9102 &&
1578 rev >= DC_REVISION_DM9102A)
1581 * The Microsoft MN-130 has a device ID of 0x0002,
1582 * which happens to be the same as the PNIC 82c168.
1583 * To keep dc_attach() from getting confused, we
1584 * pretend its ID is something different.
1585 * XXX: ideally, dc_attach() should be checking
1586 * vendorid+deviceid together to avoid such
1589 if (t->dc_vid == DC_VENDORID_MICROSOFT &&
1590 t->dc_did == DC_DEVICEID_MSMN130)
1601 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1602 * IDs against our list and return a device name if we find a match.
1603 * We do a little bit of extra work to identify the exact type of
1604 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1605 * but different revision IDs. The same is true for 98715/98715A
1606 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1607 * cases, the exact chip revision affects driver behavior.
1610 dc_probe(device_t dev)
1614 t = dc_devtype(dev);
1617 device_set_desc(dev, t->dc_name);
1618 return (BUS_PROBE_DEFAULT);
1625 dc_apply_fixup(struct dc_softc *sc, int media)
1627 struct dc_mediainfo *m;
1635 if (m->dc_media == media)
1643 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1644 reg = (p[0] | (p[1] << 8)) << 16;
1645 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1648 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1649 reg = (p[0] | (p[1] << 8)) << 16;
1650 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1655 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1657 struct dc_mediainfo *m;
1659 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1660 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1661 case DC_SIA_CODE_10BT:
1662 m->dc_media = IFM_10_T;
1664 case DC_SIA_CODE_10BT_FDX:
1665 m->dc_media = IFM_10_T | IFM_FDX;
1667 case DC_SIA_CODE_10B2:
1668 m->dc_media = IFM_10_2;
1670 case DC_SIA_CODE_10B5:
1671 m->dc_media = IFM_10_5;
1678 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1679 * Things apparently already work for cards that do
1680 * supply Media Specific Data.
1682 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1685 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1689 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1692 m->dc_next = sc->dc_mi;
1695 sc->dc_pmode = DC_PMODE_SIA;
1699 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1701 struct dc_mediainfo *m;
1703 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1704 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1705 m->dc_media = IFM_100_TX;
1707 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1708 m->dc_media = IFM_100_TX | IFM_FDX;
1711 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1713 m->dc_next = sc->dc_mi;
1716 sc->dc_pmode = DC_PMODE_SYM;
1720 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1722 struct dc_mediainfo *m;
1725 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1726 /* We abuse IFM_AUTO to represent MII. */
1727 m->dc_media = IFM_AUTO;
1728 m->dc_gp_len = l->dc_gpr_len;
1731 p += sizeof(struct dc_eblock_mii);
1733 p += 2 * l->dc_gpr_len;
1734 m->dc_reset_len = *p;
1736 m->dc_reset_ptr = p;
1738 m->dc_next = sc->dc_mi;
1743 dc_read_srom(struct dc_softc *sc, int bits)
1748 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1749 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1753 dc_parse_21143_srom(struct dc_softc *sc)
1755 struct dc_leaf_hdr *lhdr;
1756 struct dc_eblock_hdr *hdr;
1757 int have_mii, i, loff;
1761 loff = sc->dc_srom[27];
1762 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1765 ptr += sizeof(struct dc_leaf_hdr) - 1;
1767 * Look if we got a MII media block.
1769 for (i = 0; i < lhdr->dc_mcnt; i++) {
1770 hdr = (struct dc_eblock_hdr *)ptr;
1771 if (hdr->dc_type == DC_EBLOCK_MII)
1774 ptr += (hdr->dc_len & 0x7F);
1779 * Do the same thing again. Only use SIA and SYM media
1780 * blocks if no MII media block is available.
1783 ptr += sizeof(struct dc_leaf_hdr) - 1;
1784 for (i = 0; i < lhdr->dc_mcnt; i++) {
1785 hdr = (struct dc_eblock_hdr *)ptr;
1786 switch (hdr->dc_type) {
1788 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1792 dc_decode_leaf_sia(sc,
1793 (struct dc_eblock_sia *)hdr);
1797 dc_decode_leaf_sym(sc,
1798 (struct dc_eblock_sym *)hdr);
1801 /* Don't care. Yet. */
1804 ptr += (hdr->dc_len & 0x7F);
1810 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1814 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1816 *paddr = segs->ds_addr;
1820 * Attach the interface. Allocate softc structures, do ifmedia
1821 * setup and ethernet/BPF attach.
1824 dc_attach(device_t dev)
1827 u_char eaddr[ETHER_ADDR_LEN];
1829 struct dc_softc *sc;
1832 int unit, error = 0, rid, mac_offset;
1836 sc = device_get_softc(dev);
1837 unit = device_get_unit(dev);
1839 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1840 MTX_DEF | MTX_RECURSE);
1843 * Map control/status registers.
1845 pci_enable_busmaster(dev);
1848 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1850 if (sc->dc_res == NULL) {
1851 printf("dc%d: couldn't map ports/memory\n", unit);
1856 sc->dc_btag = rman_get_bustag(sc->dc_res);
1857 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1859 /* Allocate interrupt. */
1861 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1862 RF_SHAREABLE | RF_ACTIVE);
1864 if (sc->dc_irq == NULL) {
1865 printf("dc%d: couldn't map interrupt\n", unit);
1870 /* Need this info to decide on a chip type. */
1871 sc->dc_info = dc_devtype(dev);
1872 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF;
1874 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1875 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1876 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1877 dc_eeprom_width(sc);
1879 switch (sc->dc_info->dc_did) {
1880 case DC_DEVICEID_21143:
1881 sc->dc_type = DC_TYPE_21143;
1882 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1883 sc->dc_flags |= DC_REDUCED_MII_POLL;
1884 /* Save EEPROM contents so we can parse them later. */
1885 dc_read_srom(sc, sc->dc_romwidth);
1887 case DC_DEVICEID_DM9009:
1888 case DC_DEVICEID_DM9100:
1889 case DC_DEVICEID_DM9102:
1890 sc->dc_type = DC_TYPE_DM9102;
1891 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
1892 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
1893 sc->dc_flags |= DC_TX_ALIGN;
1894 sc->dc_pmode = DC_PMODE_MII;
1895 /* Increase the latency timer value. */
1896 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1897 command &= 0xFFFF00FF;
1898 command |= 0x00008000;
1899 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1901 case DC_DEVICEID_AL981:
1902 sc->dc_type = DC_TYPE_AL981;
1903 sc->dc_flags |= DC_TX_USE_TX_INTR;
1904 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1905 sc->dc_pmode = DC_PMODE_MII;
1906 dc_read_srom(sc, sc->dc_romwidth);
1908 case DC_DEVICEID_AN985:
1909 case DC_DEVICEID_ADM9511:
1910 case DC_DEVICEID_ADM9513:
1911 case DC_DEVICEID_FA511:
1912 case DC_DEVICEID_FE2500:
1913 case DC_DEVICEID_EN2242:
1914 case DC_DEVICEID_HAWKING_PN672TX:
1915 case DC_DEVICEID_3CSOHOB:
1916 case DC_DEVICEID_MSMN120:
1917 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/
1918 sc->dc_type = DC_TYPE_AN985;
1919 sc->dc_flags |= DC_64BIT_HASH;
1920 sc->dc_flags |= DC_TX_USE_TX_INTR;
1921 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1922 sc->dc_pmode = DC_PMODE_MII;
1923 /* Don't read SROM for - auto-loaded on reset */
1925 case DC_DEVICEID_98713:
1926 case DC_DEVICEID_98713_CP:
1927 if (revision < DC_REVISION_98713A) {
1928 sc->dc_type = DC_TYPE_98713;
1930 if (revision >= DC_REVISION_98713A) {
1931 sc->dc_type = DC_TYPE_98713A;
1932 sc->dc_flags |= DC_21143_NWAY;
1934 sc->dc_flags |= DC_REDUCED_MII_POLL;
1935 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1937 case DC_DEVICEID_987x5:
1938 case DC_DEVICEID_EN1217:
1940 * Macronix MX98715AEC-C/D/E parts have only a
1941 * 128-bit hash table. We need to deal with these
1942 * in the same manner as the PNIC II so that we
1943 * get the right number of bits out of the
1946 if (revision >= DC_REVISION_98715AEC_C &&
1947 revision < DC_REVISION_98725)
1948 sc->dc_flags |= DC_128BIT_HASH;
1949 sc->dc_type = DC_TYPE_987x5;
1950 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1951 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1953 case DC_DEVICEID_98727:
1954 sc->dc_type = DC_TYPE_987x5;
1955 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
1956 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1958 case DC_DEVICEID_82C115:
1959 sc->dc_type = DC_TYPE_PNICII;
1960 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
1961 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
1963 case DC_DEVICEID_82C168:
1964 sc->dc_type = DC_TYPE_PNIC;
1965 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
1966 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1967 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
1968 if (revision < DC_REVISION_82C169)
1969 sc->dc_pmode = DC_PMODE_SYM;
1971 case DC_DEVICEID_AX88140A:
1972 sc->dc_type = DC_TYPE_ASIX;
1973 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
1974 sc->dc_flags |= DC_REDUCED_MII_POLL;
1975 sc->dc_pmode = DC_PMODE_MII;
1977 case DC_DEVICEID_X3201:
1978 sc->dc_type = DC_TYPE_XIRCOM;
1979 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1982 * We don't actually need to coalesce, but we're doing
1983 * it to obtain a double word aligned buffer.
1984 * The DC_TX_COALESCE flag is required.
1986 sc->dc_pmode = DC_PMODE_MII;
1988 case DC_DEVICEID_RS7112:
1989 sc->dc_type = DC_TYPE_CONEXANT;
1990 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1991 sc->dc_flags |= DC_REDUCED_MII_POLL;
1992 sc->dc_pmode = DC_PMODE_MII;
1993 dc_read_srom(sc, sc->dc_romwidth);
1996 printf("dc%d: unknown device: %x\n", sc->dc_unit,
1997 sc->dc_info->dc_did);
2001 /* Save the cache line size. */
2002 if (DC_IS_DAVICOM(sc))
2003 sc->dc_cachesize = 0;
2005 sc->dc_cachesize = pci_read_config(dev,
2006 DC_PCI_CFLT, 4) & 0xFF;
2008 /* Reset the adapter. */
2011 /* Take 21143 out of snooze mode */
2012 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2013 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2014 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2015 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2019 * Try to learn something about the supported media.
2020 * We know that ASIX and ADMtek and Davicom devices
2021 * will *always* be using MII media, so that's a no-brainer.
2022 * The tricky ones are the Macronix/PNIC II and the
2025 if (DC_IS_INTEL(sc))
2026 dc_parse_21143_srom(sc);
2027 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2028 if (sc->dc_type == DC_TYPE_98713)
2029 sc->dc_pmode = DC_PMODE_MII;
2031 sc->dc_pmode = DC_PMODE_SYM;
2032 } else if (!sc->dc_pmode)
2033 sc->dc_pmode = DC_PMODE_MII;
2036 * Get station address from the EEPROM.
2038 switch(sc->dc_type) {
2040 case DC_TYPE_98713A:
2042 case DC_TYPE_PNICII:
2043 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2044 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2045 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2048 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2050 case DC_TYPE_DM9102:
2051 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2054 * If this is an onboard dc(4) the station address read from
2055 * the EEPROM is all zero and we have to get it from the fcode.
2057 for (i = 0; i < ETHER_ADDR_LEN; i++)
2058 if (eaddr[i] != 0x00)
2060 if (i >= ETHER_ADDR_LEN)
2061 OF_getetheraddr(dev, eaddr);
2066 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2070 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0);
2071 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1);
2073 case DC_TYPE_CONEXANT:
2074 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2077 case DC_TYPE_XIRCOM:
2078 /* The MAC comes from the CIS. */
2079 mac = pci_get_ether(dev);
2081 device_printf(dev, "No station address in CIS!\n");
2085 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2088 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2094 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
2095 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2096 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1,
2097 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag);
2099 printf("dc%d: failed to allocate busdma tag\n", unit);
2103 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
2104 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
2106 printf("dc%d: failed to allocate DMA safe memory\n", unit);
2110 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
2111 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
2114 printf("dc%d: cannot get address of the descriptors\n", unit);
2120 * Allocate a busdma tag and DMA safe memory for the multicast
2123 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
2124 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1,
2125 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag);
2127 printf("dc%d: failed to allocate busdma tag\n", unit);
2131 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2132 BUS_DMA_NOWAIT, &sc->dc_smap);
2134 printf("dc%d: failed to allocate DMA safe memory\n", unit);
2138 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2139 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2141 printf("dc%d: cannot get address of the descriptors\n", unit);
2146 /* Allocate a busdma tag for mbufs. */
2147 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
2148 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, DC_TX_LIST_CNT, MCLBYTES,
2149 0, NULL, NULL, &sc->dc_mtag);
2151 printf("dc%d: failed to allocate busdma tag\n", unit);
2156 /* Create the TX/RX busdma maps. */
2157 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2158 error = bus_dmamap_create(sc->dc_mtag, 0,
2159 &sc->dc_cdata.dc_tx_map[i]);
2161 printf("dc%d: failed to init TX ring\n", unit);
2166 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2167 error = bus_dmamap_create(sc->dc_mtag, 0,
2168 &sc->dc_cdata.dc_rx_map[i]);
2170 printf("dc%d: failed to init RX ring\n", unit);
2175 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
2177 printf("dc%d: failed to init RX ring\n", unit);
2182 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2184 printf("dc%d: can not if_alloc()\n", unit);
2189 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2190 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */
2191 ifp->if_mtu = ETHERMTU;
2192 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2194 ifp->if_flags |= IFF_NEEDSGIANT;
2195 ifp->if_ioctl = dc_ioctl;
2196 ifp->if_start = dc_start;
2197 ifp->if_watchdog = dc_watchdog;
2198 ifp->if_init = dc_init;
2199 ifp->if_baudrate = 10000000;
2200 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2201 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2202 IFQ_SET_READY(&ifp->if_snd);
2205 * Do MII setup. If this is a 21143, check for a PHY on the
2206 * MII bus after applying any necessary fixups to twiddle the
2207 * GPIO bits. If we don't end up finding a PHY, restore the
2208 * old selection (SIA only or SIA/SYM) and attach the dcphy
2211 if (DC_IS_INTEL(sc)) {
2212 dc_apply_fixup(sc, IFM_AUTO);
2214 sc->dc_pmode = DC_PMODE_MII;
2218 * Setup General Purpose port mode and data so the tulip can talk
2219 * to the MII. This needs to be done before mii_phy_probe so that
2220 * we can actually see them.
2222 if (DC_IS_XIRCOM(sc)) {
2223 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2224 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2226 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2227 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2231 error = mii_phy_probe(dev, &sc->dc_miibus,
2232 dc_ifmedia_upd, dc_ifmedia_sts);
2234 if (error && DC_IS_INTEL(sc)) {
2236 if (sc->dc_pmode != DC_PMODE_SIA)
2237 sc->dc_pmode = DC_PMODE_SYM;
2238 sc->dc_flags |= DC_21143_NWAY;
2239 mii_phy_probe(dev, &sc->dc_miibus,
2240 dc_ifmedia_upd, dc_ifmedia_sts);
2242 * For non-MII cards, we need to have the 21143
2243 * drive the LEDs. Except there are some systems
2244 * like the NEC VersaPro NoteBook PC which have no
2245 * LEDs, and twiddling these bits has adverse effects
2246 * on them. (I.e. you suddenly can't get a link.)
2248 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2249 sc->dc_flags |= DC_TULIP_LEDS;
2254 printf("dc%d: MII without any PHY!\n", sc->dc_unit);
2258 if (DC_IS_ADMTEK(sc)) {
2260 * Set automatic TX underrun recovery for the ADMtek chips
2262 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2266 * Tell the upper layer(s) we support long frames.
2268 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2269 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2270 #ifdef DEVICE_POLLING
2271 ifp->if_capabilities |= IFCAP_POLLING;
2273 ifp->if_capenable = ifp->if_capabilities;
2275 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0);
2278 sc->dc_srm_media = 0;
2280 /* Remember the SRM console media setting */
2281 if (DC_IS_INTEL(sc)) {
2282 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2283 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2284 switch ((command >> 8) & 0xff) {
2286 sc->dc_srm_media = IFM_10_T;
2289 sc->dc_srm_media = IFM_10_T | IFM_FDX;
2292 sc->dc_srm_media = IFM_100_TX;
2295 sc->dc_srm_media = IFM_100_TX | IFM_FDX;
2298 if (sc->dc_srm_media)
2299 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER;
2304 * Call MI attach routine.
2306 ether_ifattach(ifp, eaddr);
2308 /* Hook interrupt last to avoid having to lock softc */
2309 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET |
2310 (IS_MPSAFE ? INTR_MPSAFE : 0),
2311 dc_intr, sc, &sc->dc_intrhand);
2314 printf("dc%d: couldn't set up irq\n", unit);
2315 ether_ifdetach(ifp);
2327 * Shutdown hardware and free up resources. This can be called any
2328 * time after the mutex has been initialized. It is called in both
2329 * the error case in attach and the normal detach case so it needs
2330 * to be careful about only freeing resources that have actually been
2334 dc_detach(device_t dev)
2336 struct dc_softc *sc;
2338 struct dc_mediainfo *m;
2341 sc = device_get_softc(dev);
2342 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2347 /* These should only be active if attach succeeded */
2348 if (device_is_attached(dev)) {
2350 ether_ifdetach(ifp);
2354 device_delete_child(dev, sc->dc_miibus);
2355 bus_generic_detach(dev);
2357 if (sc->dc_intrhand)
2358 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2360 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2362 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2364 if (sc->dc_cdata.dc_sbuf != NULL)
2365 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
2366 if (sc->dc_ldata != NULL)
2367 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
2368 for (i = 0; i < DC_TX_LIST_CNT; i++)
2369 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]);
2370 for (i = 0; i < DC_RX_LIST_CNT; i++)
2371 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2372 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
2374 bus_dma_tag_destroy(sc->dc_stag);
2376 bus_dma_tag_destroy(sc->dc_mtag);
2378 bus_dma_tag_destroy(sc->dc_ltag);
2380 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2382 while (sc->dc_mi != NULL) {
2383 m = sc->dc_mi->dc_next;
2384 free(sc->dc_mi, M_DEVBUF);
2387 free(sc->dc_srom, M_DEVBUF);
2390 mtx_destroy(&sc->dc_mtx);
2396 * Initialize the transmit descriptors.
2399 dc_list_tx_init(struct dc_softc *sc)
2401 struct dc_chain_data *cd;
2402 struct dc_list_data *ld;
2407 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2408 if (i == DC_TX_LIST_CNT - 1)
2412 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2413 cd->dc_tx_chain[i] = NULL;
2414 ld->dc_tx_list[i].dc_data = 0;
2415 ld->dc_tx_list[i].dc_ctl = 0;
2418 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2419 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2420 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2426 * Initialize the RX descriptors and allocate mbufs for them. Note that
2427 * we arrange the descriptors in a closed ring, so that the last descriptor
2428 * points back to the first.
2431 dc_list_rx_init(struct dc_softc *sc)
2433 struct dc_chain_data *cd;
2434 struct dc_list_data *ld;
2440 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2441 if (dc_newbuf(sc, i, 1) != 0)
2443 if (i == DC_RX_LIST_CNT - 1)
2447 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2451 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2457 dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
2459 bus_dma_segment_t *segs;
2464 struct dc_softc *sc;
2468 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur];
2470 sc->dc_cdata.dc_rx_err = error;
2474 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
2475 sc->dc_cdata.dc_rx_err = 0;
2476 c->dc_data = htole32(segs->ds_addr);
2480 * Initialize an RX descriptor and attach an MBUF cluster.
2483 dc_newbuf(struct dc_softc *sc, int i, int alloc)
2490 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2494 m_new = sc->dc_cdata.dc_rx_chain[i];
2495 m_new->m_data = m_new->m_ext.ext_buf;
2497 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2498 m_adj(m_new, sizeof(u_int64_t));
2501 * If this is a PNIC chip, zero the buffer. This is part
2502 * of the workaround for the receive bug in the 82c168 and
2505 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2506 bzero(mtod(m_new, char *), m_new->m_len);
2508 /* No need to remap the mbuf if we're reusing it. */
2510 sc->dc_cdata.dc_rx_cur = i;
2511 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap,
2512 m_new, dc_dma_map_rxbuf, sc, 0);
2517 if (sc->dc_cdata.dc_rx_err != 0) {
2519 return (sc->dc_cdata.dc_rx_err);
2521 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
2522 tmp = sc->dc_cdata.dc_rx_map[i];
2523 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2524 sc->dc_sparemap = tmp;
2525 sc->dc_cdata.dc_rx_chain[i] = m_new;
2528 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2529 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2530 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2531 BUS_DMASYNC_PREREAD);
2532 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
2533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2539 * The PNIC chip has a terrible bug in it that manifests itself during
2540 * periods of heavy activity. The exact mode of failure if difficult to
2541 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2542 * will happen on slow machines. The bug is that sometimes instead of
2543 * uploading one complete frame during reception, it uploads what looks
2544 * like the entire contents of its FIFO memory. The frame we want is at
2545 * the end of the whole mess, but we never know exactly how much data has
2546 * been uploaded, so salvaging the frame is hard.
2548 * There is only one way to do it reliably, and it's disgusting.
2549 * Here's what we know:
2551 * - We know there will always be somewhere between one and three extra
2552 * descriptors uploaded.
2554 * - We know the desired received frame will always be at the end of the
2555 * total data upload.
2557 * - We know the size of the desired received frame because it will be
2558 * provided in the length field of the status word in the last descriptor.
2560 * Here's what we do:
2562 * - When we allocate buffers for the receive ring, we bzero() them.
2563 * This means that we know that the buffer contents should be all
2564 * zeros, except for data uploaded by the chip.
2566 * - We also force the PNIC chip to upload frames that include the
2567 * ethernet CRC at the end.
2569 * - We gather all of the bogus frame data into a single buffer.
2571 * - We then position a pointer at the end of this buffer and scan
2572 * backwards until we encounter the first non-zero byte of data.
2573 * This is the end of the received frame. We know we will encounter
2574 * some data at the end of the frame because the CRC will always be
2575 * there, so even if the sender transmits a packet of all zeros,
2576 * we won't be fooled.
2578 * - We know the size of the actual received frame, so we subtract
2579 * that value from the current pointer location. This brings us
2580 * to the start of the actual received packet.
2582 * - We copy this into an mbuf and pass it on, along with the actual
2585 * The performance hit is tremendous, but it beats dropping frames all
2589 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2591 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2593 struct dc_desc *cur_rx;
2594 struct dc_desc *c = NULL;
2595 struct mbuf *m = NULL;
2598 u_int32_t rxstat = 0;
2600 i = sc->dc_pnic_rx_bug_save;
2601 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2602 ptr = sc->dc_pnic_rx_buf;
2603 bzero(ptr, DC_RXLEN * 5);
2605 /* Copy all the bytes from the bogus buffers. */
2607 c = &sc->dc_ldata->dc_rx_list[i];
2608 rxstat = le32toh(c->dc_status);
2609 m = sc->dc_cdata.dc_rx_chain[i];
2610 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2612 /* If this is the last buffer, break out. */
2613 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2615 dc_newbuf(sc, i, 0);
2616 DC_INC(i, DC_RX_LIST_CNT);
2619 /* Find the length of the actual receive frame. */
2620 total_len = DC_RXBYTES(rxstat);
2622 /* Scan backwards until we hit a non-zero byte. */
2623 while (*ptr == 0x00)
2627 if ((uintptr_t)(ptr) & 0x3)
2630 /* Now find the start of the frame. */
2632 if (ptr < sc->dc_pnic_rx_buf)
2633 ptr = sc->dc_pnic_rx_buf;
2636 * Now copy the salvaged frame to the last mbuf and fake up
2637 * the status word to make it look like a successful
2640 dc_newbuf(sc, i, 0);
2641 bcopy(ptr, mtod(m, char *), total_len);
2642 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2646 * This routine searches the RX ring for dirty descriptors in the
2647 * event that the rxeof routine falls out of sync with the chip's
2648 * current descriptor pointer. This may happen sometimes as a result
2649 * of a "no RX buffer available" condition that happens when the chip
2650 * consumes all of the RX buffers before the driver has a chance to
2651 * process the RX ring. This routine may need to be called more than
2652 * once to bring the driver back in sync with the chip, however we
2653 * should still be getting RX DONE interrupts to drive the search
2654 * for new packets in the RX ring, so we should catch up eventually.
2657 dc_rx_resync(struct dc_softc *sc)
2659 struct dc_desc *cur_rx;
2662 pos = sc->dc_cdata.dc_rx_prod;
2664 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2665 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2666 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2668 DC_INC(pos, DC_RX_LIST_CNT);
2671 /* If the ring really is empty, then just return. */
2672 if (i == DC_RX_LIST_CNT)
2675 /* We've fallen behing the chip: catch it. */
2676 sc->dc_cdata.dc_rx_prod = pos;
2682 * A frame has been uploaded: pass the resulting mbuf chain up to
2683 * the higher level protocols.
2686 dc_rxeof(struct dc_softc *sc)
2690 struct dc_desc *cur_rx;
2691 int i, total_len = 0;
2697 i = sc->dc_cdata.dc_rx_prod;
2699 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2700 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
2702 #ifdef DEVICE_POLLING
2703 if (ifp->if_flags & IFF_POLLING) {
2704 if (sc->rxcycles <= 0)
2709 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2710 rxstat = le32toh(cur_rx->dc_status);
2711 m = sc->dc_cdata.dc_rx_chain[i];
2712 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
2713 BUS_DMASYNC_POSTREAD);
2714 total_len = DC_RXBYTES(rxstat);
2716 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2717 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2718 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2719 sc->dc_pnic_rx_bug_save = i;
2720 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2721 DC_INC(i, DC_RX_LIST_CNT);
2724 dc_pnic_rx_bug_war(sc, i);
2725 rxstat = le32toh(cur_rx->dc_status);
2726 total_len = DC_RXBYTES(rxstat);
2731 * If an error occurs, update stats, clear the
2732 * status word and leave the mbuf cluster in place:
2733 * it should simply get re-used next time this descriptor
2734 * comes up in the ring. However, don't report long
2735 * frames as errors since they could be vlans.
2737 if ((rxstat & DC_RXSTAT_RXERR)) {
2738 if (!(rxstat & DC_RXSTAT_GIANT) ||
2739 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2740 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2741 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2743 if (rxstat & DC_RXSTAT_COLLSEEN)
2744 ifp->if_collisions++;
2745 dc_newbuf(sc, i, 0);
2746 if (rxstat & DC_RXSTAT_CRCERR) {
2747 DC_INC(i, DC_RX_LIST_CNT);
2756 /* No errors; receive the packet. */
2757 total_len -= ETHER_CRC_LEN;
2760 * On the x86 we do not have alignment problems, so try to
2761 * allocate a new buffer for the receive ring, and pass up
2762 * the one where the packet is already, saving the expensive
2763 * copy done in m_devget().
2764 * If we are on an architecture with alignment problems, or
2765 * if the allocation fails, then use m_devget and leave the
2766 * existing buffer in the receive ring.
2768 if (dc_quick && dc_newbuf(sc, i, 1) == 0) {
2769 m->m_pkthdr.rcvif = ifp;
2770 m->m_pkthdr.len = m->m_len = total_len;
2771 DC_INC(i, DC_RX_LIST_CNT);
2777 m0 = m_devget(mtod(m, char *), total_len,
2778 ETHER_ALIGN, ifp, NULL);
2779 dc_newbuf(sc, i, 0);
2780 DC_INC(i, DC_RX_LIST_CNT);
2790 (*ifp->if_input)(ifp, m);
2794 sc->dc_cdata.dc_rx_prod = i;
2798 * A frame was downloaded to the chip. It's safe for us to clean up
2803 dc_txeof(struct dc_softc *sc)
2805 struct dc_desc *cur_tx = NULL;
2808 u_int32_t ctl, txstat;
2813 * Go through our tx list and free mbufs for those
2814 * frames that have been transmitted.
2816 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
2817 idx = sc->dc_cdata.dc_tx_cons;
2818 while (idx != sc->dc_cdata.dc_tx_prod) {
2820 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2821 txstat = le32toh(cur_tx->dc_status);
2822 ctl = le32toh(cur_tx->dc_ctl);
2824 if (txstat & DC_TXSTAT_OWN)
2827 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
2828 if (ctl & DC_TXCTL_SETUP) {
2830 * Yes, the PNIC is so brain damaged
2831 * that it will sometimes generate a TX
2832 * underrun error while DMAing the RX
2833 * filter setup frame. If we detect this,
2834 * we have to send the setup frame again,
2835 * or else the filter won't be programmed
2838 if (DC_IS_PNIC(sc)) {
2839 if (txstat & DC_TXSTAT_ERRSUM)
2842 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2844 sc->dc_cdata.dc_tx_cnt--;
2845 DC_INC(idx, DC_TX_LIST_CNT);
2849 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2851 * XXX: Why does my Xircom taunt me so?
2852 * For some reason it likes setting the CARRLOST flag
2853 * even when the carrier is there. wtf?!?
2854 * Who knows, but Conexant chips have the
2855 * same problem. Maybe they took lessons
2858 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2859 sc->dc_pmode == DC_PMODE_MII &&
2860 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2861 DC_TXSTAT_NOCARRIER)))
2862 txstat &= ~DC_TXSTAT_ERRSUM;
2864 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2865 sc->dc_pmode == DC_PMODE_MII &&
2866 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
2867 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
2868 txstat &= ~DC_TXSTAT_ERRSUM;
2871 if (txstat & DC_TXSTAT_ERRSUM) {
2873 if (txstat & DC_TXSTAT_EXCESSCOLL)
2874 ifp->if_collisions++;
2875 if (txstat & DC_TXSTAT_LATECOLL)
2876 ifp->if_collisions++;
2877 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2883 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2886 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2887 bus_dmamap_sync(sc->dc_mtag,
2888 sc->dc_cdata.dc_tx_map[idx],
2889 BUS_DMASYNC_POSTWRITE);
2890 bus_dmamap_unload(sc->dc_mtag,
2891 sc->dc_cdata.dc_tx_map[idx]);
2892 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2893 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2896 sc->dc_cdata.dc_tx_cnt--;
2897 DC_INC(idx, DC_TX_LIST_CNT);
2900 if (idx != sc->dc_cdata.dc_tx_cons) {
2901 /* Some buffers have been freed. */
2902 sc->dc_cdata.dc_tx_cons = idx;
2903 ifp->if_flags &= ~IFF_OACTIVE;
2905 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2911 struct dc_softc *sc;
2912 struct mii_data *mii;
2919 mii = device_get_softc(sc->dc_miibus);
2921 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2922 if (sc->dc_flags & DC_21143_NWAY) {
2923 r = CSR_READ_4(sc, DC_10BTSTAT);
2924 if (IFM_SUBTYPE(mii->mii_media_active) ==
2925 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2929 if (IFM_SUBTYPE(mii->mii_media_active) ==
2930 IFM_10_T && (r & DC_TSTAT_LS10)) {
2934 if (sc->dc_link == 0)
2937 r = CSR_READ_4(sc, DC_ISR);
2938 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2939 sc->dc_cdata.dc_tx_cnt == 0) {
2941 if (!(mii->mii_media_status & IFM_ACTIVE))
2949 * When the init routine completes, we expect to be able to send
2950 * packets right away, and in fact the network code will send a
2951 * gratuitous ARP the moment the init routine marks the interface
2952 * as running. However, even though the MAC may have been initialized,
2953 * there may be a delay of a few seconds before the PHY completes
2954 * autonegotiation and the link is brought up. Any transmissions
2955 * made during that delay will be lost. Dealing with this is tricky:
2956 * we can't just pause in the init routine while waiting for the
2957 * PHY to come ready since that would bring the whole system to
2958 * a screeching halt for several seconds.
2960 * What we do here is prevent the TX start routine from sending
2961 * any packets until a link has been established. After the
2962 * interface has been initialized, the tick routine will poll
2963 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2964 * that time, packets will stay in the send queue, and once the
2965 * link comes up, they will be flushed out to the wire.
2967 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2968 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2970 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2974 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2975 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
2977 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
2983 * A transmit underrun has occurred. Back off the transmit threshold,
2984 * or switch to store and forward mode if we have to.
2987 dc_tx_underrun(struct dc_softc *sc)
2992 if (DC_IS_DAVICOM(sc))
2995 if (DC_IS_INTEL(sc)) {
2997 * The real 21143 requires that the transmitter be idle
2998 * in order to change the transmit threshold or store
2999 * and forward state.
3001 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3003 for (i = 0; i < DC_TIMEOUT; i++) {
3004 isr = CSR_READ_4(sc, DC_ISR);
3005 if (isr & DC_ISR_TX_IDLE)
3009 if (i == DC_TIMEOUT) {
3010 printf("dc%d: failed to force tx to idle state\n",
3016 printf("dc%d: TX underrun -- ", sc->dc_unit);
3017 sc->dc_txthresh += DC_TXTHRESH_INC;
3018 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3019 printf("using store and forward mode\n");
3020 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3022 printf("increasing TX threshold\n");
3023 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3024 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3027 if (DC_IS_INTEL(sc))
3028 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3031 #ifdef DEVICE_POLLING
3032 static poll_handler_t dc_poll;
3035 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3037 struct dc_softc *sc = ifp->if_softc;
3039 if (!(ifp->if_capenable & IFCAP_POLLING)) {
3040 ether_poll_deregister(ifp);
3041 cmd = POLL_DEREGISTER;
3043 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3044 /* Re-enable interrupts. */
3045 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3049 sc->rxcycles = count;
3052 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE))
3055 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3058 status = CSR_READ_4(sc, DC_ISR);
3059 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3060 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3066 /* ack what we have */
3067 CSR_WRITE_4(sc, DC_ISR, status);
3069 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3070 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3071 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3073 if (dc_rx_resync(sc))
3076 /* restart transmit unit if necessary */
3077 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3078 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3080 if (status & DC_ISR_TX_UNDERRUN)
3083 if (status & DC_ISR_BUS_ERR) {
3084 printf("dc_poll: dc%d bus error\n", sc->dc_unit);
3091 #endif /* DEVICE_POLLING */
3096 struct dc_softc *sc;
3105 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3110 #ifdef DEVICE_POLLING
3111 if (ifp->if_flags & IFF_POLLING)
3113 if ((ifp->if_capenable & IFCAP_POLLING) &&
3114 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3115 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3120 /* Suppress unwanted interrupts */
3121 if (!(ifp->if_flags & IFF_UP)) {
3122 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3128 /* Disable interrupts. */
3129 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3131 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS)
3132 && status != 0xFFFFFFFF) {
3134 CSR_WRITE_4(sc, DC_ISR, status);
3136 if (status & DC_ISR_RX_OK) {
3138 curpkts = ifp->if_ipackets;
3140 if (curpkts == ifp->if_ipackets) {
3141 while (dc_rx_resync(sc))
3146 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3149 if (status & DC_ISR_TX_IDLE) {
3151 if (sc->dc_cdata.dc_tx_cnt) {
3152 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3153 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3157 if (status & DC_ISR_TX_UNDERRUN)
3160 if ((status & DC_ISR_RX_WATDOGTIMEO)
3161 || (status & DC_ISR_RX_NOBUF)) {
3163 curpkts = ifp->if_ipackets;
3165 if (curpkts == ifp->if_ipackets) {
3166 while (dc_rx_resync(sc))
3171 if (status & DC_ISR_BUS_ERR) {
3177 /* Re-enable interrupts. */
3178 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3180 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3183 #ifdef DEVICE_POLLING
3191 dc_dma_map_txbuf(arg, segs, nseg, mapsize, error)
3193 bus_dma_segment_t *segs;
3198 struct dc_softc *sc;
3200 int cur, first, frag, i;
3204 sc->dc_cdata.dc_tx_err = error;
3208 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3209 for (i = 0; i < nseg; i++) {
3210 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3211 (frag == (DC_TX_LIST_CNT - 1)) &&
3212 (first != sc->dc_cdata.dc_tx_first)) {
3213 bus_dmamap_unload(sc->dc_mtag,
3214 sc->dc_cdata.dc_tx_map[first]);
3215 sc->dc_cdata.dc_tx_err = ENOBUFS;
3219 f = &sc->dc_ldata->dc_tx_list[frag];
3220 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3223 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3225 f->dc_status = htole32(DC_TXSTAT_OWN);
3226 f->dc_data = htole32(segs[i].ds_addr);
3228 DC_INC(frag, DC_TX_LIST_CNT);
3231 sc->dc_cdata.dc_tx_err = 0;
3232 sc->dc_cdata.dc_tx_prod = frag;
3233 sc->dc_cdata.dc_tx_cnt += nseg;
3234 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3235 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping;
3236 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3237 sc->dc_ldata->dc_tx_list[first].dc_ctl |=
3238 htole32(DC_TXCTL_FINT);
3239 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3240 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3241 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3242 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3243 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3247 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3248 * pointers to the fragment pointers.
3251 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3254 int error, idx, chainlen = 0;
3257 * If there's no way we can send any packets, return now.
3259 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6)
3263 * Count the number of frags in this chain to see if
3264 * we need to m_defrag. Since the descriptor list is shared
3265 * by all packets, we'll m_defrag long chains so that they
3266 * do not use up the entire list, even if they would fit.
3268 for (m = *m_head; m != NULL; m = m->m_next)
3271 if ((chainlen > DC_TX_LIST_CNT / 4) ||
3272 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) {
3273 m = m_defrag(*m_head, M_DONTWAIT);
3280 * Start packing the mbufs in this chain into
3281 * the fragment pointers. Stop when we run out
3282 * of fragments or hit the end of the mbuf chain.
3284 idx = sc->dc_cdata.dc_tx_prod;
3285 sc->dc_cdata.dc_tx_mapping = *m_head;
3286 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3287 *m_head, dc_dma_map_txbuf, sc, 0);
3290 if (sc->dc_cdata.dc_tx_err != 0)
3291 return (sc->dc_cdata.dc_tx_err);
3292 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
3293 BUS_DMASYNC_PREWRITE);
3294 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
3295 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3300 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3301 * to the mbuf data regions directly in the transmit lists. We also save a
3302 * copy of the pointers since the transmit list fragment pointers are
3303 * physical addresses.
3307 dc_start(struct ifnet *ifp)
3309 struct dc_softc *sc;
3310 struct mbuf *m_head = NULL, *m;
3311 unsigned int queued = 0;
3318 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) {
3323 if (ifp->if_flags & IFF_OACTIVE) {
3328 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3330 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3331 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3335 if (sc->dc_flags & DC_TX_COALESCE &&
3336 (m_head->m_next != NULL ||
3337 sc->dc_flags & DC_TX_ALIGN)) {
3338 m = m_defrag(m_head, M_DONTWAIT);
3340 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3341 ifp->if_flags |= IFF_OACTIVE;
3348 if (dc_encap(sc, &m_head)) {
3349 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3350 ifp->if_flags |= IFF_OACTIVE;
3353 idx = sc->dc_cdata.dc_tx_prod;
3357 * If there's a BPF listener, bounce a copy of this frame
3360 BPF_MTAP(ifp, m_head);
3362 if (sc->dc_flags & DC_TX_ONE) {
3363 ifp->if_flags |= IFF_OACTIVE;
3370 if (!(sc->dc_flags & DC_TX_POLL))
3371 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3374 * Set a timeout in case the chip goes out to lunch.
3385 struct dc_softc *sc = xsc;
3386 struct ifnet *ifp = sc->dc_ifp;
3387 struct mii_data *mii;
3391 mii = device_get_softc(sc->dc_miibus);
3394 * Cancel pending I/O and free all RX/TX buffers.
3400 * Set cache alignment and burst length.
3402 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3403 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3405 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3407 * Evenly share the bus between receive and transmit process.
3409 if (DC_IS_INTEL(sc))
3410 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3411 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3412 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3414 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3416 if (sc->dc_flags & DC_TX_POLL)
3417 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3418 switch(sc->dc_cachesize) {
3420 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3423 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3426 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3430 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3434 if (sc->dc_flags & DC_TX_STORENFWD)
3435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3437 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3440 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3441 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3445 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3446 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3448 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3450 * The app notes for the 98713 and 98715A say that
3451 * in order to have the chips operate properly, a magic
3452 * number must be written to CSR16. Macronix does not
3453 * document the meaning of these bits so there's no way
3454 * to know exactly what they do. The 98713 has a magic
3455 * number all its own; the rest all use a different one.
3457 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3458 if (sc->dc_type == DC_TYPE_98713)
3459 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3461 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3464 if (DC_IS_XIRCOM(sc)) {
3466 * setup General Purpose Port mode and data so the tulip
3467 * can talk to the MII.
3469 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3470 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3472 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3473 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3478 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3480 /* Init circular RX list. */
3481 if (dc_list_rx_init(sc) == ENOBUFS) {
3482 printf("dc%d: initialization failed: no "
3483 "memory for rx buffers\n", sc->dc_unit);
3490 * Init TX descriptors.
3492 dc_list_tx_init(sc);
3495 * Load the address of the RX list.
3497 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3498 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3501 * Enable interrupts.
3503 #ifdef DEVICE_POLLING
3505 * ... but only if we are not polling, and make sure they are off in
3506 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3509 if (ifp->if_flags & IFF_POLLING)
3510 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3513 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3514 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3516 /* Enable transmitter. */
3517 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3520 * If this is an Intel 21143 and we're not using the
3521 * MII port, program the LED control pins so we get
3522 * link and activity indications.
3524 if (sc->dc_flags & DC_TULIP_LEDS) {
3525 CSR_WRITE_4(sc, DC_WATCHDOG,
3526 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3527 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3531 * Load the RX/multicast filter. We do this sort of late
3532 * because the filter programming scheme on the 21143 and
3533 * some clones requires DMAing a setup frame via the TX
3534 * engine, and we need the transmitter enabled for that.
3538 /* Enable receiver. */
3539 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3540 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3543 dc_setcfg(sc, sc->dc_if_media);
3545 ifp->if_flags |= IFF_RUNNING;
3546 ifp->if_flags &= ~IFF_OACTIVE;
3548 /* Don't start the ticker if this is a homePNA link. */
3549 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3552 if (sc->dc_flags & DC_21143_NWAY)
3553 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3555 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3559 if(sc->dc_srm_media) {
3562 ifr.ifr_media = sc->dc_srm_media;
3563 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3564 sc->dc_srm_media = 0;
3571 * Set media options.
3574 dc_ifmedia_upd(struct ifnet *ifp)
3576 struct dc_softc *sc;
3577 struct mii_data *mii;
3578 struct ifmedia *ifm;
3581 mii = device_get_softc(sc->dc_miibus);
3583 ifm = &mii->mii_media;
3585 if (DC_IS_DAVICOM(sc) &&
3586 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3587 dc_setcfg(sc, ifm->ifm_media);
3595 * Report current media status.
3598 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3600 struct dc_softc *sc;
3601 struct mii_data *mii;
3602 struct ifmedia *ifm;
3605 mii = device_get_softc(sc->dc_miibus);
3607 ifm = &mii->mii_media;
3608 if (DC_IS_DAVICOM(sc)) {
3609 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3610 ifmr->ifm_active = ifm->ifm_media;
3611 ifmr->ifm_status = 0;
3615 ifmr->ifm_active = mii->mii_media_active;
3616 ifmr->ifm_status = mii->mii_media_status;
3620 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3622 struct dc_softc *sc = ifp->if_softc;
3623 struct ifreq *ifr = (struct ifreq *)data;
3624 struct mii_data *mii;
3631 if (ifp->if_flags & IFF_UP) {
3632 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3633 (IFF_PROMISC | IFF_ALLMULTI);
3635 if (ifp->if_flags & IFF_RUNNING) {
3639 sc->dc_txthresh = 0;
3643 if (ifp->if_flags & IFF_RUNNING)
3646 sc->dc_if_flags = ifp->if_flags;
3656 mii = device_get_softc(sc->dc_miibus);
3657 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3659 if (sc->dc_srm_media)
3660 sc->dc_srm_media = 0;
3664 ifp->if_capenable &= ~IFCAP_POLLING;
3665 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
3668 error = ether_ioctl(ifp, command, data);
3678 dc_watchdog(struct ifnet *ifp)
3680 struct dc_softc *sc;
3687 printf("dc%d: watchdog timeout\n", sc->dc_unit);
3693 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3700 * Stop the adapter and free any mbufs allocated to the
3704 dc_stop(struct dc_softc *sc)
3707 struct dc_list_data *ld;
3708 struct dc_chain_data *cd;
3719 callout_stop(&sc->dc_stat_ch);
3721 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3722 #ifdef DEVICE_POLLING
3723 ether_poll_deregister(ifp);
3726 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3727 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3728 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3729 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3733 * Free data in the RX lists.
3735 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3736 if (cd->dc_rx_chain[i] != NULL) {
3737 m_freem(cd->dc_rx_chain[i]);
3738 cd->dc_rx_chain[i] = NULL;
3741 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
3744 * Free the TX list buffers.
3746 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3747 if (cd->dc_tx_chain[i] != NULL) {
3748 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
3749 if ((ctl & DC_TXCTL_SETUP) ||
3750 !(ctl & DC_TXCTL_LASTFRAG)) {
3751 cd->dc_tx_chain[i] = NULL;
3754 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
3755 m_freem(cd->dc_tx_chain[i]);
3756 cd->dc_tx_chain[i] = NULL;
3759 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
3765 * Device suspend routine. Stop the interface and save some PCI
3766 * settings in case the BIOS doesn't restore them properly on
3770 dc_suspend(device_t dev)
3772 struct dc_softc *sc;
3777 sc = device_get_softc(dev);
3786 * Device resume routine. Restore some PCI settings in case the BIOS
3787 * doesn't, re-enable busmastering, and restart the interface if
3791 dc_resume(device_t dev)
3793 struct dc_softc *sc;
3799 sc = device_get_softc(dev);
3802 /* reinitialize interface if necessary */
3803 if (ifp->if_flags & IFF_UP)
3813 * Stop all chip I/O so that the kernel's probe routines don't
3814 * get confused by errant DMAs when rebooting.
3817 dc_shutdown(device_t dev)
3819 struct dc_softc *sc;
3821 sc = device_get_softc(dev);
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