2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
40 * series chips and several workalikes including the following:
42 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
43 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
44 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
45 * ASIX Electronics AX88140A (www.asix.com.tw)
46 * ASIX Electronics AX88141 (www.asix.com.tw)
47 * ADMtek AL981 (www.admtek.com.tw)
48 * ADMtek AN983 (www.admtek.com.tw)
49 * ADMtek CardBus AN985 (www.admtek.com.tw)
50 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
51 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
52 * Accton EN1217 (www.accton.com)
53 * Xircom X3201 (www.xircom.com)
55 * Conexant LANfinity (www.conexant.com)
56 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
58 * Datasheets for the 21143 are available at developer.intel.com.
59 * Datasheets for the clone parts can be found at their respective sites.
60 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
61 * The PNIC II is essentially a Macronix 98715A chip; the only difference
62 * worth noting is that its multicast hash table is only 128 bits wide
65 * Written by Bill Paul <wpaul@ee.columbia.edu>
66 * Electrical Engineering Department
67 * Columbia University, New York City
70 * The Intel 21143 is the successor to the DEC 21140. It is basically
71 * the same as the 21140 but with a few new features. The 21143 supports
72 * three kinds of media attachments:
74 * o MII port, for 10Mbps and 100Mbps support and NWAY
75 * autonegotiation provided by an external PHY.
76 * o SYM port, for symbol mode 100Mbps support.
80 * The 100Mbps SYM port and 10baseT port can be used together in
81 * combination with the internal NWAY support to create a 10/100
82 * autosensing configuration.
84 * Note that not all tulip workalikes are handled in this driver: we only
85 * deal with those which are relatively well behaved. The Winbond is
86 * handled separately due to its different register offsets and the
87 * special handling needed for its various bugs. The PNIC is handled
88 * here, but I'm not thrilled about it.
90 * All of the workalike chips use some form of MII transceiver support
91 * with the exception of the Macronix chips, which also have a SYM port.
92 * The ASIX AX88140A is also documented to have a SYM port, but all
93 * the cards I've seen use an MII transceiver, probably because the
94 * AX88140A doesn't support internal NWAY.
97 #ifdef HAVE_KERNEL_OPTION_HEADERS
98 #include "opt_device_polling.h"
101 #include <sys/param.h>
102 #include <sys/endian.h>
103 #include <sys/systm.h>
104 #include <sys/sockio.h>
105 #include <sys/mbuf.h>
106 #include <sys/malloc.h>
107 #include <sys/kernel.h>
108 #include <sys/module.h>
109 #include <sys/socket.h>
112 #include <net/if_var.h>
113 #include <net/if_arp.h>
114 #include <net/ethernet.h>
115 #include <net/if_dl.h>
116 #include <net/if_media.h>
117 #include <net/if_types.h>
118 #include <net/if_vlan_var.h>
122 #include <machine/bus.h>
123 #include <machine/resource.h>
125 #include <sys/rman.h>
127 #include <dev/mii/mii.h>
128 #include <dev/mii/mii_bitbang.h>
129 #include <dev/mii/miivar.h>
131 #include <dev/pci/pcireg.h>
132 #include <dev/pci/pcivar.h>
134 #define DC_USEIOSPACE
136 #include <dev/dc/if_dcreg.h>
139 #include <dev/ofw/openfirm.h>
140 #include <machine/ofw_machdep.h>
143 MODULE_DEPEND(dc, pci, 1, 1, 1);
144 MODULE_DEPEND(dc, ether, 1, 1, 1);
145 MODULE_DEPEND(dc, miibus, 1, 1, 1);
148 * "device miibus" is required in kernel config. See GENERIC if you get
151 #include "miibus_if.h"
154 * Various supported device vendors/types and their names.
156 static const struct dc_type dc_devs[] = {
157 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
158 "Intel 21143 10/100BaseTX" },
159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
160 "Davicom DM9009 10/100BaseTX" },
161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
162 "Davicom DM9100 10/100BaseTX" },
163 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
164 "Davicom DM9102A 10/100BaseTX" },
165 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
166 "Davicom DM9102 10/100BaseTX" },
167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
168 "ADMtek AL981 10/100BaseTX" },
169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
170 "ADMtek AN983 10/100BaseTX" },
171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
172 "ADMtek AN985 CardBus 10/100BaseTX or clone" },
173 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
174 "ADMtek ADM9511 10/100BaseTX" },
175 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
176 "ADMtek ADM9513 10/100BaseTX" },
177 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
178 "ASIX AX88141 10/100BaseTX" },
179 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
180 "ASIX AX88140A 10/100BaseTX" },
181 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
182 "Macronix 98713A 10/100BaseTX" },
183 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
184 "Macronix 98713 10/100BaseTX" },
185 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
186 "Compex RL100-TX 10/100BaseTX" },
187 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
188 "Compex RL100-TX 10/100BaseTX" },
189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
190 "Macronix 98725 10/100BaseTX" },
191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
192 "Macronix 98715AEC-C 10/100BaseTX" },
193 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
194 "Macronix 98715/98715A 10/100BaseTX" },
195 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
196 "Macronix 98727/98732 10/100BaseTX" },
197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
198 "LC82C115 PNIC II 10/100BaseTX" },
199 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
200 "82c169 PNIC 10/100BaseTX" },
201 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
202 "82c168 PNIC 10/100BaseTX" },
203 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
204 "Accton EN1217 10/100BaseTX" },
205 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
206 "Accton EN2242 MiniPCI 10/100BaseTX" },
207 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
208 "Xircom X3201 10/100BaseTX" },
209 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
210 "Neteasy DRP-32TXD Cardbus 10/100" },
211 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
212 "Abocom FE2500 10/100BaseTX" },
213 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
214 "Abocom FE2500MX 10/100BaseTX" },
215 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
216 "Conexant LANfinity MiniPCI 10/100BaseTX" },
217 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
218 "Hawking CB102 CardBus 10/100" },
219 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
220 "PlaneX FNW-3602-T CardBus 10/100" },
221 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
222 "3Com OfficeConnect 10/100B" },
223 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
224 "Microsoft MN-120 CardBus 10/100" },
225 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
226 "Microsoft MN-130 10/100" },
227 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
228 "Linksys PCMPC200 CardBus 10/100" },
229 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
230 "Linksys PCMPC200 CardBus 10/100" },
231 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0,
232 "ULi M5261 FastEthernet" },
233 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0,
234 "ULi M5263 FastEthernet" },
238 static int dc_probe(device_t);
239 static int dc_attach(device_t);
240 static int dc_detach(device_t);
241 static int dc_suspend(device_t);
242 static int dc_resume(device_t);
243 static const struct dc_type *dc_devtype(device_t);
244 static void dc_discard_rxbuf(struct dc_softc *, int);
245 static int dc_newbuf(struct dc_softc *, int);
246 static int dc_encap(struct dc_softc *, struct mbuf **);
247 static void dc_pnic_rx_bug_war(struct dc_softc *, int);
248 static int dc_rx_resync(struct dc_softc *);
249 static int dc_rxeof(struct dc_softc *);
250 static void dc_txeof(struct dc_softc *);
251 static void dc_tick(void *);
252 static void dc_tx_underrun(struct dc_softc *);
253 static void dc_intr(void *);
254 static void dc_start(struct ifnet *);
255 static void dc_start_locked(struct ifnet *);
256 static int dc_ioctl(struct ifnet *, u_long, caddr_t);
257 static void dc_init(void *);
258 static void dc_init_locked(struct dc_softc *);
259 static void dc_stop(struct dc_softc *);
260 static void dc_watchdog(void *);
261 static int dc_shutdown(device_t);
262 static int dc_ifmedia_upd(struct ifnet *);
263 static int dc_ifmedia_upd_locked(struct dc_softc *);
264 static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
266 static int dc_dma_alloc(struct dc_softc *);
267 static void dc_dma_free(struct dc_softc *);
268 static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
270 static void dc_delay(struct dc_softc *);
271 static void dc_eeprom_idle(struct dc_softc *);
272 static void dc_eeprom_putbyte(struct dc_softc *, int);
273 static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
274 static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
275 static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
276 static void dc_eeprom_width(struct dc_softc *);
277 static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
279 static int dc_miibus_readreg(device_t, int, int);
280 static int dc_miibus_writereg(device_t, int, int, int);
281 static void dc_miibus_statchg(device_t);
282 static void dc_miibus_mediainit(device_t);
284 static void dc_setcfg(struct dc_softc *, int);
285 static void dc_netcfg_wait(struct dc_softc *);
286 static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
287 static uint32_t dc_mchash_be(const uint8_t *);
288 static void dc_setfilt_21143(struct dc_softc *);
289 static void dc_setfilt_asix(struct dc_softc *);
290 static void dc_setfilt_admtek(struct dc_softc *);
291 static void dc_setfilt_uli(struct dc_softc *);
292 static void dc_setfilt_xircom(struct dc_softc *);
294 static void dc_setfilt(struct dc_softc *);
296 static void dc_reset(struct dc_softc *);
297 static int dc_list_rx_init(struct dc_softc *);
298 static int dc_list_tx_init(struct dc_softc *);
300 static int dc_read_srom(struct dc_softc *, int);
301 static int dc_parse_21143_srom(struct dc_softc *);
302 static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
303 static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
304 static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
305 static void dc_apply_fixup(struct dc_softc *, int);
306 static int dc_check_multiport(struct dc_softc *);
311 static uint32_t dc_mii_bitbang_read(device_t);
312 static void dc_mii_bitbang_write(device_t, uint32_t);
314 static const struct mii_bitbang_ops dc_mii_bitbang_ops = {
316 dc_mii_bitbang_write,
318 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */
319 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */
320 DC_SIO_MII_CLK, /* MII_BIT_MDC */
321 0, /* MII_BIT_DIR_HOST_PHY */
322 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */
327 #define DC_RES SYS_RES_IOPORT
328 #define DC_RID DC_PCI_CFBIO
330 #define DC_RES SYS_RES_MEMORY
331 #define DC_RID DC_PCI_CFBMA
334 static device_method_t dc_methods[] = {
335 /* Device interface */
336 DEVMETHOD(device_probe, dc_probe),
337 DEVMETHOD(device_attach, dc_attach),
338 DEVMETHOD(device_detach, dc_detach),
339 DEVMETHOD(device_suspend, dc_suspend),
340 DEVMETHOD(device_resume, dc_resume),
341 DEVMETHOD(device_shutdown, dc_shutdown),
344 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
345 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
346 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
347 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
352 static driver_t dc_driver = {
355 sizeof(struct dc_softc)
358 static devclass_t dc_devclass;
360 DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL,
362 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
364 #define DC_SETBIT(sc, reg, x) \
365 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
367 #define DC_CLRBIT(sc, reg, x) \
368 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
370 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
371 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
374 dc_delay(struct dc_softc *sc)
378 for (idx = (300 / 33) + 1; idx > 0; idx--)
379 CSR_READ_4(sc, DC_BUSCTL);
383 dc_eeprom_width(struct dc_softc *sc)
387 /* Force EEPROM to idle state. */
390 /* Enter EEPROM access mode. */
391 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
393 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
402 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
412 for (i = 1; i <= 12; i++) {
413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
415 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
424 /* Turn off EEPROM access mode. */
432 /* Enter EEPROM access mode. */
433 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
435 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
442 /* Turn off EEPROM access mode. */
447 dc_eeprom_idle(struct dc_softc *sc)
451 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
453 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
455 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
457 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
460 for (i = 0; i < 25; i++) {
461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
471 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
475 * Send a read command and address to the EEPROM, check for ACK.
478 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
482 d = DC_EECMD_READ >> 6;
485 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
487 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
489 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
491 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
496 * Feed in each bit and strobe the clock.
498 for (i = sc->dc_romwidth; i--;) {
499 if (addr & (1 << i)) {
500 SIO_SET(DC_SIO_EE_DATAIN);
502 SIO_CLR(DC_SIO_EE_DATAIN);
505 SIO_SET(DC_SIO_EE_CLK);
507 SIO_CLR(DC_SIO_EE_CLK);
513 * Read a word of data stored in the EEPROM at address 'addr.'
514 * The PNIC 82c168/82c169 has its own non-standard way to read
518 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
523 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
525 for (i = 0; i < DC_TIMEOUT; i++) {
527 r = CSR_READ_4(sc, DC_SIO);
528 if (!(r & DC_PN_SIOCTL_BUSY)) {
529 *dest = (uint16_t)(r & 0xFFFF);
536 * Read a word of data stored in the EEPROM at address 'addr.'
537 * The Xircom X3201 has its own non-standard way to read
541 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
544 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
547 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
548 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
550 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
551 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
553 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
557 * Read a word of data stored in the EEPROM at address 'addr.'
560 dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
565 /* Force EEPROM to idle state. */
568 /* Enter EEPROM access mode. */
569 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
571 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
573 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
575 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
579 * Send address of word we want to read.
581 dc_eeprom_putbyte(sc, addr);
584 * Start reading bits from EEPROM.
586 for (i = 0x8000; i; i >>= 1) {
587 SIO_SET(DC_SIO_EE_CLK);
589 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
592 SIO_CLR(DC_SIO_EE_CLK);
596 /* Turn off EEPROM access mode. */
603 * Read a sequence of words from the EEPROM.
606 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
609 uint16_t word = 0, *ptr;
611 for (i = 0; i < cnt; i++) {
613 dc_eeprom_getword_pnic(sc, off + i, &word);
614 else if (DC_IS_XIRCOM(sc))
615 dc_eeprom_getword_xircom(sc, off + i, &word);
617 dc_eeprom_getword(sc, off + i, &word);
618 ptr = (uint16_t *)(dest + (i * 2));
620 *ptr = be16toh(word);
622 *ptr = le16toh(word);
627 * Write the MII serial port for the MII bit-bang module.
630 dc_mii_bitbang_write(device_t dev, uint32_t val)
634 sc = device_get_softc(dev);
636 CSR_WRITE_4(sc, DC_SIO, val);
637 CSR_BARRIER_4(sc, DC_SIO,
638 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
642 * Read the MII serial port for the MII bit-bang module.
645 dc_mii_bitbang_read(device_t dev)
650 sc = device_get_softc(dev);
652 val = CSR_READ_4(sc, DC_SIO);
653 CSR_BARRIER_4(sc, DC_SIO,
654 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
660 dc_miibus_readreg(device_t dev, int phy, int reg)
663 int i, rval, phy_reg = 0;
665 sc = device_get_softc(dev);
667 if (sc->dc_pmode != DC_PMODE_MII) {
668 if (phy == (MII_NPHY - 1)) {
672 * Fake something to make the probe
673 * code think there's a PHY here.
675 return (BMSR_MEDIAMASK);
678 return (DC_VENDORID_LO);
679 return (DC_VENDORID_DEC);
682 return (DC_DEVICEID_82C168);
683 return (DC_DEVICEID_21143);
691 if (DC_IS_PNIC(sc)) {
692 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
693 (phy << 23) | (reg << 18));
694 for (i = 0; i < DC_TIMEOUT; i++) {
696 rval = CSR_READ_4(sc, DC_PN_MII);
697 if (!(rval & DC_PN_MII_BUSY)) {
699 return (rval == 0xFFFF ? 0 : rval);
705 if (sc->dc_type == DC_TYPE_ULI_M5263) {
706 CSR_WRITE_4(sc, DC_ROM,
707 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
708 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
710 for (i = 0; i < DC_TIMEOUT; i++) {
712 rval = CSR_READ_4(sc, DC_ROM);
713 if ((rval & DC_ULI_PHY_OP_DONE) != 0) {
714 return (rval & DC_ULI_PHY_DATA_MASK);
718 device_printf(dev, "phy read timed out\n");
722 if (DC_IS_COMET(sc)) {
725 phy_reg = DC_AL_BMCR;
728 phy_reg = DC_AL_BMSR;
731 phy_reg = DC_AL_VENID;
734 phy_reg = DC_AL_DEVID;
737 phy_reg = DC_AL_ANAR;
740 phy_reg = DC_AL_LPAR;
743 phy_reg = DC_AL_ANER;
746 device_printf(dev, "phy_read: bad phy register %x\n",
751 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
757 if (sc->dc_type == DC_TYPE_98713) {
758 phy_reg = CSR_READ_4(sc, DC_NETCFG);
759 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
761 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
762 if (sc->dc_type == DC_TYPE_98713)
763 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
769 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
774 sc = device_get_softc(dev);
776 if (DC_IS_PNIC(sc)) {
777 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
778 (phy << 23) | (reg << 10) | data);
779 for (i = 0; i < DC_TIMEOUT; i++) {
780 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
786 if (sc->dc_type == DC_TYPE_ULI_M5263) {
787 CSR_WRITE_4(sc, DC_ROM,
788 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
789 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
790 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) |
791 DC_ULI_PHY_OP_WRITE);
796 if (DC_IS_COMET(sc)) {
799 phy_reg = DC_AL_BMCR;
802 phy_reg = DC_AL_BMSR;
805 phy_reg = DC_AL_VENID;
808 phy_reg = DC_AL_DEVID;
811 phy_reg = DC_AL_ANAR;
814 phy_reg = DC_AL_LPAR;
817 phy_reg = DC_AL_ANER;
820 device_printf(dev, "phy_write: bad phy register %x\n",
826 CSR_WRITE_4(sc, phy_reg, data);
830 if (sc->dc_type == DC_TYPE_98713) {
831 phy_reg = CSR_READ_4(sc, DC_NETCFG);
832 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
834 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);
835 if (sc->dc_type == DC_TYPE_98713)
836 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
842 dc_miibus_statchg(device_t dev)
846 struct mii_data *mii;
849 sc = device_get_softc(dev);
851 mii = device_get_softc(sc->dc_miibus);
853 if (mii == NULL || ifp == NULL ||
854 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
857 ifm = &mii->mii_media;
858 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
859 dc_setcfg(sc, ifm->ifm_media);
861 } else if (!DC_IS_ADMTEK(sc))
862 dc_setcfg(sc, mii->mii_media_active);
865 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
866 (IFM_ACTIVE | IFM_AVALID)) {
867 switch (IFM_SUBTYPE(mii->mii_media_active)) {
877 * Special support for DM9102A cards with HomePNA PHYs. Note:
878 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
879 * to be impossible to talk to the management interface of the DM9801
880 * PHY (its MDIO pin is not connected to anything). Consequently,
881 * the driver has to just 'know' about the additional mode and deal
882 * with it itself. *sigh*
885 dc_miibus_mediainit(device_t dev)
888 struct mii_data *mii;
892 rev = pci_get_revid(dev);
894 sc = device_get_softc(dev);
895 mii = device_get_softc(sc->dc_miibus);
896 ifm = &mii->mii_media;
898 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
899 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
902 #define DC_BITS_512 9
903 #define DC_BITS_128 7
907 dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
911 /* Compute CRC for the address value. */
912 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
915 * The hash table on the PNIC II and the MX98715AEC-C/D/E
916 * chips is only 128 bits wide.
918 if (sc->dc_flags & DC_128BIT_HASH)
919 return (crc & ((1 << DC_BITS_128) - 1));
921 /* The hash table on the MX98715BEC is only 64 bits wide. */
922 if (sc->dc_flags & DC_64BIT_HASH)
923 return (crc & ((1 << DC_BITS_64) - 1));
925 /* Xircom's hash filtering table is different (read: weird) */
926 /* Xircom uses the LEAST significant bits */
927 if (DC_IS_XIRCOM(sc)) {
928 if ((crc & 0x180) == 0x180)
929 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
931 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
935 return (crc & ((1 << DC_BITS_512) - 1));
939 * Calculate CRC of a multicast group address, return the lower 6 bits.
942 dc_mchash_be(const uint8_t *addr)
946 /* Compute CRC for the address value. */
947 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
949 /* Return the filter bit position. */
950 return ((crc >> 26) & 0x0000003F);
954 * 21143-style RX filter setup routine. Filter programming is done by
955 * downloading a special setup frame into the TX engine. 21143, Macronix,
956 * PNIC, PNIC II and Davicom chips are programmed this way.
958 * We always program the chip using 'hash perfect' mode, i.e. one perfect
959 * address (our node address) and a 512-bit hash filter for multicast
960 * frames. We also sneak the broadcast address into the hash filter since
964 dc_setfilt_21143(struct dc_softc *sc)
966 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
967 struct dc_desc *sframe;
969 struct ifmultiaddr *ifma;
975 i = sc->dc_cdata.dc_tx_prod;
976 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
977 sc->dc_cdata.dc_tx_cnt++;
978 sframe = &sc->dc_ldata.dc_tx_list[i];
979 sp = sc->dc_cdata.dc_sbuf;
980 bzero(sp, DC_SFRAME_LEN);
982 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
983 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
984 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
986 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
988 /* If we want promiscuous mode, set the allframes bit. */
989 if (ifp->if_flags & IFF_PROMISC)
990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
992 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
994 if (ifp->if_flags & IFF_ALLMULTI)
995 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
997 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1000 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1001 if (ifma->ifma_addr->sa_family != AF_LINK)
1003 h = dc_mchash_le(sc,
1004 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1005 sp[h >> 4] |= htole32(1 << (h & 0xF));
1007 if_maddr_runlock(ifp);
1009 if (ifp->if_flags & IFF_BROADCAST) {
1010 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1011 sp[h >> 4] |= htole32(1 << (h & 0xF));
1014 /* Set our MAC address. */
1015 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1016 sp[39] = DC_SP_MAC(eaddr[0]);
1017 sp[40] = DC_SP_MAC(eaddr[1]);
1018 sp[41] = DC_SP_MAC(eaddr[2]);
1020 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1021 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1022 BUS_DMASYNC_PREWRITE);
1023 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1024 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1027 * The PNIC takes an exceedingly long time to process its
1028 * setup frame; wait 10ms after posting the setup frame
1029 * before proceeding, just so it has time to swallow its
1034 sc->dc_wdog_timer = 5;
1038 dc_setfilt_admtek(struct dc_softc *sc)
1040 uint8_t eaddr[ETHER_ADDR_LEN];
1042 struct ifmultiaddr *ifma;
1044 uint32_t hashes[2] = { 0, 0 };
1048 /* Init our MAC address. */
1049 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1050 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1051 eaddr[1] << 8 | eaddr[0]);
1052 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1054 /* If we want promiscuous mode, set the allframes bit. */
1055 if (ifp->if_flags & IFF_PROMISC)
1056 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1058 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1060 if (ifp->if_flags & IFF_ALLMULTI)
1061 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1063 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1065 /* First, zot all the existing hash bits. */
1066 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1067 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1070 * If we're already in promisc or allmulti mode, we
1071 * don't have to bother programming the multicast filter.
1073 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1076 /* Now program new ones. */
1077 if_maddr_rlock(ifp);
1078 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1079 if (ifma->ifma_addr->sa_family != AF_LINK)
1081 if (DC_IS_CENTAUR(sc))
1082 h = dc_mchash_le(sc,
1083 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1086 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1088 hashes[0] |= (1 << h);
1090 hashes[1] |= (1 << (h - 32));
1092 if_maddr_runlock(ifp);
1094 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1095 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1099 dc_setfilt_asix(struct dc_softc *sc)
1101 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1103 struct ifmultiaddr *ifma;
1105 uint32_t hashes[2] = { 0, 0 };
1109 /* Init our MAC address. */
1110 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1111 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1112 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1113 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1114 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1116 /* If we want promiscuous mode, set the allframes bit. */
1117 if (ifp->if_flags & IFF_PROMISC)
1118 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1120 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1122 if (ifp->if_flags & IFF_ALLMULTI)
1123 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1125 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1128 * The ASIX chip has a special bit to enable reception
1129 * of broadcast frames.
1131 if (ifp->if_flags & IFF_BROADCAST)
1132 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1134 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1136 /* first, zot all the existing hash bits */
1137 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1138 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1139 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1140 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1143 * If we're already in promisc or allmulti mode, we
1144 * don't have to bother programming the multicast filter.
1146 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1149 /* now program new ones */
1150 if_maddr_rlock(ifp);
1151 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1152 if (ifma->ifma_addr->sa_family != AF_LINK)
1154 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1156 hashes[0] |= (1 << h);
1158 hashes[1] |= (1 << (h - 32));
1160 if_maddr_runlock(ifp);
1162 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1163 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1164 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1165 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1169 dc_setfilt_uli(struct dc_softc *sc)
1171 uint8_t eaddr[ETHER_ADDR_LEN];
1173 struct ifmultiaddr *ifma;
1174 struct dc_desc *sframe;
1175 uint32_t filter, *sp;
1181 i = sc->dc_cdata.dc_tx_prod;
1182 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1183 sc->dc_cdata.dc_tx_cnt++;
1184 sframe = &sc->dc_ldata.dc_tx_list[i];
1185 sp = sc->dc_cdata.dc_sbuf;
1186 bzero(sp, DC_SFRAME_LEN);
1188 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1189 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1190 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT);
1192 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1194 /* Set station address. */
1195 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1196 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]);
1197 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]);
1198 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]);
1200 /* Set broadcast address. */
1201 *sp++ = DC_SP_MAC(0xFFFF);
1202 *sp++ = DC_SP_MAC(0xFFFF);
1203 *sp++ = DC_SP_MAC(0xFFFF);
1205 /* Extract current filter configuration. */
1206 filter = CSR_READ_4(sc, DC_NETCFG);
1207 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI);
1209 /* Now build perfect filters. */
1211 if_maddr_rlock(ifp);
1212 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1213 if (ifma->ifma_addr->sa_family != AF_LINK)
1215 if (mcnt >= DC_ULI_FILTER_NPERF) {
1216 filter |= DC_NETCFG_RX_ALLMULTI;
1219 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1220 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]);
1221 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]);
1222 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]);
1225 if_maddr_runlock(ifp);
1227 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) {
1228 *sp++ = DC_SP_MAC(0xFFFF);
1229 *sp++ = DC_SP_MAC(0xFFFF);
1230 *sp++ = DC_SP_MAC(0xFFFF);
1233 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1234 CSR_WRITE_4(sc, DC_NETCFG,
1235 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1236 if (ifp->if_flags & IFF_PROMISC)
1237 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI;
1238 if (ifp->if_flags & IFF_ALLMULTI)
1239 filter |= DC_NETCFG_RX_ALLMULTI;
1240 CSR_WRITE_4(sc, DC_NETCFG,
1241 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1242 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1243 CSR_WRITE_4(sc, DC_NETCFG, filter);
1245 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1246 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1247 BUS_DMASYNC_PREWRITE);
1248 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1249 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1256 sc->dc_wdog_timer = 5;
1260 dc_setfilt_xircom(struct dc_softc *sc)
1262 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1264 struct ifmultiaddr *ifma;
1265 struct dc_desc *sframe;
1270 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1272 i = sc->dc_cdata.dc_tx_prod;
1273 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1274 sc->dc_cdata.dc_tx_cnt++;
1275 sframe = &sc->dc_ldata.dc_tx_list[i];
1276 sp = sc->dc_cdata.dc_sbuf;
1277 bzero(sp, DC_SFRAME_LEN);
1279 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1280 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1281 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1283 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1285 /* If we want promiscuous mode, set the allframes bit. */
1286 if (ifp->if_flags & IFF_PROMISC)
1287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1289 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1291 if (ifp->if_flags & IFF_ALLMULTI)
1292 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1294 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1296 if_maddr_rlock(ifp);
1297 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1298 if (ifma->ifma_addr->sa_family != AF_LINK)
1300 h = dc_mchash_le(sc,
1301 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1302 sp[h >> 4] |= htole32(1 << (h & 0xF));
1304 if_maddr_runlock(ifp);
1306 if (ifp->if_flags & IFF_BROADCAST) {
1307 h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1308 sp[h >> 4] |= htole32(1 << (h & 0xF));
1311 /* Set our MAC address. */
1312 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1313 sp[0] = DC_SP_MAC(eaddr[0]);
1314 sp[1] = DC_SP_MAC(eaddr[1]);
1315 sp[2] = DC_SP_MAC(eaddr[2]);
1317 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1318 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1319 sframe->dc_status = htole32(DC_TXSTAT_OWN);
1320 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1321 BUS_DMASYNC_PREWRITE);
1322 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1323 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1330 sc->dc_wdog_timer = 5;
1334 dc_setfilt(struct dc_softc *sc)
1337 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1338 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1339 dc_setfilt_21143(sc);
1342 dc_setfilt_asix(sc);
1344 if (DC_IS_ADMTEK(sc))
1345 dc_setfilt_admtek(sc);
1350 if (DC_IS_XIRCOM(sc))
1351 dc_setfilt_xircom(sc);
1355 dc_netcfg_wait(struct dc_softc *sc)
1360 for (i = 0; i < DC_TIMEOUT; i++) {
1361 isr = CSR_READ_4(sc, DC_ISR);
1362 if (isr & DC_ISR_TX_IDLE &&
1363 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1364 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1368 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) {
1369 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1370 device_printf(sc->dc_dev,
1371 "%s: failed to force tx to idle state\n", __func__);
1372 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1373 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1374 !DC_HAS_BROKEN_RXSTATE(sc))
1375 device_printf(sc->dc_dev,
1376 "%s: failed to force rx to idle state\n", __func__);
1381 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1382 * the netconfig register, we first have to put the transmit and/or
1383 * receive logic in the idle state.
1386 dc_setcfg(struct dc_softc *sc, int media)
1388 int restart = 0, watchdogreg;
1390 if (IFM_SUBTYPE(media) == IFM_NONE)
1393 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1395 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1399 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1400 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1401 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1402 if (sc->dc_pmode == DC_PMODE_MII) {
1403 if (DC_IS_INTEL(sc)) {
1404 /* There's a write enable bit here that reads as 1. */
1405 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1406 watchdogreg &= ~DC_WDOG_CTLWREN;
1407 watchdogreg |= DC_WDOG_JABBERDIS;
1408 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1410 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1412 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1413 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1414 if (sc->dc_type == DC_TYPE_98713)
1415 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1416 DC_NETCFG_SCRAMBLER));
1417 if (!DC_IS_DAVICOM(sc))
1418 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1419 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1421 if (DC_IS_PNIC(sc)) {
1422 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1423 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1424 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1427 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1432 if (IFM_SUBTYPE(media) == IFM_10_T) {
1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1434 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1435 if (sc->dc_pmode == DC_PMODE_MII) {
1436 /* There's a write enable bit here that reads as 1. */
1437 if (DC_IS_INTEL(sc)) {
1438 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1439 watchdogreg &= ~DC_WDOG_CTLWREN;
1440 watchdogreg |= DC_WDOG_JABBERDIS;
1441 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1443 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1445 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1446 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1447 if (sc->dc_type == DC_TYPE_98713)
1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1449 if (!DC_IS_DAVICOM(sc))
1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1451 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1453 if (DC_IS_PNIC(sc)) {
1454 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1455 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1456 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1458 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1461 if (DC_IS_INTEL(sc)) {
1462 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1463 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1464 if ((media & IFM_GMASK) == IFM_FDX)
1465 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1468 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1469 DC_CLRBIT(sc, DC_10BTCTRL,
1470 DC_TCTL_AUTONEGENBL);
1477 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1478 * PHY and we want HomePNA mode, set the portsel bit to turn
1479 * on the external MII port.
1481 if (DC_IS_DAVICOM(sc)) {
1482 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1483 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1486 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1490 if ((media & IFM_GMASK) == IFM_FDX) {
1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1492 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1493 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1495 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1496 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1497 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1505 dc_reset(struct dc_softc *sc)
1509 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1511 for (i = 0; i < DC_TIMEOUT; i++) {
1513 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1517 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1518 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) {
1520 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1524 if (i == DC_TIMEOUT)
1525 device_printf(sc->dc_dev, "reset never completed!\n");
1527 /* Wait a little while for the chip to get its brains in order. */
1530 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1531 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1532 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1535 * Bring the SIA out of reset. In some cases, it looks
1536 * like failing to unreset the SIA soon enough gets it
1537 * into a state where it will never come out of reset
1538 * until we reset the whole chip again.
1540 if (DC_IS_INTEL(sc)) {
1541 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1542 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF);
1543 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1547 static const struct dc_type *
1548 dc_devtype(device_t dev)
1550 const struct dc_type *t;
1555 devid = pci_get_devid(dev);
1556 rev = pci_get_revid(dev);
1558 while (t->dc_name != NULL) {
1559 if (devid == t->dc_devid && rev >= t->dc_minrev)
1568 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1569 * IDs against our list and return a device name if we find a match.
1570 * We do a little bit of extra work to identify the exact type of
1571 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1572 * but different revision IDs. The same is true for 98715/98715A
1573 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1574 * cases, the exact chip revision affects driver behavior.
1577 dc_probe(device_t dev)
1579 const struct dc_type *t;
1581 t = dc_devtype(dev);
1584 device_set_desc(dev, t->dc_name);
1585 return (BUS_PROBE_DEFAULT);
1592 dc_apply_fixup(struct dc_softc *sc, int media)
1594 struct dc_mediainfo *m;
1602 if (m->dc_media == media)
1610 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1611 reg = (p[0] | (p[1] << 8)) << 16;
1612 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1615 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1616 reg = (p[0] | (p[1] << 8)) << 16;
1617 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1622 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1624 struct dc_mediainfo *m;
1626 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1628 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1631 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1632 case DC_SIA_CODE_10BT:
1633 m->dc_media = IFM_10_T;
1635 case DC_SIA_CODE_10BT_FDX:
1636 m->dc_media = IFM_10_T | IFM_FDX;
1638 case DC_SIA_CODE_10B2:
1639 m->dc_media = IFM_10_2;
1641 case DC_SIA_CODE_10B5:
1642 m->dc_media = IFM_10_5;
1649 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1650 * Things apparently already work for cards that do
1651 * supply Media Specific Data.
1653 if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1656 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1660 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1663 m->dc_next = sc->dc_mi;
1666 sc->dc_pmode = DC_PMODE_SIA;
1671 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1673 struct dc_mediainfo *m;
1675 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1677 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1680 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1681 m->dc_media = IFM_100_TX;
1683 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1684 m->dc_media = IFM_100_TX | IFM_FDX;
1687 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
1689 m->dc_next = sc->dc_mi;
1692 sc->dc_pmode = DC_PMODE_SYM;
1697 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1699 struct dc_mediainfo *m;
1702 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1704 device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1707 /* We abuse IFM_AUTO to represent MII. */
1708 m->dc_media = IFM_AUTO;
1709 m->dc_gp_len = l->dc_gpr_len;
1712 p += sizeof(struct dc_eblock_mii);
1714 p += 2 * l->dc_gpr_len;
1715 m->dc_reset_len = *p;
1717 m->dc_reset_ptr = p;
1719 m->dc_next = sc->dc_mi;
1725 dc_read_srom(struct dc_softc *sc, int bits)
1729 size = DC_ROM_SIZE(bits);
1730 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
1731 if (sc->dc_srom == NULL) {
1732 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n");
1735 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1740 dc_parse_21143_srom(struct dc_softc *sc)
1742 struct dc_leaf_hdr *lhdr;
1743 struct dc_eblock_hdr *hdr;
1744 int error, have_mii, i, loff;
1748 loff = sc->dc_srom[27];
1749 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1752 ptr += sizeof(struct dc_leaf_hdr) - 1;
1754 * Look if we got a MII media block.
1756 for (i = 0; i < lhdr->dc_mcnt; i++) {
1757 hdr = (struct dc_eblock_hdr *)ptr;
1758 if (hdr->dc_type == DC_EBLOCK_MII)
1761 ptr += (hdr->dc_len & 0x7F);
1766 * Do the same thing again. Only use SIA and SYM media
1767 * blocks if no MII media block is available.
1770 ptr += sizeof(struct dc_leaf_hdr) - 1;
1772 for (i = 0; i < lhdr->dc_mcnt; i++) {
1773 hdr = (struct dc_eblock_hdr *)ptr;
1774 switch (hdr->dc_type) {
1776 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1780 error = dc_decode_leaf_sia(sc,
1781 (struct dc_eblock_sia *)hdr);
1785 error = dc_decode_leaf_sym(sc,
1786 (struct dc_eblock_sym *)hdr);
1789 /* Don't care. Yet. */
1792 ptr += (hdr->dc_len & 0x7F);
1799 dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1804 ("%s: wrong number of segments (%d)", __func__, nseg));
1806 *paddr = segs->ds_addr;
1810 dc_dma_alloc(struct dc_softc *sc)
1814 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0,
1815 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1816 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1817 NULL, NULL, &sc->dc_ptag);
1819 device_printf(sc->dc_dev,
1820 "failed to allocate parent DMA tag\n");
1824 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1825 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1826 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1,
1827 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag);
1829 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n");
1833 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1834 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1,
1835 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag);
1837 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n");
1841 /* RX descriptor list. */
1842 error = bus_dmamem_alloc(sc->dc_rx_ltag,
1843 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT |
1844 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap);
1846 device_printf(sc->dc_dev,
1847 "failed to allocate DMA'able memory for RX list\n");
1850 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap,
1851 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr,
1852 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT);
1854 device_printf(sc->dc_dev,
1855 "failed to load DMA'able memory for RX list\n");
1858 /* TX descriptor list. */
1859 error = bus_dmamem_alloc(sc->dc_tx_ltag,
1860 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT |
1861 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap);
1863 device_printf(sc->dc_dev,
1864 "failed to allocate DMA'able memory for TX list\n");
1867 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap,
1868 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr,
1869 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT);
1871 device_printf(sc->dc_dev,
1872 "cannot load DMA'able memory for TX list\n");
1877 * Allocate a busdma tag and DMA safe memory for the multicast
1880 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1881 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1882 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
1883 0, NULL, NULL, &sc->dc_stag);
1885 device_printf(sc->dc_dev,
1886 "failed to create DMA tag for setup frame\n");
1889 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
1890 BUS_DMA_NOWAIT, &sc->dc_smap);
1892 device_printf(sc->dc_dev,
1893 "failed to allocate DMA'able memory for setup frame\n");
1896 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
1897 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
1899 device_printf(sc->dc_dev,
1900 "cannot load DMA'able memory for setup frame\n");
1904 /* Allocate a busdma tag for RX mbufs. */
1905 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0,
1906 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1907 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag);
1909 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n");
1913 /* Allocate a busdma tag for TX mbufs. */
1914 error = bus_dma_tag_create(sc->dc_ptag, 1, 0,
1915 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1916 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
1917 0, NULL, NULL, &sc->dc_tx_mtag);
1919 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n");
1923 /* Create the TX/RX busdma maps. */
1924 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1925 error = bus_dmamap_create(sc->dc_tx_mtag, 0,
1926 &sc->dc_cdata.dc_tx_map[i]);
1928 device_printf(sc->dc_dev,
1929 "failed to create TX mbuf dmamap\n");
1933 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1934 error = bus_dmamap_create(sc->dc_rx_mtag, 0,
1935 &sc->dc_cdata.dc_rx_map[i]);
1937 device_printf(sc->dc_dev,
1938 "failed to create RX mbuf dmamap\n");
1942 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap);
1944 device_printf(sc->dc_dev,
1945 "failed to create spare RX mbuf dmamap\n");
1954 dc_dma_free(struct dc_softc *sc)
1959 if (sc->dc_rx_mtag != NULL) {
1960 for (i = 0; i < DC_RX_LIST_CNT; i++) {
1961 if (sc->dc_cdata.dc_rx_map[i] != NULL)
1962 bus_dmamap_destroy(sc->dc_rx_mtag,
1963 sc->dc_cdata.dc_rx_map[i]);
1965 if (sc->dc_sparemap != NULL)
1966 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap);
1967 bus_dma_tag_destroy(sc->dc_rx_mtag);
1971 if (sc->dc_rx_mtag != NULL) {
1972 for (i = 0; i < DC_TX_LIST_CNT; i++) {
1973 if (sc->dc_cdata.dc_tx_map[i] != NULL)
1974 bus_dmamap_destroy(sc->dc_tx_mtag,
1975 sc->dc_cdata.dc_tx_map[i]);
1977 bus_dma_tag_destroy(sc->dc_tx_mtag);
1980 /* RX descriptor list. */
1981 if (sc->dc_rx_ltag) {
1982 if (sc->dc_ldata.dc_rx_list_paddr != 0)
1983 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap);
1984 if (sc->dc_ldata.dc_rx_list != NULL)
1985 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list,
1987 bus_dma_tag_destroy(sc->dc_rx_ltag);
1990 /* TX descriptor list. */
1991 if (sc->dc_tx_ltag) {
1992 if (sc->dc_ldata.dc_tx_list_paddr != 0)
1993 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap);
1994 if (sc->dc_ldata.dc_tx_list != NULL)
1995 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list,
1997 bus_dma_tag_destroy(sc->dc_tx_ltag);
2000 /* multicast setup frame. */
2002 if (sc->dc_saddr != 0)
2003 bus_dmamap_unload(sc->dc_stag, sc->dc_smap);
2004 if (sc->dc_cdata.dc_sbuf != NULL)
2005 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf,
2007 bus_dma_tag_destroy(sc->dc_stag);
2012 * Attach the interface. Allocate softc structures, do ifmedia
2013 * setup and ethernet/BPF attach.
2016 dc_attach(device_t dev)
2018 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
2020 struct dc_softc *sc;
2022 struct dc_mediainfo *m;
2023 uint32_t reg, revision;
2025 int error, mac_offset, n, phy, rid, tmp;
2028 sc = device_get_softc(dev);
2031 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2035 * Map control/status registers.
2037 pci_enable_busmaster(dev);
2040 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
2042 if (sc->dc_res == NULL) {
2043 device_printf(dev, "couldn't map ports/memory\n");
2048 sc->dc_btag = rman_get_bustag(sc->dc_res);
2049 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2051 /* Allocate interrupt. */
2053 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2054 RF_SHAREABLE | RF_ACTIVE);
2056 if (sc->dc_irq == NULL) {
2057 device_printf(dev, "couldn't map interrupt\n");
2062 /* Need this info to decide on a chip type. */
2063 sc->dc_info = dc_devtype(dev);
2064 revision = pci_get_revid(dev);
2067 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
2068 if (sc->dc_info->dc_devid !=
2069 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
2070 sc->dc_info->dc_devid !=
2071 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
2072 dc_eeprom_width(sc);
2074 switch (sc->dc_info->dc_devid) {
2075 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
2076 sc->dc_type = DC_TYPE_21143;
2077 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2078 sc->dc_flags |= DC_REDUCED_MII_POLL;
2079 /* Save EEPROM contents so we can parse them later. */
2080 error = dc_read_srom(sc, sc->dc_romwidth);
2084 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
2085 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
2086 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
2087 sc->dc_type = DC_TYPE_DM9102;
2088 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
2089 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
2090 sc->dc_flags |= DC_TX_ALIGN;
2091 sc->dc_pmode = DC_PMODE_MII;
2093 /* Increase the latency timer value. */
2094 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
2096 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
2097 sc->dc_type = DC_TYPE_AL981;
2098 sc->dc_flags |= DC_TX_USE_TX_INTR;
2099 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2100 sc->dc_pmode = DC_PMODE_MII;
2101 error = dc_read_srom(sc, sc->dc_romwidth);
2105 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983):
2106 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
2107 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
2108 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
2109 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
2110 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
2111 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
2112 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
2113 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
2114 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
2115 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
2116 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
2117 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
2118 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
2119 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
2120 sc->dc_type = DC_TYPE_AN983;
2121 sc->dc_flags |= DC_64BIT_HASH;
2122 sc->dc_flags |= DC_TX_USE_TX_INTR;
2123 sc->dc_flags |= DC_TX_ADMTEK_WAR;
2124 sc->dc_pmode = DC_PMODE_MII;
2125 /* Don't read SROM for - auto-loaded on reset */
2127 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
2128 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
2129 if (revision < DC_REVISION_98713A) {
2130 sc->dc_type = DC_TYPE_98713;
2132 if (revision >= DC_REVISION_98713A) {
2133 sc->dc_type = DC_TYPE_98713A;
2134 sc->dc_flags |= DC_21143_NWAY;
2136 sc->dc_flags |= DC_REDUCED_MII_POLL;
2137 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2139 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
2140 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
2142 * Macronix MX98715AEC-C/D/E parts have only a
2143 * 128-bit hash table. We need to deal with these
2144 * in the same manner as the PNIC II so that we
2145 * get the right number of bits out of the
2148 if (revision >= DC_REVISION_98715AEC_C &&
2149 revision < DC_REVISION_98725)
2150 sc->dc_flags |= DC_128BIT_HASH;
2151 sc->dc_type = DC_TYPE_987x5;
2152 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2153 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2155 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
2156 sc->dc_type = DC_TYPE_987x5;
2157 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2158 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2160 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
2161 sc->dc_type = DC_TYPE_PNICII;
2162 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
2163 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2165 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
2166 sc->dc_type = DC_TYPE_PNIC;
2167 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
2168 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
2169 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2170 if (sc->dc_pnic_rx_buf == NULL) {
2171 device_printf(sc->dc_dev,
2172 "Could not allocate PNIC RX buffer\n");
2176 if (revision < DC_REVISION_82C169)
2177 sc->dc_pmode = DC_PMODE_SYM;
2179 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
2180 sc->dc_type = DC_TYPE_ASIX;
2181 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
2182 sc->dc_flags |= DC_REDUCED_MII_POLL;
2183 sc->dc_pmode = DC_PMODE_MII;
2185 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
2186 sc->dc_type = DC_TYPE_XIRCOM;
2187 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2190 * We don't actually need to coalesce, but we're doing
2191 * it to obtain a double word aligned buffer.
2192 * The DC_TX_COALESCE flag is required.
2194 sc->dc_pmode = DC_PMODE_MII;
2196 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
2197 sc->dc_type = DC_TYPE_CONEXANT;
2198 sc->dc_flags |= DC_TX_INTR_ALWAYS;
2199 sc->dc_flags |= DC_REDUCED_MII_POLL;
2200 sc->dc_pmode = DC_PMODE_MII;
2201 error = dc_read_srom(sc, sc->dc_romwidth);
2205 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261):
2206 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263):
2207 if (sc->dc_info->dc_devid ==
2208 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261))
2209 sc->dc_type = DC_TYPE_ULI_M5261;
2211 sc->dc_type = DC_TYPE_ULI_M5263;
2212 /* TX buffers should be aligned on 4 byte boundary. */
2213 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2215 sc->dc_pmode = DC_PMODE_MII;
2216 error = dc_read_srom(sc, sc->dc_romwidth);
2221 device_printf(dev, "unknown device: %x\n",
2222 sc->dc_info->dc_devid);
2226 /* Save the cache line size. */
2227 if (DC_IS_DAVICOM(sc))
2228 sc->dc_cachesize = 0;
2230 sc->dc_cachesize = pci_get_cachelnsz(dev);
2232 /* Reset the adapter. */
2235 /* Take 21143 out of snooze mode */
2236 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2237 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2238 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2239 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2243 * Try to learn something about the supported media.
2244 * We know that ASIX and ADMtek and Davicom devices
2245 * will *always* be using MII media, so that's a no-brainer.
2246 * The tricky ones are the Macronix/PNIC II and the
2249 if (DC_IS_INTEL(sc)) {
2250 error = dc_parse_21143_srom(sc);
2253 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2254 if (sc->dc_type == DC_TYPE_98713)
2255 sc->dc_pmode = DC_PMODE_MII;
2257 sc->dc_pmode = DC_PMODE_SYM;
2258 } else if (!sc->dc_pmode)
2259 sc->dc_pmode = DC_PMODE_MII;
2262 * Get station address from the EEPROM.
2264 switch(sc->dc_type) {
2266 case DC_TYPE_98713A:
2268 case DC_TYPE_PNICII:
2269 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2270 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2271 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2274 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2276 case DC_TYPE_DM9102:
2277 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2280 * If this is an onboard dc(4) the station address read from
2281 * the EEPROM is all zero and we have to get it from the FCode.
2283 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2284 OF_getetheraddr(dev, (caddr_t)&eaddr);
2289 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2293 reg = CSR_READ_4(sc, DC_AL_PAR0);
2294 mac = (uint8_t *)&eaddr[0];
2295 mac[0] = (reg >> 0) & 0xff;
2296 mac[1] = (reg >> 8) & 0xff;
2297 mac[2] = (reg >> 16) & 0xff;
2298 mac[3] = (reg >> 24) & 0xff;
2299 reg = CSR_READ_4(sc, DC_AL_PAR1);
2300 mac[4] = (reg >> 0) & 0xff;
2301 mac[5] = (reg >> 8) & 0xff;
2303 case DC_TYPE_CONEXANT:
2304 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2307 case DC_TYPE_XIRCOM:
2308 /* The MAC comes from the CIS. */
2309 mac = pci_get_ether(dev);
2311 device_printf(dev, "No station address in CIS!\n");
2315 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2317 case DC_TYPE_ULI_M5261:
2318 case DC_TYPE_ULI_M5263:
2319 srom = (uint16_t *)sc->dc_srom;
2320 if (srom == NULL || *srom == 0xFFFF || *srom == 0) {
2322 * No valid SROM present, read station address
2326 "Reading station address from ID Table.\n");
2327 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000);
2328 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0);
2329 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2330 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010);
2331 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2332 CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2333 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0);
2334 mac = (uint8_t *)eaddr;
2335 for (n = 0; n < ETHER_ADDR_LEN; n++)
2336 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);
2337 CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2338 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000);
2341 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3,
2345 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2349 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr));
2351 * If we still have invalid station address, see whether we can
2352 * find station address for chip 0. Some multi-port controllers
2353 * just store station address for chip 0 if they have a shared
2356 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) ||
2357 (sc->dc_eaddr[0] == 0xffffffff &&
2358 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) {
2359 error = dc_check_multiport(sc);
2361 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr));
2362 /* Extract media information. */
2363 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) {
2364 while (sc->dc_mi != NULL) {
2365 m = sc->dc_mi->dc_next;
2366 free(sc->dc_mi, M_DEVBUF);
2369 error = dc_parse_21143_srom(sc);
2373 } else if (error == ENOMEM)
2379 if ((error = dc_dma_alloc(sc)) != 0)
2382 ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2384 device_printf(dev, "can not if_alloc()\n");
2389 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2390 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2391 ifp->if_ioctl = dc_ioctl;
2392 ifp->if_start = dc_start;
2393 ifp->if_init = dc_init;
2394 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2395 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2396 IFQ_SET_READY(&ifp->if_snd);
2399 * Do MII setup. If this is a 21143, check for a PHY on the
2400 * MII bus after applying any necessary fixups to twiddle the
2401 * GPIO bits. If we don't end up finding a PHY, restore the
2402 * old selection (SIA only or SIA/SYM) and attach the dcphy
2406 if (DC_IS_INTEL(sc)) {
2407 dc_apply_fixup(sc, IFM_AUTO);
2409 sc->dc_pmode = DC_PMODE_MII;
2413 * Setup General Purpose port mode and data so the tulip can talk
2414 * to the MII. This needs to be done before mii_attach so that
2415 * we can actually see them.
2417 if (DC_IS_XIRCOM(sc)) {
2418 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2419 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2421 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2422 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2428 * Note: both the AL981 and AN983 have internal PHYs, however the
2429 * AL981 provides direct access to the PHY registers while the AN983
2430 * uses a serial MII interface. The AN983's MII interface is also
2431 * buggy in that you can read from any MII address (0 to 31), but
2432 * only address 1 behaves normally. To deal with both cases, we
2433 * pretend that the PHY is at MII address 1.
2435 if (DC_IS_ADMTEK(sc))
2436 phy = DC_ADMTEK_PHYADDR;
2439 * Note: the ukphy probes of the RS7112 report a PHY at MII address
2440 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the
2443 if (DC_IS_CONEXANT(sc))
2444 phy = DC_CONEXANT_PHYADDR;
2446 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2447 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
2449 if (error && DC_IS_INTEL(sc)) {
2451 if (sc->dc_pmode != DC_PMODE_SIA)
2452 sc->dc_pmode = DC_PMODE_SYM;
2453 sc->dc_flags |= DC_21143_NWAY;
2455 * For non-MII cards, we need to have the 21143
2456 * drive the LEDs. Except there are some systems
2457 * like the NEC VersaPro NoteBook PC which have no
2458 * LEDs, and twiddling these bits has adverse effects
2459 * on them. (I.e. you suddenly can't get a link.)
2461 if (!(pci_get_subvendor(dev) == 0x1033 &&
2462 pci_get_subdevice(dev) == 0x8028))
2463 sc->dc_flags |= DC_TULIP_LEDS;
2464 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2465 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
2470 device_printf(dev, "attaching PHYs failed\n");
2474 if (DC_IS_ADMTEK(sc)) {
2476 * Set automatic TX underrun recovery for the ADMtek chips
2478 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2482 * Tell the upper layer(s) we support long frames.
2484 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2485 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2486 ifp->if_capenable = ifp->if_capabilities;
2487 #ifdef DEVICE_POLLING
2488 ifp->if_capabilities |= IFCAP_POLLING;
2491 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2492 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2495 * Call MI attach routine.
2497 ether_ifattach(ifp, (caddr_t)eaddr);
2499 /* Hook interrupt last to avoid having to lock softc */
2500 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2501 NULL, dc_intr, sc, &sc->dc_intrhand);
2504 device_printf(dev, "couldn't set up irq\n");
2505 ether_ifdetach(ifp);
2516 * Shutdown hardware and free up resources. This can be called any
2517 * time after the mutex has been initialized. It is called in both
2518 * the error case in attach and the normal detach case so it needs
2519 * to be careful about only freeing resources that have actually been
2523 dc_detach(device_t dev)
2525 struct dc_softc *sc;
2527 struct dc_mediainfo *m;
2529 sc = device_get_softc(dev);
2530 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2534 #ifdef DEVICE_POLLING
2535 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
2536 ether_poll_deregister(ifp);
2539 /* These should only be active if attach succeeded */
2540 if (device_is_attached(dev)) {
2544 callout_drain(&sc->dc_stat_ch);
2545 callout_drain(&sc->dc_wdog_ch);
2546 ether_ifdetach(ifp);
2549 device_delete_child(dev, sc->dc_miibus);
2550 bus_generic_detach(dev);
2552 if (sc->dc_intrhand)
2553 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2555 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2557 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2564 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2566 while (sc->dc_mi != NULL) {
2567 m = sc->dc_mi->dc_next;
2568 free(sc->dc_mi, M_DEVBUF);
2571 free(sc->dc_srom, M_DEVBUF);
2573 mtx_destroy(&sc->dc_mtx);
2579 * Initialize the transmit descriptors.
2582 dc_list_tx_init(struct dc_softc *sc)
2584 struct dc_chain_data *cd;
2585 struct dc_list_data *ld;
2590 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2591 if (i == DC_TX_LIST_CNT - 1)
2595 ld->dc_tx_list[i].dc_status = 0;
2596 ld->dc_tx_list[i].dc_ctl = 0;
2597 ld->dc_tx_list[i].dc_data = 0;
2598 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2599 cd->dc_tx_chain[i] = NULL;
2602 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2604 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
2605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2610 * Initialize the RX descriptors and allocate mbufs for them. Note that
2611 * we arrange the descriptors in a closed ring, so that the last descriptor
2612 * points back to the first.
2615 dc_list_rx_init(struct dc_softc *sc)
2617 struct dc_chain_data *cd;
2618 struct dc_list_data *ld;
2624 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2625 if (dc_newbuf(sc, i) != 0)
2627 if (i == DC_RX_LIST_CNT - 1)
2631 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2635 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2636 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2641 * Initialize an RX descriptor and attach an MBUF cluster.
2644 dc_newbuf(struct dc_softc *sc, int i)
2648 bus_dma_segment_t segs[1];
2651 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2654 m->m_len = m->m_pkthdr.len = MCLBYTES;
2655 m_adj(m, sizeof(u_int64_t));
2658 * If this is a PNIC chip, zero the buffer. This is part
2659 * of the workaround for the receive bug in the 82c168 and
2662 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2663 bzero(mtod(m, char *), m->m_len);
2665 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap,
2671 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__,
2673 if (sc->dc_cdata.dc_rx_chain[i] != NULL)
2674 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]);
2676 map = sc->dc_cdata.dc_rx_map[i];
2677 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2678 sc->dc_sparemap = map;
2679 sc->dc_cdata.dc_rx_chain[i] = m;
2680 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2681 BUS_DMASYNC_PREREAD);
2683 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2684 sc->dc_ldata.dc_rx_list[i].dc_data =
2685 htole32(DC_ADDR_LO(segs[0].ds_addr));
2686 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2687 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2688 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2694 * The PNIC chip has a terrible bug in it that manifests itself during
2695 * periods of heavy activity. The exact mode of failure if difficult to
2696 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2697 * will happen on slow machines. The bug is that sometimes instead of
2698 * uploading one complete frame during reception, it uploads what looks
2699 * like the entire contents of its FIFO memory. The frame we want is at
2700 * the end of the whole mess, but we never know exactly how much data has
2701 * been uploaded, so salvaging the frame is hard.
2703 * There is only one way to do it reliably, and it's disgusting.
2704 * Here's what we know:
2706 * - We know there will always be somewhere between one and three extra
2707 * descriptors uploaded.
2709 * - We know the desired received frame will always be at the end of the
2710 * total data upload.
2712 * - We know the size of the desired received frame because it will be
2713 * provided in the length field of the status word in the last descriptor.
2715 * Here's what we do:
2717 * - When we allocate buffers for the receive ring, we bzero() them.
2718 * This means that we know that the buffer contents should be all
2719 * zeros, except for data uploaded by the chip.
2721 * - We also force the PNIC chip to upload frames that include the
2722 * ethernet CRC at the end.
2724 * - We gather all of the bogus frame data into a single buffer.
2726 * - We then position a pointer at the end of this buffer and scan
2727 * backwards until we encounter the first non-zero byte of data.
2728 * This is the end of the received frame. We know we will encounter
2729 * some data at the end of the frame because the CRC will always be
2730 * there, so even if the sender transmits a packet of all zeros,
2731 * we won't be fooled.
2733 * - We know the size of the actual received frame, so we subtract
2734 * that value from the current pointer location. This brings us
2735 * to the start of the actual received packet.
2737 * - We copy this into an mbuf and pass it on, along with the actual
2740 * The performance hit is tremendous, but it beats dropping frames all
2744 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2746 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2748 struct dc_desc *cur_rx;
2749 struct dc_desc *c = NULL;
2750 struct mbuf *m = NULL;
2753 uint32_t rxstat = 0;
2755 i = sc->dc_pnic_rx_bug_save;
2756 cur_rx = &sc->dc_ldata.dc_rx_list[idx];
2757 ptr = sc->dc_pnic_rx_buf;
2758 bzero(ptr, DC_RXLEN * 5);
2760 /* Copy all the bytes from the bogus buffers. */
2762 c = &sc->dc_ldata.dc_rx_list[i];
2763 rxstat = le32toh(c->dc_status);
2764 m = sc->dc_cdata.dc_rx_chain[i];
2765 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2767 /* If this is the last buffer, break out. */
2768 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2770 dc_discard_rxbuf(sc, i);
2771 DC_INC(i, DC_RX_LIST_CNT);
2774 /* Find the length of the actual receive frame. */
2775 total_len = DC_RXBYTES(rxstat);
2777 /* Scan backwards until we hit a non-zero byte. */
2778 while (*ptr == 0x00)
2782 if ((uintptr_t)(ptr) & 0x3)
2785 /* Now find the start of the frame. */
2787 if (ptr < sc->dc_pnic_rx_buf)
2788 ptr = sc->dc_pnic_rx_buf;
2791 * Now copy the salvaged frame to the last mbuf and fake up
2792 * the status word to make it look like a successful
2795 bcopy(ptr, mtod(m, char *), total_len);
2796 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2800 * This routine searches the RX ring for dirty descriptors in the
2801 * event that the rxeof routine falls out of sync with the chip's
2802 * current descriptor pointer. This may happen sometimes as a result
2803 * of a "no RX buffer available" condition that happens when the chip
2804 * consumes all of the RX buffers before the driver has a chance to
2805 * process the RX ring. This routine may need to be called more than
2806 * once to bring the driver back in sync with the chip, however we
2807 * should still be getting RX DONE interrupts to drive the search
2808 * for new packets in the RX ring, so we should catch up eventually.
2811 dc_rx_resync(struct dc_softc *sc)
2813 struct dc_desc *cur_rx;
2816 pos = sc->dc_cdata.dc_rx_prod;
2818 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2819 cur_rx = &sc->dc_ldata.dc_rx_list[pos];
2820 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2822 DC_INC(pos, DC_RX_LIST_CNT);
2825 /* If the ring really is empty, then just return. */
2826 if (i == DC_RX_LIST_CNT)
2829 /* We've fallen behing the chip: catch it. */
2830 sc->dc_cdata.dc_rx_prod = pos;
2836 dc_discard_rxbuf(struct dc_softc *sc, int i)
2840 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2841 m = sc->dc_cdata.dc_rx_chain[i];
2842 bzero(mtod(m, char *), m->m_len);
2845 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2846 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2847 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD |
2848 BUS_DMASYNC_PREWRITE);
2852 * A frame has been uploaded: pass the resulting mbuf chain up to
2853 * the higher level protocols.
2856 dc_rxeof(struct dc_softc *sc)
2860 struct dc_desc *cur_rx;
2861 int i, total_len, rx_npkts;
2869 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD |
2870 BUS_DMASYNC_POSTWRITE);
2871 for (i = sc->dc_cdata.dc_rx_prod;
2872 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
2873 DC_INC(i, DC_RX_LIST_CNT)) {
2874 #ifdef DEVICE_POLLING
2875 if (ifp->if_capenable & IFCAP_POLLING) {
2876 if (sc->rxcycles <= 0)
2881 cur_rx = &sc->dc_ldata.dc_rx_list[i];
2882 rxstat = le32toh(cur_rx->dc_status);
2883 if ((rxstat & DC_RXSTAT_OWN) != 0)
2885 m = sc->dc_cdata.dc_rx_chain[i];
2886 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2887 BUS_DMASYNC_POSTREAD);
2888 total_len = DC_RXBYTES(rxstat);
2891 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2892 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2893 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2894 sc->dc_pnic_rx_bug_save = i;
2895 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0)
2897 dc_pnic_rx_bug_war(sc, i);
2898 rxstat = le32toh(cur_rx->dc_status);
2899 total_len = DC_RXBYTES(rxstat);
2904 * If an error occurs, update stats, clear the
2905 * status word and leave the mbuf cluster in place:
2906 * it should simply get re-used next time this descriptor
2907 * comes up in the ring. However, don't report long
2908 * frames as errors since they could be vlans.
2910 if ((rxstat & DC_RXSTAT_RXERR)) {
2911 if (!(rxstat & DC_RXSTAT_GIANT) ||
2912 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2913 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2914 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2915 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2916 if (rxstat & DC_RXSTAT_COLLSEEN)
2917 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
2918 dc_discard_rxbuf(sc, i);
2919 if (rxstat & DC_RXSTAT_CRCERR)
2922 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2929 /* No errors; receive the packet. */
2930 total_len -= ETHER_CRC_LEN;
2931 #ifdef __NO_STRICT_ALIGNMENT
2933 * On architectures without alignment problems we try to
2934 * allocate a new buffer for the receive ring, and pass up
2935 * the one where the packet is already, saving the expensive
2936 * copy done in m_devget().
2937 * If we are on an architecture with alignment problems, or
2938 * if the allocation fails, then use m_devget and leave the
2939 * existing buffer in the receive ring.
2941 if (dc_newbuf(sc, i) != 0) {
2942 dc_discard_rxbuf(sc, i);
2943 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2946 m->m_pkthdr.rcvif = ifp;
2947 m->m_pkthdr.len = m->m_len = total_len;
2952 m0 = m_devget(mtod(m, char *), total_len,
2953 ETHER_ALIGN, ifp, NULL);
2954 dc_discard_rxbuf(sc, i);
2956 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2963 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2965 (*ifp->if_input)(ifp, m);
2969 sc->dc_cdata.dc_rx_prod = i;
2974 * A frame was downloaded to the chip. It's safe for us to clean up
2978 dc_txeof(struct dc_softc *sc)
2980 struct dc_desc *cur_tx;
2983 uint32_t ctl, txstat;
2985 if (sc->dc_cdata.dc_tx_cnt == 0)
2991 * Go through our tx list and free mbufs for those
2992 * frames that have been transmitted.
2994 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD |
2995 BUS_DMASYNC_POSTWRITE);
2997 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod;
2998 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) {
2999 cur_tx = &sc->dc_ldata.dc_tx_list[idx];
3000 txstat = le32toh(cur_tx->dc_status);
3001 ctl = le32toh(cur_tx->dc_ctl);
3003 if (txstat & DC_TXSTAT_OWN)
3006 if (sc->dc_cdata.dc_tx_chain[idx] == NULL)
3009 if (ctl & DC_TXCTL_SETUP) {
3010 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP);
3012 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
3013 BUS_DMASYNC_POSTWRITE);
3015 * Yes, the PNIC is so brain damaged
3016 * that it will sometimes generate a TX
3017 * underrun error while DMAing the RX
3018 * filter setup frame. If we detect this,
3019 * we have to send the setup frame again,
3020 * or else the filter won't be programmed
3023 if (DC_IS_PNIC(sc)) {
3024 if (txstat & DC_TXSTAT_ERRSUM)
3027 sc->dc_cdata.dc_tx_chain[idx] = NULL;
3031 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
3033 * XXX: Why does my Xircom taunt me so?
3034 * For some reason it likes setting the CARRLOST flag
3035 * even when the carrier is there. wtf?!?
3036 * Who knows, but Conexant chips have the
3037 * same problem. Maybe they took lessons
3040 if (/*sc->dc_type == DC_TYPE_21143 &&*/
3041 sc->dc_pmode == DC_PMODE_MII &&
3042 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3043 DC_TXSTAT_NOCARRIER)))
3044 txstat &= ~DC_TXSTAT_ERRSUM;
3046 if (/*sc->dc_type == DC_TYPE_21143 &&*/
3047 sc->dc_pmode == DC_PMODE_MII &&
3048 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3049 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
3050 txstat &= ~DC_TXSTAT_ERRSUM;
3053 if (txstat & DC_TXSTAT_ERRSUM) {
3054 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3055 if (txstat & DC_TXSTAT_EXCESSCOLL)
3056 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
3057 if (txstat & DC_TXSTAT_LATECOLL)
3058 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
3059 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
3060 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3065 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3066 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & DC_TXSTAT_COLLCNT) >> 3);
3068 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3069 BUS_DMASYNC_POSTWRITE);
3070 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3071 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
3072 sc->dc_cdata.dc_tx_chain[idx] = NULL;
3074 sc->dc_cdata.dc_tx_cons = idx;
3076 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3077 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3078 if (sc->dc_cdata.dc_tx_cnt == 0)
3079 sc->dc_wdog_timer = 0;
3082 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3083 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3089 struct dc_softc *sc;
3090 struct mii_data *mii;
3097 mii = device_get_softc(sc->dc_miibus);
3100 * Reclaim transmitted frames for controllers that do
3101 * not generate TX completion interrupt for every frame.
3103 if (sc->dc_flags & DC_TX_USE_TX_INTR)
3106 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
3107 if (sc->dc_flags & DC_21143_NWAY) {
3108 r = CSR_READ_4(sc, DC_10BTSTAT);
3109 if (IFM_SUBTYPE(mii->mii_media_active) ==
3110 IFM_100_TX && (r & DC_TSTAT_LS100)) {
3114 if (IFM_SUBTYPE(mii->mii_media_active) ==
3115 IFM_10_T && (r & DC_TSTAT_LS10)) {
3119 if (sc->dc_link == 0)
3123 * For NICs which never report DC_RXSTATE_WAIT, we
3124 * have to bite the bullet...
3126 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
3127 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
3128 sc->dc_cdata.dc_tx_cnt == 0)
3135 * When the init routine completes, we expect to be able to send
3136 * packets right away, and in fact the network code will send a
3137 * gratuitous ARP the moment the init routine marks the interface
3138 * as running. However, even though the MAC may have been initialized,
3139 * there may be a delay of a few seconds before the PHY completes
3140 * autonegotiation and the link is brought up. Any transmissions
3141 * made during that delay will be lost. Dealing with this is tricky:
3142 * we can't just pause in the init routine while waiting for the
3143 * PHY to come ready since that would bring the whole system to
3144 * a screeching halt for several seconds.
3146 * What we do here is prevent the TX start routine from sending
3147 * any packets until a link has been established. After the
3148 * interface has been initialized, the tick routine will poll
3149 * the state of the PHY until the IFM_ACTIVE flag is set. Until
3150 * that time, packets will stay in the send queue, and once the
3151 * link comes up, they will be flushed out to the wire.
3153 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3154 dc_start_locked(ifp);
3156 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3157 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3159 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3163 * A transmit underrun has occurred. Back off the transmit threshold,
3164 * or switch to store and forward mode if we have to.
3167 dc_tx_underrun(struct dc_softc *sc)
3169 uint32_t netcfg, isr;
3173 netcfg = CSR_READ_4(sc, DC_NETCFG);
3174 device_printf(sc->dc_dev, "TX underrun -- ");
3175 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) {
3176 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) {
3177 printf("using store and forward mode\n");
3178 netcfg |= DC_NETCFG_STORENFWD;
3180 printf("increasing TX threshold\n");
3181 sc->dc_txthresh += DC_TXTHRESH_INC;
3182 netcfg &= ~DC_NETCFG_TX_THRESH;
3183 netcfg |= sc->dc_txthresh;
3186 if (DC_IS_INTEL(sc)) {
3188 * The real 21143 requires that the transmitter be idle
3189 * in order to change the transmit threshold or store
3190 * and forward state.
3192 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON);
3194 for (i = 0; i < DC_TIMEOUT; i++) {
3195 isr = CSR_READ_4(sc, DC_ISR);
3196 if (isr & DC_ISR_TX_IDLE)
3200 if (i == DC_TIMEOUT) {
3201 device_printf(sc->dc_dev,
3202 "%s: failed to force tx to idle state\n",
3208 printf("resetting\n");
3213 CSR_WRITE_4(sc, DC_NETCFG, netcfg);
3214 if (DC_IS_INTEL(sc))
3215 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON);
3217 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3222 #ifdef DEVICE_POLLING
3223 static poll_handler_t dc_poll;
3226 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3228 struct dc_softc *sc = ifp->if_softc;
3233 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3238 sc->rxcycles = count;
3239 rx_npkts = dc_rxeof(sc);
3241 if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3242 !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3243 dc_start_locked(ifp);
3245 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3248 status = CSR_READ_4(sc, DC_ISR);
3249 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3250 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3256 /* ack what we have */
3257 CSR_WRITE_4(sc, DC_ISR, status);
3259 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3260 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3261 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff));
3263 if (dc_rx_resync(sc))
3266 /* restart transmit unit if necessary */
3267 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3268 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3270 if (status & DC_ISR_TX_UNDERRUN)
3273 if (status & DC_ISR_BUS_ERR) {
3274 if_printf(ifp, "%s: bus error\n", __func__);
3275 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3282 #endif /* DEVICE_POLLING */
3287 struct dc_softc *sc;
3298 status = CSR_READ_4(sc, DC_ISR);
3299 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) {
3304 #ifdef DEVICE_POLLING
3305 if (ifp->if_capenable & IFCAP_POLLING) {
3310 /* Disable interrupts. */
3311 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3313 for (n = 16; n > 0; n--) {
3314 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3316 /* Ack interrupts. */
3317 CSR_WRITE_4(sc, DC_ISR, status);
3319 if (status & DC_ISR_RX_OK) {
3320 if (dc_rxeof(sc) == 0) {
3321 while (dc_rx_resync(sc))
3326 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3329 if (status & DC_ISR_TX_IDLE) {
3331 if (sc->dc_cdata.dc_tx_cnt) {
3332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3333 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3337 if (status & DC_ISR_TX_UNDERRUN)
3340 if ((status & DC_ISR_RX_WATDOGTIMEO)
3341 || (status & DC_ISR_RX_NOBUF)) {
3342 r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3343 if_inc_counter(ifp, IFCOUNTER_IERRORS, (r & 0xffff) + ((r >> 17) & 0x7ff));
3344 if (dc_rxeof(sc) == 0) {
3345 while (dc_rx_resync(sc))
3350 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3351 dc_start_locked(ifp);
3353 if (status & DC_ISR_BUS_ERR) {
3354 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3359 status = CSR_READ_4(sc, DC_ISR);
3360 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0)
3364 /* Re-enable interrupts. */
3365 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3366 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3372 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3373 * pointers to the fragment pointers.
3376 dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3378 bus_dma_segment_t segs[DC_MAXFRAGS];
3382 int cur, defragged, error, first, frag, i, idx, nseg;
3386 if (sc->dc_flags & DC_TX_COALESCE &&
3387 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3388 m = m_defrag(*m_head, M_NOWAIT);
3392 * Count the number of frags in this chain to see if we
3393 * need to m_collapse. Since the descriptor list is shared
3394 * by all packets, we'll m_collapse long chains so that they
3395 * do not use up the entire list, even if they would fit.
3398 for (m = *m_head; m != NULL; m = m->m_next)
3400 if (i > DC_TX_LIST_CNT / 4 ||
3401 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3403 m = m_collapse(*m_head, M_NOWAIT, DC_MAXFRAGS);
3407 if (defragged != 0) {
3416 idx = sc->dc_cdata.dc_tx_prod;
3417 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3418 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3419 if (error == EFBIG) {
3420 if (defragged != 0 || (m = m_collapse(*m_head, M_NOWAIT,
3421 DC_MAXFRAGS)) == NULL) {
3424 return (defragged != 0 ? error : ENOBUFS);
3427 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3428 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3434 } else if (error != 0)
3436 KASSERT(nseg <= DC_MAXFRAGS,
3437 ("%s: wrong number of segments (%d)", __func__, nseg));
3444 /* Check descriptor overruns. */
3445 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3446 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3449 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3450 BUS_DMASYNC_PREWRITE);
3452 first = cur = frag = sc->dc_cdata.dc_tx_prod;
3453 for (i = 0; i < nseg; i++) {
3454 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3455 (frag == (DC_TX_LIST_CNT - 1)) &&
3456 (first != sc->dc_cdata.dc_tx_first)) {
3457 bus_dmamap_unload(sc->dc_tx_mtag,
3458 sc->dc_cdata.dc_tx_map[first]);
3464 f = &sc->dc_ldata.dc_tx_list[frag];
3465 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3468 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3470 f->dc_status = htole32(DC_TXSTAT_OWN);
3471 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr));
3473 DC_INC(frag, DC_TX_LIST_CNT);
3476 sc->dc_cdata.dc_tx_prod = frag;
3477 sc->dc_cdata.dc_tx_cnt += nseg;
3478 sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3479 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3480 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3481 sc->dc_ldata.dc_tx_list[first].dc_ctl |=
3482 htole32(DC_TXCTL_FINT);
3483 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3484 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3485 if (sc->dc_flags & DC_TX_USE_TX_INTR &&
3486 ++sc->dc_cdata.dc_tx_pkts >= 8) {
3487 sc->dc_cdata.dc_tx_pkts = 0;
3488 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3490 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3492 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3496 * Swap the last and the first dmamaps to ensure the map for
3497 * this transmission is placed at the last descriptor.
3499 map = sc->dc_cdata.dc_tx_map[cur];
3500 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first];
3501 sc->dc_cdata.dc_tx_map[first] = map;
3507 dc_start(struct ifnet *ifp)
3509 struct dc_softc *sc;
3513 dc_start_locked(ifp);
3518 * Main transmit routine
3519 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3520 * regions directly in the transmit lists. We also save a copy of the
3521 * pointers since the transmit list fragment pointers are physical
3525 dc_start_locked(struct ifnet *ifp)
3527 struct dc_softc *sc;
3528 struct mbuf *m_head;
3535 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
3536 IFF_DRV_RUNNING || sc->dc_link == 0)
3539 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3541 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
3543 * If there's no way we can send any packets, return now.
3545 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3546 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3549 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3553 if (dc_encap(sc, &m_head)) {
3556 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3557 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3563 * If there's a BPF listener, bounce a copy of this frame
3566 BPF_MTAP(ifp, m_head);
3571 if (!(sc->dc_flags & DC_TX_POLL))
3572 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3575 * Set a timeout in case the chip goes out to lunch.
3577 sc->dc_wdog_timer = 5;
3584 struct dc_softc *sc = xsc;
3592 dc_init_locked(struct dc_softc *sc)
3594 struct ifnet *ifp = sc->dc_ifp;
3595 struct mii_data *mii;
3596 struct ifmedia *ifm;
3600 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3603 mii = device_get_softc(sc->dc_miibus);
3606 * Cancel pending I/O and free all RX/TX buffers.
3610 if (DC_IS_INTEL(sc)) {
3611 ifm = &mii->mii_media;
3612 dc_apply_fixup(sc, ifm->ifm_media);
3616 * Set cache alignment and burst length.
3618 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc))
3619 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3621 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3623 * Evenly share the bus between receive and transmit process.
3625 if (DC_IS_INTEL(sc))
3626 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3627 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3628 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3630 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3632 if (sc->dc_flags & DC_TX_POLL)
3633 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3634 switch(sc->dc_cachesize) {
3636 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3639 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3642 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3646 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3650 if (sc->dc_flags & DC_TX_STORENFWD)
3651 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3653 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3654 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3656 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3657 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3661 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3662 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3664 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3666 * The app notes for the 98713 and 98715A say that
3667 * in order to have the chips operate properly, a magic
3668 * number must be written to CSR16. Macronix does not
3669 * document the meaning of these bits so there's no way
3670 * to know exactly what they do. The 98713 has a magic
3671 * number all its own; the rest all use a different one.
3673 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3674 if (sc->dc_type == DC_TYPE_98713)
3675 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3677 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3680 if (DC_IS_XIRCOM(sc)) {
3682 * setup General Purpose Port mode and data so the tulip
3683 * can talk to the MII.
3685 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3686 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3688 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3689 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3693 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3694 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3696 /* Init circular RX list. */
3697 if (dc_list_rx_init(sc) == ENOBUFS) {
3698 device_printf(sc->dc_dev,
3699 "initialization failed: no memory for rx buffers\n");
3705 * Init TX descriptors.
3707 dc_list_tx_init(sc);
3710 * Load the address of the RX list.
3712 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3713 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3716 * Enable interrupts.
3718 #ifdef DEVICE_POLLING
3720 * ... but only if we are not polling, and make sure they are off in
3721 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3724 if (ifp->if_capenable & IFCAP_POLLING)
3725 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3728 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3729 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3731 /* Initialize TX jabber and RX watchdog timer. */
3733 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK |
3736 /* Enable transmitter. */
3737 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3740 * If this is an Intel 21143 and we're not using the
3741 * MII port, program the LED control pins so we get
3742 * link and activity indications.
3744 if (sc->dc_flags & DC_TULIP_LEDS) {
3745 CSR_WRITE_4(sc, DC_WATCHDOG,
3746 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3747 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3751 * Load the RX/multicast filter. We do this sort of late
3752 * because the filter programming scheme on the 21143 and
3753 * some clones requires DMAing a setup frame via the TX
3754 * engine, and we need the transmitter enabled for that.
3758 /* Enable receiver. */
3759 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3760 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3762 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3763 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3765 dc_ifmedia_upd_locked(sc);
3767 /* Clear missed frames and overflow counter. */
3768 CSR_READ_4(sc, DC_FRAMESDISCARDED);
3770 /* Don't start the ticker if this is a homePNA link. */
3771 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3774 if (sc->dc_flags & DC_21143_NWAY)
3775 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3777 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3780 sc->dc_wdog_timer = 0;
3781 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3785 * Set media options.
3788 dc_ifmedia_upd(struct ifnet *ifp)
3790 struct dc_softc *sc;
3795 error = dc_ifmedia_upd_locked(sc);
3801 dc_ifmedia_upd_locked(struct dc_softc *sc)
3803 struct mii_data *mii;
3804 struct ifmedia *ifm;
3810 mii = device_get_softc(sc->dc_miibus);
3811 error = mii_mediachg(mii);
3813 ifm = &mii->mii_media;
3814 if (DC_IS_INTEL(sc))
3815 dc_setcfg(sc, ifm->ifm_media);
3816 else if (DC_IS_DAVICOM(sc) &&
3817 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3818 dc_setcfg(sc, ifm->ifm_media);
3825 * Report current media status.
3828 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3830 struct dc_softc *sc;
3831 struct mii_data *mii;
3832 struct ifmedia *ifm;
3835 mii = device_get_softc(sc->dc_miibus);
3838 ifm = &mii->mii_media;
3839 if (DC_IS_DAVICOM(sc)) {
3840 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3841 ifmr->ifm_active = ifm->ifm_media;
3842 ifmr->ifm_status = 0;
3847 ifmr->ifm_active = mii->mii_media_active;
3848 ifmr->ifm_status = mii->mii_media_status;
3853 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3855 struct dc_softc *sc = ifp->if_softc;
3856 struct ifreq *ifr = (struct ifreq *)data;
3857 struct mii_data *mii;
3863 if (ifp->if_flags & IFF_UP) {
3864 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3865 (IFF_PROMISC | IFF_ALLMULTI);
3867 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3871 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3875 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3878 sc->dc_if_flags = ifp->if_flags;
3884 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3890 mii = device_get_softc(sc->dc_miibus);
3891 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3894 #ifdef DEVICE_POLLING
3895 if (ifr->ifr_reqcap & IFCAP_POLLING &&
3896 !(ifp->if_capenable & IFCAP_POLLING)) {
3897 error = ether_poll_register(dc_poll, ifp);
3901 /* Disable interrupts */
3902 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3903 ifp->if_capenable |= IFCAP_POLLING;
3907 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
3908 ifp->if_capenable & IFCAP_POLLING) {
3909 error = ether_poll_deregister(ifp);
3910 /* Enable interrupts. */
3912 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3913 ifp->if_capenable &= ~IFCAP_POLLING;
3917 #endif /* DEVICE_POLLING */
3920 error = ether_ioctl(ifp, command, data);
3928 dc_watchdog(void *xsc)
3930 struct dc_softc *sc = xsc;
3935 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
3936 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3941 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3942 device_printf(sc->dc_dev, "watchdog timeout\n");
3944 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3947 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3948 dc_start_locked(ifp);
3952 * Stop the adapter and free any mbufs allocated to the
3956 dc_stop(struct dc_softc *sc)
3959 struct dc_list_data *ld;
3960 struct dc_chain_data *cd;
3962 uint32_t ctl, netcfg;
3970 callout_stop(&sc->dc_stat_ch);
3971 callout_stop(&sc->dc_wdog_ch);
3972 sc->dc_wdog_timer = 0;
3975 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3977 netcfg = CSR_READ_4(sc, DC_NETCFG);
3978 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3979 CSR_WRITE_4(sc, DC_NETCFG,
3980 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
3981 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3982 /* Wait the completion of TX/RX SM. */
3983 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
3986 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3987 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3990 * Free data in the RX lists.
3992 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3993 if (cd->dc_rx_chain[i] != NULL) {
3994 bus_dmamap_sync(sc->dc_rx_mtag,
3995 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD);
3996 bus_dmamap_unload(sc->dc_rx_mtag,
3998 m_freem(cd->dc_rx_chain[i]);
3999 cd->dc_rx_chain[i] = NULL;
4002 bzero(ld->dc_rx_list, DC_RX_LIST_SZ);
4003 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
4004 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4007 * Free the TX list buffers.
4009 for (i = 0; i < DC_TX_LIST_CNT; i++) {
4010 if (cd->dc_tx_chain[i] != NULL) {
4011 ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
4012 if (ctl & DC_TXCTL_SETUP) {
4013 bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
4014 BUS_DMASYNC_POSTWRITE);
4016 bus_dmamap_sync(sc->dc_tx_mtag,
4017 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE);
4018 bus_dmamap_unload(sc->dc_tx_mtag,
4020 m_freem(cd->dc_tx_chain[i]);
4022 cd->dc_tx_chain[i] = NULL;
4025 bzero(ld->dc_tx_list, DC_TX_LIST_SZ);
4026 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
4027 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4031 * Device suspend routine. Stop the interface and save some PCI
4032 * settings in case the BIOS doesn't restore them properly on
4036 dc_suspend(device_t dev)
4038 struct dc_softc *sc;
4040 sc = device_get_softc(dev);
4050 * Device resume routine. Restore some PCI settings in case the BIOS
4051 * doesn't, re-enable busmastering, and restart the interface if
4055 dc_resume(device_t dev)
4057 struct dc_softc *sc;
4060 sc = device_get_softc(dev);
4063 /* reinitialize interface if necessary */
4065 if (ifp->if_flags & IFF_UP)
4075 * Stop all chip I/O so that the kernel's probe routines don't
4076 * get confused by errant DMAs when rebooting.
4079 dc_shutdown(device_t dev)
4081 struct dc_softc *sc;
4083 sc = device_get_softc(dev);
4093 dc_check_multiport(struct dc_softc *sc)
4095 struct dc_softc *dsc;
4101 dc = devclass_find("dc");
4102 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {
4103 child = devclass_get_device(dc, unit);
4106 if (child == sc->dc_dev)
4108 if (device_get_parent(child) != device_get_parent(sc->dc_dev))
4110 if (unit > device_get_unit(sc->dc_dev))
4112 if (device_is_attached(child) == 0)
4114 dsc = device_get_softc(child);
4115 device_printf(sc->dc_dev,
4116 "Using station address of %s as base\n",
4117 device_get_nameunit(child));
4118 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN);
4119 eaddr = (uint8_t *)sc->dc_eaddr;
4121 /* Prepare SROM to parse again. */
4122 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL &&
4123 sc->dc_romwidth != 0) {
4124 free(sc->dc_srom, M_DEVBUF);
4125 sc->dc_romwidth = dsc->dc_romwidth;
4126 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth),
4127 M_DEVBUF, M_NOWAIT);
4128 if (sc->dc_srom == NULL) {
4129 device_printf(sc->dc_dev,
4130 "Could not allocate SROM buffer\n");
4133 bcopy(dsc->dc_srom, sc->dc_srom,
4134 DC_ROM_SIZE(sc->dc_romwidth));