1 /* $NetBSD: dc21040reg.h,v 1.15 1998/05/22 18:50:59 matt Exp $ */
6 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
8 * Copyright (c) 1994, 1995, 1996 Matt Thomas <matt@3am-software.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Id: dc21040reg.h,v 1.24 1997/05/16 19:47:09 thomas Exp
33 #if !defined(_DC21040_H)
36 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
37 #define TULIP_BITFIELD2(a, b) b, a
38 #define TULIP_BITFIELD3(a, b, c) c, b, a
39 #define TULIP_BITFIELD4(a, b, c, d) d, c, b, a
41 #define TULIP_BITFIELD2(a, b) a, b
42 #define TULIP_BITFIELD3(a, b, c) a, b, c
43 #define TULIP_BITFIELD4(a, b, c, d) a, b, c, d
48 u_int32_t TULIP_BITFIELD3(d_length1 : 11,
55 #define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */
56 #define TULIP_DSTS_ERRSUM 0x00008000 /* Error Summary */
60 #define TULIP_DSTS_TxBABBLE 0x00004000 /* Transmitter Babbled */
61 #define TULIP_DSTS_TxCARRLOSS 0x00000800 /* Carrier Loss */
62 #define TULIP_DSTS_TxNOCARR 0x00000400 /* No Carrier */
63 #define TULIP_DSTS_TxLATECOLL 0x00000200 /* Late Collision */
64 #define TULIP_DSTS_TxEXCCOLL 0x00000100 /* Excessive Collisions */
65 #define TULIP_DSTS_TxNOHRTBT 0x00000080 /* No Heartbeat */
66 #define TULIP_DSTS_TxCOLLMASK 0x00000078 /* Collision Count (mask) */
67 #define TULIP_DSTS_V_TxCOLLCNT 0x00000003 /* Collision Count (bit) */
68 #define TULIP_DSTS_TxLINKFAIL 0x00000004 /* Link Failure */
69 #define TULIP_DSTS_TxUNDERFLOW 0x00000002 /* Underflow Error */
70 #define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */
74 #define TULIP_DSTS_RxBADLENGTH 0x00004000 /* Length Error */
75 #define TULIP_DSTS_RxDATATYPE 0x00003000 /* Data Type */
76 #define TULIP_DSTS_RxRUNT 0x00000800 /* Runt Frame */
77 #define TULIP_DSTS_RxMULTICAST 0x00000400 /* Multicast Frame */
78 #define TULIP_DSTS_RxFIRSTDESC 0x00000200 /* First Descriptor */
79 #define TULIP_DSTS_RxLASTDESC 0x00000100 /* Last Descriptor */
80 #define TULIP_DSTS_RxTOOLONG 0x00000080 /* Frame Too Long */
81 #define TULIP_DSTS_RxCOLLSEEN 0x00000040 /* Collision Seen */
82 #define TULIP_DSTS_RxFRAMETYPE 0x00000020 /* Frame Type */
83 #define TULIP_DSTS_RxWATCHDOG 0x00000010 /* Receive Watchdog */
84 #define TULIP_DSTS_RxDRBBLBIT 0x00000004 /* Dribble Bit */
85 #define TULIP_DSTS_RxBADCRC 0x00000002 /* CRC Error */
86 #define TULIP_DSTS_RxOVERFLOW 0x00000001 /* Overflow */
89 #define TULIP_DFLAG_ENDRING 0x0008 /* End of Transmit Ring */
90 #define TULIP_DFLAG_CHAIN 0x0004 /* Chain using d_addr2 */
92 #define TULIP_DFLAG_TxWANTINTR 0x0200 /* Signal Interrupt on Completion */
93 #define TULIP_DFLAG_TxLASTSEG 0x0100 /* Last Segment */
94 #define TULIP_DFLAG_TxFIRSTSEG 0x0080 /* First Segment */
95 #define TULIP_DFLAG_TxINVRSFILT 0x0040 /* Inverse Filtering */
96 #define TULIP_DFLAG_TxSETUPPKT 0x0020 /* Setup Packet */
97 #define TULIP_DFLAG_TxHASCRC 0x0010 /* Don't Append the CRC */
98 #define TULIP_DFLAG_TxNOPADDING 0x0002 /* Don't AutoPad */
99 #define TULIP_DFLAG_TxHASHFILT 0x0001 /* Hash/Perfect Filtering */
102 * The 21040 Registers (IO Space Addresses)
104 #define TULIP_REG_BUSMODE 0x00 /* CSR0 -- Bus Mode */
105 #define TULIP_REG_TXPOLL 0x08 /* CSR1 -- Transmit Poll Demand */
106 #define TULIP_REG_RXPOLL 0x10 /* CSR2 -- Receive Poll Demand */
107 #define TULIP_REG_RXLIST 0x18 /* CSR3 -- Receive List Base Addr */
108 #define TULIP_REG_TXLIST 0x20 /* CSR4 -- Transmit List Base Addr */
109 #define TULIP_REG_STATUS 0x28 /* CSR5 -- Status */
110 #define TULIP_REG_CMD 0x30 /* CSR6 -- Command */
111 #define TULIP_REG_INTR 0x38 /* CSR7 -- Interrupt Control */
112 #define TULIP_REG_MISSES 0x40 /* CSR8 -- Missed Frame Counter */
113 #define TULIP_REG_ADDRROM 0x48 /* CSR9 -- ENET ROM Register */
114 #define TULIP_REG_RSRVD 0x50 /* CSR10 -- Reserved */
115 #define TULIP_REG_FULL_DUPLEX 0x58 /* CSR11 -- Full Duplex */
116 #define TULIP_REG_SIA_STATUS 0x60 /* CSR12 -- SIA Status */
117 #define TULIP_REG_SIA_CONN 0x68 /* CSR13 -- SIA Connectivity */
118 #define TULIP_REG_SIA_TXRX 0x70 /* CSR14 -- SIA Tx Rx */
119 #define TULIP_REG_SIA_GEN 0x78 /* CSR15 -- SIA General */
122 * CSR5 -- Status Register
123 * CSR7 -- Interrupt Control
125 #define TULIP_STS_ERRORMASK 0x03800000L /* ( R) Error Bits (Valid when SYSERROR is set) */
126 #define TULIP_STS_ERR_PARITY 0x00000000L /* 000 - Parity Error (Perform Reset) */
127 #define TULIP_STS_ERR_MASTER 0x00800000L /* 001 - Master Abort */
128 #define TULIP_STS_ERR_TARGET 0x01000000L /* 010 - Target Abort */
129 #define TULIP_STS_ERR_SHIFT 23
130 #define TULIP_STS_TXSTATEMASK 0x00700000L /* ( R) Transmission Process State */
131 #define TULIP_STS_TXS_RESET 0x00000000L /* 000 - Rset or transmit jabber expired */
132 #define TULIP_STS_TXS_FETCH 0x00100000L /* 001 - Fetching transmit descriptor */
133 #define TULIP_STS_TXS_WAITEND 0x00200000L /* 010 - Wait for end of transmission */
134 #define TULIP_STS_TXS_READING 0x00300000L /* 011 - Read buffer and enqueue data */
135 #define TULIP_STS_TXS_RSRVD 0x00400000L /* 100 - Reserved */
136 #define TULIP_STS_TXS_SETUP 0x00500000L /* 101 - Setup Packet */
137 #define TULIP_STS_TXS_SUSPEND 0x00600000L /* 110 - Transmit FIFO underflow or an
138 unavailable transmit descriptor */
139 #define TULIP_STS_TXS_CLOSE 0x00700000L /* 111 - Close transmit descriptor */
140 #define TULIP_STS_RXSTATEMASK 0x000E0000L /* ( R) Receive Process State*/
141 #define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */
142 #define TULIP_STS_RXS_FETCH 0x00020000L /* 001 - Running -- Fetch receive descriptor */
143 #define TULIP_STS_RXS_ENDCHECK 0x00040000L /* 010 - Running -- Check for end of receive
144 packet before prefetch of next descriptor */
145 #define TULIP_STS_RXS_WAIT 0x00060000L /* 011 - Running -- Wait for receive packet */
146 #define TULIP_STS_RXS_SUSPEND 0x00080000L /* 100 - Suspended -- As a result of
147 unavailable receive buffers */
148 #define TULIP_STS_RXS_CLOSE 0x000A0000L /* 101 - Running -- Close receive descriptor */
149 #define TULIP_STS_RXS_FLUSH 0x000C0000L /* 110 - Running -- Flush the current frame
150 from the receive FIFO as a result of
151 an unavailable receive buffer */
152 #define TULIP_STS_RXS_DEQUEUE 0x000E0000L /* 111 - Running -- Dequeue the receive frame
153 from the receive FIFO into the receive
155 #define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */
156 #define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */
157 #define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */
158 #define TULIP_STS_LINKFAIL 0x00001000L /* (RW) Link Failure (21040) */
159 #define TULIP_STS_FULDPLXSHRT 0x00000800L /* (RW) Full Duplex Short Fram Rcvd (21040) */
160 #define TULIP_STS_GPTIMEOUT 0x00000800L /* (RW) General Purpose Timeout (21140) */
161 #define TULIP_STS_AUI 0x00000400L /* (RW) AUI/TP Switch (21040) */
162 #define TULIP_STS_RXTIMEOUT 0x00000200L /* (RW) Receive Watchbog Timeout */
163 #define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */
164 #define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buffer Unavailable */
165 #define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */
166 #define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */
167 #define TULIP_STS_LINKPASS 0x00000010L /* (RW) LinkPass (21041) */
168 #define TULIP_STS_TXBABBLE 0x00000008L /* (RW) Transmit Jabber Timeout */
169 #define TULIP_STS_TXNOBUF 0x00000004L /* (RW) Transmit Buffer Unavailable */
170 #define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */
171 #define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */
174 * CSR6 -- Command (Operation Mode) Register
176 #define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */
177 #define TULIP_CMD_SCRAMBLER 0x01000000L /* (RW) Scrambler Mode (21140) */
178 #define TULIP_CMD_PCSFUNCTION 0x00800000L /* (RW) PCS Function (21140) */
179 #define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */
180 #define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Forward (21140) */
181 #define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */
182 #define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */
183 #define TULIP_CMD_ENHCAPTEFFCT 0x00040000L /* (RW) Enhanced Capture Effecty (21041) */
184 #define TULIP_CMD_CAPTREFFCT 0x00020000L /* (RW) Capture Effect (!802.3) */
185 #define TULIP_CMD_BACKPRESSURE 0x00010000L /* (RW) Back Pressure (!802.3) (21040) */
186 #define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */
187 #define TULIP_CMD_THRSHLD72 0x00000000L /* 00 - 72 Bytes */
188 #define TULIP_CMD_THRSHLD96 0x00004000L /* 01 - 96 Bytes */
189 #define TULIP_CMD_THRSHLD128 0x00008000L /* 10 - 128 bytes */
190 #define TULIP_CMD_THRSHLD160 0x0000C000L /* 11 - 160 Bytes */
191 #define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */
192 #define TULIP_CMD_FORCECOLL 0x00001000L /* (RW) Force Collisions */
193 #define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */
194 #define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */
195 #define TULIP_CMD_FLAKYOSCDIS 0x00000100L /* (RW) Flakey Oscillator Disable */
196 #define TULIP_CMD_ALLMULTI 0x00000080L /* (RW) Pass All Multicasts */
197 #define TULIP_CMD_PROMISCUOUS 0x00000040L /* (RW) Promiscuous Mode */
198 #define TULIP_CMD_BACKOFFCTR 0x00000020L /* (RW) Start/Stop Backoff Counter (!802.3) */
199 #define TULIP_CMD_INVFILTER 0x00000010L /* (R ) Inverse Filtering */
200 #define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */
201 #define TULIP_CMD_HASHONLYFLTR 0x00000004L /* (R ) Hash Only Filtering */
202 #define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */
203 #define TULIP_CMD_HASHPRFCTFLTR 0x00000001L /* (R ) Hash/Perfect Receive Filtering */
205 #define TULIP_SIASTS_OTHERRXACTIVITY 0x00000200L
206 #define TULIP_SIASTS_RXACTIVITY 0x00000100L
207 #define TULIP_SIASTS_LINKFAIL 0x00000004L
208 #define TULIP_SIASTS_LINK100FAIL 0x00000002L
209 #define TULIP_SIACONN_RESET 0x00000000L
212 * 21040 SIA definitions
214 #define TULIP_21040_PROBE_10BASET_TIMEOUT 2500
215 #define TULIP_21040_PROBE_AUIBNC_TIMEOUT 300
216 #define TULIP_21040_PROBE_EXTSIA_TIMEOUT 300
218 #define TULIP_21040_SIACONN_10BASET 0x0000EF01L
219 #define TULIP_21040_SIATXRX_10BASET 0x0000FFFFL
220 #define TULIP_21040_SIAGEN_10BASET 0x00000000L
222 #define TULIP_21040_SIACONN_10BASET_FD 0x0000EF01L
223 #define TULIP_21040_SIATXRX_10BASET_FD 0x0000FFFDL
224 #define TULIP_21040_SIAGEN_10BASET_FD 0x00000000L
226 #define TULIP_21040_SIACONN_AUIBNC 0x0000EF09L
227 #define TULIP_21040_SIATXRX_AUIBNC 0x00000705L
228 #define TULIP_21040_SIAGEN_AUIBNC 0x00000006L
230 #define TULIP_21040_SIACONN_EXTSIA 0x00003041L
231 #define TULIP_21040_SIATXRX_EXTSIA 0x00000000L
232 #define TULIP_21040_SIAGEN_EXTSIA 0x00000006L
235 * 21041 SIA definitions
238 #define TULIP_21041_PROBE_10BASET_TIMEOUT 2500
239 #define TULIP_21041_PROBE_AUIBNC_TIMEOUT 300
241 #define TULIP_21041_SIACONN_10BASET 0x0000EF01L
242 #define TULIP_21041_SIATXRX_10BASET 0x0000FF3FL
243 #define TULIP_21041_SIAGEN_10BASET 0x00000000L
245 #define TULIP_21041P2_SIACONN_10BASET 0x0000EF01L
246 #define TULIP_21041P2_SIATXRX_10BASET 0x0000FFFFL
247 #define TULIP_21041P2_SIAGEN_10BASET 0x00000000L
249 #define TULIP_21041_SIACONN_10BASET_FD 0x0000EF01L
250 #define TULIP_21041_SIATXRX_10BASET_FD 0x0000FF3DL
251 #define TULIP_21041_SIAGEN_10BASET_FD 0x00000000L
253 #define TULIP_21041P2_SIACONN_10BASET_FD 0x0000EF01L
254 #define TULIP_21041P2_SIATXRX_10BASET_FD 0x0000FFFFL
255 #define TULIP_21041P2_SIAGEN_10BASET_FD 0x00000000L
257 #define TULIP_21041_SIACONN_AUI 0x0000EF09L
258 #define TULIP_21041_SIATXRX_AUI 0x0000F73DL
259 #define TULIP_21041_SIAGEN_AUI 0x0000000EL
261 #define TULIP_21041P2_SIACONN_AUI 0x0000EF09L
262 #define TULIP_21041P2_SIATXRX_AUI 0x0000F7FDL
263 #define TULIP_21041P2_SIAGEN_AUI 0x0000000EL
265 #define TULIP_21041_SIACONN_BNC 0x0000EF09L
266 #define TULIP_21041_SIATXRX_BNC 0x0000F73DL
267 #define TULIP_21041_SIAGEN_BNC 0x00000006L
269 #define TULIP_21041P2_SIACONN_BNC 0x0000EF09L
270 #define TULIP_21041P2_SIATXRX_BNC 0x0000F7FDL
271 #define TULIP_21041P2_SIAGEN_BNC 0x00000006L
274 * 21142 SIA definitions
277 #define TULIP_21142_PROBE_10BASET_TIMEOUT 2500
278 #define TULIP_21142_PROBE_AUIBNC_TIMEOUT 300
280 #define TULIP_21142_SIACONN_10BASET 0x00000001L
281 #define TULIP_21142_SIATXRX_10BASET 0x00007F3FL
282 #define TULIP_21142_SIAGEN_10BASET 0x00000008L
284 #define TULIP_21142_SIACONN_10BASET_FD 0x00000001L
285 #define TULIP_21142_SIATXRX_10BASET_FD 0x00007F3DL
286 #define TULIP_21142_SIAGEN_10BASET_FD 0x00000008L
288 #define TULIP_21142_SIACONN_AUI 0x00000009L
289 #define TULIP_21142_SIATXRX_AUI 0x00000705L
290 #define TULIP_21142_SIAGEN_AUI 0x0000000EL
292 #define TULIP_21142_SIACONN_BNC 0x00000009L
293 #define TULIP_21142_SIATXRX_BNC 0x00000705L
294 #define TULIP_21142_SIAGEN_BNC 0x00000006L
299 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L
300 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L
302 #define TULIP_BUSMODE_SWRESET 0x00000001L
303 #define TULIP_BUSMODE_DESCSKIPLEN_MASK 0x0000007CL
304 #define TULIP_BUSMODE_BIGENDIAN 0x00000080L
305 #define TULIP_BUSMODE_BURSTLEN_MASK 0x00003F00L
306 #define TULIP_BUSMODE_BURSTLEN_DEFAULT 0x00000000L
307 #define TULIP_BUSMODE_BURSTLEN_1LW 0x00000100L
308 #define TULIP_BUSMODE_BURSTLEN_2LW 0x00000200L
309 #define TULIP_BUSMODE_BURSTLEN_4LW 0x00000400L
310 #define TULIP_BUSMODE_BURSTLEN_8LW 0x00000800L
311 #define TULIP_BUSMODE_BURSTLEN_16LW 0x00001000L
312 #define TULIP_BUSMODE_BURSTLEN_32LW 0x00002000L
313 #define TULIP_BUSMODE_CACHE_NOALIGN 0x00000000L
314 #define TULIP_BUSMODE_CACHE_ALIGN8 0x00004000L
315 #define TULIP_BUSMODE_CACHE_ALIGN16 0x00008000L
316 #define TULIP_BUSMODE_CACHE_ALIGN32 0x0000C000L
317 #define TULIP_BUSMODE_TXPOLL_NEVER 0x00000000L
318 #define TULIP_BUSMODE_TXPOLL_200000ns 0x00020000L
319 #define TULIP_BUSMODE_TXPOLL_800000ns 0x00040000L
320 #define TULIP_BUSMODE_TXPOLL_1600000ns 0x00060000L
321 #define TULIP_BUSMODE_TXPOLL_12800ns 0x00080000L /* 21041 only */
322 #define TULIP_BUSMODE_TXPOLL_25600ns 0x000A0000L /* 21041 only */
323 #define TULIP_BUSMODE_TXPOLL_51200ns 0x000C0000L /* 21041 only */
324 #define TULIP_BUSMODE_TXPOLL_102400ns 0x000E0000L /* 21041 only */
325 #define TULIP_BUSMODE_DESC_BIGENDIAN 0x00100000L /* 21041 only */
326 #define TULIP_BUSMODE_READMULTIPLE 0x00200000L /* */
328 #define TULIP_REG_CFDA 0x40
329 #define TULIP_CFDA_SLEEP 0x80000000L
330 #define TULIP_CFDA_SNOOZE 0x40000000L
332 #define TULIP_GP_PINSET 0x00000100L
334 * These are the defintitions used for the DEC 21140
337 #define TULIP_GP_EB_PINS 0x0000001F /* General Purpose Pin directions */
338 #define TULIP_GP_EB_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
339 #define TULIP_GP_EB_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
340 #define TULIP_GP_EB_INIT 0x0000000B /* No loopback --- point-to-point */
343 * These are the defintitions used for the SMC9332 (21140) board.
345 #define TULIP_GP_SMC_9332_PINS 0x0000003F /* General Purpose Pin directions */
346 #define TULIP_GP_SMC_9332_OK10 0x00000080 /* 10 Mb/sec Signal Detect gep<7> */
347 #define TULIP_GP_SMC_9332_OK100 0x00000040 /* 100 Mb/sec Signal Detect gep<6> */
348 #define TULIP_GP_SMC_9332_INIT 0x00000009 /* No loopback --- point-to-point */
351 * There are the definitions used for the DEC DE500
352 * 10/100 family of boards
354 #define TULIP_GP_DE500_PINS 0x0000001FL
355 #define TULIP_GP_DE500_LINK_PASS 0x00000080L
356 #define TULIP_GP_DE500_SYM_LINK 0x00000040L
357 #define TULIP_GP_DE500_SIGNAL_DETECT 0x00000020L
358 #define TULIP_GP_DE500_PHY_RESET 0x00000010L
359 #define TULIP_GP_DE500_HALFDUPLEX 0x00000008L
360 #define TULIP_GP_DE500_PHY_LOOPBACK 0x00000004L
361 #define TULIP_GP_DE500_FORCE_LED 0x00000002L
362 #define TULIP_GP_DE500_FORCE_100 0x00000001L
365 * These are the defintitions used for the Cogent EM100
368 #define TULIP_GP_EM100_PINS 0x0000003F /* General Purpose Pin directions */
369 #define TULIP_GP_EM100_INIT 0x00000009 /* No loopback --- point-to-point */
370 #define TULIP_COGENT_EM100TX_ID 0x12
371 #define TULIP_COGENT_EM100FX_ID 0x15
375 * These are the defintitions used for the Znyx ZX342
378 #define TULIP_ZNYX_ID_ZX312 0x0602
379 #define TULIP_ZNYX_ID_ZX312T 0x0622
380 #define TULIP_ZNYX_ID_ZX314_INTA 0x0701
381 #define TULIP_ZNYX_ID_ZX314 0x0711
382 #define TULIP_ZNYX_ID_ZX315_INTA 0x0801
383 #define TULIP_ZNYX_ID_ZX315 0x0811
384 #define TULIP_ZNYX_ID_ZX342 0x0901
385 #define TULIP_ZNYX_ID_ZX342B 0x0921
386 #define TULIP_ZNYX_ID_ZX342_X3 0x0902
387 #define TULIP_ZNYX_ID_ZX342_X4 0x0903
388 #define TULIP_ZNYX_ID_ZX344 0x0A01
389 #define TULIP_ZNYX_ID_ZX351 0x0B01
390 #define TULIP_ZNYX_ID_ZX345 0x0C01
391 #define TULIP_ZNYX_ID_ZX311 0x0D01
392 #define TULIP_ZNYX_ID_ZX346 0x0E01
394 #define TULIP_GP_ZX34X_PINS 0x0000001F /* General Purpose Pin directions */
395 #define TULIP_GP_ZX344_PINS 0x0000000B /* General Purpose Pin directions */
396 #define TULIP_GP_ZX345_PINS 0x00000003 /* General Purpose Pin directions */
397 #define TULIP_GP_ZX346_PINS 0x00000043 /* General Purpose Pin directions */
398 #define TULIP_GP_ZX34X_LNKFAIL 0x00000080 /* 10Mb/s Link Failure */
399 #define TULIP_GP_ZX34X_SYMDET 0x00000040 /* 100Mb/s Symbol Detect */
400 #define TULIP_GP_ZX345_PHYACT 0x00000040 /* PHY Activity */
401 #define TULIP_GP_ZX34X_SIGDET 0x00000020 /* 100Mb/s Signal Detect */
402 #define TULIP_GP_ZX346_AUTONEG_ENABLED 0x00000020 /* 802.3u autoneg enabled */
403 #define TULIP_GP_ZX342_COLENA 0x00000008 /* 10t Ext LB */
404 #define TULIP_GP_ZX344_ROTINT 0x00000008 /* PPB IRQ rotation */
405 #define TULIP_GP_ZX345_SPEED10 0x00000008 /* 10Mb speed detect */
406 #define TULIP_GP_ZX346_SPEED100 0x00000008 /* 100Mb speed detect */
407 #define TULIP_GP_ZX34X_NCOLENA 0x00000004 /* 10t Int LB */
408 #define TULIP_GP_ZX34X_RXMATCH 0x00000004 /* RX Match */
409 #define TULIP_GP_ZX346_FULLDUPLEX 0x00000004 /* Full Duplex Sensed */
410 #define TULIP_GP_ZX34X_LB102 0x00000002 /* 100tx twister LB */
411 #define TULIP_GP_ZX34X_NLB101 0x00000001 /* PDT/PDR LB */
412 #define TULIP_GP_ZX34X_INIT 0x00000009
417 #define TULIP_GP_ASANTE_PINS 0x000000bf /* GP pin config */
418 #define TULIP_GP_ASANTE_PHYRESET 0x00000008 /* Reset PHY */
421 * ACCTON EN1207 specialties
424 #define TULIP_CSR8_EN1207 0x08
425 #define TULIP_CSR9_EN1207 0x00
426 #define TULIP_CSR10_EN1207 0x03
427 #define TULIP_CSR11_EN1207 0x1F
429 #define TULIP_GP_EN1207_BNC_INIT 0x0000011B
430 #define TULIP_GP_EN1207_UTP_INIT 0x9E00000B
431 #define TULIP_GP_EN1207_100_INIT 0x6D00031B
434 * SROM definitions for the 21140 and 21041.
436 #define SROMXREG 0x0400
437 #define SROMSEL 0x0800
438 #define SROMRD 0x4000
439 #define SROMWR 0x2000
440 #define SROMDIN 0x0008
441 #define SROMDOUT 0x0004
442 #define SROMDOUTON 0x0004
443 #define SROMDOUTOFF 0x0004
444 #define SROMCLKON 0x0002
445 #define SROMCLKOFF 0x0002
446 #define SROMCSON 0x0001
447 #define SROMCSOFF 0x0001
448 #define SROMCS 0x0001
450 #define SROMCMD_MODE 4
454 #define SROM_BITWIDTH 6
457 * MII Definitions for the 21041 and 21140/21140A/21142
459 #define MII_PREAMBLE (~0)
460 #define MII_TEST 0xAAAAAAAA
461 #define MII_RDCMD 0xF6 /* 1111.0110 */
462 #define MII_WRCMD 0xF5 /* 1111.0101 */
463 #define MII_DIN 0x00080000
464 #define MII_RD 0x00040000
465 #define MII_WR 0x00000000
466 #define MII_DOUT 0x00020000
467 #define MII_CLK 0x00010000
468 #define MII_CLKON MII_CLK
469 #define MII_CLKOFF MII_CLK
471 #define PHYREG_CONTROL 0
472 #define PHYREG_STATUS 1
473 #define PHYREG_IDLOW 2
474 #define PHYREG_IDHIGH 3
475 #define PHYREG_AUTONEG_ADVERTISEMENT 4
476 #define PHYREG_AUTONEG_ABILITIES 5
477 #define PHYREG_AUTONEG_EXPANSION 6
478 #define PHYREG_AUTONEG_NEXTPAGE 7
480 #define PHYSTS_100BASET4 0x8000
481 #define PHYSTS_100BASETX_FD 0x4000
482 #define PHYSTS_100BASETX 0x2000
483 #define PHYSTS_10BASET_FD 0x1000
484 #define PHYSTS_10BASET 0x0800
485 #define PHYSTS_AUTONEG_DONE 0x0020
486 #define PHYSTS_REMOTE_FAULT 0x0010
487 #define PHYSTS_CAN_AUTONEG 0x0008
488 #define PHYSTS_LINK_UP 0x0004
489 #define PHYSTS_JABBER_DETECT 0x0002
490 #define PHYSTS_EXTENDED_REGS 0x0001
492 #define PHYCTL_RESET 0x8000
493 #define PHYCTL_SELECT_100MB 0x2000
494 #define PHYCTL_AUTONEG_ENABLE 0x1000
495 #define PHYCTL_ISOLATE 0x0400
496 #define PHYCTL_AUTONEG_RESTART 0x0200
497 #define PHYCTL_FULL_DUPLEX 0x0100
499 #define DEC_VENDORID 0x1011
500 #define CHIPID_21040 0x0002
501 #define CHIPID_21140 0x0009
502 #define CHIPID_21041 0x0014
503 #define CHIPID_21142 0x0019
504 #define PCI_VENDORID(x) ((x) & 0xFFFF)
505 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
508 * Generic SROM Format
514 u_int8_t sh_idbuf[18];
516 u_int8_t sh_adapter_count;
517 u_int8_t sh_ieee802_address[6];
518 } tulip_srom_header_t;
522 u_int8_t sai_leaf_offset_lowbyte;
523 u_int8_t sai_leaf_offset_highbyte;
524 } tulip_srom_adapter_info_t;
527 TULIP_SROM_CONNTYPE_10BASET =0x0000,
528 TULIP_SROM_CONNTYPE_BNC =0x0001,
529 TULIP_SROM_CONNTYPE_AUI =0x0002,
530 TULIP_SROM_CONNTYPE_100BASETX =0x0003,
531 TULIP_SROM_CONNTYPE_100BASET4 =0x0006,
532 TULIP_SROM_CONNTYPE_100BASEFX =0x0007,
533 TULIP_SROM_CONNTYPE_MII_10BASET =0x0009,
534 TULIP_SROM_CONNTYPE_MII_100BASETX =0x000D,
535 TULIP_SROM_CONNTYPE_MII_100BASET4 =0x000F,
536 TULIP_SROM_CONNTYPE_MII_100BASEFX =0x0010,
537 TULIP_SROM_CONNTYPE_10BASET_NWAY =0x0100,
538 TULIP_SROM_CONNTYPE_10BASET_FD =0x0204,
539 TULIP_SROM_CONNTYPE_MII_10BASET_FD =0x020A,
540 TULIP_SROM_CONNTYPE_100BASETX_FD =0x020E,
541 TULIP_SROM_CONNTYPE_MII_100BASETX_FD =0x0211,
542 TULIP_SROM_CONNTYPE_10BASET_NOLINKPASS =0x0400,
543 TULIP_SROM_CONNTYPE_AUTOSENSE =0x0800,
544 TULIP_SROM_CONNTYPE_AUTOSENSE_POWERUP =0x8800,
545 TULIP_SROM_CONNTYPE_AUTOSENSE_NWAY =0x9000,
546 TULIP_SROM_CONNTYPE_NOT_USED =0xFFFF
547 } tulip_srom_connection_t;
550 TULIP_SROM_MEDIA_10BASET =0x0000,
551 TULIP_SROM_MEDIA_BNC =0x0001,
552 TULIP_SROM_MEDIA_AUI =0x0002,
553 TULIP_SROM_MEDIA_100BASETX =0x0003,
554 TULIP_SROM_MEDIA_10BASET_FD =0x0004,
555 TULIP_SROM_MEDIA_100BASETX_FD =0x0005,
556 TULIP_SROM_MEDIA_100BASET4 =0x0006,
557 TULIP_SROM_MEDIA_100BASEFX =0x0007,
558 TULIP_SROM_MEDIA_100BASEFX_FD =0x0008
559 } tulip_srom_media_t;
561 #define TULIP_SROM_21041_EXTENDED 0x40
563 #define TULIP_SROM_2114X_NOINDICATOR 0x8000
564 #define TULIP_SROM_2114X_DEFAULT 0x4000
565 #define TULIP_SROM_2114X_POLARITY 0x0080
566 #define TULIP_SROM_2114X_CMDBITS(n) (((n) & 0x0071) << 18)
567 #define TULIP_SROM_2114X_BITPOS(b) (1 << (((b) & 0x0E) >> 1))
571 #endif /* !defined(_DC21040_H) */