2 * Copyright (C) 2015 Alexander Kabaev
3 * Copyright (C) 2010 Andrew Turner
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* A driver for the Davicom DM9000 MAC. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
40 #include <sys/mutex.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/ethernet.h>
57 #include <dev/mii/mii.h>
58 #include <dev/mii/miivar.h>
60 #include <dev/dme/if_dmereg.h>
61 #include <dev/dme/if_dmevar.h>
63 #include <dev/ofw/ofw_bus.h>
64 #include <dev/ofw/ofw_bus_subr.h>
66 #include <dev/extres/regulator/regulator.h>
67 #include <dev/gpio/gpiobusvar.h>
69 #include "miibus_if.h"
72 struct ifnet *dme_ifp;
75 bus_space_handle_t dme_handle;
76 bus_space_tag_t dme_tag;
79 struct resource *dme_res;
80 struct resource *dme_irq;
83 struct callout dme_tick_ch;
84 struct gpiobus_pin *gpio_rset;
86 uint8_t dme_macaddr[ETHER_ADDR_LEN];
87 regulator_t dme_vcc_regulator;
88 uint8_t dme_txbusy: 1;
89 uint8_t dme_txready: 1;
93 #define DME_CHIP_DM9000 0x00
94 #define DME_CHIP_DM9000A 0x19
95 #define DME_CHIP_DM9000B 0x1a
99 static int dme_probe(device_t);
100 static int dme_attach(device_t);
101 static int dme_detach(device_t);
103 static void dme_intr(void *arg);
104 static void dme_init_locked(struct dme_softc *);
106 static void dme_prepare(struct dme_softc *);
107 static void dme_transmit(struct dme_softc *);
109 static int dme_miibus_writereg(device_t dev, int phy, int reg, int data);
110 static int dme_miibus_readreg(device_t dev, int phy, int reg);
112 /* The bit on the address bus attached to the CMD pin */
113 #define BASE_ADDR 0x000
114 #define CMD_ADDR BASE_ADDR
116 #define DATA_ADDR 0x002
124 #define NOTR(args...) (void)0
130 dme_read_reg(struct dme_softc *sc, uint8_t reg)
133 /* Send the register to read from */
134 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, reg);
135 bus_space_barrier(sc->dme_tag, sc->dme_handle, CMD_ADDR, 1,
136 BUS_SPACE_BARRIER_WRITE);
138 /* Get the value of the register */
139 return bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
143 dme_write_reg(struct dme_softc *sc, uint8_t reg, uint8_t value)
146 /* Send the register to write to */
147 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, reg);
148 bus_space_barrier(sc->dme_tag, sc->dme_handle, CMD_ADDR, 1,
149 BUS_SPACE_BARRIER_WRITE);
151 /* Write the value to the register */
152 bus_space_write_1(sc->dme_tag, sc->dme_handle, DATA_ADDR, value);
153 bus_space_barrier(sc->dme_tag, sc->dme_handle, DATA_ADDR, 1,
154 BUS_SPACE_BARRIER_WRITE);
158 dme_reset(struct dme_softc *sc)
162 /* Send a soft reset #1 */
163 dme_write_reg(sc, DME_NCR, NCR_RST | NCR_LBK_MAC);
164 DELAY(100); /* Wait for the MAC to reset */
165 ncr = dme_read_reg(sc, DME_NCR);
167 device_printf(sc->dme_dev, "device did not complete first reset\n");
169 /* Send a soft reset #2 per Application Notes v1.22 */
170 dme_write_reg(sc, DME_NCR, 0);
171 dme_write_reg(sc, DME_NCR, NCR_RST | NCR_LBK_MAC);
172 DELAY(100); /* Wait for the MAC to reset */
173 ncr = dme_read_reg(sc, DME_NCR);
175 device_printf(sc->dme_dev, "device did not complete second reset\n");
177 /* Reset trasmit state */
181 DTR3("dme_reset, flags %#x busy %d ready %d",
182 sc->dme_ifp ? sc->dme_ifp->if_drv_flags : 0,
183 sc->dme_txbusy, sc->dme_txready);
187 * Parse string MAC address into usable form
190 dme_parse_macaddr(const char *str, uint8_t *mac)
193 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
195 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
196 &amac[0], &amac[1], &amac[2],
197 &amac[3], &amac[4], &amac[5]);
198 if (count < ETHER_ADDR_LEN) {
199 memset(mac, 0, ETHER_ADDR_LEN);
203 /* Copy aligned to result */
204 for (i = 0; i < ETHER_ADDR_LEN; i ++)
205 mac[i] = (amac[i] & 0xff);
211 * Try to determine our own MAC address
214 dme_get_macaddr(struct dme_softc *sc)
220 /* Cannot use resource_string_value with static hints mode */
221 snprintf(devid_str, 32, "hint.%s.%d.macaddr",
222 device_get_name(sc->dme_dev),
223 device_get_unit(sc->dme_dev));
225 /* Try resource hints */
226 if ((var = kern_getenv(devid_str)) != NULL) {
227 if (!dme_parse_macaddr(var, sc->dme_macaddr)) {
228 device_printf(sc->dme_dev, "MAC address: %s (hints)\n", var);
234 * Try to read MAC address from the device, in case U-Boot has
235 * pre-programmed one for us.
237 for (i = 0; i < ETHER_ADDR_LEN; i++)
238 sc->dme_macaddr[i] = dme_read_reg(sc, DME_PAR(i));
240 device_printf(sc->dme_dev, "MAC address %6D (existing)\n",
241 sc->dme_macaddr, ":");
245 dme_config(struct dme_softc *sc)
249 /* Mask all interrupts and reset receive pointer */
250 dme_write_reg(sc, DME_IMR, IMR_PAR);
252 /* Disable GPIO0 to enable the internal PHY */
253 dme_write_reg(sc, DME_GPCR, 1);
254 dme_write_reg(sc, DME_GPR, 0);
258 * Supposedly requires special initialization for DSP PHYs
259 * used by DM9000B. Maybe belongs in dedicated PHY driver?
261 if (sc->dme_rev == DME_CHIP_DM9000B) {
262 dme_miibus_writereg(sc->dme_dev, DME_INT_PHY, MII_BMCR,
264 dme_miibus_writereg(sc->dme_dev, DME_INT_PHY, MII_DME_DSPCR,
266 /* Wait 100ms for it to complete. */
267 for (i = 0; i < 100; i++) {
270 reg = dme_miibus_readreg(sc->dme_dev, DME_INT_PHY, MII_BMCR);
271 if ((reg & BMCR_RESET) == 0)
278 /* Select the internal PHY and normal loopback */
279 dme_write_reg(sc, DME_NCR, NCR_LBK_NORMAL);
280 /* Clear any TX requests */
281 dme_write_reg(sc, DME_TCR, 0);
282 /* Setup backpressure thresholds to 4k and 600us */
283 dme_write_reg(sc, DME_BPTR, BPTR_BPHW(3) | BPTR_JPT(0x0f));
284 /* Setup flow control */
285 dme_write_reg(sc, DME_FCTR, FCTR_HWOT(0x3) | FCTR_LWOT(0x08));
286 /* Enable flow control */
287 dme_write_reg(sc, DME_FCR, 0xff);
288 /* Clear special modes */
289 dme_write_reg(sc, DME_SMCR, 0);
290 /* Clear TX status */
291 dme_write_reg(sc, DME_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
292 /* Clear interrrupts */
293 dme_write_reg(sc, DME_ISR, 0xff);
294 /* Set multicast address filter */
295 for (i = 0; i < 8; i++)
296 dme_write_reg(sc, DME_MAR(i), 0xff);
297 /* Set the MAC address */
298 for (i = 0; i < ETHER_ADDR_LEN; i++)
299 dme_write_reg(sc, DME_PAR(i), sc->dme_macaddr[i]);
300 /* Enable the RX buffer */
301 dme_write_reg(sc, DME_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
303 /* Enable interrupts we care about */
304 dme_write_reg(sc, DME_IMR, IMR_PAR | IMR_PRI | IMR_PTI);
308 dme_prepare(struct dme_softc *sc)
312 uint16_t total_len, len;
314 DME_ASSERT_LOCKED(sc);
316 KASSERT(sc->dme_txready == 0,
317 ("dme_prepare: called with txready set\n"));
320 IFQ_DEQUEUE(&ifp->if_snd, m);
322 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
323 DTR3("dme_prepare none, flags %#x busy %d ready %d",
324 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
325 return; /* Nothing to transmit */
328 /* Element has now been removed from the queue, so we better send it */
331 /* Setup the controller to accept the writes */
332 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, DME_MWCMD);
335 * TODO: Fix the case where an mbuf is
336 * not a multiple of the write size.
339 for (mp = m; mp != NULL; mp = mp->m_next) {
342 /* Ignore empty parts */
349 bus_space_write_multi_2(sc->dme_tag, sc->dme_handle,
350 DATA_ADDR, mtod(mp, uint16_t *), (len + 1) / 2);
352 bus_space_write_multi_1(sc->dme_tag, sc->dme_handle,
353 DATA_ADDR, mtod(mp, uint8_t *), len);
357 if (total_len % (sc->dme_bits >> 3) != 0)
358 panic("dme_prepare: length is not compatible with IO_MODE");
360 sc->dme_txlen = total_len;
362 DTR3("dme_prepare done, flags %#x busy %d ready %d",
363 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
369 dme_transmit(struct dme_softc *sc)
372 DME_ASSERT_LOCKED(sc);
373 KASSERT(sc->dme_txready, ("transmit without txready"));
375 dme_write_reg(sc, DME_TXPLL, sc->dme_txlen & 0xff);
376 dme_write_reg(sc, DME_TXPLH, (sc->dme_txlen >> 8) & 0xff );
378 /* Request to send the packet */
379 dme_read_reg(sc, DME_ISR);
381 dme_write_reg(sc, DME_TCR, TCR_TXREQ);
385 DTR3("dme_transmit done, flags %#x busy %d ready %d",
386 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
391 dme_start_locked(struct ifnet *ifp)
393 struct dme_softc *sc;
396 DME_ASSERT_LOCKED(sc);
398 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
402 DTR3("dme_start, flags %#x busy %d ready %d",
403 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
404 KASSERT(sc->dme_txbusy == 0 || sc->dme_txready == 0,
405 ("dme: send without empty queue\n"));
409 if (sc->dme_txbusy == 0) {
410 /* We are ready to transmit right away */
412 dme_prepare(sc); /* Prepare next one */
415 * We need to wait until the current packet has
418 if (sc->dme_txready != 0)
419 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
423 dme_start(struct ifnet *ifp)
425 struct dme_softc *sc;
429 dme_start_locked(ifp);
434 dme_stop(struct dme_softc *sc)
438 DME_ASSERT_LOCKED(sc);
439 /* Disable receiver */
440 dme_write_reg(sc, DME_RCR, 0x00);
441 /* Mask interrupts */
442 dme_write_reg(sc, DME_IMR, 0x00);
444 callout_stop(&sc->dme_tick_ch);
447 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
449 DTR3("dme_stop, flags %#x busy %d ready %d",
450 sc->dme_ifp->if_drv_flags, sc->dme_txbusy, sc->dme_txready);
456 dme_rxeof(struct dme_softc *sc)
462 DME_ASSERT_LOCKED(sc);
466 /* Read the first byte to check it correct */
467 (void)dme_read_reg(sc, DME_MRCMDX);
468 i = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
469 switch(bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR)) {
480 i = dme_read_reg(sc, DME_MRRL);
481 i |= dme_read_reg(sc, DME_MRRH) << 8;
483 len = dme_read_reg(sc, DME_ROCR);
485 bus_space_write_1(sc->dme_tag, sc->dme_handle, CMD_ADDR, DME_MRCMD);
487 switch(sc->dme_bits) {
489 i = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
491 i |= bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
493 len = bus_space_read_1(sc->dme_tag, sc->dme_handle, DATA_ADDR);
494 len |= bus_space_read_1(sc->dme_tag, sc->dme_handle,
498 bus_space_read_2(sc->dme_tag, sc->dme_handle, DATA_ADDR);
499 len = bus_space_read_2(sc->dme_tag, sc->dme_handle, DATA_ADDR);
505 reg = bus_space_read_4(sc->dme_tag, sc->dme_handle, DATA_ADDR);
511 MGETHDR(m, M_NOWAIT, MT_DATA);
515 if (len > MHLEN - ETHER_ALIGN) {
517 if (!(m->m_flags & M_EXT)) {
523 m->m_pkthdr.rcvif = ifp;
524 m->m_len = m->m_pkthdr.len = len;
525 m_adj(m, ETHER_ALIGN);
529 bus_space_read_multi_2(sc->dme_tag, sc->dme_handle, DATA_ADDR,
530 mtod(m, uint16_t *), (len + 1) / 2);
532 bus_space_read_multi_1(sc->dme_tag, sc->dme_handle, DATA_ADDR,
533 mtod(m, uint8_t *), len);
535 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
537 (*ifp->if_input)(ifp, m);
546 struct dme_softc *sc;
547 struct mii_data *mii;
549 sc = (struct dme_softc *)arg;
551 /* Probably too frequent? */
552 mii = device_get_softc(sc->dme_miibus);
555 callout_reset(&sc->dme_tick_ch, hz, dme_tick, sc);
561 struct dme_softc *sc;
562 uint32_t intr_status;
564 sc = (struct dme_softc *)arg;
568 intr_status = dme_read_reg(sc, DME_ISR);
569 dme_write_reg(sc, DME_ISR, intr_status);
571 DTR4("dme_intr flags %#x busy %d ready %d intr %#x",
572 sc->dme_ifp->if_drv_flags, sc->dme_txbusy,
573 sc->dme_txready, intr_status);
575 if (intr_status & ISR_PT) {
576 uint8_t nsr, tx_status;
580 nsr = dme_read_reg(sc, DME_NSR);
582 if (nsr & NSR_TX1END)
583 tx_status = dme_read_reg(sc, DME_TSR1);
584 else if (nsr & NSR_TX2END)
585 tx_status = dme_read_reg(sc, DME_TSR2);
589 DTR4("dme_intr flags %#x busy %d ready %d nsr %#x",
590 sc->dme_ifp->if_drv_flags, sc->dme_txbusy,
591 sc->dme_txready, nsr);
593 /* Prepare packet to send if none is currently pending */
594 if (sc->dme_txready == 0)
596 /* Send the packet out of one is waiting for transmit */
597 if (sc->dme_txready != 0) {
598 /* Initiate transmission of the prepared packet */
600 /* Prepare next packet to send */
603 * We need to wait until the current packet has
606 if (sc->dme_txready != 0)
607 sc->dme_ifp->if_drv_flags |= IFF_DRV_OACTIVE;
611 if (intr_status & ISR_PR) {
612 /* Read the packets off the device */
613 while (dme_rxeof(sc) == 0)
620 dme_setmode(struct dme_softc *sc)
625 dme_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
627 struct dme_softc *sc;
628 struct mii_data *mii;
633 ifr = (struct ifreq *)data;
638 * Switch interface state between "running" and
639 * "stopped", reflecting the UP flag.
642 if (ifp->if_flags & IFF_UP) {
643 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
647 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
656 mii = device_get_softc(sc->dme_miibus);
657 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
660 error = ether_ioctl(ifp, command, data);
666 static void dme_init_locked(struct dme_softc *sc)
668 struct ifnet *ifp = sc->dme_ifp;
670 DME_ASSERT_LOCKED(sc);
672 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
678 ifp->if_drv_flags |= IFF_DRV_RUNNING;
679 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
681 callout_reset(&sc->dme_tick_ch, hz, dme_tick, sc);
687 struct dme_softc *sc = xcs;
695 dme_ifmedia_upd(struct ifnet *ifp)
697 struct dme_softc *sc;
698 struct mii_data *mii;
701 mii = device_get_softc(sc->dme_miibus);
711 dme_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
713 struct dme_softc *sc;
714 struct mii_data *mii;
717 mii = device_get_softc(sc->dme_miibus);
721 ifmr->ifm_active = mii->mii_media_active;
722 ifmr->ifm_status = mii->mii_media_status;
726 static struct ofw_compat_data compat_data[] = {
727 { "davicom,dm9000", true },
732 dme_probe(device_t dev)
734 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
736 device_set_desc(dev, "Davicom DM9000");
741 dme_attach(device_t dev)
743 struct dme_softc *sc;
748 sc = device_get_softc(dev);
753 mtx_init(&sc->dme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
755 callout_init_mtx(&sc->dme_tick_ch, &sc->dme_mtx, 0);
758 sc->dme_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
760 if (sc->dme_res == NULL) {
761 device_printf(dev, "unable to map memory\n");
767 sc->dme_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
769 if (sc->dme_irq == NULL) {
770 device_printf(dev, "unable to map memory\n");
775 * Power the chip up, if necessary
777 error = regulator_get_by_ofw_property(dev, 0, "vcc-supply", &sc->dme_vcc_regulator);
779 error = regulator_enable(sc->dme_vcc_regulator);
781 device_printf(dev, "unable to enable power supply\n");
788 * Delay a little. This seems required on rev-1 boards (green.)
792 /* Bring controller out of reset */
793 error = ofw_gpiobus_parse_gpios(dev, "reset-gpios", &sc->gpio_rset);
795 device_printf(dev, "too many reset gpios\n");
796 sc->gpio_rset = NULL;
801 if (sc->gpio_rset != NULL) {
802 error = GPIO_PIN_SET(sc->gpio_rset->dev, sc->gpio_rset->pin, 0);
804 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
805 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev));
809 error = GPIO_PIN_SETFLAGS(sc->gpio_rset->dev, sc->gpio_rset->pin,
812 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
813 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev));
819 error = GPIO_PIN_SET(sc->gpio_rset->dev, sc->gpio_rset->pin, 1);
821 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
822 sc->gpio_rset->pin, device_get_nameunit(sc->gpio_rset->dev));
828 device_printf(dev, "Unable to find reset GPIO\n");
830 sc->dme_tag = rman_get_bustag(sc->dme_res);
831 sc->dme_handle = rman_get_bushandle(sc->dme_res);
833 /* Reset the chip as soon as possible */
837 switch((dme_read_reg(sc, DME_ISR) >> 6) & 0x03) {
852 device_printf(dev, "Unable to determine device mode\n");
859 /* Read vendor and device id's */
860 data = dme_read_reg(sc, DME_VIDH) << 8;
861 data |= dme_read_reg(sc, DME_VIDL);
862 device_printf(dev, "Vendor ID: 0x%04x\n", data);
864 /* Read vendor and device id's */
865 data = dme_read_reg(sc, DME_PIDH) << 8;
866 data |= dme_read_reg(sc, DME_PIDL);
867 device_printf(dev, "Product ID: 0x%04x\n", data);
870 data = dme_read_reg(sc, DME_CHIPR);
871 device_printf(dev, "Revision: 0x%04x\n", data);
872 if (data != DME_CHIP_DM9000A && data != DME_CHIP_DM9000B)
873 data = DME_CHIP_DM9000;
876 device_printf(dev, "using %d-bit IO mode\n", sc->dme_bits);
877 KASSERT(sc->dme_bits == 8, ("wrong io mode"));
879 /* Try to figure our mac address */
882 /* Configure chip after reset */
885 ifp = sc->dme_ifp = if_alloc(IFT_ETHER);
887 device_printf(dev, "unable to allocate ifp\n");
894 error = mii_attach(dev, &sc->dme_miibus, ifp, dme_ifmedia_upd,
895 dme_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
896 /* This should never happen as the DM9000 contains it's own PHY */
898 device_printf(dev, "PHY probe failed\n");
902 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
903 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
904 ifp->if_start = dme_start;
905 ifp->if_ioctl = dme_ioctl;
906 ifp->if_init = dme_init;
907 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
909 ether_ifattach(ifp, sc->dme_macaddr);
911 error = bus_setup_intr(dev, sc->dme_irq, INTR_TYPE_NET | INTR_MPSAFE,
912 NULL, dme_intr, sc, &sc->dme_intrhand);
914 device_printf(dev, "couldn't set up irq\n");
925 dme_detach(device_t dev)
927 struct dme_softc *sc;
930 sc = device_get_softc(dev);
931 KASSERT(mtx_initialized(&sc->dme_mtx), ("dme mutex not initialized"));
935 if (device_is_attached(dev)) {
940 callout_drain(&sc->dme_tick_ch);
944 device_delete_child(dev, sc->dme_miibus);
945 bus_generic_detach(dev);
947 if (sc->dme_vcc_regulator != 0)
948 regulator_release(sc->dme_vcc_regulator);
949 if (sc->dme_intrhand)
950 bus_teardown_intr(dev, sc->dme_irq, sc->dme_intrhand);
952 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dme_irq);
954 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->dme_res);
959 mtx_destroy(&sc->dme_mtx);
965 * The MII bus interface
968 dme_miibus_readreg(device_t dev, int phy, int reg)
970 struct dme_softc *sc;
973 /* We have up to 4 PHY's */
977 sc = device_get_softc(dev);
979 /* Send the register to read to the phy and start the read */
980 dme_write_reg(sc, DME_EPAR, (phy << 6) | reg);
981 dme_write_reg(sc, DME_EPCR, EPCR_EPOS | EPCR_ERPRR);
983 /* Wait for the data to be read */
984 for (i = 0; i < DME_TIMEOUT; i++) {
985 if ((dme_read_reg(sc, DME_EPCR) & EPCR_ERRE) == 0)
990 /* Clear the comand */
991 dme_write_reg(sc, DME_EPCR, 0);
993 if (i == DME_TIMEOUT)
996 rval = (dme_read_reg(sc, DME_EPDRH) << 8) | dme_read_reg(sc, DME_EPDRL);
1001 dme_miibus_writereg(device_t dev, int phy, int reg, int data)
1003 struct dme_softc *sc;
1006 /* We have up to 4 PHY's */
1010 sc = device_get_softc(dev);
1012 /* Send the register and data to write to the phy */
1013 dme_write_reg(sc, DME_EPAR, (phy << 6) | reg);
1014 dme_write_reg(sc, DME_EPDRL, data & 0xFF);
1015 dme_write_reg(sc, DME_EPDRH, (data >> 8) & 0xFF);
1016 /* Start the write */
1017 dme_write_reg(sc, DME_EPCR, EPCR_EPOS | EPCR_ERPRW);
1019 /* Wait for the data to be written */
1020 for (i = 0; i < DME_TIMEOUT; i++) {
1021 if ((dme_read_reg(sc, DME_EPCR) & EPCR_ERRE) == 0)
1026 /* Clear the comand */
1027 dme_write_reg(sc, DME_EPCR, 0);
1032 static device_method_t dme_methods[] = {
1033 /* Device interface */
1034 DEVMETHOD(device_probe, dme_probe),
1035 DEVMETHOD(device_attach, dme_attach),
1036 DEVMETHOD(device_detach, dme_detach),
1038 /* bus interface, for miibus */
1039 DEVMETHOD(bus_print_child, bus_generic_print_child),
1040 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1043 DEVMETHOD(miibus_readreg, dme_miibus_readreg),
1044 DEVMETHOD(miibus_writereg, dme_miibus_writereg),
1049 static driver_t dme_driver = {
1052 sizeof(struct dme_softc)
1055 static devclass_t dme_devclass;
1057 MODULE_DEPEND(dme, ether, 1, 1, 1);
1058 MODULE_DEPEND(dme, miibus, 1, 1, 1);
1059 DRIVER_MODULE(dme, simplebus, dme_driver, dme_devclass, 0, 0);
1060 DRIVER_MODULE(miibus, dme, miibus_driver, miibus_devclass, 0, 0);