3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
41 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
42 * device driver that provides support for the XFree86 Direct Rendering
43 * Infrastructure (DRI).
45 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
47 * -# The DRM provides synchronized access to the graphics hardware via
48 * the use of an optimized two-tiered lock.
49 * -# The DRM enforces the DRI security policy for access to the graphics
50 * hardware by only allowing authenticated X11 clients access to
51 * restricted regions of memory.
52 * -# The DRM provides a generic DMA engine, complete with multiple
53 * queues and the ability to detect the need for an OpenGL context
55 * -# The DRM is extensible via the use of small device-specific modules
56 * that rely extensively on the API exported by the DRM module.
67 #if defined(__linux__)
68 #include <linux/config.h>
69 #include <asm/ioctl.h> /* For _IO* macros */
70 #define DRM_IOCTL_NR(n) _IOC_NR(n)
71 #define DRM_IOC_VOID _IOC_NONE
72 #define DRM_IOC_READ _IOC_READ
73 #define DRM_IOC_WRITE _IOC_WRITE
74 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
75 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
76 #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
77 #if defined(__FreeBSD__) && defined(IN_MODULE)
78 /* Prevent name collision when including sys/ioccom.h */
80 #include <sys/ioccom.h>
81 #define ioctl(a,b,c) xf86ioctl(a,b,c)
83 #include <sys/ioccom.h>
84 #endif /* __FreeBSD__ && xf86ioctl */
85 #define DRM_IOCTL_NR(n) ((n) & 0xff)
86 #define DRM_IOC_VOID IOC_VOID
87 #define DRM_IOC_READ IOC_OUT
88 #define DRM_IOC_WRITE IOC_IN
89 #define DRM_IOC_READWRITE IOC_INOUT
90 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
93 #define XFREE86_VERSION(major,minor,patch,snap) \
94 ((major << 16) | (minor << 8) | patch)
96 #ifndef CONFIG_XFREE86_VERSION
97 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
100 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
101 #define DRM_PROC_DEVICES "/proc/devices"
102 #define DRM_PROC_MISC "/proc/misc"
103 #define DRM_PROC_DRM "/proc/drm"
104 #define DRM_DEV_DRM "/dev/drm"
105 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
106 #define DRM_DEV_UID 0
107 #define DRM_DEV_GID 0
110 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
114 #if defined(__linux__) || defined(__NetBSD__)
115 #define DRM_MAJOR 226
117 #define DRM_MAX_MINOR 255
119 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
120 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
121 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
122 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
124 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
125 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
126 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
127 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
128 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
130 typedef unsigned long drm_handle_t; /**< To mapped regions */
131 typedef unsigned int drm_context_t; /**< GLXContext handle */
132 typedef unsigned int drm_drawable_t;
133 typedef unsigned int drm_magic_t; /**< Magic for authentication */
138 * \warning If you change this structure, make sure you change
139 * XF86DRIClipRectRec in the server as well
141 * \note KW: Actually it's illegal to change either for
142 * backwards-compatibility reasons.
144 typedef struct drm_clip_rect {
154 typedef struct drm_tex_region {
157 unsigned char in_use;
158 unsigned char padding;
165 * The lock structure is a simple cache-line aligned integer. To avoid
166 * processor bus contention on a multiprocessor system, there should not be any
167 * other data stored in the same cache line.
169 typedef struct drm_hw_lock {
170 __volatile__ unsigned int lock; /**< lock variable */
171 char padding[60]; /**< Pad to cache line */
174 /* This is beyond ugly, and only works on GCC. However, it allows me to use
175 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
176 * fix is to use uint32_t instead of size_t, but that fix will break existing
177 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
178 * eventually happen, though. I chose 'unsigned long' to be the fallback type
179 * because that works on all the platforms I know about. Hopefully, the
180 * real fix will happen before that bites us.
184 # define DRM_SIZE_T __SIZE_TYPE__
186 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
187 # define DRM_SIZE_T unsigned long
191 * DRM_IOCTL_VERSION ioctl argument type.
193 * \sa drmGetVersion().
195 typedef struct drm_version {
196 int version_major; /**< Major version */
197 int version_minor; /**< Minor version */
198 int version_patchlevel; /**< Patch level */
199 DRM_SIZE_T name_len; /**< Length of name buffer */
200 char __user *name; /**< Name of driver */
201 DRM_SIZE_T date_len; /**< Length of date buffer */
202 char __user *date; /**< User-space buffer to hold date */
203 DRM_SIZE_T desc_len; /**< Length of desc buffer */
204 char __user *desc; /**< User-space buffer to hold desc */
208 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
210 * \sa drmGetBusid() and drmSetBusId().
212 typedef struct drm_unique {
213 DRM_SIZE_T unique_len; /**< Length of unique */
214 char __user *unique; /**< Unique name for driver instantiation */
219 typedef struct drm_list {
220 int count; /**< Length of user-space structures */
221 drm_version_t __user *version;
224 typedef struct drm_block {
229 * DRM_IOCTL_CONTROL ioctl argument type.
231 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
233 typedef struct drm_control {
244 * Type of memory to map.
246 typedef enum drm_map_type {
247 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
248 _DRM_REGISTERS = 1, /**< no caching, no core dump */
249 _DRM_SHM = 2, /**< shared, cached */
250 _DRM_AGP = 3, /**< AGP/GART */
251 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
252 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
256 * Memory mapping flags.
258 typedef enum drm_map_flags {
259 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
260 _DRM_READ_ONLY = 0x02,
261 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
262 _DRM_KERNEL = 0x08, /**< kernel requires access */
263 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
264 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
265 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
268 typedef struct drm_ctx_priv_map {
269 unsigned int ctx_id; /**< Context requesting private mapping */
270 void *handle; /**< Handle of map */
271 } drm_ctx_priv_map_t;
274 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
279 typedef struct drm_map {
280 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
281 unsigned long size; /**< Requested physical size (bytes) */
282 drm_map_type_t type; /**< Type of memory to map */
283 drm_map_flags_t flags; /**< Flags */
284 void *handle; /**< User-space: "Handle" to pass to mmap() */
285 /**< Kernel-space: kernel-virtual address */
286 int mtrr; /**< MTRR slot used */
291 * DRM_IOCTL_GET_CLIENT ioctl argument type.
293 typedef struct drm_client {
294 int idx; /**< Which client desired? */
295 int auth; /**< Is client authenticated? */
296 unsigned long pid; /**< Process ID */
297 unsigned long uid; /**< User ID */
298 unsigned long magic; /**< Magic */
299 unsigned long iocs; /**< Ioctl count */
309 _DRM_STAT_VALUE, /**< Generic value */
310 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
311 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
313 _DRM_STAT_IRQ, /**< IRQ */
314 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
315 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
316 _DRM_STAT_DMA, /**< DMA */
317 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
318 _DRM_STAT_MISSED /**< Missed DMA opportunity */
319 /* Add to the *END* of the list */
323 * DRM_IOCTL_GET_STATS ioctl argument type.
325 typedef struct drm_stats {
329 drm_stat_type_t type;
334 * Hardware locking flags.
336 typedef enum drm_lock_flags {
337 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
338 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
339 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
340 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
341 /* These *HALT* flags aren't supported yet
342 -- they will be used to support the
343 full-screen DGA-like mode. */
344 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
345 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
349 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
351 * \sa drmGetLock() and drmUnlock().
353 typedef struct drm_lock {
355 drm_lock_flags_t flags;
362 * These values \e must match xf86drm.h.
366 typedef enum drm_dma_flags {
367 /* Flags for DMA buffer dispatch */
368 _DRM_DMA_BLOCK = 0x01, /**<
369 * Block until buffer dispatched.
371 * \note The buffer may not yet have
372 * been processed by the hardware --
373 * getting a hardware lock with the
374 * hardware quiescent will ensure
375 * that the buffer has been
378 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
379 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
381 /* Flags for DMA buffer request */
382 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
383 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
384 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
388 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
392 typedef struct drm_buf_desc {
393 int count; /**< Number of buffers of this size */
394 int size; /**< Size in bytes */
395 int low_mark; /**< Low water mark */
396 int high_mark; /**< High water mark */
398 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
399 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
400 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
401 _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */
403 unsigned long agp_start; /**<
404 * Start address of where the AGP buffers are
405 * in the AGP aperture
410 * DRM_IOCTL_INFO_BUFS ioctl argument type.
412 typedef struct drm_buf_info {
413 int count; /**< Number of buffers described in list */
414 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
418 * DRM_IOCTL_FREE_BUFS ioctl argument type.
420 typedef struct drm_buf_free {
430 typedef struct drm_buf_pub {
431 int idx; /**< Index into the master buffer list */
432 int total; /**< Buffer size */
433 int used; /**< Amount of buffer in use (for DMA) */
434 void __user *address; /**< Address of buffer */
438 * DRM_IOCTL_MAP_BUFS ioctl argument type.
440 typedef struct drm_buf_map {
441 int count; /**< Length of the buffer list */
442 void __user *virtual; /**< Mmap'd area in user-virtual */
443 drm_buf_pub_t __user *list; /**< Buffer information */
447 * DRM_IOCTL_DMA ioctl argument type.
449 * Indices here refer to the offset into the buffer list in drm_buf_get.
453 typedef struct drm_dma {
454 int context; /**< Context handle */
455 int send_count; /**< Number of buffers to send */
456 int __user *send_indices; /**< List of handles to buffers */
457 int __user *send_sizes; /**< Lengths of data to send */
458 drm_dma_flags_t flags; /**< Flags */
459 int request_count; /**< Number of buffers requested */
460 int request_size; /**< Desired size for buffers */
461 int __user *request_indices; /**< Buffer information */
462 int __user *request_sizes;
463 int granted_count; /**< Number of buffers granted */
467 _DRM_CONTEXT_PRESERVED = 0x01,
468 _DRM_CONTEXT_2DONLY = 0x02
472 * DRM_IOCTL_ADD_CTX ioctl argument type.
474 * \sa drmCreateContext() and drmDestroyContext().
476 typedef struct drm_ctx {
477 drm_context_t handle;
478 drm_ctx_flags_t flags;
482 * DRM_IOCTL_RES_CTX ioctl argument type.
484 typedef struct drm_ctx_res {
486 drm_ctx_t __user *contexts;
490 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
492 typedef struct drm_draw {
493 drm_drawable_t handle;
497 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
499 typedef struct drm_auth {
504 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
506 * \sa drmGetInterruptFromBusID().
508 typedef struct drm_irq_busid {
509 int irq; /**< IRQ number */
510 int busnum; /**< bus number */
511 int devnum; /**< device number */
512 int funcnum; /**< function number */
516 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
517 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
518 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
519 } drm_vblank_seq_type_t;
521 #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
523 struct drm_wait_vblank_request {
524 drm_vblank_seq_type_t type;
525 unsigned int sequence;
526 unsigned long signal;
529 struct drm_wait_vblank_reply {
530 drm_vblank_seq_type_t type;
531 unsigned int sequence;
537 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
539 * \sa drmWaitVBlank().
541 typedef union drm_wait_vblank {
542 struct drm_wait_vblank_request request;
543 struct drm_wait_vblank_reply reply;
547 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
549 * \sa drmAgpEnable().
551 typedef struct drm_agp_mode {
552 unsigned long mode; /**< AGP mode */
556 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
558 * \sa drmAgpAlloc() and drmAgpFree().
560 typedef struct drm_agp_buffer {
561 unsigned long size; /**< In bytes -- will round to page boundary */
562 unsigned long handle; /**< Used for binding / unbinding */
563 unsigned long type; /**< Type of memory to allocate */
564 unsigned long physical; /**< Physical used by i810 */
568 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
570 * \sa drmAgpBind() and drmAgpUnbind().
572 typedef struct drm_agp_binding {
573 unsigned long handle; /**< From drm_agp_buffer */
574 unsigned long offset; /**< In bytes -- will round to page boundary */
578 * DRM_IOCTL_AGP_INFO ioctl argument type.
580 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
581 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
582 * drmAgpVendorId() and drmAgpDeviceId().
584 typedef struct drm_agp_info {
585 int agp_version_major;
586 int agp_version_minor;
588 unsigned long aperture_base; /**< physical address */
589 unsigned long aperture_size; /**< bytes */
590 unsigned long memory_allowed; /**< bytes */
591 unsigned long memory_used;
593 /** \name PCI information */
595 unsigned short id_vendor;
596 unsigned short id_device;
601 * DRM_IOCTL_SG_ALLOC ioctl argument type.
603 typedef struct drm_scatter_gather {
604 unsigned long size; /**< In bytes -- will round to page boundary */
605 unsigned long handle; /**< Used for mapping / unmapping */
606 } drm_scatter_gather_t;
609 * DRM_IOCTL_SET_VERSION ioctl argument type.
611 typedef struct drm_set_version {
619 * \name Ioctls Definitions
623 #define DRM_IOCTL_BASE 'd'
624 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
625 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
626 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
627 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
629 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
630 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
631 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
632 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
633 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
634 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
635 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
636 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
638 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
639 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
640 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
641 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
642 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
643 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
644 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
645 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
646 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
647 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
648 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
650 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
652 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
653 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
655 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
656 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
657 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
658 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
659 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
660 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
661 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
662 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
663 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
664 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
665 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
666 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
667 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
669 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
670 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
671 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
672 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
673 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
674 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
675 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
676 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
678 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
679 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
681 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
686 * Device specific ioctls should only be in their respective headers
687 * The device specific ioctl range is from 0x40 to 0x79.
689 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
690 * drmCommandReadWrite().
692 #define DRM_COMMAND_BASE 0x40