sys/dev/drm/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include "dev/drm/drmP.h"
  33 #include "dev/drm/drm.h"
  34 #include "dev/drm/i915_drm.h"
  35 #include "dev/drm/i915_drv.h"
  36
  37 /* Really want an OS-independent resettable timer.  Would like to have
  38  * this loop run for (eg) 3 sec, but have the timer reset every time
  39  * the head pointer changes, so that EBUSY only happens if the ring
  40  * actually stalls for (eg) 3 seconds.
  41  */
  42 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  43 {
  44         drm_i915_private_t *dev_priv = dev->dev_private;
  45         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  46         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  47         u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  48         u32 last_acthd = I915_READ(acthd_reg);
  49         u32 acthd;
  50         int i;
  51
  52         for (i = 0; i < 100000; i++) {
  53                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  54                 acthd = I915_READ(acthd_reg);
  55                 ring->space = ring->head - (ring->tail + 8);
  56                 if (ring->space < 0)
  57                         ring->space += ring->Size;
  58                 if (ring->space >= n)
  59                         return 0;
  60
  61                 if (ring->head != last_head)
  62                         i = 0;
  63
  64                 if (acthd != last_acthd)
  65                         i = 0;
  66
  67                 last_head = ring->head;
  68                 last_acthd = acthd;
  69                 DRM_UDELAY(10 * 1000);
  70         }
  71
  72         return -EBUSY;
  73 }
  74
  75 int i915_init_hardware_status(struct drm_device *dev)
  76 {
  77         drm_i915_private_t *dev_priv = dev->dev_private;
  78         drm_dma_handle_t *dmah;
  79
  80         /* Program Hardware Status Page */
  81 #ifdef __FreeBSD__
  82         DRM_UNLOCK();
  83 #endif
  84         dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  85 #ifdef __FreeBSD__
  86         DRM_LOCK();
  87 #endif
  88         if (!dmah) {
  89                 DRM_ERROR("Can not allocate hardware status page\n");
  90                 return -ENOMEM;
  91         }
  92
  93         dev_priv->status_page_dmah = dmah;
  94         dev_priv->hw_status_page = dmah->vaddr;
  95         dev_priv->dma_status_page = dmah->busaddr;
  96
  97         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  98
  99         I915_WRITE(0x02080, dev_priv->dma_status_page);
 100         DRM_DEBUG("Enabled hardware status page\n");
 101         return 0;
 102 }
 103
 104 void i915_free_hardware_status(struct drm_device *dev)
 105 {
 106         drm_i915_private_t *dev_priv = dev->dev_private;
 107         if (dev_priv->status_page_dmah) {
 108                 drm_pci_free(dev, dev_priv->status_page_dmah);
 109                 dev_priv->status_page_dmah = NULL;
 110                 /* Need to rewrite hardware status page */
 111                 I915_WRITE(0x02080, 0x1ffff000);
 112         }
 113
 114         if (dev_priv->status_gfx_addr) {
 115                 dev_priv->status_gfx_addr = 0;
 116                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117                 I915_WRITE(0x02080, 0x1ffff000);
 118         }
 119 }
 120
 121 #if I915_RING_VALIDATE
 122 /**
 123  * Validate the cached ring tail value
 124  *
 125  * If the X server writes to the ring and DRM doesn't
 126  * reload the head and tail pointers, it will end up writing
 127  * data to the wrong place in the ring, causing havoc.
 128  */
 129 void i915_ring_validate(struct drm_device *dev, const char *func, int line)
 130 {
 131         drm_i915_private_t *dev_priv = dev->dev_private;
 132         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 133         u32     tail = I915_READ(PRB0_TAIL) & HEAD_ADDR;
 134         u32     head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 135
 136         if (tail != ring->tail) {
 137                 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n",
 138                           func, line,
 139                           ring->head, head, ring->tail, tail);
 140 #ifdef __linux__
 141                 BUG_ON(1);
 142 #endif
 143         }
 144 }
 145 #endif
 146
 147 void i915_kernel_lost_context(struct drm_device * dev)
 148 {
 149         drm_i915_private_t *dev_priv = dev->dev_private;
 150         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 151
 152         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 153         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 154         ring->space = ring->head - (ring->tail + 8);
 155         if (ring->space < 0)
 156                 ring->space += ring->Size;
 157 }
 158
 159 static int i915_dma_cleanup(struct drm_device * dev)
 160 {
 161         drm_i915_private_t *dev_priv = dev->dev_private;
 162         /* Make sure interrupts are disabled here because the uninstall ioctl
 163          * may not have been called from userspace and after dev_private
 164          * is freed, it's too late.
 165          */
 166         if (dev->irq_enabled)
 167                 drm_irq_uninstall(dev);
 168
 169         if (dev_priv->ring.virtual_start) {
 170                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 171                 dev_priv->ring.virtual_start = 0;
 172                 dev_priv->ring.map.handle = 0;
 173                 dev_priv->ring.map.size = 0;
 174         }
 175
 176         if (I915_NEED_GFX_HWS(dev))
 177                 i915_free_hardware_status(dev);
 178
 179         return 0;
 180 }
 181
 182 #if defined(I915_HAVE_BUFFER)
 183 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 184 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 185 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 186         ((void *) ((unsigned char *) (p) +                      \
 187                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 188
 189 #define DRI2_SAREA_BLOCK_END            0x0000
 190 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 191 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 192
 193 static int
 194 setup_dri2_sarea(struct drm_device * dev,
 195                  struct drm_file *file_priv,
 196                  drm_i915_init_t * init)
 197 {
 198         drm_i915_private_t *dev_priv = dev->dev_private;
 199         int ret;
 200         unsigned int *p, *end, *next;
 201
 202         mutex_lock(&dev->struct_mutex);
 203         dev_priv->sarea_bo =
 204                 drm_lookup_buffer_object(file_priv,
 205                                          init->sarea_handle, 1);
 206         mutex_unlock(&dev->struct_mutex);
 207
 208         if (!dev_priv->sarea_bo) {
 209                 DRM_ERROR("did not find sarea bo\n");
 210                 return -EINVAL;
 211         }
 212
 213         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 214                           dev_priv->sarea_bo->num_pages,
 215                           &dev_priv->sarea_kmap);
 216         if (ret) {
 217                 DRM_ERROR("could not map sarea bo\n");
 218                 return ret;
 219         }
 220
 221         p = dev_priv->sarea_kmap.virtual;
 222         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 223         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 224                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 225                 case DRI2_SAREA_BLOCK_LOCK:
 226                         dev->lock.hw_lock = (void *) (p + 1);
 227                         dev->sigdata.lock = dev->lock.hw_lock;
 228                         break;
 229                 }
 230                 next = DRI2_SAREA_BLOCK_NEXT(p);
 231                 if (next <= p || end < next) {
 232                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 233                                   next, p, end);
 234                         return -EINVAL;
 235                 }
 236                 p = next;
 237         }
 238
 239         return 0;
 240 }
 241 #endif
 242
 243 static int i915_initialize(struct drm_device * dev,
 244                            struct drm_file *file_priv,
 245                            drm_i915_init_t * init)
 246 {
 247         drm_i915_private_t *dev_priv = dev->dev_private;
 248 #if defined(I915_HAVE_BUFFER)
 249         int ret;
 250 #endif
 251         dev_priv->sarea = drm_getsarea(dev);
 252         if (!dev_priv->sarea) {
 253                 DRM_ERROR("can not find sarea!\n");
 254                 i915_dma_cleanup(dev);
 255                 return -EINVAL;
 256         }
 257
 258 #ifdef I915_HAVE_BUFFER
 259         dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 260 #endif
 261
 262         if (init->sarea_priv_offset)
 263                 dev_priv->sarea_priv = (drm_i915_sarea_t *)
 264                         ((u8 *) dev_priv->sarea->handle +
 265                          init->sarea_priv_offset);
 266         else {
 267                 /* No sarea_priv for you! */
 268                 dev_priv->sarea_priv = NULL;
 269         }
 270
 271         if (init->ring_size != 0) {
 272                 dev_priv->ring.Size = init->ring_size;
 273                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 274
 275                 dev_priv->ring.map.offset = init->ring_start;
 276                 dev_priv->ring.map.size = init->ring_size;
 277                 dev_priv->ring.map.type = 0;
 278                 dev_priv->ring.map.flags = 0;
 279                 dev_priv->ring.map.mtrr = 0;
 280
 281                 drm_core_ioremap(&dev_priv->ring.map, dev);
 282
 283                 if (dev_priv->ring.map.handle == NULL) {
 284                         i915_dma_cleanup(dev);
 285                         DRM_ERROR("can not ioremap virtual address for"
 286                                   " ring buffer\n");
 287                         return -ENOMEM;
 288                 }
 289
 290                 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 291         }
 292
 293         dev_priv->cpp = init->cpp;
 294
 295         if (dev_priv->sarea_priv)
 296                 dev_priv->sarea_priv->pf_current_page = 0;
 297
 298         /* We are using separate values as placeholders for mechanisms for
 299          * private backbuffer/depthbuffer usage.
 300          */
 301
 302         /* Allow hardware batchbuffers unless told otherwise.
 303          */
 304         dev_priv->allow_batchbuffer = 1;
 305
 306         /* Enable vblank on pipe A for older X servers
 307          */
 308         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 309
 310 #ifdef I915_HAVE_BUFFER
 311         mutex_init(&dev_priv->cmdbuf_mutex);
 312 #endif
 313 #if defined(I915_HAVE_BUFFER)
 314         if (init->func == I915_INIT_DMA2) {
 315                 ret = setup_dri2_sarea(dev, file_priv, init);
 316                 if (ret) {
 317                         i915_dma_cleanup(dev);
 318                         DRM_ERROR("could not set up dri2 sarea\n");
 319                         return ret;
 320                 }
 321         }
 322 #endif
 323
 324         return 0;
 325 }
 326
 327 static int i915_dma_resume(struct drm_device * dev)
 328 {
 329         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 330
 331         DRM_DEBUG("\n");
 332
 333         if (!dev_priv->sarea) {
 334                 DRM_ERROR("can not find sarea!\n");
 335                 return -EINVAL;
 336         }
 337
 338         if (dev_priv->ring.map.handle == NULL) {
 339                 DRM_ERROR("can not ioremap virtual address for"
 340                           " ring buffer\n");
 341                 return -ENOMEM;
 342         }
 343
 344         /* Program Hardware Status Page */
 345         if (!dev_priv->hw_status_page) {
 346                 DRM_ERROR("Can not find hardware status page\n");
 347                 return -EINVAL;
 348         }
 349         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 350
 351         if (dev_priv->status_gfx_addr != 0)
 352                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 353         else
 354                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 355         DRM_DEBUG("Enabled hardware status page\n");
 356
 357         return 0;
 358 }
 359
 360 static int i915_dma_init(struct drm_device *dev, void *data,
 361                          struct drm_file *file_priv)
 362 {
 363         drm_i915_init_t *init = data;
 364         int retcode = 0;
 365
 366         switch (init->func) {
 367         case I915_INIT_DMA:
 368         case I915_INIT_DMA2:
 369                 retcode = i915_initialize(dev, file_priv, init);
 370                 break;
 371         case I915_CLEANUP_DMA:
 372                 retcode = i915_dma_cleanup(dev);
 373                 break;
 374         case I915_RESUME_DMA:
 375                 retcode = i915_dma_resume(dev);
 376                 break;
 377         default:
 378                 retcode = -EINVAL;
 379                 break;
 380         }
 381
 382         return retcode;
 383 }
 384
 385 /* Implement basically the same security restrictions as hardware does
 386  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 387  *
 388  * Most of the calculations below involve calculating the size of a
 389  * particular instruction.  It's important to get the size right as
 390  * that tells us where the next instruction to check is.  Any illegal
 391  * instruction detected will be given a size of zero, which is a
 392  * signal to abort the rest of the buffer.
 393  */
 394 static int do_validate_cmd(int cmd)
 395 {
 396         switch (((cmd >> 29) & 0x7)) {
 397         case 0x0:
 398                 switch ((cmd >> 23) & 0x3f) {
 399                 case 0x0:
 400                         return 1;       /* MI_NOOP */
 401                 case 0x4:
 402                         return 1;       /* MI_FLUSH */
 403                 default:
 404                         return 0;       /* disallow everything else */
 405                 }
 406                 break;
 407         case 0x1:
 408                 return 0;       /* reserved */
 409         case 0x2:
 410                 return (cmd & 0xff) + 2;        /* 2d commands */
 411         case 0x3:
 412                 if (((cmd >> 24) & 0x1f) <= 0x18)
 413                         return 1;
 414
 415                 switch ((cmd >> 24) & 0x1f) {
 416                 case 0x1c:
 417                         return 1;
 418                 case 0x1d:
 419                         switch ((cmd >> 16) & 0xff) {
 420                         case 0x3:
 421                                 return (cmd & 0x1f) + 2;
 422                         case 0x4:
 423                                 return (cmd & 0xf) + 2;
 424                         default:
 425                                 return (cmd & 0xffff) + 2;
 426                         }
 427                 case 0x1e:
 428                         if (cmd & (1 << 23))
 429                                 return (cmd & 0xffff) + 1;
 430                         else
 431                                 return 1;
 432                 case 0x1f:
 433                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 434                                 return (cmd & 0x1ffff) + 2;
 435                         else if (cmd & (1 << 17))       /* indirect random */
 436                                 if ((cmd & 0xffff) == 0)
 437                                         return 0;       /* unknown length, too hard */
 438                                 else
 439                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 440                         else
 441                                 return 2;       /* indirect sequential */
 442                 default:
 443                         return 0;
 444                 }
 445         default:
 446                 return 0;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int validate_cmd(int cmd)
 453 {
 454         int ret = do_validate_cmd(cmd);
 455
 456 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 457
 458         return ret;
 459 }
 460
 461 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 462                           int dwords)
 463 {
 464         drm_i915_private_t *dev_priv = dev->dev_private;
 465         int i;
 466         RING_LOCALS;
 467
 468         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 469                 return -EINVAL;
 470
 471         BEGIN_LP_RING((dwords+1)&~1);
 472
 473         for (i = 0; i < dwords;) {
 474                 int cmd, sz;
 475
 476                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 477                         return -EINVAL;
 478
 479                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 480                         return -EINVAL;
 481
 482                 OUT_RING(cmd);
 483
 484                 while (++i, --sz) {
 485                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 486                                                          sizeof(cmd))) {
 487                                 return -EINVAL;
 488                         }
 489                         OUT_RING(cmd);
 490                 }
 491         }
 492
 493         if (dwords & 1)
 494                 OUT_RING(0);
 495
 496         ADVANCE_LP_RING();
 497
 498         return 0;
 499 }
 500
 501 int i915_emit_box(struct drm_device * dev,
 502                   struct drm_clip_rect __user * boxes,
 503                   int i, int DR1, int DR4)
 504 {
 505         drm_i915_private_t *dev_priv = dev->dev_private;
 506         struct drm_clip_rect box;
 507         RING_LOCALS;
 508
 509         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 510                 return -EFAULT;
 511         }
 512
 513         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 514                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 515                           box.x1, box.y1, box.x2, box.y2);
 516                 return -EINVAL;
 517         }
 518
 519         if (IS_I965G(dev)) {
 520                 BEGIN_LP_RING(4);
 521                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 522                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 523                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 524                 OUT_RING(DR4);
 525                 ADVANCE_LP_RING();
 526         } else {
 527                 BEGIN_LP_RING(6);
 528                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 529                 OUT_RING(DR1);
 530                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 531                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 532                 OUT_RING(DR4);
 533                 OUT_RING(0);
 534                 ADVANCE_LP_RING();
 535         }
 536
 537         return 0;
 538 }
 539
 540 /* XXX: Emitting the counter should really be moved to part of the IRQ
 541  * emit. For now, do it in both places:
 542  */
 543
 544 void i915_emit_breadcrumb(struct drm_device *dev)
 545 {
 546         drm_i915_private_t *dev_priv = dev->dev_private;
 547         RING_LOCALS;
 548
 549         if (++dev_priv->counter > BREADCRUMB_MASK) {
 550                  dev_priv->counter = 1;
 551                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 552         }
 553
 554         if (dev_priv->sarea_priv)
 555                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 556
 557         BEGIN_LP_RING(4);
 558         OUT_RING(MI_STORE_DWORD_INDEX);
 559         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 560         OUT_RING(dev_priv->counter);
 561         OUT_RING(0);
 562         ADVANCE_LP_RING();
 563 }
 564
 565
 566 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 567 {
 568         drm_i915_private_t *dev_priv = dev->dev_private;
 569         uint32_t flush_cmd = MI_FLUSH;
 570         RING_LOCALS;
 571
 572         flush_cmd |= flush;
 573
 574         i915_kernel_lost_context(dev);
 575
 576         BEGIN_LP_RING(4);
 577         OUT_RING(flush_cmd);
 578         OUT_RING(0);
 579         OUT_RING(0);
 580         OUT_RING(0);
 581         ADVANCE_LP_RING();
 582
 583         return 0;
 584 }
 585
 586
 587 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 588                                    drm_i915_cmdbuffer_t * cmd)
 589 {
 590 #ifdef I915_HAVE_FENCE
 591         drm_i915_private_t *dev_priv = dev->dev_private;
 592 #endif
 593         int nbox = cmd->num_cliprects;
 594         int i = 0, count, ret;
 595
 596         if (cmd->sz & 0x3) {
 597                 DRM_ERROR("alignment\n");
 598                 return -EINVAL;
 599         }
 600
 601         i915_kernel_lost_context(dev);
 602
 603         count = nbox ? nbox : 1;
 604
 605         for (i = 0; i < count; i++) {
 606                 if (i < nbox) {
 607                         ret = i915_emit_box(dev, cmd->cliprects, i,
 608                                             cmd->DR1, cmd->DR4);
 609                         if (ret)
 610                                 return ret;
 611                 }
 612
 613                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 614                 if (ret)
 615                         return ret;
 616         }
 617
 618         i915_emit_breadcrumb(dev);
 619 #ifdef I915_HAVE_FENCE
 620         if (unlikely((dev_priv->counter & 0xFF) == 0))
 621                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 622 #endif
 623         return 0;
 624 }
 625
 626 int i915_dispatch_batchbuffer(struct drm_device * dev,
 627                               drm_i915_batchbuffer_t * batch)
 628 {
 629         drm_i915_private_t *dev_priv = dev->dev_private;
 630         struct drm_clip_rect __user *boxes = batch->cliprects;
 631         int nbox = batch->num_cliprects;
 632         int i = 0, count;
 633         RING_LOCALS;
 634
 635         if ((batch->start | batch->used) & 0x7) {
 636                 DRM_ERROR("alignment\n");
 637                 return -EINVAL;
 638         }
 639
 640         i915_kernel_lost_context(dev);
 641
 642         count = nbox ? nbox : 1;
 643
 644         for (i = 0; i < count; i++) {
 645                 if (i < nbox) {
 646                         int ret = i915_emit_box(dev, boxes, i,
 647                                                 batch->DR1, batch->DR4);
 648                         if (ret)
 649                                 return ret;
 650                 }
 651
 652                 if (IS_I830(dev) || IS_845G(dev)) {
 653                         BEGIN_LP_RING(4);
 654                         OUT_RING(MI_BATCH_BUFFER);
 655                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 656                         OUT_RING(batch->start + batch->used - 4);
 657                         OUT_RING(0);
 658                         ADVANCE_LP_RING();
 659                 } else {
 660                         BEGIN_LP_RING(2);
 661                         if (IS_I965G(dev)) {
 662                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 663                                 OUT_RING(batch->start);
 664                         } else {
 665                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 666                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 667                         }
 668                         ADVANCE_LP_RING();
 669                 }
 670         }
 671
 672         i915_emit_breadcrumb(dev);
 673 #ifdef I915_HAVE_FENCE
 674         if (unlikely((dev_priv->counter & 0xFF) == 0))
 675                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 676 #endif
 677         return 0;
 678 }
 679
 680 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 681 {
 682         drm_i915_private_t *dev_priv = dev->dev_private;
 683         u32 num_pages, current_page, next_page, dspbase;
 684         int shift = 2 * plane, x, y;
 685         RING_LOCALS;
 686
 687         /* Calculate display base offset */
 688         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 689         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 690         next_page = (current_page + 1) % num_pages;
 691
 692         switch (next_page) {
 693         default:
 694         case 0:
 695                 dspbase = dev_priv->sarea_priv->front_offset;
 696                 break;
 697         case 1:
 698                 dspbase = dev_priv->sarea_priv->back_offset;
 699                 break;
 700         case 2:
 701                 dspbase = dev_priv->sarea_priv->third_offset;
 702                 break;
 703         }
 704
 705         if (plane == 0) {
 706                 x = dev_priv->sarea_priv->planeA_x;
 707                 y = dev_priv->sarea_priv->planeA_y;
 708         } else {
 709                 x = dev_priv->sarea_priv->planeB_x;
 710                 y = dev_priv->sarea_priv->planeB_y;
 711         }
 712
 713         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 714
 715         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 716                   dspbase);
 717
 718         BEGIN_LP_RING(4);
 719         OUT_RING(sync ? 0 :
 720                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 721                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 722         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 723                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 724         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 725         OUT_RING(dspbase);
 726         ADVANCE_LP_RING();
 727
 728         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 729         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
 730 }
 731
 732 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 733 {
 734         drm_i915_private_t *dev_priv = dev->dev_private;
 735         int i;
 736
 737         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 738                   planes, dev_priv->sarea_priv->pf_current_page);
 739
 740         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 741
 742         for (i = 0; i < 2; i++)
 743                 if (planes & (1 << i))
 744                         i915_do_dispatch_flip(dev, i, sync);
 745
 746         i915_emit_breadcrumb(dev);
 747 #ifdef I915_HAVE_FENCE
 748         if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
 749                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 750 #endif
 751 }
 752
 753 int i915_quiescent(struct drm_device *dev)
 754 {
 755         drm_i915_private_t *dev_priv = dev->dev_private;
 756         int ret;
 757
 758         i915_kernel_lost_context(dev);
 759         ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 760         if (ret)
 761         {
 762                 i915_kernel_lost_context (dev);
 763                 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
 764                            dev_priv->ring.head,
 765                            dev_priv->ring.tail,
 766                            dev_priv->ring.space);
 767         }
 768         return ret;
 769 }
 770
 771 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 772                             struct drm_file *file_priv)
 773 {
 774
 775         LOCK_TEST_WITH_RETURN(dev, file_priv);
 776
 777         return i915_quiescent(dev);
 778 }
 779
 780 static int i915_batchbuffer(struct drm_device *dev, void *data,
 781                             struct drm_file *file_priv)
 782 {
 783         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 784         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 785             dev_priv->sarea_priv;
 786         drm_i915_batchbuffer_t *batch = data;
 787         int ret;
 788
 789         if (!dev_priv->allow_batchbuffer) {
 790                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 791                 return -EINVAL;
 792         }
 793
 794         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 795                   batch->start, batch->used, batch->num_cliprects);
 796
 797         LOCK_TEST_WITH_RETURN(dev, file_priv);
 798
 799         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 800                                                         batch->num_cliprects *
 801                                                         sizeof(struct drm_clip_rect)))
 802                 return -EFAULT;
 803
 804         ret = i915_dispatch_batchbuffer(dev, batch);
 805
 806         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 807         return ret;
 808 }
 809
 810 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 811                           struct drm_file *file_priv)
 812 {
 813         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 814         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 815             dev_priv->sarea_priv;
 816         drm_i915_cmdbuffer_t *cmdbuf = data;
 817         int ret;
 818
 819         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 820                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 821
 822         LOCK_TEST_WITH_RETURN(dev, file_priv);
 823
 824         if (cmdbuf->num_cliprects &&
 825             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 826                                 cmdbuf->num_cliprects *
 827                                 sizeof(struct drm_clip_rect))) {
 828                 DRM_ERROR("Fault accessing cliprects\n");
 829                 return -EFAULT;
 830         }
 831
 832         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 833         if (ret) {
 834                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 835                 return ret;
 836         }
 837
 838         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 839         return 0;
 840 }
 841
 842 #if defined(DRM_DEBUG_CODE)
 843 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 844 #else
 845 #define DRM_DEBUG_RELOCATION    0
 846 #endif
 847
 848 static int i915_do_cleanup_pageflip(struct drm_device * dev)
 849 {
 850         drm_i915_private_t *dev_priv = dev->dev_private;
 851         int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 852
 853         DRM_DEBUG("\n");
 854
 855         for (i = 0, planes = 0; i < 2; i++)
 856                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 857                         dev_priv->sarea_priv->pf_current_page =
 858                                 (dev_priv->sarea_priv->pf_current_page &
 859                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 860
 861                         planes |= 1 << i;
 862                 }
 863
 864         if (planes)
 865                 i915_dispatch_flip(dev, planes, 0);
 866
 867         return 0;
 868 }
 869
 870 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 871 {
 872         drm_i915_flip_t *param = data;
 873
 874         DRM_DEBUG("\n");
 875
 876         LOCK_TEST_WITH_RETURN(dev, file_priv);
 877
 878         /* This is really planes */
 879         if (param->pipes & ~0x3) {
 880                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 881                           param->pipes);
 882                 return -EINVAL;
 883         }
 884
 885         i915_dispatch_flip(dev, param->pipes, 0);
 886
 887         return 0;
 888 }
 889
 890
 891 static int i915_getparam(struct drm_device *dev, void *data,
 892                          struct drm_file *file_priv)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         drm_i915_getparam_t *param = data;
 896         int value;
 897
 898         if (!dev_priv) {
 899                 DRM_ERROR("called with no initialization\n");
 900                 return -EINVAL;
 901         }
 902
 903         switch (param->param) {
 904         case I915_PARAM_IRQ_ACTIVE:
 905                 value = dev->irq_enabled ? 1 : 0;
 906                 break;
 907         case I915_PARAM_ALLOW_BATCHBUFFER:
 908                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 909                 break;
 910         case I915_PARAM_LAST_DISPATCH:
 911                 value = READ_BREADCRUMB(dev_priv);
 912                 break;
 913         case I915_PARAM_CHIPSET_ID:
 914                 value = dev->pci_device;
 915                 break;
 916         case I915_PARAM_HAS_GEM:
 917                 value = 1;
 918                 break;
 919         default:
 920                 DRM_ERROR("Unknown parameter %d\n", param->param);
 921                 return -EINVAL;
 922         }
 923
 924         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 925                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 926                 return -EFAULT;
 927         }
 928
 929         return 0;
 930 }
 931
 932 static int i915_setparam(struct drm_device *dev, void *data,
 933                          struct drm_file *file_priv)
 934 {
 935         drm_i915_private_t *dev_priv = dev->dev_private;
 936         drm_i915_setparam_t *param = data;
 937
 938         if (!dev_priv) {
 939                 DRM_ERROR("called with no initialization\n");
 940                 return -EINVAL;
 941         }
 942
 943         switch (param->param) {
 944         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 945                 break;
 946         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 947                 dev_priv->tex_lru_log_granularity = param->value;
 948                 break;
 949         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 950                 dev_priv->allow_batchbuffer = param->value;
 951                 break;
 952         default:
 953                 DRM_ERROR("unknown parameter %d\n", param->param);
 954                 return -EINVAL;
 955         }
 956
 957         return 0;
 958 }
 959
 960 drm_i915_mmio_entry_t mmio_table[] = {
 961         [MMIO_REGS_PS_DEPTH_COUNT] = {
 962                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 963                 0x2350,
 964                 8
 965         }
 966 };
 967
 968 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 969
 970 static int i915_mmio(struct drm_device *dev, void *data,
 971                      struct drm_file *file_priv)
 972 {
 973         uint32_t buf[8];
 974         drm_i915_private_t *dev_priv = dev->dev_private;
 975         drm_i915_mmio_entry_t *e;
 976         drm_i915_mmio_t *mmio = data;
 977         void __iomem *base;
 978         int i;
 979
 980         if (!dev_priv) {
 981                 DRM_ERROR("called with no initialization\n");
 982                 return -EINVAL;
 983         }
 984
 985         if (mmio->reg >= mmio_table_size)
 986                 return -EINVAL;
 987
 988         e = &mmio_table[mmio->reg];
 989         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 990
 991         switch (mmio->read_write) {
 992         case I915_MMIO_READ:
 993                 if (!(e->flag & I915_MMIO_MAY_READ))
 994                         return -EINVAL;
 995                 for (i = 0; i < e->size / 4; i++)
 996                         buf[i] = I915_READ(e->offset + i * 4);
 997                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 998                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 999                         return -EFAULT;
1000                 }
1001                 break;
1002
1003         case I915_MMIO_WRITE:
1004                 if (!(e->flag & I915_MMIO_MAY_WRITE))
1005                         return -EINVAL;
1006                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
1007                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
1008                         return -EFAULT;
1009                 }
1010                 for (i = 0; i < e->size / 4; i++)
1011                         I915_WRITE(e->offset + i * 4, buf[i]);
1012                 break;
1013         }
1014         return 0;
1015 }
1016
1017 static int i915_set_status_page(struct drm_device *dev, void *data,
1018                                 struct drm_file *file_priv)
1019 {
1020         drm_i915_private_t *dev_priv = dev->dev_private;
1021         drm_i915_hws_addr_t *hws = data;
1022
1023         if (!I915_NEED_GFX_HWS(dev))
1024                 return -EINVAL;
1025
1026         if (!dev_priv) {
1027                 DRM_ERROR("called with no initialization\n");
1028                 return -EINVAL;
1029         }
1030         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1031
1032         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1033
1034         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1035         dev_priv->hws_map.size = 4*1024;
1036         dev_priv->hws_map.type = 0;
1037         dev_priv->hws_map.flags = 0;
1038         dev_priv->hws_map.mtrr = 0;
1039
1040         drm_core_ioremap(&dev_priv->hws_map, dev);
1041         if (dev_priv->hws_map.handle == NULL) {
1042                 i915_dma_cleanup(dev);
1043                 dev_priv->status_gfx_addr = 0;
1044                 DRM_ERROR("can not ioremap virtual address for"
1045                                 " G33 hw status page\n");
1046                 return -ENOMEM;
1047         }
1048         dev_priv->hw_status_page = dev_priv->hws_map.handle;
1049
1050         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1051         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1052         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1053                         dev_priv->status_gfx_addr);
1054         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1055         return 0;
1056 }
1057
1058 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1059 {
1060         struct drm_i915_private *dev_priv;
1061         unsigned long base, size;
1062         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1063
1064         /* i915 has 4 more counters */
1065         dev->counters += 4;
1066         dev->types[6] = _DRM_STAT_IRQ;
1067         dev->types[7] = _DRM_STAT_PRIMARY;
1068         dev->types[8] = _DRM_STAT_SECONDARY;
1069         dev->types[9] = _DRM_STAT_DMA;
1070
1071         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1072         if (dev_priv == NULL)
1073                 return -ENOMEM;
1074
1075         memset(dev_priv, 0, sizeof(drm_i915_private_t));
1076
1077         dev->dev_private = (void *)dev_priv;
1078         dev_priv->dev = dev;
1079
1080         /* Add register map (needed for suspend/resume) */
1081         base = drm_get_resource_start(dev, mmio_bar);
1082         size = drm_get_resource_len(dev, mmio_bar);
1083
1084         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1085                 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1086 #ifdef I915_HAVE_GEM
1087         i915_gem_load(dev);
1088 #endif
1089         DRM_SPININIT(&dev_priv->swaps_lock, "swap");
1090         DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
1091
1092 #ifdef __linux__
1093 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1094         intel_init_chipset_flush_compat(dev);
1095 #endif
1096 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
1097         intel_opregion_init(dev);
1098 #endif
1099 #endif
1100
1101         /* Init HWS */
1102         if (!I915_NEED_GFX_HWS(dev)) {
1103                 ret = i915_init_hardware_status(dev);
1104                 if(ret)
1105                         return ret;
1106         }
1107
1108         return ret;
1109 }
1110
1111 int i915_driver_unload(struct drm_device *dev)
1112 {
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114
1115         i915_free_hardware_status(dev);
1116
1117         drm_rmmap(dev, dev_priv->mmio_map);
1118
1119         DRM_SPINUNINIT(&dev_priv->swaps_lock);
1120         DRM_SPINUNINIT(&dev_priv->user_irq_lock);
1121
1122 #ifdef __linux__
1123 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
1124         intel_opregion_free(dev);
1125 #endif
1126 #endif
1127
1128         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1129                  DRM_MEM_DRIVER);
1130         dev->dev_private = NULL;
1131
1132 #ifdef __linux__
1133 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1134         intel_fini_chipset_flush_compat(dev);
1135 #endif
1136 #endif
1137         return 0;
1138 }
1139
1140 void i915_driver_lastclose(struct drm_device * dev)
1141 {
1142         drm_i915_private_t *dev_priv = dev->dev_private;
1143
1144         /* agp off can use this to get called before dev_priv */
1145         if (!dev_priv)
1146                 return;
1147
1148 #ifdef I915_HAVE_BUFFER
1149         if (dev_priv->val_bufs) {
1150                 vfree(dev_priv->val_bufs);
1151                 dev_priv->val_bufs = NULL;
1152         }
1153 #endif
1154 #ifdef I915_HAVE_GEM
1155         i915_gem_lastclose(dev);
1156 #endif
1157         if (drm_getsarea(dev) && dev_priv->sarea_priv)
1158                 i915_do_cleanup_pageflip(dev);
1159         if (dev_priv->sarea_priv)
1160                 dev_priv->sarea_priv = NULL;
1161         if (dev_priv->agp_heap)
1162                 i915_mem_takedown(&(dev_priv->agp_heap));
1163 #if defined(I915_HAVE_BUFFER)
1164         if (dev_priv->sarea_kmap.virtual) {
1165                 drm_bo_kunmap(&dev_priv->sarea_kmap);
1166                 dev_priv->sarea_kmap.virtual = NULL;
1167                 dev->lock.hw_lock = NULL;
1168                 dev->sigdata.lock = NULL;
1169         }
1170
1171         if (dev_priv->sarea_bo) {
1172                 mutex_lock(&dev->struct_mutex);
1173                 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
1174                 mutex_unlock(&dev->struct_mutex);
1175                 dev_priv->sarea_bo = NULL;
1176         }
1177 #endif
1178         i915_dma_cleanup(dev);
1179 }
1180
1181 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1182 {
1183         struct drm_i915_file_private *i915_file_priv;
1184
1185         DRM_DEBUG("\n");
1186         i915_file_priv = (struct drm_i915_file_private *)
1187             drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1188
1189         if (!i915_file_priv)
1190                 return -ENOMEM;
1191
1192         file_priv->driver_priv = i915_file_priv;
1193
1194         i915_file_priv->mm.last_gem_seqno = 0;
1195         i915_file_priv->mm.last_gem_throttle_seqno = 0;
1196
1197         return 0;
1198 }
1199
1200 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1201 {
1202         drm_i915_private_t *dev_priv = dev->dev_private;
1203         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1204 }
1205
1206 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1207 {
1208         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1209
1210         drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1211 }
1212
1213 struct drm_ioctl_desc i915_ioctls[] = {
1214         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1215         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1216         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1217         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1218         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1219         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1220         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1221         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1222         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1223         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1224         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1225         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1226         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1227         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1228         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1229         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1230         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1231         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1232 #ifdef I915_HAVE_BUFFER
1233         DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1234 #endif
1235 #ifdef I915_HAVE_GEM
1236         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
1237         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1238         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1239         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1240         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1241         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1242         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH),
1243         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH),
1244         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1245         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1246         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1247         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1248         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1249         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1250         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1251         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1252 #endif
1253 };
1254
1255 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1256
1257 /**
1258  * Determine if the device really is AGP or not.
1259  *
1260  * All Intel graphics chipsets are treated as AGP, even if they are really
1261  * PCI-e.
1262  *
1263  * \param dev   The device to be tested.
1264  *
1265  * \returns
1266  * A value of 1 is always retured to indictate every i9x5 is AGP.
1267  */
1268 int i915_driver_device_is_agp(struct drm_device * dev)
1269 {
1270         return 1;
1271 }
1272
1273 int i915_driver_firstopen(struct drm_device *dev)
1274 {
1275 #ifdef I915_HAVE_BUFFER
1276         drm_bo_driver_init(dev);
1277 #endif
1278         return 0;
1279 }