sys/dev/drm/i915_drm.h

   1 /* $FreeBSD$ */
   2
   3 #ifndef _I915_DRM_H_
   4 #define _I915_DRM_H_
   5
   6 /* Please note that modifications to all structs defined here are
   7  * subject to backwards-compatibility constraints.
   8  */
   9
  10 #include "drm.h"
  11
  12 /* Each region is a minimum of 16k, and there are at most 255 of them.
  13  */
  14 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  15                                  * of chars for next/prev indices */
  16 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  17
  18 typedef struct _drm_i915_init {
  19         enum {
  20                 I915_INIT_DMA = 0x01,
  21                 I915_CLEANUP_DMA = 0x02,
  22                 I915_RESUME_DMA = 0x03
  23         } func;
  24         unsigned int mmio_offset;
  25         int sarea_priv_offset;
  26         unsigned int ring_start;
  27         unsigned int ring_end;
  28         unsigned int ring_size;
  29         unsigned int front_offset;
  30         unsigned int back_offset;
  31         unsigned int depth_offset;
  32         unsigned int w;
  33         unsigned int h;
  34         unsigned int pitch;
  35         unsigned int pitch_bits;
  36         unsigned int back_pitch;
  37         unsigned int depth_pitch;
  38         unsigned int cpp;
  39         unsigned int chipset;
  40 } drm_i915_init_t;
  41
  42 typedef struct _drm_i915_sarea {
  43         drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
  44         int last_upload;        /* last time texture was uploaded */
  45         int last_enqueue;       /* last time a buffer was enqueued */
  46         int last_dispatch;      /* age of the most recently dispatched buffer */
  47         int ctxOwner;           /* last context to upload state */
  48         int texAge;
  49         int pf_enabled;         /* is pageflipping allowed? */
  50         int pf_active;
  51         int pf_current_page;    /* which buffer is being displayed? */
  52         int perf_boxes;         /* performance boxes to be displayed */
  53 } drm_i915_sarea_t;
  54
  55 /* Flags for perf_boxes
  56  */
  57 #define I915_BOX_RING_EMPTY    0x1
  58 #define I915_BOX_FLIP          0x2
  59 #define I915_BOX_WAIT          0x4
  60 #define I915_BOX_TEXTURE_LOAD  0x8
  61 #define I915_BOX_LOST_CONTEXT  0x10
  62
  63 /* I915 specific ioctls
  64  * The device specific ioctl range is 0x40 to 0x79.
  65  */
  66 #define DRM_I915_INIT           0x00
  67 #define DRM_I915_FLUSH          0x01
  68 #define DRM_I915_FLIP           0x02
  69 #define DRM_I915_BATCHBUFFER    0x03
  70 #define DRM_I915_IRQ_EMIT       0x04
  71 #define DRM_I915_IRQ_WAIT       0x05
  72 #define DRM_I915_GETPARAM       0x06
  73 #define DRM_I915_SETPARAM       0x07
  74 #define DRM_I915_ALLOC          0x08
  75 #define DRM_I915_FREE           0x09
  76 #define DRM_I915_INIT_HEAP      0x0a
  77 #define DRM_I915_CMDBUFFER      0x0b
  78
  79 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
  80 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
  81 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
  82 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
  83 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
  84 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
  85 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
  86 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
  87 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
  88 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
  89 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
  90 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
  91
  92 /* Allow drivers to submit batchbuffers directly to hardware, relying
  93  * on the security mechanisms provided by hardware.
  94  */
  95 typedef struct _drm_i915_batchbuffer {
  96         int start;              /* agp offset */
  97         int used;               /* nr bytes in use */
  98         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
  99         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 100         int num_cliprects;      /* mulitpass with multiple cliprects? */
 101         drm_clip_rect_t __user *cliprects;      /* pointer to userspace cliprects */
 102 } drm_i915_batchbuffer_t;
 103
 104 /* As above, but pass a pointer to userspace buffer which can be
 105  * validated by the kernel prior to sending to hardware.
 106  */
 107 typedef struct _drm_i915_cmdbuffer {
 108         char __user *buf;       /* pointer to userspace command buffer */
 109         int sz;                 /* nr bytes in buf */
 110         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 111         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 112         int num_cliprects;      /* mulitpass with multiple cliprects? */
 113         drm_clip_rect_t __user *cliprects;      /* pointer to userspace cliprects */
 114 } drm_i915_cmdbuffer_t;
 115
 116 /* Userspace can request & wait on irq's:
 117  */
 118 typedef struct drm_i915_irq_emit {
 119         int __user *irq_seq;
 120 } drm_i915_irq_emit_t;
 121
 122 typedef struct drm_i915_irq_wait {
 123         int irq_seq;
 124 } drm_i915_irq_wait_t;
 125
 126 /* Ioctl to query kernel params:
 127  */
 128 #define I915_PARAM_IRQ_ACTIVE            1
 129 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 130
 131 typedef struct drm_i915_getparam {
 132         int param;
 133         int __user *value;
 134 } drm_i915_getparam_t;
 135
 136 /* Ioctl to set kernel params:
 137  */
 138 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 139 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 140 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 141
 142 typedef struct drm_i915_setparam {
 143         int param;
 144         int value;
 145 } drm_i915_setparam_t;
 146
 147 /* A memory manager for regions of shared memory:
 148  */
 149 #define I915_MEM_REGION_AGP 1
 150
 151 typedef struct drm_i915_mem_alloc {
 152         int region;
 153         int alignment;
 154         int size;
 155         int __user *region_offset;      /* offset from start of fb or agp */
 156 } drm_i915_mem_alloc_t;
 157
 158 typedef struct drm_i915_mem_free {
 159         int region;
 160         int region_offset;
 161 } drm_i915_mem_free_t;
 162
 163 typedef struct drm_i915_mem_init_heap {
 164         int region;
 165         int size;
 166         int start;
 167 } drm_i915_mem_init_heap_t;
 168
 169 #endif                          /* _I915_DRM_H_ */