2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
33 /* Please note that modifications to all structs defined here are
34 * subject to backwards-compatibility constraints.
37 #include "dev/drm/drm.h"
39 /* Each region is a minimum of 16k, and there are at most 255 of them.
41 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
42 * of chars for next/prev indices */
43 #define I915_LOG_MIN_TEX_REGION_SIZE 14
45 typedef struct _drm_i915_init {
48 I915_CLEANUP_DMA = 0x02,
49 I915_RESUME_DMA = 0x03
51 unsigned int mmio_offset;
52 int sarea_priv_offset;
53 unsigned int ring_start;
54 unsigned int ring_end;
55 unsigned int ring_size;
56 unsigned int front_offset;
57 unsigned int back_offset;
58 unsigned int depth_offset;
62 unsigned int pitch_bits;
63 unsigned int back_pitch;
64 unsigned int depth_pitch;
69 typedef struct _drm_i915_sarea {
70 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
71 int last_upload; /* last time texture was uploaded */
72 int last_enqueue; /* last time a buffer was enqueued */
73 int last_dispatch; /* age of the most recently dispatched buffer */
74 int ctxOwner; /* last context to upload state */
76 int pf_enabled; /* is pageflipping allowed? */
78 int pf_current_page; /* which buffer is being displayed? */
79 int perf_boxes; /* performance boxes to be displayed */
82 /* Flags for perf_boxes
84 #define I915_BOX_RING_EMPTY 0x1
85 #define I915_BOX_FLIP 0x2
86 #define I915_BOX_WAIT 0x4
87 #define I915_BOX_TEXTURE_LOAD 0x8
88 #define I915_BOX_LOST_CONTEXT 0x10
90 /* I915 specific ioctls
91 * The device specific ioctl range is 0x40 to 0x79.
93 #define DRM_I915_INIT 0x00
94 #define DRM_I915_FLUSH 0x01
95 #define DRM_I915_FLIP 0x02
96 #define DRM_I915_BATCHBUFFER 0x03
97 #define DRM_I915_IRQ_EMIT 0x04
98 #define DRM_I915_IRQ_WAIT 0x05
99 #define DRM_I915_GETPARAM 0x06
100 #define DRM_I915_SETPARAM 0x07
101 #define DRM_I915_ALLOC 0x08
102 #define DRM_I915_FREE 0x09
103 #define DRM_I915_INIT_HEAP 0x0a
104 #define DRM_I915_CMDBUFFER 0x0b
106 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
107 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
108 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
109 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
110 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
111 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
112 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
113 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
114 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
115 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
116 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
117 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
119 /* Allow drivers to submit batchbuffers directly to hardware, relying
120 * on the security mechanisms provided by hardware.
122 typedef struct _drm_i915_batchbuffer {
123 int start; /* agp offset */
124 int used; /* nr bytes in use */
125 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
126 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
127 int num_cliprects; /* mulitpass with multiple cliprects? */
128 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
129 } drm_i915_batchbuffer_t;
131 /* As above, but pass a pointer to userspace buffer which can be
132 * validated by the kernel prior to sending to hardware.
134 typedef struct _drm_i915_cmdbuffer {
135 char __user *buf; /* pointer to userspace command buffer */
136 int sz; /* nr bytes in buf */
137 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
138 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
139 int num_cliprects; /* mulitpass with multiple cliprects? */
140 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
141 } drm_i915_cmdbuffer_t;
143 /* Userspace can request & wait on irq's:
145 typedef struct drm_i915_irq_emit {
147 } drm_i915_irq_emit_t;
149 typedef struct drm_i915_irq_wait {
151 } drm_i915_irq_wait_t;
153 /* Ioctl to query kernel params:
155 #define I915_PARAM_IRQ_ACTIVE 1
156 #define I915_PARAM_ALLOW_BATCHBUFFER 2
158 typedef struct drm_i915_getparam {
161 } drm_i915_getparam_t;
163 /* Ioctl to set kernel params:
165 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
166 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
167 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
169 typedef struct drm_i915_setparam {
172 } drm_i915_setparam_t;
174 /* A memory manager for regions of shared memory:
176 #define I915_MEM_REGION_AGP 1
178 typedef struct drm_i915_mem_alloc {
182 int __user *region_offset; /* offset from start of fb or agp */
183 } drm_i915_mem_alloc_t;
185 typedef struct drm_i915_mem_free {
188 } drm_i915_mem_free_t;
190 typedef struct drm_i915_mem_init_heap {
194 } drm_i915_mem_init_heap_t;
196 #endif /* _I915_DRM_H_ */