1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
36 #include "dev/drm/drm_mm.h"
37 #include "dev/drm/i915_reg.h"
39 /* General customization:
42 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
44 #define DRIVER_NAME "i915"
45 #define DRIVER_DESC "Intel Graphics"
46 #define DRIVER_DATE "20080730"
53 #define I915_NUM_PIPE 2
58 * 1.2: Add Power Management
59 * 1.3: Add vblank support
60 * 1.4: Fix cmdbuffer path, add heap destroy
61 * 1.5: Add vblank pipe configuration
62 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
63 * - Support vertical blank on secondary display pipe
65 #define DRIVER_MAJOR 1
66 #define DRIVER_MINOR 6
67 #define DRIVER_PATCHLEVEL 0
69 #define WATCH_COHERENCY 0
74 #define WATCH_INACTIVE 0
75 #define WATCH_PWRITE 0
77 typedef struct _drm_i915_ring_buffer {
85 struct drm_gem_object *ring_obj;
86 } drm_i915_ring_buffer_t;
89 struct mem_block *next;
90 struct mem_block *prev;
93 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
96 struct opregion_header;
98 struct opregion_swsci;
101 struct intel_opregion {
102 struct opregion_header *header;
103 struct opregion_acpi *acpi;
104 struct opregion_swsci *swsci;
105 struct opregion_asle *asle;
109 typedef struct drm_i915_private {
110 struct drm_device *dev;
112 drm_local_map_t *sarea;
113 drm_local_map_t *mmio_map;
115 drm_i915_sarea_t *sarea_priv;
116 drm_i915_ring_buffer_t ring;
118 drm_dma_handle_t *status_page_dmah;
119 void *hw_status_page;
120 dma_addr_t dma_status_page;
122 unsigned int status_gfx_addr;
123 drm_local_map_t hws_map;
124 struct drm_gem_object *hws_obj;
132 wait_queue_head_t irq_queue;
133 /** Protects user_irq_refcount and irq_mask_reg */
134 DRM_SPINTYPE user_irq_lock;
135 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
136 int user_irq_refcount;
137 /** Cached value of IER to avoid reads in updating the bitfield */
141 int tex_lru_log_granularity;
142 int allow_batchbuffer;
143 struct mem_block *agp_heap;
144 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
147 struct intel_opregion opregion;
154 u32 saveRENDERSTANDBY;
178 u32 savePFIT_PGM_RATIOS;
180 u32 saveBLC_PWM_CTL2;
205 u32 savePP_ON_DELAYS;
206 u32 savePP_OFF_DELAYS;
214 u32 savePFIT_CONTROL;
215 u32 save_palette_a[256];
216 u32 save_palette_b[256];
217 u32 saveFBC_CFB_BASE;
220 u32 saveFBC_CONTROL2;
224 u32 saveCACHE_MODE_0;
227 u32 saveMI_ARB_STATE;
240 struct drm_mm gtt_space;
243 * List of objects currently involved in rendering from the
246 * A reference is held on the buffer while on this list.
248 struct list_head active_list;
251 * List of objects which are not in the ringbuffer but which
252 * still have a write_domain which needs to be flushed before
255 * A reference is held on the buffer while on this list.
257 struct list_head flushing_list;
260 * LRU list of objects which are not in the ringbuffer and
261 * are ready to unbind, but are still in the GTT.
263 * A reference is not held on the buffer while on this list,
264 * as merely being GTT-bound shouldn't prevent its being
265 * freed, and we'll pull it off the list in the free path.
267 struct list_head inactive_list;
270 * List of breadcrumbs associated with GPU requests currently
273 struct list_head request_list;
276 * We leave the user IRQ off as much as possible,
277 * but this means that requests will finish and never
278 * be retired once the system goes idle. Set a timer to
279 * fire periodically while the ring is running. When it
280 * fires, go retire requests.
282 struct delayed_work retire_work;
284 uint32_t next_gem_seqno;
287 * Waiting sequence number, if any
289 uint32_t waiting_gem_seqno;
292 * Last seq seen at irq time
294 uint32_t irq_gem_seqno;
297 * Flag if the X Server, and thus DRM, is not currently in
298 * control of the device.
300 * This is set between LeaveVT and EnterVT. It needs to be
301 * replaced with a semaphore. It also needs to be
302 * transitioned away from for kernel modesetting.
307 * Flag if the hardware appears to be wedged.
309 * This is set when attempts to idle the device timeout.
310 * It prevents command submission from occuring and makes
311 * every pending request fail
315 /** Bit 6 swizzling required for X tiling */
316 uint32_t bit_6_swizzle_x;
317 /** Bit 6 swizzling required for Y tiling */
318 uint32_t bit_6_swizzle_y;
320 } drm_i915_private_t;
322 enum intel_chip_family {
329 /** driver private structure attached to each drm_gem_object */
330 struct drm_i915_gem_object {
331 struct drm_gem_object *obj;
333 /** Current space allocated to this object in the GTT, if any. */
334 struct drm_mm_node *gtt_space;
336 /** This object's place on the active/flushing/inactive lists */
337 struct list_head list;
340 * This is set if the object is on the active or flushing lists
341 * (has pending rendering), and is not set if it's on inactive (ready
347 * This is set if the object has been written to since last bound
352 /** AGP memory structure for our GTT binding. */
353 DRM_AGP_MEM *agp_mem;
355 struct page **page_list;
358 * Current offset of the object in GTT space.
360 * This is the same as gtt_space->start
364 /** Boolean whether this object has a valid gtt offset. */
367 /** How many users have pinned this object in GTT space */
370 /** Breadcrumb of last rendering to the buffer. */
371 uint32_t last_rendering_seqno;
373 /** Current tiling mode for the object. */
374 uint32_t tiling_mode;
376 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
380 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
381 * GEM_DOMAIN_CPU is not in the object's read domain.
383 uint8_t *page_cpu_valid;
387 * Request queue structure.
389 * The request queue allows us to note sequence numbers that have been emitted
390 * and may be associated with active buffers to be retired.
392 * By keeping this list, we can avoid having to do questionable
393 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
394 * an emission time with seqnos for tracking how far ahead of the GPU we are.
396 struct drm_i915_gem_request {
397 /** GEM sequence number associated with this request. */
400 /** Time at which this request was emitted, in jiffies. */
401 unsigned long emitted_jiffies;
403 /** Cache domains that were flushed at the start of the request. */
404 uint32_t flush_domains;
406 struct list_head list;
409 struct drm_i915_file_private {
411 uint32_t last_gem_seqno;
412 uint32_t last_gem_throttle_seqno;
416 extern struct drm_ioctl_desc i915_ioctls[];
417 extern int i915_max_ioctl;
420 extern void i915_kernel_lost_context(struct drm_device * dev);
421 extern int i915_driver_load(struct drm_device *, unsigned long flags);
422 extern int i915_driver_unload(struct drm_device *);
423 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
424 extern void i915_driver_lastclose(struct drm_device * dev);
425 extern void i915_driver_preclose(struct drm_device *dev,
426 struct drm_file *file_priv);
427 extern void i915_driver_postclose(struct drm_device *dev,
428 struct drm_file *file_priv);
429 extern int i915_driver_device_is_agp(struct drm_device * dev);
430 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
432 extern int i915_emit_box(struct drm_device *dev,
433 struct drm_clip_rect __user *boxes,
434 int i, int DR1, int DR4);
437 extern int i915_irq_emit(struct drm_device *dev, void *data,
438 struct drm_file *file_priv);
439 extern int i915_irq_wait(struct drm_device *dev, void *data,
440 struct drm_file *file_priv);
441 void i915_user_irq_get(struct drm_device *dev);
442 void i915_user_irq_put(struct drm_device *dev);
444 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
445 extern void i915_driver_irq_preinstall(struct drm_device * dev);
446 extern int i915_driver_irq_postinstall(struct drm_device *dev);
447 extern void i915_driver_irq_uninstall(struct drm_device * dev);
448 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
449 struct drm_file *file_priv);
450 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
451 struct drm_file *file_priv);
452 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
453 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
454 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
455 extern u32 g45_get_vblank_counter(struct drm_device *dev, int crtc);
456 extern int i915_vblank_swap(struct drm_device *dev, void *data,
457 struct drm_file *file_priv);
460 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
463 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
467 extern int i915_mem_alloc(struct drm_device *dev, void *data,
468 struct drm_file *file_priv);
469 extern int i915_mem_free(struct drm_device *dev, void *data,
470 struct drm_file *file_priv);
471 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
472 struct drm_file *file_priv);
473 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
474 struct drm_file *file_priv);
475 extern void i915_mem_takedown(struct mem_block **heap);
476 extern void i915_mem_release(struct drm_device * dev,
477 struct drm_file *file_priv, struct mem_block *heap);
480 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
481 struct drm_file *file_priv);
482 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
483 struct drm_file *file_priv);
484 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
485 struct drm_file *file_priv);
486 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
487 struct drm_file *file_priv);
488 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv);
490 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
491 struct drm_file *file_priv);
492 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
493 struct drm_file *file_priv);
494 int i915_gem_execbuffer(struct drm_device *dev, void *data,
495 struct drm_file *file_priv);
496 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
497 struct drm_file *file_priv);
498 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
499 struct drm_file *file_priv);
500 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
501 struct drm_file *file_priv);
502 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
503 struct drm_file *file_priv);
504 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
505 struct drm_file *file_priv);
506 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
507 struct drm_file *file_priv);
508 int i915_gem_set_tiling(struct drm_device *dev, void *data,
509 struct drm_file *file_priv);
510 int i915_gem_get_tiling(struct drm_device *dev, void *data,
511 struct drm_file *file_priv);
512 void i915_gem_load(struct drm_device *dev);
513 int i915_gem_proc_init(struct drm_minor *minor);
514 void i915_gem_proc_cleanup(struct drm_minor *minor);
515 int i915_gem_init_object(struct drm_gem_object *obj);
516 void i915_gem_free_object(struct drm_gem_object *obj);
517 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
518 void i915_gem_object_unpin(struct drm_gem_object *obj);
519 void i915_gem_lastclose(struct drm_device *dev);
520 uint32_t i915_get_gem_seqno(struct drm_device *dev);
521 void i915_gem_retire_requests(struct drm_device *dev);
522 void i915_gem_retire_work_handler(struct work_struct *work);
523 void i915_gem_clflush_object(struct drm_gem_object *obj);
525 /* i915_gem_tiling.c */
526 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
528 /* i915_gem_debug.c */
529 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
530 const char *where, uint32_t mark);
532 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
534 #define i915_verify_inactive(dev, file, line)
536 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
537 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
538 const char *where, uint32_t mark);
539 void i915_dump_lru(struct drm_device *dev, const char *where);
540 #endif /* I915_HAVE_GEM */
543 extern int i915_save_state(struct drm_device *dev);
544 extern int i915_restore_state(struct drm_device *dev);
546 /* i915_opregion.c */
547 extern int intel_opregion_init(struct drm_device *dev);
548 extern void intel_opregion_free(struct drm_device *dev);
549 extern void opregion_asle_intr(struct drm_device *dev);
550 extern void opregion_enable_asle(struct drm_device *dev);
553 * Lock test for when it's just for synchronization of ring access.
555 * In that case, we don't need to do it when GEM is initialized as nobody else
556 * has access to the ring.
558 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
559 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
560 LOCK_TEST_WITH_RETURN(dev, file_priv); \
563 #if defined(__FreeBSD__) && !defined(__bool_true_false_are_defined)
564 typedef boolean_t bool;
567 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
568 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
569 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
570 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
571 #define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg))
572 #define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val))
574 #define I915_VERBOSE 0
576 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
579 #define BEGIN_LP_RING(n) do { \
581 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
582 if (dev_priv->ring.space < (n)*4) \
583 i915_wait_ring(dev, (n)*4, __func__); \
585 outring = dev_priv->ring.tail; \
586 ringmask = dev_priv->ring.tail_mask; \
587 virt = dev_priv->ring.virtual_start; \
590 #define OUT_RING(n) do { \
591 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
592 *(volatile unsigned int *)(virt + outring) = (n); \
595 outring &= ringmask; \
598 #define ADVANCE_LP_RING() do { \
599 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
600 dev_priv->ring.tail = outring; \
601 dev_priv->ring.space -= outcount * 4; \
602 I915_WRITE(PRB0_TAIL, outring); \
606 * Reads a dword out of the status page, which is written to from the command
607 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
610 * The following dwords have a reserved meaning:
611 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
612 * 0x04: ring 0 head pointer
613 * 0x05: ring 1 head pointer (915-class)
614 * 0x06: ring 2 head pointer (915-class)
615 * 0x10-0x1b: Context status DWords (GM45)
616 * 0x1f: Last written status offset. (GM45)
618 * The area from dword 0x20 to 0x3ff is available for driver usage.
620 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
621 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
622 #define I915_GEM_HWS_INDEX 0x20
623 #define I915_BREADCRUMB_INDEX 0x21
625 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
627 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
628 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
629 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
630 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
631 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
633 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
634 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
635 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
636 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
637 (dev)->pci_device == 0x27AE)
638 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
639 (dev)->pci_device == 0x2982 || \
640 (dev)->pci_device == 0x2992 || \
641 (dev)->pci_device == 0x29A2 || \
642 (dev)->pci_device == 0x2A02 || \
643 (dev)->pci_device == 0x2A12 || \
644 (dev)->pci_device == 0x2A42 || \
645 (dev)->pci_device == 0x2E02 || \
646 (dev)->pci_device == 0x2E12 || \
647 (dev)->pci_device == 0x2E22 || \
648 (dev)->pci_device == 0x2E32)
650 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
652 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
654 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
655 (dev)->pci_device == 0x2E12 || \
656 (dev)->pci_device == 0x2E22 || \
657 (dev)->pci_device == 0x2E32 || \
660 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
661 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
662 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
664 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
665 (dev)->pci_device == 0x29B2 || \
666 (dev)->pci_device == 0x29D2 || \
669 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
670 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
672 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
673 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
676 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
678 #define PRIMARY_RINGBUFFER_SIZE (128*1024)