sys/dev/drm/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  *
   3  * $FreeBSD$
   4  */
   5 /**************************************************************************
   6  *
   7  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   8  * All Rights Reserved.
   9  *
  10  **************************************************************************/
  11
  12 #ifndef _I915_DRV_H_
  13 #define _I915_DRV_H_
  14
  15 /* General customization:
  16  */
  17
  18 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  19
  20 #define DRIVER_NAME             "i915"
  21 #define DRIVER_DESC             "Intel Graphics"
  22 #define DRIVER_DATE             "20041217"
  23
  24 /* Interface history:
  25  *
  26  * 1.1: Original.
  27  * 1.2: Add Power Management
  28  */
  29 #define DRIVER_MAJOR            1
  30 #define DRIVER_MINOR            2
  31 #define DRIVER_PATCHLEVEL       0
  32
  33 typedef struct _drm_i915_ring_buffer {
  34         int tail_mask;
  35         unsigned long Start;
  36         unsigned long End;
  37         unsigned long Size;
  38         u8 *virtual_start;
  39         int head;
  40         int tail;
  41         int space;
  42         drm_local_map_t map;
  43 } drm_i915_ring_buffer_t;
  44
  45 struct mem_block {
  46         struct mem_block *next;
  47         struct mem_block *prev;
  48         int start;
  49         int size;
  50         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  51 };
  52
  53 typedef struct drm_i915_private {
  54         drm_local_map_t *sarea;
  55         drm_local_map_t *mmio_map;
  56
  57         drm_i915_sarea_t *sarea_priv;
  58         drm_i915_ring_buffer_t ring;
  59
  60         void *hw_status_page;
  61         unsigned long counter;
  62         dma_addr_t dma_status_page;
  63
  64         int back_offset;
  65         int front_offset;
  66         int current_page;
  67         int page_flipping;
  68         int use_mi_batchbuffer_start;
  69
  70         wait_queue_head_t irq_queue;
  71         atomic_t irq_received;
  72         atomic_t irq_emitted;
  73
  74         int tex_lru_log_granularity;
  75         int allow_batchbuffer;
  76         struct mem_block *agp_heap;
  77         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  78 } drm_i915_private_t;
  79
  80                                 /* i915_dma.c */
  81 extern void i915_kernel_lost_context(drm_device_t * dev);
  82 extern void i915_driver_pretakedown(drm_device_t * dev);
  83 extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
  84
  85 /* i915_irq.c */
  86 extern int i915_irq_emit(DRM_IOCTL_ARGS);
  87 extern int i915_irq_wait(DRM_IOCTL_ARGS);
  88
  89 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  90 extern void i915_driver_irq_preinstall(drm_device_t * dev);
  91 extern void i915_driver_irq_postinstall(drm_device_t * dev);
  92 extern void i915_driver_irq_uninstall(drm_device_t * dev);
  93
  94 /* i915_mem.c */
  95 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
  96 extern int i915_mem_free(DRM_IOCTL_ARGS);
  97 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
  98 extern void i915_mem_takedown(struct mem_block **heap);
  99 extern void i915_mem_release(drm_device_t * dev,
 100                              DRMFILE filp, struct mem_block *heap);
 101
 102 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 103 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 104 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 105 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 106
 107 #define I915_VERBOSE 0
 108
 109 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 110                         volatile char *virt;
 111
 112 #define BEGIN_LP_RING(n) do {                           \
 113         if (I915_VERBOSE)                               \
 114                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 115                           n, __FUNCTION__);             \
 116         if (dev_priv->ring.space < n*4)                 \
 117                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
 118         outcount = 0;                                   \
 119         outring = dev_priv->ring.tail;                  \
 120         ringmask = dev_priv->ring.tail_mask;            \
 121         virt = dev_priv->ring.virtual_start;            \
 122 } while (0)
 123
 124 #define OUT_RING(n) do {                                        \
 125         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 126         *(volatile unsigned int *)(virt + outring) = n;         \
 127         outcount++;                                             \
 128         outring += 4;                                           \
 129         outring &= ringmask;                                    \
 130 } while (0)
 131
 132 #define ADVANCE_LP_RING() do {                                          \
 133         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 134         dev_priv->ring.tail = outring;                                  \
 135         dev_priv->ring.space -= outcount * 4;                           \
 136         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 137 } while(0)
 138
 139 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 140
 141 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 142 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 143 #define CMD_REPORT_HEAD                 (7<<23)
 144 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 145 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 146
 147 #define INST_PARSER_CLIENT   0x00000000
 148 #define INST_OP_FLUSH        0x02000000
 149 #define INST_FLUSH_MAP_CACHE 0x00000001
 150
 151 #define BB1_START_ADDR_MASK   (~0x7)
 152 #define BB1_PROTECTED         (1<<0)
 153 #define BB1_UNPROTECTED       (0<<0)
 154 #define BB2_END_ADDR_MASK     (~0x7)
 155
 156 #define I915REG_HWSTAM          0x02098
 157 #define I915REG_INT_IDENTITY_R  0x020a4
 158 #define I915REG_INT_MASK_R      0x020a8
 159 #define I915REG_INT_ENABLE_R    0x020a0
 160
 161 #define SRX_INDEX               0x3c4
 162 #define SRX_DATA                0x3c5
 163 #define SR01                    1
 164 #define SR01_SCREEN_OFF         (1<<5)
 165
 166 #define PPCR                    0x61204
 167 #define PPCR_ON                 (1<<0)
 168
 169 #define DVOB                    0x61140
 170 #define DVOB_ON                 (1<<31)
 171 #define DVOC                    0x61160
 172 #define DVOC_ON                 (1<<31)
 173 #define LVDS                    0x61180
 174 #define LVDS_ON                 (1<<31)
 175
 176 #define ADPA                    0x61100
 177 #define ADPA_DPMS_MASK          (~(3<<10))
 178 #define ADPA_DPMS_ON            (0<<10)
 179 #define ADPA_DPMS_SUSPEND       (1<<10)
 180 #define ADPA_DPMS_STANDBY       (2<<10)
 181 #define ADPA_DPMS_OFF           (3<<10)
 182
 183 #define NOPID                   0x2094
 184 #define LP_RING                 0x2030
 185 #define HP_RING                 0x2040
 186 #define RING_TAIL               0x00
 187 #define TAIL_ADDR               0x001FFFF8
 188 #define RING_HEAD               0x04
 189 #define HEAD_WRAP_COUNT         0xFFE00000
 190 #define HEAD_WRAP_ONE           0x00200000
 191 #define HEAD_ADDR               0x001FFFFC
 192 #define RING_START              0x08
 193 #define START_ADDR              0x0xFFFFF000
 194 #define RING_LEN                0x0C
 195 #define RING_NR_PAGES           0x001FF000
 196 #define RING_REPORT_MASK        0x00000006
 197 #define RING_REPORT_64K         0x00000002
 198 #define RING_REPORT_128K        0x00000004
 199 #define RING_NO_REPORT          0x00000000
 200 #define RING_VALID_MASK         0x00000001
 201 #define RING_VALID              0x00000001
 202 #define RING_INVALID            0x00000000
 203
 204 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 205 #define SC_UPDATE_SCISSOR       (0x1<<1)
 206 #define SC_ENABLE_MASK          (0x1<<0)
 207 #define SC_ENABLE               (0x1<<0)
 208
 209 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 210 #define SCI_YMIN_MASK      (0xffff<<16)
 211 #define SCI_XMIN_MASK      (0xffff<<0)
 212 #define SCI_YMAX_MASK      (0xffff<<16)
 213 #define SCI_XMAX_MASK      (0xffff<<0)
 214
 215 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 216 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 217 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 218 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 219 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 220 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 221 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 222
 223 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 224 #define MI_BATCH_BUFFER_START   (0x31<<23)
 225 #define MI_BATCH_BUFFER_END     (0xA<<23)
 226 #define MI_BATCH_NON_SECURE     (1)
 227
 228 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 229 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 230 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 231
 232 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 233
 234 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 235 #define ASYNC_FLIP                (1<<22)
 236
 237 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 238
 239 #endif