1 /* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
2 * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
4 * Copyright 2000 Gareth Hughes
5 * Copyright 2002 Frank C. Earl
6 * Copyright 2002-2003 Leif Delgass
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
24 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
25 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
29 * Frank C. Earl <fearl@airmail.net>
30 * Leif Delgass <ldelgass@retinalburn.net>
35 #ifndef __MACH64_DRM_H__
36 #define __MACH64_DRM_H__
38 /* WARNING: If you change any of these defines, make sure to change the
39 * defines in the Xserver file (mach64_sarea.h)
41 #ifndef __MACH64_SAREA_DEFINES__
42 #define __MACH64_SAREA_DEFINES__
44 /* What needs to be changed for the current vertex buffer?
45 * GH: We're going to be pedantic about this. We want the card to do as
46 * little as possible, so let's avoid having it fetch a whole bunch of
47 * register values that don't change all that often, if at all.
49 #define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
50 #define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
51 #define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
52 #define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
53 #define MACH64_UPLOAD_DP_FOG_CLR 0x0010
54 #define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
55 #define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
56 #define MACH64_UPLOAD_SETUP_CNTL 0x0080
57 #define MACH64_UPLOAD_MISC 0x0100
58 #define MACH64_UPLOAD_TEXTURE 0x0200
59 #define MACH64_UPLOAD_TEX0IMAGE 0x0400
60 #define MACH64_UPLOAD_TEX1IMAGE 0x0800
61 #define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
62 #define MACH64_UPLOAD_CONTEXT 0x00ff
63 #define MACH64_UPLOAD_ALL 0x1fff
67 #define MACH64_BUFFER_SIZE 16384
69 /* Max number of swaps allowed on the ring
70 * before the client must wait
72 #define MACH64_MAX_QUEUED_FRAMES 3
74 /* Byte offsets for host blit buffer data
76 #define MACH64_HOSTDATA_BLIT_OFFSET 104
78 /* Keep these small for testing.
80 #define MACH64_NR_SAREA_CLIPRECTS 8
82 #define MACH64_CARD_HEAP 0
83 #define MACH64_AGP_HEAP 1
84 #define MACH64_NR_TEX_HEAPS 2
85 #define MACH64_NR_TEX_REGIONS 64
86 #define MACH64_LOG_TEX_GRANULARITY 16
88 #define MACH64_TEX_MAXLEVELS 1
90 #define MACH64_NR_CONTEXT_REGS 15
91 #define MACH64_NR_TEXTURE_REGS 4
93 #endif /* __MACH64_SAREA_DEFINES__ */
96 unsigned int dst_off_pitch;
98 unsigned int z_off_pitch;
100 unsigned int alpha_tst_cntl;
102 unsigned int scale_3d_cntl;
104 unsigned int sc_left_right;
105 unsigned int sc_top_bottom;
107 unsigned int dp_fog_clr;
108 unsigned int dp_write_mask;
109 unsigned int dp_pix_width;
113 unsigned int clr_cmp_cntl;
114 unsigned int gui_traj_cntl;
116 unsigned int setup_cntl;
118 unsigned int tex_size_pitch;
119 unsigned int tex_cntl;
120 unsigned int secondary_tex_off;
121 unsigned int tex_offset;
122 } drm_mach64_context_regs_t;
124 typedef struct drm_mach64_sarea {
125 /* The channel for communication of state information to the kernel
126 * on firing a vertex dma buffer.
128 drm_mach64_context_regs_t context_state;
130 unsigned int vertsize;
132 /* The current cliprects, or a subset thereof.
134 drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
137 /* Counters for client-side throttling of rendering clients.
139 unsigned int frames_queued;
141 /* Texture memory LRU.
143 drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
145 unsigned int tex_age[MACH64_NR_TEX_HEAPS];
147 } drm_mach64_sarea_t;
149 /* WARNING: If you change any of these defines, make sure to change the
150 * defines in the Xserver file (mach64_common.h)
153 /* Mach64 specific ioctls
154 * The device specific ioctl range is 0x40 to 0x79.
157 #define DRM_MACH64_INIT 0x00
158 #define DRM_MACH64_IDLE 0x01
159 #define DRM_MACH64_RESET 0x02
160 #define DRM_MACH64_SWAP 0x03
161 #define DRM_MACH64_CLEAR 0x04
162 #define DRM_MACH64_VERTEX 0x05
163 #define DRM_MACH64_BLIT 0x06
164 #define DRM_MACH64_FLUSH 0x07
165 #define DRM_MACH64_GETPARAM 0x08
167 #define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
168 #define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
169 #define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
170 #define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
171 #define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
172 #define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
173 #define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
174 #define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
175 #define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
177 /* Buffer flags for clears
179 #define MACH64_FRONT 0x1
180 #define MACH64_BACK 0x2
181 #define MACH64_DEPTH 0x4
183 /* Primitive types for vertex buffers
185 #define MACH64_PRIM_POINTS 0x00000000
186 #define MACH64_PRIM_LINES 0x00000001
187 #define MACH64_PRIM_LINE_LOOP 0x00000002
188 #define MACH64_PRIM_LINE_STRIP 0x00000003
189 #define MACH64_PRIM_TRIANGLES 0x00000004
190 #define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
191 #define MACH64_PRIM_TRIANGLE_FAN 0x00000006
192 #define MACH64_PRIM_QUADS 0x00000007
193 #define MACH64_PRIM_QUAD_STRIP 0x00000008
194 #define MACH64_PRIM_POLYGON 0x00000009
196 typedef enum _drm_mach64_dma_mode_t {
197 MACH64_MODE_DMA_ASYNC,
198 MACH64_MODE_DMA_SYNC,
200 } drm_mach64_dma_mode_t;
202 typedef struct drm_mach64_init {
204 DRM_MACH64_INIT_DMA = 0x01,
205 DRM_MACH64_CLEANUP_DMA = 0x02
208 unsigned long sarea_priv_offset;
210 drm_mach64_dma_mode_t dma_mode;
213 unsigned int front_offset, front_pitch;
214 unsigned int back_offset, back_pitch;
216 unsigned int depth_bpp;
217 unsigned int depth_offset, depth_pitch;
219 unsigned long fb_offset;
220 unsigned long mmio_offset;
221 unsigned long ring_offset;
222 unsigned long buffers_offset;
223 unsigned long agp_textures_offset;
226 typedef struct drm_mach64_clear {
229 unsigned int clear_color;
230 unsigned int clear_depth;
231 } drm_mach64_clear_t;
233 typedef struct drm_mach64_vertex {
235 void *buf; /* Address of vertex buffer */
236 unsigned long used; /* Number of bytes in buffer */
237 int discard; /* Client finished with buffer? */
238 } drm_mach64_vertex_t;
240 typedef struct drm_mach64_blit {
246 unsigned short width, height;
249 typedef struct drm_mach64_getparam {
251 MACH64_PARAM_FRAMES_QUEUED = 0x01,
252 MACH64_PARAM_IRQ_NR = 0x02
255 } drm_mach64_getparam_t;