1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 /* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 * DMA support for MGA G200 / G400.
35 * \author Rickard E. (Rik) Faith <faith@valinux.com>
36 * \author Jeff Hartmann <jhartmann@valinux.com>
37 * \author Keith Whitwell <keith@tungstengraphics.com>
38 * \author Gareth Hughes <gareth@valinux.com>
41 #include "dev/drm/drmP.h"
42 #include "dev/drm/drm.h"
43 #include "dev/drm/drm_sarea.h"
44 #include "dev/drm/mga_drm.h"
45 #include "dev/drm/mga_drv.h"
47 #define MGA_DEFAULT_USEC_TIMEOUT 10000
48 #define MGA_FREELIST_DEBUG 0
50 #define MINIMAL_CLEANUP 0
51 #define FULL_CLEANUP 1
52 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
54 /* ================================================================
58 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
64 for (i = 0; i < dev_priv->usec_timeout; i++) {
65 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
66 if (status == MGA_ENDPRDMASTS) {
67 MGA_WRITE8(MGA_CRTC_INDEX, 0);
74 DRM_ERROR("failed!\n");
75 DRM_INFO(" status=0x%08x\n", status);
80 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
82 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
83 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
87 /* The primary DMA stream should look like new right about now.
90 primary->space = primary->size;
91 primary->last_flush = 0;
93 sarea_priv->last_wrap = 0;
95 /* FIXME: Reset counters, buffer ages etc...
98 /* FIXME: What else do we need to reinitialize? WARP stuff?
104 /* ================================================================
108 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
110 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
117 /* We need to wait so that we can do an safe flush */
118 for (i = 0; i < dev_priv->usec_timeout; i++) {
119 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
120 if (status == MGA_ENDPRDMASTS)
125 if (primary->tail == primary->last_flush) {
126 DRM_DEBUG(" bailing out...\n");
130 tail = primary->tail + dev_priv->primary->offset;
132 /* We need to pad the stream between flushes, as the card
133 * actually (partially?) reads the first of these commands.
134 * See page 4-16 in the G400 manual, middle of the page or so.
138 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
139 MGA_DMAPAD, 0x00000000,
140 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
144 primary->last_flush = primary->tail;
146 head = MGA_READ(MGA_PRIMADDRESS);
149 primary->space = primary->size - primary->tail;
151 primary->space = head - tail;
154 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
155 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
156 DRM_DEBUG(" space = 0x%06x\n", primary->space);
158 mga_flush_write_combine();
159 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
161 DRM_DEBUG("done.\n");
164 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
166 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
173 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
174 MGA_DMAPAD, 0x00000000,
175 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
179 tail = primary->tail + dev_priv->primary->offset;
182 primary->last_flush = 0;
183 primary->last_wrap++;
185 head = MGA_READ(MGA_PRIMADDRESS);
187 if (head == dev_priv->primary->offset) {
188 primary->space = primary->size;
190 primary->space = head - dev_priv->primary->offset;
193 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
194 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
195 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
196 DRM_DEBUG(" space = 0x%06x\n", primary->space);
198 mga_flush_write_combine();
199 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
201 set_bit(0, &primary->wrapped);
202 DRM_DEBUG("done.\n");
205 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
207 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
208 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
209 u32 head = dev_priv->primary->offset;
212 sarea_priv->last_wrap++;
213 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
215 mga_flush_write_combine();
216 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
218 clear_bit(0, &primary->wrapped);
219 DRM_DEBUG("done.\n");
222 /* ================================================================
223 * Freelist management
226 #define MGA_BUFFER_USED ~0
227 #define MGA_BUFFER_FREE 0
229 #if MGA_FREELIST_DEBUG
230 static void mga_freelist_print(struct drm_device * dev)
232 drm_mga_private_t *dev_priv = dev->dev_private;
233 drm_mga_freelist_t *entry;
236 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
237 dev_priv->sarea_priv->last_dispatch,
238 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
239 dev_priv->primary->offset));
240 DRM_INFO("current freelist:\n");
242 for (entry = dev_priv->head->next; entry; entry = entry->next) {
243 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
244 entry, entry->buf->idx, entry->age.head,
245 entry->age.head - dev_priv->primary->offset);
251 static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
253 struct drm_device_dma *dma = dev->dma;
255 drm_mga_buf_priv_t *buf_priv;
256 drm_mga_freelist_t *entry;
258 DRM_DEBUG("count=%d\n", dma->buf_count);
260 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
261 if (dev_priv->head == NULL)
264 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
265 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
267 for (i = 0; i < dma->buf_count; i++) {
268 buf = dma->buflist[i];
269 buf_priv = buf->dev_private;
271 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
275 memset(entry, 0, sizeof(drm_mga_freelist_t));
277 entry->next = dev_priv->head->next;
278 entry->prev = dev_priv->head;
279 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
282 if (dev_priv->head->next != NULL)
283 dev_priv->head->next->prev = entry;
284 if (entry->next == NULL)
285 dev_priv->tail = entry;
287 buf_priv->list_entry = entry;
288 buf_priv->discard = 0;
289 buf_priv->dispatched = 0;
291 dev_priv->head->next = entry;
297 static void mga_freelist_cleanup(struct drm_device * dev)
299 drm_mga_private_t *dev_priv = dev->dev_private;
300 drm_mga_freelist_t *entry;
301 drm_mga_freelist_t *next;
304 entry = dev_priv->head;
307 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
311 dev_priv->head = dev_priv->tail = NULL;
315 /* FIXME: Still needed?
317 static void mga_freelist_reset(struct drm_device * dev)
319 drm_device_dma_t *dma = dev->dma;
321 drm_mga_buf_priv_t *buf_priv;
324 for (i = 0; i < dma->buf_count; i++) {
325 buf = dma->buflist[i];
326 buf_priv = buf->dev_private;
327 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
332 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
334 drm_mga_private_t *dev_priv = dev->dev_private;
335 drm_mga_freelist_t *next;
336 drm_mga_freelist_t *prev;
337 drm_mga_freelist_t *tail = dev_priv->tail;
341 head = MGA_READ(MGA_PRIMADDRESS);
342 wrap = dev_priv->sarea_priv->last_wrap;
344 DRM_DEBUG(" tail=0x%06lx %d\n",
346 tail->age.head - dev_priv->primary->offset : 0,
348 DRM_DEBUG(" head=0x%06lx %d\n",
349 head - dev_priv->primary->offset, wrap);
351 if (TEST_AGE(&tail->age, head, wrap)) {
352 prev = dev_priv->tail->prev;
353 next = dev_priv->tail;
355 next->prev = next->next = NULL;
356 dev_priv->tail = prev;
357 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
361 DRM_DEBUG("returning NULL!\n");
365 int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
367 drm_mga_private_t *dev_priv = dev->dev_private;
368 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
369 drm_mga_freelist_t *head, *entry, *prev;
371 DRM_DEBUG("age=0x%06lx wrap=%d\n",
372 buf_priv->list_entry->age.head -
373 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
375 entry = buf_priv->list_entry;
376 head = dev_priv->head;
378 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
379 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
380 prev = dev_priv->tail;
395 /* ================================================================
396 * DMA initialization, cleanup
399 int mga_driver_load(struct drm_device *dev, unsigned long flags)
401 drm_mga_private_t *dev_priv;
404 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
408 dev->dev_private = (void *)dev_priv;
409 memset(dev_priv, 0, sizeof(drm_mga_private_t));
411 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
412 dev_priv->chipset = flags;
414 dev_priv->mmio_base = drm_get_resource_start(dev, 1);
415 dev_priv->mmio_size = drm_get_resource_len(dev, 1);
418 dev->types[6] = _DRM_STAT_IRQ;
419 dev->types[7] = _DRM_STAT_PRIMARY;
420 dev->types[8] = _DRM_STAT_SECONDARY;
422 ret = drm_vblank_init(dev, 1);
425 (void) mga_driver_unload(dev);
433 * Bootstrap the driver for AGP DMA.
436 * Investigate whether there is any benifit to storing the WARP microcode in
437 * AGP memory. If not, the microcode may as well always be put in PCI
441 * This routine needs to set dma_bs->agp_mode to the mode actually configured
442 * in the hardware. Looking just at the Linux AGP driver code, I don't see
443 * an easy way to determine this.
445 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
447 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
448 drm_mga_dma_bootstrap_t * dma_bs)
450 drm_mga_private_t *const dev_priv =
451 (drm_mga_private_t *)dev->dev_private;
452 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
455 const unsigned secondary_size = dma_bs->secondary_bin_count
456 * dma_bs->secondary_bin_size;
457 const unsigned agp_size = (dma_bs->agp_size << 20);
458 struct drm_buf_desc req;
459 struct drm_agp_mode mode;
460 struct drm_agp_info info;
461 struct drm_agp_buffer agp_req;
462 struct drm_agp_binding bind_req;
465 err = drm_agp_acquire(dev);
467 DRM_ERROR("Unable to acquire AGP: %d\n", err);
471 err = drm_agp_info(dev, &info);
473 DRM_ERROR("Unable to get AGP info: %d\n", err);
477 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
478 err = drm_agp_enable(dev, mode);
480 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
484 /* In addition to the usual AGP mode configuration, the G200 AGP cards
485 * need to have the AGP mode "manually" set.
488 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
489 if (mode.mode & 0x02) {
490 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
492 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
496 /* Allocate and bind AGP memory. */
497 agp_req.size = agp_size;
499 err = drm_agp_alloc(dev, &agp_req);
501 dev_priv->agp_size = 0;
502 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
507 dev_priv->agp_size = agp_size;
508 dev_priv->agp_handle = agp_req.handle;
510 bind_req.handle = agp_req.handle;
512 err = drm_agp_bind( dev, &bind_req );
514 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
518 /* Make drm_addbufs happy by not trying to create a mapping for less
521 if (warp_size < PAGE_SIZE)
522 warp_size = PAGE_SIZE;
525 err = drm_addmap(dev, offset, warp_size,
526 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
528 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
533 err = drm_addmap(dev, offset, dma_bs->primary_size,
534 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary);
536 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
540 offset += dma_bs->primary_size;
541 err = drm_addmap(dev, offset, secondary_size,
542 _DRM_AGP, 0, & dev->agp_buffer_map);
544 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
548 (void)memset( &req, 0, sizeof(req) );
549 req.count = dma_bs->secondary_bin_count;
550 req.size = dma_bs->secondary_bin_size;
551 req.flags = _DRM_AGP_BUFFER;
552 req.agp_start = offset;
554 err = drm_addbufs_agp(dev, &req);
556 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
562 struct drm_map_list *_entry;
563 unsigned long agp_token = 0;
565 list_for_each_entry(_entry, &dev->maplist, head) {
566 if (_entry->map == dev->agp_buffer_map)
567 agp_token = _entry->user_token;
572 dev->agp_buffer_token = agp_token;
576 offset += secondary_size;
577 err = drm_addmap(dev, offset, agp_size - offset,
578 _DRM_AGP, 0, & dev_priv->agp_textures);
580 DRM_ERROR("Unable to map AGP texture region: %d\n", err);
584 drm_core_ioremap(dev_priv->warp, dev);
585 drm_core_ioremap(dev_priv->primary, dev);
586 drm_core_ioremap(dev->agp_buffer_map, dev);
588 if (!dev_priv->warp->handle ||
589 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
590 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
591 dev_priv->warp->handle, dev_priv->primary->handle,
592 dev->agp_buffer_map->handle);
596 dev_priv->dma_access = MGA_PAGPXFER;
597 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
599 DRM_INFO("Initialized card for AGP DMA.\n");
604 * Bootstrap the driver for PCI DMA.
607 * The algorithm for decreasing the size of the primary DMA buffer could be
608 * better. The size should be rounded up to the nearest page size, then
609 * decrease the request size by a single page each pass through the loop.
612 * Determine whether the maximum address passed to drm_pci_alloc is correct.
613 * The same goes for drm_addbufs_pci.
615 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
617 static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
618 drm_mga_dma_bootstrap_t * dma_bs)
620 drm_mga_private_t *const dev_priv =
621 (drm_mga_private_t *) dev->dev_private;
622 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
623 unsigned int primary_size;
624 unsigned int bin_count;
626 struct drm_buf_desc req;
629 if (dev->dma == NULL) {
630 DRM_ERROR("dev->dma is NULL\n");
634 /* Make drm_addbufs happy by not trying to create a mapping for less
637 if (warp_size < PAGE_SIZE)
638 warp_size = PAGE_SIZE;
640 /* The proper alignment is 0x100 for this mapping */
641 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
642 _DRM_READ_ONLY, &dev_priv->warp);
644 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
649 /* Other than the bottom two bits being used to encode other
650 * information, there don't appear to be any restrictions on the
651 * alignment of the primary or secondary DMA buffers.
654 for (primary_size = dma_bs->primary_size; primary_size != 0;
655 primary_size >>= 1 ) {
656 /* The proper alignment for this mapping is 0x04 */
657 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
658 _DRM_READ_ONLY, &dev_priv->primary);
664 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
668 if (dev_priv->primary->size != dma_bs->primary_size) {
669 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
670 dma_bs->primary_size,
671 (unsigned)dev_priv->primary->size);
672 dma_bs->primary_size = dev_priv->primary->size;
675 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
677 (void)memset(&req, 0, sizeof(req));
678 req.count = bin_count;
679 req.size = dma_bs->secondary_bin_size;
681 err = drm_addbufs_pci(dev, &req);
687 if (bin_count == 0) {
688 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
692 if (bin_count != dma_bs->secondary_bin_count) {
693 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
694 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
696 dma_bs->secondary_bin_count = bin_count;
699 dev_priv->dma_access = 0;
700 dev_priv->wagp_enable = 0;
702 dma_bs->agp_mode = 0;
704 DRM_INFO("Initialized card for PCI DMA.\n");
709 static int mga_do_dma_bootstrap(struct drm_device *dev,
710 drm_mga_dma_bootstrap_t *dma_bs)
712 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
714 drm_mga_private_t *const dev_priv =
715 (drm_mga_private_t *) dev->dev_private;
718 dev_priv->used_new_dma_init = 1;
720 /* The first steps are the same for both PCI and AGP based DMA. Map
721 * the cards MMIO registers and map a status page.
723 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
724 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
726 DRM_ERROR("Unable to map MMIO region: %d\n", err);
731 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
732 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
735 DRM_ERROR("Unable to map status region: %d\n", err);
740 /* The DMA initialization procedure is slightly different for PCI and
741 * AGP cards. AGP cards just allocate a large block of AGP memory and
742 * carve off portions of it for internal uses. The remaining memory
743 * is returned to user-mode to be used for AGP textures.
747 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
750 /* If we attempted to initialize the card for AGP DMA but failed,
751 * clean-up any mess that may have been created.
755 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
759 /* Not only do we want to try and initialized PCI cards for PCI DMA,
760 * but we also try to initialized AGP cards that could not be
761 * initialized for AGP DMA. This covers the case where we have an AGP
762 * card in a system with an unsupported AGP chipset. In that case the
763 * card will be detected as AGP, but we won't be able to allocate any
767 if (!is_agp || err) {
768 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
775 int mga_dma_bootstrap(struct drm_device *dev, void *data,
776 struct drm_file *file_priv)
778 drm_mga_dma_bootstrap_t *bootstrap = data;
780 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
781 const drm_mga_private_t *const dev_priv =
782 (drm_mga_private_t *) dev->dev_private;
785 err = mga_do_dma_bootstrap(dev, bootstrap);
787 mga_do_cleanup_dma(dev, FULL_CLEANUP);
791 if (dev_priv->agp_textures != NULL) {
792 bootstrap->texture_handle = dev_priv->agp_textures->offset;
793 bootstrap->texture_size = dev_priv->agp_textures->size;
795 bootstrap->texture_handle = 0;
796 bootstrap->texture_size = 0;
799 bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
805 static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
807 drm_mga_private_t *dev_priv;
812 dev_priv = dev->dev_private;
815 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
817 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
819 dev_priv->maccess = init->maccess;
821 dev_priv->fb_cpp = init->fb_cpp;
822 dev_priv->front_offset = init->front_offset;
823 dev_priv->front_pitch = init->front_pitch;
824 dev_priv->back_offset = init->back_offset;
825 dev_priv->back_pitch = init->back_pitch;
827 dev_priv->depth_cpp = init->depth_cpp;
828 dev_priv->depth_offset = init->depth_offset;
829 dev_priv->depth_pitch = init->depth_pitch;
831 /* FIXME: Need to support AGP textures...
833 dev_priv->texture_offset = init->texture_offset[0];
834 dev_priv->texture_size = init->texture_size[0];
836 dev_priv->sarea = drm_getsarea(dev);
837 if (!dev_priv->sarea) {
838 DRM_ERROR("failed to find sarea!\n");
842 if (!dev_priv->used_new_dma_init) {
844 dev_priv->dma_access = MGA_PAGPXFER;
845 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
847 dev_priv->status = drm_core_findmap(dev, init->status_offset);
848 if (!dev_priv->status) {
849 DRM_ERROR("failed to find status page!\n");
852 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
853 if (!dev_priv->mmio) {
854 DRM_ERROR("failed to find mmio region!\n");
857 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
858 if (!dev_priv->warp) {
859 DRM_ERROR("failed to find warp microcode region!\n");
862 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
863 if (!dev_priv->primary) {
864 DRM_ERROR("failed to find primary dma region!\n");
867 dev->agp_buffer_token = init->buffers_offset;
868 dev->agp_buffer_map =
869 drm_core_findmap(dev, init->buffers_offset);
870 if (!dev->agp_buffer_map) {
871 DRM_ERROR("failed to find dma buffer region!\n");
875 drm_core_ioremap(dev_priv->warp, dev);
876 drm_core_ioremap(dev_priv->primary, dev);
877 drm_core_ioremap(dev->agp_buffer_map, dev);
880 dev_priv->sarea_priv =
881 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
882 init->sarea_priv_offset);
884 if (!dev_priv->warp->handle ||
885 !dev_priv->primary->handle ||
886 ((dev_priv->dma_access != 0) &&
887 ((dev->agp_buffer_map == NULL) ||
888 (dev->agp_buffer_map->handle == NULL)))) {
889 DRM_ERROR("failed to ioremap agp regions!\n");
893 ret = mga_warp_install_microcode(dev_priv);
895 DRM_ERROR("failed to install WARP ucode: %d!\n", ret);
899 ret = mga_warp_init(dev_priv);
901 DRM_ERROR("failed to init WARP engine: %d!\n", ret);
905 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
907 mga_do_wait_for_idle(dev_priv);
909 /* Init the primary DMA registers.
911 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
913 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
914 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
915 + dev_priv->primary->size);
916 dev_priv->prim.size = dev_priv->primary->size;
918 dev_priv->prim.tail = 0;
919 dev_priv->prim.space = dev_priv->prim.size;
920 dev_priv->prim.wrapped = 0;
922 dev_priv->prim.last_flush = 0;
923 dev_priv->prim.last_wrap = 0;
925 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
927 dev_priv->prim.status[0] = dev_priv->primary->offset;
928 dev_priv->prim.status[1] = 0;
930 dev_priv->sarea_priv->last_wrap = 0;
931 dev_priv->sarea_priv->last_frame.head = 0;
932 dev_priv->sarea_priv->last_frame.wrap = 0;
934 if (mga_freelist_init(dev, dev_priv) < 0) {
935 DRM_ERROR("could not initialize freelist\n");
942 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
947 /* Make sure interrupts are disabled here because the uninstall ioctl
948 * may not have been called from userspace and after dev_private
949 * is freed, it's too late.
951 if (dev->irq_enabled)
952 drm_irq_uninstall(dev);
954 if (dev->dev_private) {
955 drm_mga_private_t *dev_priv = dev->dev_private;
957 if ((dev_priv->warp != NULL)
958 && (dev_priv->warp->type != _DRM_CONSISTENT))
959 drm_core_ioremapfree(dev_priv->warp, dev);
961 if ((dev_priv->primary != NULL)
962 && (dev_priv->primary->type != _DRM_CONSISTENT))
963 drm_core_ioremapfree(dev_priv->primary, dev);
965 if (dev->agp_buffer_map != NULL)
966 drm_core_ioremapfree(dev->agp_buffer_map, dev);
968 if (dev_priv->used_new_dma_init) {
969 if (dev_priv->agp_handle != 0) {
970 struct drm_agp_binding unbind_req;
971 struct drm_agp_buffer free_req;
973 unbind_req.handle = dev_priv->agp_handle;
974 drm_agp_unbind(dev, &unbind_req);
976 free_req.handle = dev_priv->agp_handle;
977 drm_agp_free(dev, &free_req);
979 dev_priv->agp_textures = NULL;
980 dev_priv->agp_size = 0;
981 dev_priv->agp_handle = 0;
984 if ((dev->agp != NULL) && dev->agp->acquired) {
985 err = drm_agp_release(dev);
989 dev_priv->warp = NULL;
990 dev_priv->primary = NULL;
991 dev_priv->sarea = NULL;
992 dev_priv->sarea_priv = NULL;
993 dev->agp_buffer_map = NULL;
996 dev_priv->mmio = NULL;
997 dev_priv->status = NULL;
998 dev_priv->used_new_dma_init = 0;
1001 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
1002 dev_priv->warp_pipe = 0;
1003 memset(dev_priv->warp_pipe_phys, 0,
1004 sizeof(dev_priv->warp_pipe_phys));
1006 if (dev_priv->head != NULL) {
1007 mga_freelist_cleanup(dev);
1014 int mga_dma_init(struct drm_device *dev, void *data,
1015 struct drm_file *file_priv)
1017 drm_mga_init_t *init = data;
1020 LOCK_TEST_WITH_RETURN(dev, file_priv);
1022 switch (init->func) {
1024 err = mga_do_init_dma(dev, init);
1026 (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1029 case MGA_CLEANUP_DMA:
1030 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1036 /* ================================================================
1037 * Primary DMA stream management
1040 int mga_dma_flush(struct drm_device *dev, void *data,
1041 struct drm_file *file_priv)
1043 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1044 struct drm_lock *lock = data;
1046 LOCK_TEST_WITH_RETURN(dev, file_priv);
1048 DRM_DEBUG("%s%s%s\n",
1049 (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1050 (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1051 (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1053 WRAP_WAIT_WITH_RETURN(dev_priv);
1055 if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1056 mga_do_dma_flush(dev_priv);
1059 if (lock->flags & _DRM_LOCK_QUIESCENT) {
1061 int ret = mga_do_wait_for_idle(dev_priv);
1063 DRM_INFO("-EBUSY\n");
1066 return mga_do_wait_for_idle(dev_priv);
1073 int mga_dma_reset(struct drm_device *dev, void *data,
1074 struct drm_file *file_priv)
1076 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1078 LOCK_TEST_WITH_RETURN(dev, file_priv);
1080 return mga_do_dma_reset(dev_priv);
1083 /* ================================================================
1084 * DMA buffer management
1087 static int mga_dma_get_buffers(struct drm_device * dev,
1088 struct drm_file *file_priv, struct drm_dma * d)
1090 struct drm_buf *buf;
1093 for (i = d->granted_count; i < d->request_count; i++) {
1094 buf = mga_freelist_get(dev);
1098 buf->file_priv = file_priv;
1100 if (DRM_COPY_TO_USER(&d->request_indices[i],
1101 &buf->idx, sizeof(buf->idx)))
1103 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1104 &buf->total, sizeof(buf->total)))
1112 int mga_dma_buffers(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv)
1115 struct drm_device_dma *dma = dev->dma;
1116 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1117 struct drm_dma *d = data;
1120 LOCK_TEST_WITH_RETURN(dev, file_priv);
1122 /* Please don't send us buffers.
1124 if (d->send_count != 0) {
1125 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1126 DRM_CURRENTPID, d->send_count);
1130 /* We'll send you buffers.
1132 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1133 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1134 DRM_CURRENTPID, d->request_count, dma->buf_count);
1138 WRAP_TEST_WITH_RETURN(dev_priv);
1140 d->granted_count = 0;
1142 if (d->request_count) {
1143 ret = mga_dma_get_buffers(dev, file_priv, d);
1150 * Called just before the module is unloaded.
1152 int mga_driver_unload(struct drm_device * dev)
1154 drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1155 dev->dev_private = NULL;
1161 * Called when the last opener of the device is closed.
1163 void mga_driver_lastclose(struct drm_device * dev)
1165 mga_do_cleanup_dma(dev, FULL_CLEANUP);
1168 int mga_driver_dma_quiescent(struct drm_device * dev)
1170 drm_mga_private_t *dev_priv = dev->dev_private;
1171 return mga_do_wait_for_idle(dev_priv);