sys/dev/drm/mga_state.c

   1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
   2  * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com */
   3 /*-
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Jeff Hartmann <jhartmann@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *
  31  * Rewritten by:
  32  *    Gareth Hughes <gareth@valinux.com>
  33  * $FreeBSD$
  34  *
  35  * $FreeBSD$
  36  */
  37
  38 #include "dev/drm/drmP.h"
  39 #include "dev/drm/drm.h"
  40 #include "dev/drm/mga_drm.h"
  41 #include "dev/drm/mga_drv.h"
  42
  43 /* ================================================================
  44  * DMA hardware state programming functions
  45  */
  46
  47 static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
  48                                drm_clip_rect_t * box)
  49 {
  50         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  51         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  52         unsigned int pitch = dev_priv->front_pitch;
  53         DMA_LOCALS;
  54
  55         BEGIN_DMA(2);
  56
  57         /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
  58          */
  59         if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
  60                 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
  61                           MGA_LEN + MGA_EXEC, 0x80000000,
  62                           MGA_DWGCTL, ctx->dwgctl,
  63                           MGA_LEN + MGA_EXEC, 0x80000000);
  64         }
  65         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
  66                   MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
  67                   MGA_YTOP, box->y1 * pitch,
  68                   MGA_YBOT, (box->y2 - 1) * pitch);
  69
  70         ADVANCE_DMA();
  71 }
  72
  73 static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
  74 {
  75         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  76         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  77         DMA_LOCALS;
  78
  79         BEGIN_DMA(3);
  80
  81         DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
  82                   MGA_MACCESS, ctx->maccess,
  83                   MGA_PLNWT, ctx->plnwt,
  84                   MGA_DWGCTL, ctx->dwgctl);
  85
  86         DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
  87                   MGA_FOGCOL, ctx->fogcolor,
  88                   MGA_WFLAG, ctx->wflag,
  89                   MGA_ZORG, dev_priv->depth_offset);
  90
  91         DMA_BLOCK(MGA_FCOL, ctx->fcol,
  92                   MGA_DMAPAD, 0x00000000,
  93                   MGA_DMAPAD, 0x00000000,
  94                   MGA_DMAPAD, 0x00000000);
  95
  96         ADVANCE_DMA();
  97 }
  98
  99 static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
 100 {
 101         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 102         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 103         DMA_LOCALS;
 104
 105         BEGIN_DMA(4);
 106
 107         DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
 108                   MGA_MACCESS, ctx->maccess,
 109                   MGA_PLNWT, ctx->plnwt,
 110                   MGA_DWGCTL, ctx->dwgctl);
 111
 112         DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
 113                   MGA_FOGCOL, ctx->fogcolor,
 114                   MGA_WFLAG, ctx->wflag,
 115                   MGA_ZORG, dev_priv->depth_offset);
 116
 117         DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
 118                   MGA_TDUALSTAGE0, ctx->tdualstage0,
 119                   MGA_TDUALSTAGE1, ctx->tdualstage1,
 120                   MGA_FCOL, ctx->fcol);
 121
 122         DMA_BLOCK(MGA_STENCIL, ctx->stencil,
 123                   MGA_STENCILCTL, ctx->stencilctl,
 124                   MGA_DMAPAD, 0x00000000,
 125                   MGA_DMAPAD, 0x00000000);
 126
 127         ADVANCE_DMA();
 128 }
 129
 130 static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
 131 {
 132         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 133         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 134         DMA_LOCALS;
 135
 136         BEGIN_DMA(4);
 137
 138         DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
 139                   MGA_TEXCTL, tex->texctl,
 140                   MGA_TEXFILTER, tex->texfilter,
 141                   MGA_TEXBORDERCOL, tex->texbordercol);
 142
 143         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 144                   MGA_TEXORG1, tex->texorg1,
 145                   MGA_TEXORG2, tex->texorg2,
 146                   MGA_TEXORG3, tex->texorg3);
 147
 148         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 149                   MGA_TEXWIDTH, tex->texwidth,
 150                   MGA_TEXHEIGHT, tex->texheight,
 151                   MGA_WR24, tex->texwidth);
 152
 153         DMA_BLOCK(MGA_WR34, tex->texheight,
 154                   MGA_TEXTRANS, 0x0000ffff,
 155                   MGA_TEXTRANSHIGH, 0x0000ffff,
 156                   MGA_DMAPAD, 0x00000000);
 157
 158         ADVANCE_DMA();
 159 }
 160
 161 static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
 162 {
 163         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 164         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 165         DMA_LOCALS;
 166
 167 /*      printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
 168 /*             tex->texctl, tex->texctl2); */
 169
 170         BEGIN_DMA(6);
 171
 172         DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
 173                   MGA_TEXCTL, tex->texctl,
 174                   MGA_TEXFILTER, tex->texfilter,
 175                   MGA_TEXBORDERCOL, tex->texbordercol);
 176
 177         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 178                   MGA_TEXORG1, tex->texorg1,
 179                   MGA_TEXORG2, tex->texorg2,
 180                   MGA_TEXORG3, tex->texorg3);
 181
 182         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 183                   MGA_TEXWIDTH, tex->texwidth,
 184                   MGA_TEXHEIGHT, tex->texheight,
 185                   MGA_WR49, 0x00000000);
 186
 187         DMA_BLOCK(MGA_WR57, 0x00000000,
 188                   MGA_WR53, 0x00000000,
 189                   MGA_WR61, 0x00000000,
 190                   MGA_WR52, MGA_G400_WR_MAGIC);
 191
 192         DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
 193                   MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
 194                   MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
 195                   MGA_DMAPAD, 0x00000000);
 196
 197         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 198                   MGA_DMAPAD, 0x00000000,
 199                   MGA_TEXTRANS, 0x0000ffff,
 200                   MGA_TEXTRANSHIGH, 0x0000ffff);
 201
 202         ADVANCE_DMA();
 203 }
 204
 205 static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
 206 {
 207         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 208         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
 209         DMA_LOCALS;
 210
 211 /*      printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
 212 /*             tex->texctl, tex->texctl2); */
 213
 214         BEGIN_DMA(5);
 215
 216         DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
 217                                 MGA_MAP1_ENABLE |
 218                                 MGA_G400_TC2_MAGIC),
 219                   MGA_TEXCTL, tex->texctl,
 220                   MGA_TEXFILTER, tex->texfilter,
 221                   MGA_TEXBORDERCOL, tex->texbordercol);
 222
 223         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 224                   MGA_TEXORG1, tex->texorg1,
 225                   MGA_TEXORG2, tex->texorg2,
 226                   MGA_TEXORG3, tex->texorg3);
 227
 228         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 229                   MGA_TEXWIDTH, tex->texwidth,
 230                   MGA_TEXHEIGHT, tex->texheight,
 231                   MGA_WR49, 0x00000000);
 232
 233         DMA_BLOCK(MGA_WR57, 0x00000000,
 234                   MGA_WR53, 0x00000000,
 235                   MGA_WR61, 0x00000000,
 236                   MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
 237
 238         DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
 239                   MGA_TEXTRANS, 0x0000ffff,
 240                   MGA_TEXTRANSHIGH, 0x0000ffff,
 241                   MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
 242
 243         ADVANCE_DMA();
 244 }
 245
 246 static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
 247 {
 248         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 249         unsigned int pipe = sarea_priv->warp_pipe;
 250         DMA_LOCALS;
 251
 252         BEGIN_DMA(3);
 253
 254         DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
 255                   MGA_WVRTXSZ, 0x00000007,
 256                   MGA_WFLAG, 0x00000000,
 257                   MGA_WR24, 0x00000000);
 258
 259         DMA_BLOCK(MGA_WR25, 0x00000100,
 260                   MGA_WR34, 0x00000000,
 261                   MGA_WR42, 0x0000ffff,
 262                   MGA_WR60, 0x0000ffff);
 263
 264         /* Padding required to to hardware bug.
 265          */
 266         DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
 267                   MGA_DMAPAD, 0xffffffff,
 268                   MGA_DMAPAD, 0xffffffff,
 269                   MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
 270                                MGA_WMODE_START | MGA_WAGP_ENABLE));
 271
 272         ADVANCE_DMA();
 273 }
 274
 275 static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
 276 {
 277         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 278         unsigned int pipe = sarea_priv->warp_pipe;
 279         DMA_LOCALS;
 280
 281 /*      printk("mga_g400_emit_pipe %x\n", pipe); */
 282
 283         BEGIN_DMA(10);
 284
 285         DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
 286                   MGA_DMAPAD, 0x00000000,
 287                   MGA_DMAPAD, 0x00000000,
 288                   MGA_DMAPAD, 0x00000000);
 289
 290         if (pipe & MGA_T2) {
 291                 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
 292                           MGA_DMAPAD, 0x00000000,
 293                           MGA_DMAPAD, 0x00000000,
 294                           MGA_DMAPAD, 0x00000000);
 295
 296                 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
 297                           MGA_WACCEPTSEQ, 0x00000000,
 298                           MGA_WACCEPTSEQ, 0x00000000,
 299                           MGA_WACCEPTSEQ, 0x1e000000);
 300         } else {
 301                 if (dev_priv->warp_pipe & MGA_T2) {
 302                         /* Flush the WARP pipe */
 303                         DMA_BLOCK(MGA_YDST, 0x00000000,
 304                                   MGA_FXLEFT, 0x00000000,
 305                                   MGA_FXRIGHT, 0x00000001,
 306                                   MGA_DWGCTL, MGA_DWGCTL_FLUSH);
 307
 308                         DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
 309                                   MGA_DWGSYNC, 0x00007000,
 310                                   MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
 311                                   MGA_LEN + MGA_EXEC, 0x00000000);
 312
 313                         DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
 314                                                 MGA_G400_TC2_MAGIC),
 315                                   MGA_LEN + MGA_EXEC, 0x00000000,
 316                                   MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
 317                                   MGA_DMAPAD, 0x00000000);
 318                 }
 319
 320                 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
 321                           MGA_DMAPAD, 0x00000000,
 322                           MGA_DMAPAD, 0x00000000,
 323                           MGA_DMAPAD, 0x00000000);
 324
 325                 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
 326                           MGA_WACCEPTSEQ, 0x00000000,
 327                           MGA_WACCEPTSEQ, 0x00000000,
 328                           MGA_WACCEPTSEQ, 0x18000000);
 329         }
 330
 331         DMA_BLOCK(MGA_WFLAG, 0x00000000,
 332                   MGA_WFLAG1, 0x00000000,
 333                   MGA_WR56, MGA_G400_WR56_MAGIC,
 334                   MGA_DMAPAD, 0x00000000);
 335
 336         DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0              */
 337                   MGA_WR57, 0x00000000, /* tex0              */
 338                   MGA_WR53, 0x00000000, /* tex1              */
 339                   MGA_WR61, 0x00000000);        /* tex1              */
 340
 341         DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC,  /* tex0 width        */
 342                   MGA_WR62, MGA_G400_WR_MAGIC,  /* tex0 height       */
 343                   MGA_WR52, MGA_G400_WR_MAGIC,  /* tex1 width        */
 344                   MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height       */
 345
 346         /* Padding required to to hardware bug */
 347         DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
 348                   MGA_DMAPAD, 0xffffffff,
 349                   MGA_DMAPAD, 0xffffffff,
 350                   MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
 351                                 MGA_WMODE_START | MGA_WAGP_ENABLE));
 352
 353         ADVANCE_DMA();
 354 }
 355
 356 static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
 357 {
 358         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 359         unsigned int dirty = sarea_priv->dirty;
 360
 361         if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
 362                 mga_g200_emit_pipe(dev_priv);
 363                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 364         }
 365
 366         if (dirty & MGA_UPLOAD_CONTEXT) {
 367                 mga_g200_emit_context(dev_priv);
 368                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 369         }
 370
 371         if (dirty & MGA_UPLOAD_TEX0) {
 372                 mga_g200_emit_tex0(dev_priv);
 373                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 374         }
 375 }
 376
 377 static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
 378 {
 379         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 380         unsigned int dirty = sarea_priv->dirty;
 381         int multitex = sarea_priv->warp_pipe & MGA_T2;
 382
 383         if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
 384                 mga_g400_emit_pipe(dev_priv);
 385                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 386         }
 387
 388         if (dirty & MGA_UPLOAD_CONTEXT) {
 389                 mga_g400_emit_context(dev_priv);
 390                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 391         }
 392
 393         if (dirty & MGA_UPLOAD_TEX0) {
 394                 mga_g400_emit_tex0(dev_priv);
 395                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 396         }
 397
 398         if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
 399                 mga_g400_emit_tex1(dev_priv);
 400                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
 401         }
 402 }
 403
 404 /* ================================================================
 405  * SAREA state verification
 406  */
 407
 408 /* Disallow all write destinations except the front and backbuffer.
 409  */
 410 static int mga_verify_context(drm_mga_private_t * dev_priv)
 411 {
 412         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 413         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 414
 415         if (ctx->dstorg != dev_priv->front_offset &&
 416             ctx->dstorg != dev_priv->back_offset) {
 417                 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
 418                           ctx->dstorg, dev_priv->front_offset,
 419                           dev_priv->back_offset);
 420                 ctx->dstorg = 0;
 421                 return DRM_ERR(EINVAL);
 422         }
 423
 424         return 0;
 425 }
 426
 427 /* Disallow texture reads from PCI space.
 428  */
 429 static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
 430 {
 431         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 432         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
 433         unsigned int org;
 434
 435         org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
 436
 437         if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
 438                 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
 439                 tex->texorg = 0;
 440                 return DRM_ERR(EINVAL);
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int mga_verify_state(drm_mga_private_t * dev_priv)
 447 {
 448         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 449         unsigned int dirty = sarea_priv->dirty;
 450         int ret = 0;
 451
 452         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 453                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 454
 455         if (dirty & MGA_UPLOAD_CONTEXT)
 456                 ret |= mga_verify_context(dev_priv);
 457
 458         if (dirty & MGA_UPLOAD_TEX0)
 459                 ret |= mga_verify_tex(dev_priv, 0);
 460
 461         if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
 462                 if (dirty & MGA_UPLOAD_TEX1)
 463                         ret |= mga_verify_tex(dev_priv, 1);
 464
 465                 if (dirty & MGA_UPLOAD_PIPE)
 466                         ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
 467         } else {
 468                 if (dirty & MGA_UPLOAD_PIPE)
 469                         ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
 470         }
 471
 472         return (ret == 0);
 473 }
 474
 475 static int mga_verify_iload(drm_mga_private_t * dev_priv,
 476                             unsigned int dstorg, unsigned int length)
 477 {
 478         if (dstorg < dev_priv->texture_offset ||
 479             dstorg + length > (dev_priv->texture_offset +
 480                                dev_priv->texture_size)) {
 481                 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
 482                 return DRM_ERR(EINVAL);
 483         }
 484
 485         if (length & MGA_ILOAD_MASK) {
 486                 DRM_ERROR("*** bad iload length: 0x%x\n",
 487                           length & MGA_ILOAD_MASK);
 488                 return DRM_ERR(EINVAL);
 489         }
 490
 491         return 0;
 492 }
 493
 494 static int mga_verify_blit(drm_mga_private_t * dev_priv,
 495                            unsigned int srcorg, unsigned int dstorg)
 496 {
 497         if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
 498             (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
 499                 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
 500                 return DRM_ERR(EINVAL);
 501         }
 502         return 0;
 503 }
 504
 505 /* ================================================================
 506  *
 507  */
 508
 509 static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
 510 {
 511         drm_mga_private_t *dev_priv = dev->dev_private;
 512         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 513         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 514         drm_clip_rect_t *pbox = sarea_priv->boxes;
 515         int nbox = sarea_priv->nbox;
 516         int i;
 517         DMA_LOCALS;
 518         DRM_DEBUG("\n");
 519
 520         BEGIN_DMA(1);
 521
 522         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 523                   MGA_DMAPAD, 0x00000000,
 524                   MGA_DWGSYNC, 0x00007100,
 525                   MGA_DWGSYNC, 0x00007000);
 526
 527         ADVANCE_DMA();
 528
 529         for (i = 0; i < nbox; i++) {
 530                 drm_clip_rect_t *box = &pbox[i];
 531                 u32 height = box->y2 - box->y1;
 532
 533                 DRM_DEBUG("   from=%d,%d to=%d,%d\n",
 534                           box->x1, box->y1, box->x2, box->y2);
 535
 536                 if (clear->flags & MGA_FRONT) {
 537                         BEGIN_DMA(2);
 538
 539                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 540                                   MGA_PLNWT, clear->color_mask,
 541                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 542                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 543
 544                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 545                                   MGA_FCOL, clear->clear_color,
 546                                   MGA_DSTORG, dev_priv->front_offset,
 547                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 548
 549                         ADVANCE_DMA();
 550                 }
 551
 552                 if (clear->flags & MGA_BACK) {
 553                         BEGIN_DMA(2);
 554
 555                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 556                                   MGA_PLNWT, clear->color_mask,
 557                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 558                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 559
 560                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 561                                   MGA_FCOL, clear->clear_color,
 562                                   MGA_DSTORG, dev_priv->back_offset,
 563                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 564
 565                         ADVANCE_DMA();
 566                 }
 567
 568                 if (clear->flags & MGA_DEPTH) {
 569                         BEGIN_DMA(2);
 570
 571                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 572                                   MGA_PLNWT, clear->depth_mask,
 573                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 574                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 575
 576                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 577                                   MGA_FCOL, clear->clear_depth,
 578                                   MGA_DSTORG, dev_priv->depth_offset,
 579                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 580
 581                         ADVANCE_DMA();
 582                 }
 583
 584         }
 585
 586         BEGIN_DMA(1);
 587
 588         /* Force reset of DWGCTL */
 589         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 590                   MGA_DMAPAD, 0x00000000,
 591                   MGA_PLNWT, ctx->plnwt,
 592                   MGA_DWGCTL, ctx->dwgctl);
 593
 594         ADVANCE_DMA();
 595
 596         FLUSH_DMA();
 597 }
 598
 599 static void mga_dma_dispatch_swap(drm_device_t * dev)
 600 {
 601         drm_mga_private_t *dev_priv = dev->dev_private;
 602         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 603         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 604         drm_clip_rect_t *pbox = sarea_priv->boxes;
 605         int nbox = sarea_priv->nbox;
 606         int i;
 607         DMA_LOCALS;
 608         DRM_DEBUG("\n");
 609
 610         sarea_priv->last_frame.head = dev_priv->prim.tail;
 611         sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
 612
 613         BEGIN_DMA(4 + nbox);
 614
 615         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 616                   MGA_DMAPAD, 0x00000000,
 617                   MGA_DWGSYNC, 0x00007100,
 618                   MGA_DWGSYNC, 0x00007000);
 619
 620         DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
 621                   MGA_MACCESS, dev_priv->maccess,
 622                   MGA_SRCORG, dev_priv->back_offset,
 623                   MGA_AR5, dev_priv->front_pitch);
 624
 625         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 626                   MGA_DMAPAD, 0x00000000,
 627                   MGA_PLNWT, 0xffffffff,
 628                   MGA_DWGCTL, MGA_DWGCTL_COPY);
 629
 630         for (i = 0; i < nbox; i++) {
 631                 drm_clip_rect_t *box = &pbox[i];
 632                 u32 height = box->y2 - box->y1;
 633                 u32 start = box->y1 * dev_priv->front_pitch;
 634
 635                 DRM_DEBUG("   from=%d,%d to=%d,%d\n",
 636                           box->x1, box->y1, box->x2, box->y2);
 637
 638                 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
 639                           MGA_AR3, start + box->x1,
 640                           MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
 641                           MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
 642         }
 643
 644         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 645                   MGA_PLNWT, ctx->plnwt,
 646                   MGA_SRCORG, dev_priv->front_offset,
 647                   MGA_DWGCTL, ctx->dwgctl);
 648
 649         ADVANCE_DMA();
 650
 651         FLUSH_DMA();
 652
 653         DRM_DEBUG("%s... done.\n", __FUNCTION__);
 654 }
 655
 656 static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
 657 {
 658         drm_mga_private_t *dev_priv = dev->dev_private;
 659         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 660         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 661         u32 address = (u32) buf->bus_address;
 662         u32 length = (u32) buf->used;
 663         int i = 0;
 664         DMA_LOCALS;
 665         DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
 666
 667         if (buf->used) {
 668                 buf_priv->dispatched = 1;
 669
 670                 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 671
 672                 do {
 673                         if (i < sarea_priv->nbox) {
 674                                 mga_emit_clip_rect(dev_priv,
 675                                                    &sarea_priv->boxes[i]);
 676                         }
 677
 678                         BEGIN_DMA(1);
 679
 680                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 681                                   MGA_DMAPAD, 0x00000000,
 682                                   MGA_SECADDRESS, (address |
 683                                                    MGA_DMA_VERTEX),
 684                                   MGA_SECEND, ((address + length) |
 685                                                MGA_PAGPXFER));
 686
 687                         ADVANCE_DMA();
 688                 } while (++i < sarea_priv->nbox);
 689         }
 690
 691         if (buf_priv->discard) {
 692                 AGE_BUFFER(buf_priv);
 693                 buf->pending = 0;
 694                 buf->used = 0;
 695                 buf_priv->dispatched = 0;
 696
 697                 mga_freelist_put(dev, buf);
 698         }
 699
 700         FLUSH_DMA();
 701 }
 702
 703 static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
 704                                      unsigned int start, unsigned int end)
 705 {
 706         drm_mga_private_t *dev_priv = dev->dev_private;
 707         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 708         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 709         u32 address = (u32) buf->bus_address;
 710         int i = 0;
 711         DMA_LOCALS;
 712         DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
 713
 714         if (start != end) {
 715                 buf_priv->dispatched = 1;
 716
 717                 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 718
 719                 do {
 720                         if (i < sarea_priv->nbox) {
 721                                 mga_emit_clip_rect(dev_priv,
 722                                                    &sarea_priv->boxes[i]);
 723                         }
 724
 725                         BEGIN_DMA(1);
 726
 727                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 728                                   MGA_DMAPAD, 0x00000000,
 729                                   MGA_SETUPADDRESS, address + start,
 730                                   MGA_SETUPEND, ((address + end) |
 731                                                  MGA_PAGPXFER));
 732
 733                         ADVANCE_DMA();
 734                 } while (++i < sarea_priv->nbox);
 735         }
 736
 737         if (buf_priv->discard) {
 738                 AGE_BUFFER(buf_priv);
 739                 buf->pending = 0;
 740                 buf->used = 0;
 741                 buf_priv->dispatched = 0;
 742
 743                 mga_freelist_put(dev, buf);
 744         }
 745
 746         FLUSH_DMA();
 747 }
 748
 749 /* This copies a 64 byte aligned agp region to the frambuffer with a
 750  * standard blit, the ioctl needs to do checking.
 751  */
 752 static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
 753                                    unsigned int dstorg, unsigned int length)
 754 {
 755         drm_mga_private_t *dev_priv = dev->dev_private;
 756         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 757         drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
 758         u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
 759         u32 y2;
 760         DMA_LOCALS;
 761         DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
 762
 763         y2 = length / 64;
 764
 765         BEGIN_DMA(5);
 766
 767         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 768                   MGA_DMAPAD, 0x00000000,
 769                   MGA_DWGSYNC, 0x00007100,
 770                   MGA_DWGSYNC, 0x00007000);
 771
 772         DMA_BLOCK(MGA_DSTORG, dstorg,
 773                   MGA_MACCESS, 0x00000000,
 774                   MGA_SRCORG, srcorg,
 775                   MGA_AR5, 64);
 776
 777         DMA_BLOCK(MGA_PITCH, 64,
 778                   MGA_PLNWT, 0xffffffff,
 779                   MGA_DMAPAD, 0x00000000,
 780                   MGA_DWGCTL, MGA_DWGCTL_COPY);
 781
 782         DMA_BLOCK(MGA_AR0, 63,
 783                   MGA_AR3, 0,
 784                   MGA_FXBNDRY, (63 << 16) | 0,
 785                   MGA_YDSTLEN + MGA_EXEC, y2);
 786
 787         DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
 788                   MGA_SRCORG, dev_priv->front_offset,
 789                   MGA_PITCH, dev_priv->front_pitch,
 790                   MGA_DWGSYNC, 0x00007000);
 791
 792         ADVANCE_DMA();
 793
 794         AGE_BUFFER(buf_priv);
 795
 796         buf->pending = 0;
 797         buf->used = 0;
 798         buf_priv->dispatched = 0;
 799
 800         mga_freelist_put(dev, buf);
 801
 802         FLUSH_DMA();
 803 }
 804
 805 static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
 806 {
 807         drm_mga_private_t *dev_priv = dev->dev_private;
 808         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 809         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 810         drm_clip_rect_t *pbox = sarea_priv->boxes;
 811         int nbox = sarea_priv->nbox;
 812         u32 scandir = 0, i;
 813         DMA_LOCALS;
 814         DRM_DEBUG("\n");
 815
 816         BEGIN_DMA(4 + nbox);
 817
 818         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 819                   MGA_DMAPAD, 0x00000000,
 820                   MGA_DWGSYNC, 0x00007100,
 821                   MGA_DWGSYNC, 0x00007000);
 822
 823         DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
 824                   MGA_PLNWT, blit->planemask,
 825                   MGA_SRCORG, blit->srcorg,
 826                   MGA_DSTORG, blit->dstorg);
 827
 828         DMA_BLOCK(MGA_SGN, scandir,
 829                   MGA_MACCESS, dev_priv->maccess,
 830                   MGA_AR5, blit->ydir * blit->src_pitch,
 831                   MGA_PITCH, blit->dst_pitch);
 832
 833         for (i = 0; i < nbox; i++) {
 834                 int srcx = pbox[i].x1 + blit->delta_sx;
 835                 int srcy = pbox[i].y1 + blit->delta_sy;
 836                 int dstx = pbox[i].x1 + blit->delta_dx;
 837                 int dsty = pbox[i].y1 + blit->delta_dy;
 838                 int h = pbox[i].y2 - pbox[i].y1;
 839                 int w = pbox[i].x2 - pbox[i].x1 - 1;
 840                 int start;
 841
 842                 if (blit->ydir == -1) {
 843                         srcy = blit->height - srcy - 1;
 844                 }
 845
 846                 start = srcy * blit->src_pitch + srcx;
 847
 848                 DMA_BLOCK(MGA_AR0, start + w,
 849                           MGA_AR3, start,
 850                           MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
 851                           MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
 852         }
 853
 854         /* Do something to flush AGP?
 855          */
 856
 857         /* Force reset of DWGCTL */
 858         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 859                   MGA_PLNWT, ctx->plnwt,
 860                   MGA_PITCH, dev_priv->front_pitch,
 861                   MGA_DWGCTL, ctx->dwgctl);
 862
 863         ADVANCE_DMA();
 864 }
 865
 866 /* ================================================================
 867  *
 868  */
 869
 870 static int mga_dma_clear(DRM_IOCTL_ARGS)
 871 {
 872         DRM_DEVICE;
 873         drm_mga_private_t *dev_priv = dev->dev_private;
 874         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 875         drm_mga_clear_t clear;
 876
 877         LOCK_TEST_WITH_RETURN(dev, filp);
 878
 879         DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
 880                                  sizeof(clear));
 881
 882         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 883                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 884
 885         WRAP_TEST_WITH_RETURN(dev_priv);
 886
 887         mga_dma_dispatch_clear(dev, &clear);
 888
 889         /* Make sure we restore the 3D state next time.
 890          */
 891         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 892
 893         return 0;
 894 }
 895
 896 static int mga_dma_swap(DRM_IOCTL_ARGS)
 897 {
 898         DRM_DEVICE;
 899         drm_mga_private_t *dev_priv = dev->dev_private;
 900         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 901
 902         LOCK_TEST_WITH_RETURN(dev, filp);
 903
 904         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 905                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 906
 907         WRAP_TEST_WITH_RETURN(dev_priv);
 908
 909         mga_dma_dispatch_swap(dev);
 910
 911         /* Make sure we restore the 3D state next time.
 912          */
 913         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 914
 915         return 0;
 916 }
 917
 918 static int mga_dma_vertex(DRM_IOCTL_ARGS)
 919 {
 920         DRM_DEVICE;
 921         drm_mga_private_t *dev_priv = dev->dev_private;
 922         drm_device_dma_t *dma = dev->dma;
 923         drm_buf_t *buf;
 924         drm_mga_buf_priv_t *buf_priv;
 925         drm_mga_vertex_t vertex;
 926
 927         LOCK_TEST_WITH_RETURN(dev, filp);
 928
 929         DRM_COPY_FROM_USER_IOCTL(vertex,
 930                                  (drm_mga_vertex_t __user *) data,
 931                                  sizeof(vertex));
 932
 933         if (vertex.idx < 0 || vertex.idx > dma->buf_count)
 934                 return DRM_ERR(EINVAL);
 935         buf = dma->buflist[vertex.idx];
 936         buf_priv = buf->dev_private;
 937
 938         buf->used = vertex.used;
 939         buf_priv->discard = vertex.discard;
 940
 941         if (!mga_verify_state(dev_priv)) {
 942                 if (vertex.discard) {
 943                         if (buf_priv->dispatched == 1)
 944                                 AGE_BUFFER(buf_priv);
 945                         buf_priv->dispatched = 0;
 946                         mga_freelist_put(dev, buf);
 947                 }
 948                 return DRM_ERR(EINVAL);
 949         }
 950
 951         WRAP_TEST_WITH_RETURN(dev_priv);
 952
 953         mga_dma_dispatch_vertex(dev, buf);
 954
 955         return 0;
 956 }
 957
 958 static int mga_dma_indices(DRM_IOCTL_ARGS)
 959 {
 960         DRM_DEVICE;
 961         drm_mga_private_t *dev_priv = dev->dev_private;
 962         drm_device_dma_t *dma = dev->dma;
 963         drm_buf_t *buf;
 964         drm_mga_buf_priv_t *buf_priv;
 965         drm_mga_indices_t indices;
 966
 967         LOCK_TEST_WITH_RETURN(dev, filp);
 968
 969         DRM_COPY_FROM_USER_IOCTL(indices,
 970                                  (drm_mga_indices_t __user *) data,
 971                                  sizeof(indices));
 972
 973         if (indices.idx < 0 || indices.idx > dma->buf_count)
 974                 return DRM_ERR(EINVAL);
 975
 976         buf = dma->buflist[indices.idx];
 977         buf_priv = buf->dev_private;
 978
 979         buf_priv->discard = indices.discard;
 980
 981         if (!mga_verify_state(dev_priv)) {
 982                 if (indices.discard) {
 983                         if (buf_priv->dispatched == 1)
 984                                 AGE_BUFFER(buf_priv);
 985                         buf_priv->dispatched = 0;
 986                         mga_freelist_put(dev, buf);
 987                 }
 988                 return DRM_ERR(EINVAL);
 989         }
 990
 991         WRAP_TEST_WITH_RETURN(dev_priv);
 992
 993         mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
 994
 995         return 0;
 996 }
 997
 998 static int mga_dma_iload(DRM_IOCTL_ARGS)
 999 {
1000         DRM_DEVICE;
1001         drm_device_dma_t *dma = dev->dma;
1002         drm_mga_private_t *dev_priv = dev->dev_private;
1003         drm_buf_t *buf;
1004         drm_mga_buf_priv_t *buf_priv;
1005         drm_mga_iload_t iload;
1006         DRM_DEBUG("\n");
1007
1008         LOCK_TEST_WITH_RETURN(dev, filp);
1009
1010         DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
1011                                  sizeof(iload));
1012
1013 #if 0
1014         if (mga_do_wait_for_idle(dev_priv) < 0) {
1015                 if (MGA_DMA_DEBUG)
1016                         DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1017                 return DRM_ERR(EBUSY);
1018         }
1019 #endif
1020         if (iload.idx < 0 || iload.idx > dma->buf_count)
1021                 return DRM_ERR(EINVAL);
1022
1023         buf = dma->buflist[iload.idx];
1024         buf_priv = buf->dev_private;
1025
1026         if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
1027                 mga_freelist_put(dev, buf);
1028                 return DRM_ERR(EINVAL);
1029         }
1030
1031         WRAP_TEST_WITH_RETURN(dev_priv);
1032
1033         mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
1034
1035         /* Make sure we restore the 3D state next time.
1036          */
1037         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1038
1039         return 0;
1040 }
1041
1042 static int mga_dma_blit(DRM_IOCTL_ARGS)
1043 {
1044         DRM_DEVICE;
1045         drm_mga_private_t *dev_priv = dev->dev_private;
1046         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1047         drm_mga_blit_t blit;
1048         DRM_DEBUG("\n");
1049
1050         LOCK_TEST_WITH_RETURN(dev, filp);
1051
1052         DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
1053                                  sizeof(blit));
1054
1055         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1056                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1057
1058         if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
1059                 return DRM_ERR(EINVAL);
1060
1061         WRAP_TEST_WITH_RETURN(dev_priv);
1062
1063         mga_dma_dispatch_blit(dev, &blit);
1064
1065         /* Make sure we restore the 3D state next time.
1066          */
1067         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1068
1069         return 0;
1070 }
1071
1072 static int mga_getparam(DRM_IOCTL_ARGS)
1073 {
1074         DRM_DEVICE;
1075         drm_mga_private_t *dev_priv = dev->dev_private;
1076         drm_mga_getparam_t param;
1077         int value;
1078
1079         if (!dev_priv) {
1080                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1081                 return DRM_ERR(EINVAL);
1082         }
1083
1084         DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
1085                                  sizeof(param));
1086
1087         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1088
1089         switch (param.param) {
1090         case MGA_PARAM_IRQ_NR:
1091                 value = dev->irq;
1092                 break;
1093         default:
1094                 return DRM_ERR(EINVAL);
1095         }
1096
1097         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1098                 DRM_ERROR("copy_to_user\n");
1099                 return DRM_ERR(EFAULT);
1100         }
1101
1102         return 0;
1103 }
1104
1105 drm_ioctl_desc_t mga_ioctls[] = {
1106         [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1},
1107         [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0},
1108         [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0},
1109         [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0},
1110         [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0},
1111         [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0},
1112         [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0},
1113         [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0},
1114         [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0},
1115         [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0},
1116 };
1117
1118 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);