1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com */
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 * Gareth Hughes <gareth@valinux.com>
38 #include "dev/drm/drmP.h"
39 #include "dev/drm/drm.h"
40 #include "dev/drm/mga_drm.h"
41 #include "dev/drm/mga_drv.h"
43 /* ================================================================
44 * DMA hardware state programming functions
47 static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
48 drm_clip_rect_t * box)
50 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
51 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
52 unsigned int pitch = dev_priv->front_pitch;
57 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
59 if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
60 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
61 MGA_LEN + MGA_EXEC, 0x80000000,
62 MGA_DWGCTL, ctx->dwgctl,
63 MGA_LEN + MGA_EXEC, 0x80000000);
65 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
66 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
67 MGA_YTOP, box->y1 * pitch,
68 MGA_YBOT, (box->y2 - 1) * pitch);
73 static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
75 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
76 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
81 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
82 MGA_MACCESS, ctx->maccess,
83 MGA_PLNWT, ctx->plnwt,
84 MGA_DWGCTL, ctx->dwgctl);
86 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
87 MGA_FOGCOL, ctx->fogcolor,
88 MGA_WFLAG, ctx->wflag,
89 MGA_ZORG, dev_priv->depth_offset);
91 DMA_BLOCK(MGA_FCOL, ctx->fcol,
92 MGA_DMAPAD, 0x00000000,
93 MGA_DMAPAD, 0x00000000,
94 MGA_DMAPAD, 0x00000000);
99 static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
101 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
102 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
107 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
108 MGA_MACCESS, ctx->maccess,
109 MGA_PLNWT, ctx->plnwt,
110 MGA_DWGCTL, ctx->dwgctl);
112 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
113 MGA_FOGCOL, ctx->fogcolor,
114 MGA_WFLAG, ctx->wflag,
115 MGA_ZORG, dev_priv->depth_offset);
117 DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
118 MGA_TDUALSTAGE0, ctx->tdualstage0,
119 MGA_TDUALSTAGE1, ctx->tdualstage1,
120 MGA_FCOL, ctx->fcol);
122 DMA_BLOCK(MGA_STENCIL, ctx->stencil,
123 MGA_STENCILCTL, ctx->stencilctl,
124 MGA_DMAPAD, 0x00000000,
125 MGA_DMAPAD, 0x00000000);
130 static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
132 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
133 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
138 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
139 MGA_TEXCTL, tex->texctl,
140 MGA_TEXFILTER, tex->texfilter,
141 MGA_TEXBORDERCOL, tex->texbordercol);
143 DMA_BLOCK(MGA_TEXORG, tex->texorg,
144 MGA_TEXORG1, tex->texorg1,
145 MGA_TEXORG2, tex->texorg2,
146 MGA_TEXORG3, tex->texorg3);
148 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
149 MGA_TEXWIDTH, tex->texwidth,
150 MGA_TEXHEIGHT, tex->texheight,
151 MGA_WR24, tex->texwidth);
153 DMA_BLOCK(MGA_WR34, tex->texheight,
154 MGA_TEXTRANS, 0x0000ffff,
155 MGA_TEXTRANSHIGH, 0x0000ffff,
156 MGA_DMAPAD, 0x00000000);
161 static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
163 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
164 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
167 /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
168 /* tex->texctl, tex->texctl2); */
172 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
173 MGA_TEXCTL, tex->texctl,
174 MGA_TEXFILTER, tex->texfilter,
175 MGA_TEXBORDERCOL, tex->texbordercol);
177 DMA_BLOCK(MGA_TEXORG, tex->texorg,
178 MGA_TEXORG1, tex->texorg1,
179 MGA_TEXORG2, tex->texorg2,
180 MGA_TEXORG3, tex->texorg3);
182 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
183 MGA_TEXWIDTH, tex->texwidth,
184 MGA_TEXHEIGHT, tex->texheight,
185 MGA_WR49, 0x00000000);
187 DMA_BLOCK(MGA_WR57, 0x00000000,
188 MGA_WR53, 0x00000000,
189 MGA_WR61, 0x00000000,
190 MGA_WR52, MGA_G400_WR_MAGIC);
192 DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
193 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
194 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
195 MGA_DMAPAD, 0x00000000);
197 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
198 MGA_DMAPAD, 0x00000000,
199 MGA_TEXTRANS, 0x0000ffff,
200 MGA_TEXTRANSHIGH, 0x0000ffff);
205 static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
207 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
208 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
211 /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
212 /* tex->texctl, tex->texctl2); */
216 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
219 MGA_TEXCTL, tex->texctl,
220 MGA_TEXFILTER, tex->texfilter,
221 MGA_TEXBORDERCOL, tex->texbordercol);
223 DMA_BLOCK(MGA_TEXORG, tex->texorg,
224 MGA_TEXORG1, tex->texorg1,
225 MGA_TEXORG2, tex->texorg2,
226 MGA_TEXORG3, tex->texorg3);
228 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
229 MGA_TEXWIDTH, tex->texwidth,
230 MGA_TEXHEIGHT, tex->texheight,
231 MGA_WR49, 0x00000000);
233 DMA_BLOCK(MGA_WR57, 0x00000000,
234 MGA_WR53, 0x00000000,
235 MGA_WR61, 0x00000000,
236 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
238 DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
239 MGA_TEXTRANS, 0x0000ffff,
240 MGA_TEXTRANSHIGH, 0x0000ffff,
241 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
246 static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
248 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
249 unsigned int pipe = sarea_priv->warp_pipe;
254 DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
255 MGA_WVRTXSZ, 0x00000007,
256 MGA_WFLAG, 0x00000000,
257 MGA_WR24, 0x00000000);
259 DMA_BLOCK(MGA_WR25, 0x00000100,
260 MGA_WR34, 0x00000000,
261 MGA_WR42, 0x0000ffff,
262 MGA_WR60, 0x0000ffff);
264 /* Padding required to to hardware bug.
266 DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
267 MGA_DMAPAD, 0xffffffff,
268 MGA_DMAPAD, 0xffffffff,
269 MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
270 MGA_WMODE_START | MGA_WAGP_ENABLE));
275 static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
277 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
278 unsigned int pipe = sarea_priv->warp_pipe;
281 /* printk("mga_g400_emit_pipe %x\n", pipe); */
285 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
286 MGA_DMAPAD, 0x00000000,
287 MGA_DMAPAD, 0x00000000,
288 MGA_DMAPAD, 0x00000000);
291 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
292 MGA_DMAPAD, 0x00000000,
293 MGA_DMAPAD, 0x00000000,
294 MGA_DMAPAD, 0x00000000);
296 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
297 MGA_WACCEPTSEQ, 0x00000000,
298 MGA_WACCEPTSEQ, 0x00000000,
299 MGA_WACCEPTSEQ, 0x1e000000);
301 if (dev_priv->warp_pipe & MGA_T2) {
302 /* Flush the WARP pipe */
303 DMA_BLOCK(MGA_YDST, 0x00000000,
304 MGA_FXLEFT, 0x00000000,
305 MGA_FXRIGHT, 0x00000001,
306 MGA_DWGCTL, MGA_DWGCTL_FLUSH);
308 DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
309 MGA_DWGSYNC, 0x00007000,
310 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
311 MGA_LEN + MGA_EXEC, 0x00000000);
313 DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
315 MGA_LEN + MGA_EXEC, 0x00000000,
316 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
317 MGA_DMAPAD, 0x00000000);
320 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
321 MGA_DMAPAD, 0x00000000,
322 MGA_DMAPAD, 0x00000000,
323 MGA_DMAPAD, 0x00000000);
325 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
326 MGA_WACCEPTSEQ, 0x00000000,
327 MGA_WACCEPTSEQ, 0x00000000,
328 MGA_WACCEPTSEQ, 0x18000000);
331 DMA_BLOCK(MGA_WFLAG, 0x00000000,
332 MGA_WFLAG1, 0x00000000,
333 MGA_WR56, MGA_G400_WR56_MAGIC,
334 MGA_DMAPAD, 0x00000000);
336 DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */
337 MGA_WR57, 0x00000000, /* tex0 */
338 MGA_WR53, 0x00000000, /* tex1 */
339 MGA_WR61, 0x00000000); /* tex1 */
341 DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
342 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
343 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
344 MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */
346 /* Padding required to to hardware bug */
347 DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
348 MGA_DMAPAD, 0xffffffff,
349 MGA_DMAPAD, 0xffffffff,
350 MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
351 MGA_WMODE_START | MGA_WAGP_ENABLE));
356 static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
358 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
359 unsigned int dirty = sarea_priv->dirty;
361 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
362 mga_g200_emit_pipe(dev_priv);
363 dev_priv->warp_pipe = sarea_priv->warp_pipe;
366 if (dirty & MGA_UPLOAD_CONTEXT) {
367 mga_g200_emit_context(dev_priv);
368 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
371 if (dirty & MGA_UPLOAD_TEX0) {
372 mga_g200_emit_tex0(dev_priv);
373 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
377 static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
379 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
380 unsigned int dirty = sarea_priv->dirty;
381 int multitex = sarea_priv->warp_pipe & MGA_T2;
383 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
384 mga_g400_emit_pipe(dev_priv);
385 dev_priv->warp_pipe = sarea_priv->warp_pipe;
388 if (dirty & MGA_UPLOAD_CONTEXT) {
389 mga_g400_emit_context(dev_priv);
390 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
393 if (dirty & MGA_UPLOAD_TEX0) {
394 mga_g400_emit_tex0(dev_priv);
395 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
398 if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
399 mga_g400_emit_tex1(dev_priv);
400 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
404 /* ================================================================
405 * SAREA state verification
408 /* Disallow all write destinations except the front and backbuffer.
410 static int mga_verify_context(drm_mga_private_t * dev_priv)
412 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
413 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
415 if (ctx->dstorg != dev_priv->front_offset &&
416 ctx->dstorg != dev_priv->back_offset) {
417 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
418 ctx->dstorg, dev_priv->front_offset,
419 dev_priv->back_offset);
421 return DRM_ERR(EINVAL);
427 /* Disallow texture reads from PCI space.
429 static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
431 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
432 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
435 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
437 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
438 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
440 return DRM_ERR(EINVAL);
446 static int mga_verify_state(drm_mga_private_t * dev_priv)
448 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
449 unsigned int dirty = sarea_priv->dirty;
452 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
453 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
455 if (dirty & MGA_UPLOAD_CONTEXT)
456 ret |= mga_verify_context(dev_priv);
458 if (dirty & MGA_UPLOAD_TEX0)
459 ret |= mga_verify_tex(dev_priv, 0);
461 if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
462 if (dirty & MGA_UPLOAD_TEX1)
463 ret |= mga_verify_tex(dev_priv, 1);
465 if (dirty & MGA_UPLOAD_PIPE)
466 ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
468 if (dirty & MGA_UPLOAD_PIPE)
469 ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
475 static int mga_verify_iload(drm_mga_private_t * dev_priv,
476 unsigned int dstorg, unsigned int length)
478 if (dstorg < dev_priv->texture_offset ||
479 dstorg + length > (dev_priv->texture_offset +
480 dev_priv->texture_size)) {
481 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
482 return DRM_ERR(EINVAL);
485 if (length & MGA_ILOAD_MASK) {
486 DRM_ERROR("*** bad iload length: 0x%x\n",
487 length & MGA_ILOAD_MASK);
488 return DRM_ERR(EINVAL);
494 static int mga_verify_blit(drm_mga_private_t * dev_priv,
495 unsigned int srcorg, unsigned int dstorg)
497 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
498 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
499 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
500 return DRM_ERR(EINVAL);
505 /* ================================================================
509 static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
511 drm_mga_private_t *dev_priv = dev->dev_private;
512 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
513 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
514 drm_clip_rect_t *pbox = sarea_priv->boxes;
515 int nbox = sarea_priv->nbox;
522 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
523 MGA_DMAPAD, 0x00000000,
524 MGA_DWGSYNC, 0x00007100,
525 MGA_DWGSYNC, 0x00007000);
529 for (i = 0; i < nbox; i++) {
530 drm_clip_rect_t *box = &pbox[i];
531 u32 height = box->y2 - box->y1;
533 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
534 box->x1, box->y1, box->x2, box->y2);
536 if (clear->flags & MGA_FRONT) {
539 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
540 MGA_PLNWT, clear->color_mask,
541 MGA_YDSTLEN, (box->y1 << 16) | height,
542 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
544 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
545 MGA_FCOL, clear->clear_color,
546 MGA_DSTORG, dev_priv->front_offset,
547 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
552 if (clear->flags & MGA_BACK) {
555 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
556 MGA_PLNWT, clear->color_mask,
557 MGA_YDSTLEN, (box->y1 << 16) | height,
558 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
560 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
561 MGA_FCOL, clear->clear_color,
562 MGA_DSTORG, dev_priv->back_offset,
563 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
568 if (clear->flags & MGA_DEPTH) {
571 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
572 MGA_PLNWT, clear->depth_mask,
573 MGA_YDSTLEN, (box->y1 << 16) | height,
574 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
576 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
577 MGA_FCOL, clear->clear_depth,
578 MGA_DSTORG, dev_priv->depth_offset,
579 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
588 /* Force reset of DWGCTL */
589 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
590 MGA_DMAPAD, 0x00000000,
591 MGA_PLNWT, ctx->plnwt,
592 MGA_DWGCTL, ctx->dwgctl);
599 static void mga_dma_dispatch_swap(drm_device_t * dev)
601 drm_mga_private_t *dev_priv = dev->dev_private;
602 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
603 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
604 drm_clip_rect_t *pbox = sarea_priv->boxes;
605 int nbox = sarea_priv->nbox;
610 sarea_priv->last_frame.head = dev_priv->prim.tail;
611 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
615 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
616 MGA_DMAPAD, 0x00000000,
617 MGA_DWGSYNC, 0x00007100,
618 MGA_DWGSYNC, 0x00007000);
620 DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
621 MGA_MACCESS, dev_priv->maccess,
622 MGA_SRCORG, dev_priv->back_offset,
623 MGA_AR5, dev_priv->front_pitch);
625 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
626 MGA_DMAPAD, 0x00000000,
627 MGA_PLNWT, 0xffffffff,
628 MGA_DWGCTL, MGA_DWGCTL_COPY);
630 for (i = 0; i < nbox; i++) {
631 drm_clip_rect_t *box = &pbox[i];
632 u32 height = box->y2 - box->y1;
633 u32 start = box->y1 * dev_priv->front_pitch;
635 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
636 box->x1, box->y1, box->x2, box->y2);
638 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
639 MGA_AR3, start + box->x1,
640 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
641 MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
644 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
645 MGA_PLNWT, ctx->plnwt,
646 MGA_SRCORG, dev_priv->front_offset,
647 MGA_DWGCTL, ctx->dwgctl);
653 DRM_DEBUG("%s... done.\n", __FUNCTION__);
656 static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
658 drm_mga_private_t *dev_priv = dev->dev_private;
659 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
660 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
661 u32 address = (u32) buf->bus_address;
662 u32 length = (u32) buf->used;
665 DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
668 buf_priv->dispatched = 1;
670 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
673 if (i < sarea_priv->nbox) {
674 mga_emit_clip_rect(dev_priv,
675 &sarea_priv->boxes[i]);
680 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
681 MGA_DMAPAD, 0x00000000,
682 MGA_SECADDRESS, (address |
684 MGA_SECEND, ((address + length) |
688 } while (++i < sarea_priv->nbox);
691 if (buf_priv->discard) {
692 AGE_BUFFER(buf_priv);
695 buf_priv->dispatched = 0;
697 mga_freelist_put(dev, buf);
703 static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
704 unsigned int start, unsigned int end)
706 drm_mga_private_t *dev_priv = dev->dev_private;
707 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
708 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
709 u32 address = (u32) buf->bus_address;
712 DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
715 buf_priv->dispatched = 1;
717 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
720 if (i < sarea_priv->nbox) {
721 mga_emit_clip_rect(dev_priv,
722 &sarea_priv->boxes[i]);
727 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
728 MGA_DMAPAD, 0x00000000,
729 MGA_SETUPADDRESS, address + start,
730 MGA_SETUPEND, ((address + end) |
734 } while (++i < sarea_priv->nbox);
737 if (buf_priv->discard) {
738 AGE_BUFFER(buf_priv);
741 buf_priv->dispatched = 0;
743 mga_freelist_put(dev, buf);
749 /* This copies a 64 byte aligned agp region to the frambuffer with a
750 * standard blit, the ioctl needs to do checking.
752 static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
753 unsigned int dstorg, unsigned int length)
755 drm_mga_private_t *dev_priv = dev->dev_private;
756 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
757 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
758 u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
761 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
767 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
768 MGA_DMAPAD, 0x00000000,
769 MGA_DWGSYNC, 0x00007100,
770 MGA_DWGSYNC, 0x00007000);
772 DMA_BLOCK(MGA_DSTORG, dstorg,
773 MGA_MACCESS, 0x00000000,
777 DMA_BLOCK(MGA_PITCH, 64,
778 MGA_PLNWT, 0xffffffff,
779 MGA_DMAPAD, 0x00000000,
780 MGA_DWGCTL, MGA_DWGCTL_COPY);
782 DMA_BLOCK(MGA_AR0, 63,
784 MGA_FXBNDRY, (63 << 16) | 0,
785 MGA_YDSTLEN + MGA_EXEC, y2);
787 DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
788 MGA_SRCORG, dev_priv->front_offset,
789 MGA_PITCH, dev_priv->front_pitch,
790 MGA_DWGSYNC, 0x00007000);
794 AGE_BUFFER(buf_priv);
798 buf_priv->dispatched = 0;
800 mga_freelist_put(dev, buf);
805 static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
807 drm_mga_private_t *dev_priv = dev->dev_private;
808 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
809 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
810 drm_clip_rect_t *pbox = sarea_priv->boxes;
811 int nbox = sarea_priv->nbox;
818 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
819 MGA_DMAPAD, 0x00000000,
820 MGA_DWGSYNC, 0x00007100,
821 MGA_DWGSYNC, 0x00007000);
823 DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
824 MGA_PLNWT, blit->planemask,
825 MGA_SRCORG, blit->srcorg,
826 MGA_DSTORG, blit->dstorg);
828 DMA_BLOCK(MGA_SGN, scandir,
829 MGA_MACCESS, dev_priv->maccess,
830 MGA_AR5, blit->ydir * blit->src_pitch,
831 MGA_PITCH, blit->dst_pitch);
833 for (i = 0; i < nbox; i++) {
834 int srcx = pbox[i].x1 + blit->delta_sx;
835 int srcy = pbox[i].y1 + blit->delta_sy;
836 int dstx = pbox[i].x1 + blit->delta_dx;
837 int dsty = pbox[i].y1 + blit->delta_dy;
838 int h = pbox[i].y2 - pbox[i].y1;
839 int w = pbox[i].x2 - pbox[i].x1 - 1;
842 if (blit->ydir == -1) {
843 srcy = blit->height - srcy - 1;
846 start = srcy * blit->src_pitch + srcx;
848 DMA_BLOCK(MGA_AR0, start + w,
850 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
851 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
854 /* Do something to flush AGP?
857 /* Force reset of DWGCTL */
858 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
859 MGA_PLNWT, ctx->plnwt,
860 MGA_PITCH, dev_priv->front_pitch,
861 MGA_DWGCTL, ctx->dwgctl);
866 /* ================================================================
870 static int mga_dma_clear(DRM_IOCTL_ARGS)
873 drm_mga_private_t *dev_priv = dev->dev_private;
874 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
875 drm_mga_clear_t clear;
877 LOCK_TEST_WITH_RETURN(dev, filp);
879 DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
882 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
883 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
885 WRAP_TEST_WITH_RETURN(dev_priv);
887 mga_dma_dispatch_clear(dev, &clear);
889 /* Make sure we restore the 3D state next time.
891 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
896 static int mga_dma_swap(DRM_IOCTL_ARGS)
899 drm_mga_private_t *dev_priv = dev->dev_private;
900 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
902 LOCK_TEST_WITH_RETURN(dev, filp);
904 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
905 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
907 WRAP_TEST_WITH_RETURN(dev_priv);
909 mga_dma_dispatch_swap(dev);
911 /* Make sure we restore the 3D state next time.
913 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
918 static int mga_dma_vertex(DRM_IOCTL_ARGS)
921 drm_mga_private_t *dev_priv = dev->dev_private;
922 drm_device_dma_t *dma = dev->dma;
924 drm_mga_buf_priv_t *buf_priv;
925 drm_mga_vertex_t vertex;
927 LOCK_TEST_WITH_RETURN(dev, filp);
929 DRM_COPY_FROM_USER_IOCTL(vertex,
930 (drm_mga_vertex_t __user *) data,
933 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
934 return DRM_ERR(EINVAL);
935 buf = dma->buflist[vertex.idx];
936 buf_priv = buf->dev_private;
938 buf->used = vertex.used;
939 buf_priv->discard = vertex.discard;
941 if (!mga_verify_state(dev_priv)) {
942 if (vertex.discard) {
943 if (buf_priv->dispatched == 1)
944 AGE_BUFFER(buf_priv);
945 buf_priv->dispatched = 0;
946 mga_freelist_put(dev, buf);
948 return DRM_ERR(EINVAL);
951 WRAP_TEST_WITH_RETURN(dev_priv);
953 mga_dma_dispatch_vertex(dev, buf);
958 static int mga_dma_indices(DRM_IOCTL_ARGS)
961 drm_mga_private_t *dev_priv = dev->dev_private;
962 drm_device_dma_t *dma = dev->dma;
964 drm_mga_buf_priv_t *buf_priv;
965 drm_mga_indices_t indices;
967 LOCK_TEST_WITH_RETURN(dev, filp);
969 DRM_COPY_FROM_USER_IOCTL(indices,
970 (drm_mga_indices_t __user *) data,
973 if (indices.idx < 0 || indices.idx > dma->buf_count)
974 return DRM_ERR(EINVAL);
976 buf = dma->buflist[indices.idx];
977 buf_priv = buf->dev_private;
979 buf_priv->discard = indices.discard;
981 if (!mga_verify_state(dev_priv)) {
982 if (indices.discard) {
983 if (buf_priv->dispatched == 1)
984 AGE_BUFFER(buf_priv);
985 buf_priv->dispatched = 0;
986 mga_freelist_put(dev, buf);
988 return DRM_ERR(EINVAL);
991 WRAP_TEST_WITH_RETURN(dev_priv);
993 mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
998 static int mga_dma_iload(DRM_IOCTL_ARGS)
1001 drm_device_dma_t *dma = dev->dma;
1002 drm_mga_private_t *dev_priv = dev->dev_private;
1004 drm_mga_buf_priv_t *buf_priv;
1005 drm_mga_iload_t iload;
1008 LOCK_TEST_WITH_RETURN(dev, filp);
1010 DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
1014 if (mga_do_wait_for_idle(dev_priv) < 0) {
1016 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1017 return DRM_ERR(EBUSY);
1020 if (iload.idx < 0 || iload.idx > dma->buf_count)
1021 return DRM_ERR(EINVAL);
1023 buf = dma->buflist[iload.idx];
1024 buf_priv = buf->dev_private;
1026 if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
1027 mga_freelist_put(dev, buf);
1028 return DRM_ERR(EINVAL);
1031 WRAP_TEST_WITH_RETURN(dev_priv);
1033 mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
1035 /* Make sure we restore the 3D state next time.
1037 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1042 static int mga_dma_blit(DRM_IOCTL_ARGS)
1045 drm_mga_private_t *dev_priv = dev->dev_private;
1046 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1047 drm_mga_blit_t blit;
1050 LOCK_TEST_WITH_RETURN(dev, filp);
1052 DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
1055 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1056 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1058 if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
1059 return DRM_ERR(EINVAL);
1061 WRAP_TEST_WITH_RETURN(dev_priv);
1063 mga_dma_dispatch_blit(dev, &blit);
1065 /* Make sure we restore the 3D state next time.
1067 dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1072 static int mga_getparam(DRM_IOCTL_ARGS)
1075 drm_mga_private_t *dev_priv = dev->dev_private;
1076 drm_mga_getparam_t param;
1080 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1081 return DRM_ERR(EINVAL);
1084 DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
1087 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1089 switch (param.param) {
1090 case MGA_PARAM_IRQ_NR:
1094 return DRM_ERR(EINVAL);
1097 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1098 DRM_ERROR("copy_to_user\n");
1099 return DRM_ERR(EFAULT);
1105 drm_ioctl_desc_t mga_ioctls[] = {
1106 [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1},
1107 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0},
1108 [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0},
1109 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0},
1110 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0},
1111 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0},
1112 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0},
1113 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0},
1114 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0},
1115 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0},
1118 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);