1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Gareth Hughes <gareth@valinux.com>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include "dev/drm/drmP.h"
36 #include "dev/drm/drm.h"
37 #include "dev/drm/r128_drm.h"
38 #include "dev/drm/r128_drv.h"
40 #define R128_FIFO_DEBUG 0
42 /* CCE microcode (from ATI) */
43 static u32 r128_cce_microcode[] = {
44 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
45 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
46 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
47 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
48 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
49 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
50 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
51 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
52 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
53 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
54 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
55 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
56 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
57 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
58 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
59 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
60 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
61 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
62 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
63 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
64 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
65 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
66 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
67 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
68 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
69 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
70 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
71 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
72 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
73 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
74 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
75 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
76 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
77 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
78 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
84 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
87 static int R128_READ_PLL(drm_device_t * dev, int addr)
89 drm_r128_private_t *dev_priv = dev->dev_private;
91 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
92 return R128_READ(R128_CLOCK_CNTL_DATA);
96 static void r128_status(drm_r128_private_t * dev_priv)
98 printk("GUI_STAT = 0x%08x\n",
99 (unsigned int)R128_READ(R128_GUI_STAT));
100 printk("PM4_STAT = 0x%08x\n",
101 (unsigned int)R128_READ(R128_PM4_STAT));
102 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
103 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
104 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
105 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
106 printk("PM4_MICRO_CNTL = 0x%08x\n",
107 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
108 printk("PM4_BUFFER_CNTL = 0x%08x\n",
109 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
113 /* ================================================================
114 * Engine, FIFO control
117 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
122 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
123 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
125 for (i = 0; i < dev_priv->usec_timeout; i++) {
126 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
133 DRM_ERROR("failed!\n");
135 return DRM_ERR(EBUSY);
138 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
142 for (i = 0; i < dev_priv->usec_timeout; i++) {
143 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
144 if (slots >= entries)
150 DRM_ERROR("failed!\n");
152 return DRM_ERR(EBUSY);
155 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
159 ret = r128_do_wait_for_fifo(dev_priv, 64);
163 for (i = 0; i < dev_priv->usec_timeout; i++) {
164 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
165 r128_do_pixcache_flush(dev_priv);
172 DRM_ERROR("failed!\n");
174 return DRM_ERR(EBUSY);
177 /* ================================================================
178 * CCE control, initialization
181 /* Load the microcode for the CCE */
182 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
188 r128_do_wait_for_idle(dev_priv);
190 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
191 for (i = 0; i < 256; i++) {
192 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
193 R128_WRITE(R128_PM4_MICROCODE_DATAL,
194 r128_cce_microcode[i * 2 + 1]);
198 /* Flush any pending commands to the CCE. This should only be used just
199 * prior to a wait for idle, as it informs the engine that the command
202 static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
206 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
207 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
210 /* Wait for the CCE to go idle.
212 int r128_do_cce_idle(drm_r128_private_t * dev_priv)
216 for (i = 0; i < dev_priv->usec_timeout; i++) {
217 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
218 int pm4stat = R128_READ(R128_PM4_STAT);
219 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
220 dev_priv->cce_fifo_size) &&
221 !(pm4stat & (R128_PM4_BUSY |
222 R128_PM4_GUI_ACTIVE))) {
223 return r128_do_pixcache_flush(dev_priv);
230 DRM_ERROR("failed!\n");
231 r128_status(dev_priv);
233 return DRM_ERR(EBUSY);
236 /* Start the Concurrent Command Engine.
238 static void r128_do_cce_start(drm_r128_private_t * dev_priv)
240 r128_do_wait_for_idle(dev_priv);
242 R128_WRITE(R128_PM4_BUFFER_CNTL,
243 dev_priv->cce_mode | dev_priv->ring.size_l2qw
244 | R128_PM4_BUFFER_CNTL_NOUPDATE);
245 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
246 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
248 dev_priv->cce_running = 1;
251 /* Reset the Concurrent Command Engine. This will not flush any pending
252 * commands, so you must wait for the CCE command stream to complete
253 * before calling this routine.
255 static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
257 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
258 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
259 dev_priv->ring.tail = 0;
262 /* Stop the Concurrent Command Engine. This will not flush any pending
263 * commands, so you must flush the command stream and wait for the CCE
264 * to go idle before calling this routine.
266 static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
268 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
269 R128_WRITE(R128_PM4_BUFFER_CNTL,
270 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
272 dev_priv->cce_running = 0;
275 /* Reset the engine. This will stop the CCE if it is running.
277 static int r128_do_engine_reset(drm_device_t * dev)
279 drm_r128_private_t *dev_priv = dev->dev_private;
280 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
282 r128_do_pixcache_flush(dev_priv);
284 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
285 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
287 R128_WRITE_PLL(R128_MCLK_CNTL,
288 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
290 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
292 /* Taken from the sample code - do not change */
293 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
294 R128_READ(R128_GEN_RESET_CNTL);
295 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
296 R128_READ(R128_GEN_RESET_CNTL);
298 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
299 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
300 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
302 /* Reset the CCE ring */
303 r128_do_cce_reset(dev_priv);
305 /* The CCE is no longer running after an engine reset */
306 dev_priv->cce_running = 0;
308 /* Reset any pending vertex, indirect buffers */
309 r128_freelist_reset(dev);
314 static void r128_cce_init_ring_buffer(drm_device_t * dev,
315 drm_r128_private_t * dev_priv)
322 /* The manual (p. 2) says this address is in "VM space". This
323 * means it's an offset from the start of AGP space.
326 if (!dev_priv->is_pci)
327 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
330 ring_start = dev_priv->cce_ring->offset -
331 (unsigned long)dev->sg->virtual;
333 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
335 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
336 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
338 /* Set watermark control */
339 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
340 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
341 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
342 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
343 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
345 /* Force read. Why? Because it's in the examples... */
346 R128_READ(R128_PM4_BUFFER_ADDR);
348 /* Turn on bus mastering */
349 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
350 R128_WRITE(R128_BUS_CNTL, tmp);
353 static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
355 drm_r128_private_t *dev_priv;
359 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
360 if (dev_priv == NULL)
361 return DRM_ERR(ENOMEM);
363 memset(dev_priv, 0, sizeof(drm_r128_private_t));
365 dev_priv->is_pci = init->is_pci;
367 if (dev_priv->is_pci && !dev->sg) {
368 DRM_ERROR("PCI GART memory not allocated!\n");
369 dev->dev_private = (void *)dev_priv;
370 r128_do_cleanup_cce(dev);
371 return DRM_ERR(EINVAL);
374 dev_priv->usec_timeout = init->usec_timeout;
375 if (dev_priv->usec_timeout < 1 ||
376 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
377 DRM_DEBUG("TIMEOUT problem!\n");
378 dev->dev_private = (void *)dev_priv;
379 r128_do_cleanup_cce(dev);
380 return DRM_ERR(EINVAL);
383 dev_priv->cce_mode = init->cce_mode;
385 /* GH: Simple idle check.
387 atomic_set(&dev_priv->idle_count, 0);
389 /* We don't support anything other than bus-mastering ring mode,
390 * but the ring can be in either AGP or PCI space for the ring
393 if ((init->cce_mode != R128_PM4_192BM) &&
394 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
395 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
396 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
397 DRM_DEBUG("Bad cce_mode!\n");
398 dev->dev_private = (void *)dev_priv;
399 r128_do_cleanup_cce(dev);
400 return DRM_ERR(EINVAL);
403 switch (init->cce_mode) {
404 case R128_PM4_NONPM4:
405 dev_priv->cce_fifo_size = 0;
407 case R128_PM4_192PIO:
409 dev_priv->cce_fifo_size = 192;
411 case R128_PM4_128PIO_64INDBM:
412 case R128_PM4_128BM_64INDBM:
413 dev_priv->cce_fifo_size = 128;
415 case R128_PM4_64PIO_128INDBM:
416 case R128_PM4_64BM_128INDBM:
417 case R128_PM4_64PIO_64VCBM_64INDBM:
418 case R128_PM4_64BM_64VCBM_64INDBM:
419 case R128_PM4_64PIO_64VCPIO_64INDPIO:
420 dev_priv->cce_fifo_size = 64;
424 switch (init->fb_bpp) {
426 dev_priv->color_fmt = R128_DATATYPE_RGB565;
430 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
433 dev_priv->front_offset = init->front_offset;
434 dev_priv->front_pitch = init->front_pitch;
435 dev_priv->back_offset = init->back_offset;
436 dev_priv->back_pitch = init->back_pitch;
438 switch (init->depth_bpp) {
440 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
445 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
448 dev_priv->depth_offset = init->depth_offset;
449 dev_priv->depth_pitch = init->depth_pitch;
450 dev_priv->span_offset = init->span_offset;
452 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
453 (dev_priv->front_offset >> 5));
454 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
455 (dev_priv->back_offset >> 5));
456 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
457 (dev_priv->depth_offset >> 5) |
459 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
460 (dev_priv->span_offset >> 5));
464 if (!dev_priv->sarea) {
465 DRM_ERROR("could not find sarea!\n");
466 dev->dev_private = (void *)dev_priv;
467 r128_do_cleanup_cce(dev);
468 return DRM_ERR(EINVAL);
471 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
472 if (!dev_priv->mmio) {
473 DRM_ERROR("could not find mmio region!\n");
474 dev->dev_private = (void *)dev_priv;
475 r128_do_cleanup_cce(dev);
476 return DRM_ERR(EINVAL);
478 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
479 if (!dev_priv->cce_ring) {
480 DRM_ERROR("could not find cce ring region!\n");
481 dev->dev_private = (void *)dev_priv;
482 r128_do_cleanup_cce(dev);
483 return DRM_ERR(EINVAL);
485 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
486 if (!dev_priv->ring_rptr) {
487 DRM_ERROR("could not find ring read pointer!\n");
488 dev->dev_private = (void *)dev_priv;
489 r128_do_cleanup_cce(dev);
490 return DRM_ERR(EINVAL);
492 dev->agp_buffer_token = init->buffers_offset;
493 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
494 if (!dev->agp_buffer_map) {
495 DRM_ERROR("could not find dma buffer region!\n");
496 dev->dev_private = (void *)dev_priv;
497 r128_do_cleanup_cce(dev);
498 return DRM_ERR(EINVAL);
501 if (!dev_priv->is_pci) {
502 dev_priv->agp_textures =
503 drm_core_findmap(dev, init->agp_textures_offset);
504 if (!dev_priv->agp_textures) {
505 DRM_ERROR("could not find agp texture region!\n");
506 dev->dev_private = (void *)dev_priv;
507 r128_do_cleanup_cce(dev);
508 return DRM_ERR(EINVAL);
512 dev_priv->sarea_priv =
513 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
514 init->sarea_priv_offset);
517 if (!dev_priv->is_pci) {
518 drm_core_ioremap(dev_priv->cce_ring, dev);
519 drm_core_ioremap(dev_priv->ring_rptr, dev);
520 drm_core_ioremap(dev->agp_buffer_map, dev);
521 if (!dev_priv->cce_ring->handle ||
522 !dev_priv->ring_rptr->handle ||
523 !dev->agp_buffer_map->handle) {
524 DRM_ERROR("Could not ioremap agp regions!\n");
525 dev->dev_private = (void *)dev_priv;
526 r128_do_cleanup_cce(dev);
527 return DRM_ERR(ENOMEM);
532 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
533 dev_priv->ring_rptr->handle =
534 (void *)dev_priv->ring_rptr->offset;
535 dev->agp_buffer_map->handle =
536 (void *)dev->agp_buffer_map->offset;
540 if (!dev_priv->is_pci)
541 dev_priv->cce_buffers_offset = dev->agp->base;
544 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
546 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
547 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
548 + init->ring_size / sizeof(u32));
549 dev_priv->ring.size = init->ring_size;
550 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
552 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
554 dev_priv->ring.high_mark = 128;
556 dev_priv->sarea_priv->last_frame = 0;
557 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
559 dev_priv->sarea_priv->last_dispatch = 0;
560 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
563 if (dev_priv->is_pci) {
565 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
566 dev_priv->gart_info.addr = NULL;
567 dev_priv->gart_info.bus_addr = 0;
568 dev_priv->gart_info.is_pcie = 0;
569 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
570 DRM_ERROR("failed to init PCI GART!\n");
571 dev->dev_private = (void *)dev_priv;
572 r128_do_cleanup_cce(dev);
573 return DRM_ERR(ENOMEM);
575 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
580 r128_cce_init_ring_buffer(dev, dev_priv);
581 r128_cce_load_microcode(dev_priv);
583 dev->dev_private = (void *)dev_priv;
585 r128_do_engine_reset(dev);
590 int r128_do_cleanup_cce(drm_device_t * dev)
593 /* Make sure interrupts are disabled here because the uninstall ioctl
594 * may not have been called from userspace and after dev_private
595 * is freed, it's too late.
597 if (dev->irq_enabled)
598 drm_irq_uninstall(dev);
600 if (dev->dev_private) {
601 drm_r128_private_t *dev_priv = dev->dev_private;
604 if (!dev_priv->is_pci) {
605 if (dev_priv->cce_ring != NULL)
606 drm_core_ioremapfree(dev_priv->cce_ring, dev);
607 if (dev_priv->ring_rptr != NULL)
608 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
609 if (dev->agp_buffer_map != NULL) {
610 drm_core_ioremapfree(dev->agp_buffer_map, dev);
611 dev->agp_buffer_map = NULL;
616 if (dev_priv->gart_info.bus_addr)
617 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
618 DRM_ERROR("failed to cleanup PCI GART!\n");
621 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
623 dev->dev_private = NULL;
629 int r128_cce_init(DRM_IOCTL_ARGS)
632 drm_r128_init_t init;
636 LOCK_TEST_WITH_RETURN(dev, filp);
638 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
643 return r128_do_init_cce(dev, &init);
644 case R128_CLEANUP_CCE:
645 return r128_do_cleanup_cce(dev);
648 return DRM_ERR(EINVAL);
651 int r128_cce_start(DRM_IOCTL_ARGS)
654 drm_r128_private_t *dev_priv = dev->dev_private;
657 LOCK_TEST_WITH_RETURN(dev, filp);
659 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
660 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
664 r128_do_cce_start(dev_priv);
669 /* Stop the CCE. The engine must have been idled before calling this
672 int r128_cce_stop(DRM_IOCTL_ARGS)
675 drm_r128_private_t *dev_priv = dev->dev_private;
676 drm_r128_cce_stop_t stop;
680 LOCK_TEST_WITH_RETURN(dev, filp);
682 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
685 /* Flush any pending CCE commands. This ensures any outstanding
686 * commands are exectuted by the engine before we turn it off.
689 r128_do_cce_flush(dev_priv);
692 /* If we fail to make the engine go idle, we return an error
693 * code so that the DRM ioctl wrapper can try again.
696 ret = r128_do_cce_idle(dev_priv);
701 /* Finally, we can turn off the CCE. If the engine isn't idle,
702 * we will get some dropped triangles as they won't be fully
703 * rendered before the CCE is shut down.
705 r128_do_cce_stop(dev_priv);
707 /* Reset the engine */
708 r128_do_engine_reset(dev);
713 /* Just reset the CCE ring. Called as part of an X Server engine reset.
715 int r128_cce_reset(DRM_IOCTL_ARGS)
718 drm_r128_private_t *dev_priv = dev->dev_private;
721 LOCK_TEST_WITH_RETURN(dev, filp);
724 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
725 return DRM_ERR(EINVAL);
728 r128_do_cce_reset(dev_priv);
730 /* The CCE is no longer running after an engine reset */
731 dev_priv->cce_running = 0;
736 int r128_cce_idle(DRM_IOCTL_ARGS)
739 drm_r128_private_t *dev_priv = dev->dev_private;
742 LOCK_TEST_WITH_RETURN(dev, filp);
744 if (dev_priv->cce_running) {
745 r128_do_cce_flush(dev_priv);
748 return r128_do_cce_idle(dev_priv);
751 int r128_engine_reset(DRM_IOCTL_ARGS)
756 LOCK_TEST_WITH_RETURN(dev, filp);
758 return r128_do_engine_reset(dev);
761 int r128_fullscreen(DRM_IOCTL_ARGS)
763 return DRM_ERR(EINVAL);
766 /* ================================================================
767 * Freelist management
769 #define R128_BUFFER_USED 0xffffffff
770 #define R128_BUFFER_FREE 0
773 static int r128_freelist_init(drm_device_t * dev)
775 drm_device_dma_t *dma = dev->dma;
776 drm_r128_private_t *dev_priv = dev->dev_private;
778 drm_r128_buf_priv_t *buf_priv;
779 drm_r128_freelist_t *entry;
782 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
783 if (dev_priv->head == NULL)
784 return DRM_ERR(ENOMEM);
786 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
787 dev_priv->head->age = R128_BUFFER_USED;
789 for (i = 0; i < dma->buf_count; i++) {
790 buf = dma->buflist[i];
791 buf_priv = buf->dev_private;
793 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
795 return DRM_ERR(ENOMEM);
797 entry->age = R128_BUFFER_FREE;
799 entry->prev = dev_priv->head;
800 entry->next = dev_priv->head->next;
802 dev_priv->tail = entry;
804 buf_priv->discard = 0;
805 buf_priv->dispatched = 0;
806 buf_priv->list_entry = entry;
808 dev_priv->head->next = entry;
810 if (dev_priv->head->next)
811 dev_priv->head->next->prev = entry;
819 static drm_buf_t *r128_freelist_get(drm_device_t * dev)
821 drm_device_dma_t *dma = dev->dma;
822 drm_r128_private_t *dev_priv = dev->dev_private;
823 drm_r128_buf_priv_t *buf_priv;
827 /* FIXME: Optimize -- use freelist code */
829 for (i = 0; i < dma->buf_count; i++) {
830 buf = dma->buflist[i];
831 buf_priv = buf->dev_private;
836 for (t = 0; t < dev_priv->usec_timeout; t++) {
837 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
839 for (i = 0; i < dma->buf_count; i++) {
840 buf = dma->buflist[i];
841 buf_priv = buf->dev_private;
842 if (buf->pending && buf_priv->age <= done_age) {
843 /* The buffer has been processed, so it
853 DRM_DEBUG("returning NULL!\n");
857 void r128_freelist_reset(drm_device_t * dev)
859 drm_device_dma_t *dma = dev->dma;
862 for (i = 0; i < dma->buf_count; i++) {
863 drm_buf_t *buf = dma->buflist[i];
864 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
869 /* ================================================================
870 * CCE command submission
873 int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
875 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
878 for (i = 0; i < dev_priv->usec_timeout; i++) {
879 r128_update_ring_snapshot(dev_priv);
880 if (ring->space >= n)
885 /* FIXME: This is being ignored... */
886 DRM_ERROR("failed!\n");
887 return DRM_ERR(EBUSY);
890 static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
895 for (i = d->granted_count; i < d->request_count; i++) {
896 buf = r128_freelist_get(dev);
898 return DRM_ERR(EAGAIN);
902 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
904 return DRM_ERR(EFAULT);
905 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
907 return DRM_ERR(EFAULT);
914 int r128_cce_buffers(DRM_IOCTL_ARGS)
917 drm_device_dma_t *dma = dev->dma;
919 drm_dma_t __user *argp = (void __user *)data;
922 LOCK_TEST_WITH_RETURN(dev, filp);
924 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
926 /* Please don't send us buffers.
928 if (d.send_count != 0) {
929 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
930 DRM_CURRENTPID, d.send_count);
931 return DRM_ERR(EINVAL);
934 /* We'll send you buffers.
936 if (d.request_count < 0 || d.request_count > dma->buf_count) {
937 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
938 DRM_CURRENTPID, d.request_count, dma->buf_count);
939 return DRM_ERR(EINVAL);
944 if (d.request_count) {
945 ret = r128_cce_get_buffers(filp, dev, &d);
948 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));