1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Rickard E. (Rik) Faith <faith@valinux.com>
30 * Kevin E. Martin <martin@valinux.com>
31 * Gareth Hughes <gareth@valinux.com>
32 * Michel D�zer <daenzerm@student.ethz.ch>
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #ifndef __R128_DRV_H__
39 #define __R128_DRV_H__
41 /* General customization:
43 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
45 #define DRIVER_NAME "r128"
46 #define DRIVER_DESC "ATI Rage 128"
47 #define DRIVER_DATE "20030725"
52 * 2.4 - Add support for ycbcr textures (no new ioctls)
53 * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
55 #define DRIVER_MAJOR 2
56 #define DRIVER_MINOR 5
57 #define DRIVER_PATCHLEVEL 0
59 #define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR )
61 typedef struct drm_r128_freelist {
64 struct drm_r128_freelist *next;
65 struct drm_r128_freelist *prev;
66 } drm_r128_freelist_t;
68 typedef struct drm_r128_ring_buffer {
79 } drm_r128_ring_buffer_t;
81 typedef struct drm_r128_private {
82 drm_r128_ring_buffer_t ring;
83 drm_r128_sarea_t *sarea_priv;
89 drm_r128_freelist_t *head;
90 drm_r128_freelist_t *tail;
94 unsigned long cce_buffers_offset;
101 u32 crtc_offset_cntl;
103 atomic_t vbl_received;
106 unsigned int front_offset;
107 unsigned int front_pitch;
108 unsigned int back_offset;
109 unsigned int back_pitch;
112 unsigned int depth_offset;
113 unsigned int depth_pitch;
114 unsigned int span_offset;
116 u32 front_pitch_offset_c;
117 u32 back_pitch_offset_c;
118 u32 depth_pitch_offset_c;
119 u32 span_pitch_offset_c;
121 drm_local_map_t *sarea;
122 drm_local_map_t *mmio;
123 drm_local_map_t *cce_ring;
124 drm_local_map_t *ring_rptr;
125 drm_local_map_t *agp_textures;
126 struct drm_ati_pcigart_info gart_info;
127 } drm_r128_private_t;
129 typedef struct drm_r128_buf_priv {
134 drm_r128_freelist_t *list_entry;
135 } drm_r128_buf_priv_t;
137 extern struct drm_ioctl_desc r128_ioctls[];
138 extern int r128_max_ioctl;
141 extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
142 extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
143 extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
144 extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
145 extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
146 extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
147 extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
148 extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
150 extern void r128_freelist_reset(struct drm_device * dev);
152 extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
154 extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
155 extern int r128_do_cleanup_cce(struct drm_device * dev);
157 extern int r128_enable_vblank(struct drm_device *dev, int crtc);
158 extern void r128_disable_vblank(struct drm_device *dev, int crtc);
159 extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc);
160 extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
161 extern void r128_driver_irq_preinstall(struct drm_device * dev);
162 extern int r128_driver_irq_postinstall(struct drm_device * dev);
163 extern void r128_driver_irq_uninstall(struct drm_device * dev);
164 extern void r128_driver_lastclose(struct drm_device * dev);
165 extern void r128_driver_preclose(struct drm_device * dev,
166 struct drm_file *file_priv);
168 extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
171 /* Register definitions, register access macros and drmAddMap constants
172 * for Rage 128 kernel driver.
175 #define R128_AUX_SC_CNTL 0x1660
176 # define R128_AUX1_SC_EN (1 << 0)
177 # define R128_AUX1_SC_MODE_OR (0 << 1)
178 # define R128_AUX1_SC_MODE_NAND (1 << 1)
179 # define R128_AUX2_SC_EN (1 << 2)
180 # define R128_AUX2_SC_MODE_OR (0 << 3)
181 # define R128_AUX2_SC_MODE_NAND (1 << 3)
182 # define R128_AUX3_SC_EN (1 << 4)
183 # define R128_AUX3_SC_MODE_OR (0 << 5)
184 # define R128_AUX3_SC_MODE_NAND (1 << 5)
185 #define R128_AUX1_SC_LEFT 0x1664
186 #define R128_AUX1_SC_RIGHT 0x1668
187 #define R128_AUX1_SC_TOP 0x166c
188 #define R128_AUX1_SC_BOTTOM 0x1670
189 #define R128_AUX2_SC_LEFT 0x1674
190 #define R128_AUX2_SC_RIGHT 0x1678
191 #define R128_AUX2_SC_TOP 0x167c
192 #define R128_AUX2_SC_BOTTOM 0x1680
193 #define R128_AUX3_SC_LEFT 0x1684
194 #define R128_AUX3_SC_RIGHT 0x1688
195 #define R128_AUX3_SC_TOP 0x168c
196 #define R128_AUX3_SC_BOTTOM 0x1690
198 #define R128_BRUSH_DATA0 0x1480
199 #define R128_BUS_CNTL 0x0030
200 # define R128_BUS_MASTER_DIS (1 << 6)
202 #define R128_CLOCK_CNTL_INDEX 0x0008
203 #define R128_CLOCK_CNTL_DATA 0x000c
204 # define R128_PLL_WR_EN (1 << 7)
205 #define R128_CONSTANT_COLOR_C 0x1d34
206 #define R128_CRTC_OFFSET 0x0224
207 #define R128_CRTC_OFFSET_CNTL 0x0228
208 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
210 #define R128_DP_GUI_MASTER_CNTL 0x146c
211 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
212 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
213 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
214 # define R128_GMC_BRUSH_NONE (15 << 4)
215 # define R128_GMC_DST_16BPP (4 << 8)
216 # define R128_GMC_DST_24BPP (5 << 8)
217 # define R128_GMC_DST_32BPP (6 << 8)
218 # define R128_GMC_DST_DATATYPE_SHIFT 8
219 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
220 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
221 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
222 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
223 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
224 # define R128_GMC_WR_MSK_DIS (1 << 30)
225 # define R128_ROP3_S 0x00cc0000
226 # define R128_ROP3_P 0x00f00000
227 #define R128_DP_WRITE_MASK 0x16cc
228 #define R128_DST_PITCH_OFFSET_C 0x1c80
229 # define R128_DST_TILE (1 << 31)
231 #define R128_GEN_INT_CNTL 0x0040
232 # define R128_CRTC_VBLANK_INT_EN (1 << 0)
233 #define R128_GEN_INT_STATUS 0x0044
234 # define R128_CRTC_VBLANK_INT (1 << 0)
235 # define R128_CRTC_VBLANK_INT_AK (1 << 0)
236 #define R128_GEN_RESET_CNTL 0x00f0
237 # define R128_SOFT_RESET_GUI (1 << 0)
239 #define R128_GUI_SCRATCH_REG0 0x15e0
240 #define R128_GUI_SCRATCH_REG1 0x15e4
241 #define R128_GUI_SCRATCH_REG2 0x15e8
242 #define R128_GUI_SCRATCH_REG3 0x15ec
243 #define R128_GUI_SCRATCH_REG4 0x15f0
244 #define R128_GUI_SCRATCH_REG5 0x15f4
246 #define R128_GUI_STAT 0x1740
247 # define R128_GUI_FIFOCNT_MASK 0x0fff
248 # define R128_GUI_ACTIVE (1 << 31)
250 #define R128_MCLK_CNTL 0x000f
251 # define R128_FORCE_GCP (1 << 16)
252 # define R128_FORCE_PIPE3D_CP (1 << 17)
253 # define R128_FORCE_RCP (1 << 18)
255 #define R128_PC_GUI_CTLSTAT 0x1748
256 #define R128_PC_NGUI_CTLSTAT 0x0184
257 # define R128_PC_FLUSH_GUI (3 << 0)
258 # define R128_PC_RI_GUI (1 << 2)
259 # define R128_PC_FLUSH_ALL 0x00ff
260 # define R128_PC_BUSY (1 << 31)
262 #define R128_PCI_GART_PAGE 0x017c
263 #define R128_PRIM_TEX_CNTL_C 0x1cb0
265 #define R128_SCALE_3D_CNTL 0x1a00
266 #define R128_SEC_TEX_CNTL_C 0x1d00
267 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
268 #define R128_SETUP_CNTL 0x1bc4
269 #define R128_STEN_REF_MASK_C 0x1d40
271 #define R128_TEX_CNTL_C 0x1c9c
272 # define R128_TEX_CACHE_FLUSH (1 << 23)
274 #define R128_WAIT_UNTIL 0x1720
275 # define R128_EVENT_CRTC_OFFSET (1 << 0)
276 #define R128_WINDOW_XY_OFFSET 0x1bcc
280 #define R128_PM4_BUFFER_OFFSET 0x0700
281 #define R128_PM4_BUFFER_CNTL 0x0704
282 # define R128_PM4_MASK (15 << 28)
283 # define R128_PM4_NONPM4 (0 << 28)
284 # define R128_PM4_192PIO (1 << 28)
285 # define R128_PM4_192BM (2 << 28)
286 # define R128_PM4_128PIO_64INDBM (3 << 28)
287 # define R128_PM4_128BM_64INDBM (4 << 28)
288 # define R128_PM4_64PIO_128INDBM (5 << 28)
289 # define R128_PM4_64BM_128INDBM (6 << 28)
290 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
291 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
292 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
293 # define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27)
295 #define R128_PM4_BUFFER_WM_CNTL 0x0708
296 # define R128_WMA_SHIFT 0
297 # define R128_WMB_SHIFT 8
298 # define R128_WMC_SHIFT 16
299 # define R128_WB_WM_SHIFT 24
301 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
302 #define R128_PM4_BUFFER_DL_RPTR 0x0710
303 #define R128_PM4_BUFFER_DL_WPTR 0x0714
304 # define R128_PM4_BUFFER_DL_DONE (1 << 31)
306 #define R128_PM4_VC_FPU_SETUP 0x071c
308 #define R128_PM4_IW_INDOFF 0x0738
309 #define R128_PM4_IW_INDSIZE 0x073c
311 #define R128_PM4_STAT 0x07b8
312 # define R128_PM4_FIFOCNT_MASK 0x0fff
313 # define R128_PM4_BUSY (1 << 16)
314 # define R128_PM4_GUI_ACTIVE (1 << 31)
316 #define R128_PM4_MICROCODE_ADDR 0x07d4
317 #define R128_PM4_MICROCODE_RADDR 0x07d8
318 #define R128_PM4_MICROCODE_DATAH 0x07dc
319 #define R128_PM4_MICROCODE_DATAL 0x07e0
321 #define R128_PM4_BUFFER_ADDR 0x07f0
322 #define R128_PM4_MICRO_CNTL 0x07fc
323 # define R128_PM4_MICRO_FREERUN (1 << 30)
325 #define R128_PM4_FIFO_DATA_EVEN 0x1000
326 #define R128_PM4_FIFO_DATA_ODD 0x1004
328 /* CCE command packets
330 #define R128_CCE_PACKET0 0x00000000
331 #define R128_CCE_PACKET1 0x40000000
332 #define R128_CCE_PACKET2 0x80000000
333 #define R128_CCE_PACKET3 0xC0000000
334 # define R128_CNTL_HOSTDATA_BLT 0x00009400
335 # define R128_CNTL_PAINT_MULTI 0x00009A00
336 # define R128_CNTL_BITBLT_MULTI 0x00009B00
337 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
339 #define R128_CCE_PACKET_MASK 0xC0000000
340 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
341 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
342 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
343 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
345 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
346 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
347 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
348 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
349 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
350 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
351 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
352 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
353 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
354 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
355 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
356 #define R128_CCE_VC_CNTL_NUM_SHIFT 16
358 #define R128_DATATYPE_VQ 0
359 #define R128_DATATYPE_CI4 1
360 #define R128_DATATYPE_CI8 2
361 #define R128_DATATYPE_ARGB1555 3
362 #define R128_DATATYPE_RGB565 4
363 #define R128_DATATYPE_RGB888 5
364 #define R128_DATATYPE_ARGB8888 6
365 #define R128_DATATYPE_RGB332 7
366 #define R128_DATATYPE_Y8 8
367 #define R128_DATATYPE_RGB8 9
368 #define R128_DATATYPE_CI16 10
369 #define R128_DATATYPE_YVYU422 11
370 #define R128_DATATYPE_VYUY422 12
371 #define R128_DATATYPE_AYUV444 14
372 #define R128_DATATYPE_ARGB4444 15
375 #define R128_AGP_OFFSET 0x02000000
377 #define R128_WATERMARK_L 16
378 #define R128_WATERMARK_M 8
379 #define R128_WATERMARK_N 8
380 #define R128_WATERMARK_K 128
382 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
384 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
385 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
386 #define R128_MAX_VB_AGE 0x7fffffff
387 #define R128_MAX_VB_VERTS (0xffff)
389 #define R128_RING_HIGH_MARK 128
391 #define R128_PERFORMANCE_BOXES 0
393 #define R128_PCIGART_TABLE_SIZE 32768
395 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
396 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
397 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
398 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
400 #define R128_WRITE_PLL(addr,val) \
402 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
403 ((addr) & 0x1f) | R128_PLL_WR_EN); \
404 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
407 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
408 ((n) << 16) | ((reg) >> 2))
409 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
410 (((reg1) >> 2) << 11) | ((reg0) >> 2))
411 #define CCE_PACKET2() (R128_CCE_PACKET2)
412 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
415 static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
417 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
418 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
419 if (ring->space <= 0)
420 ring->space += ring->size;
423 /* ================================================================
427 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
429 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
430 if ( ring->space < ring->high_mark ) { \
431 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
432 r128_update_ring_snapshot( dev_priv ); \
433 if ( ring->space >= ring->high_mark ) \
434 goto __ring_space_done; \
437 DRM_ERROR( "ring space check failed!\n" ); \
444 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
446 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
447 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
448 int __ret = r128_do_cce_idle( dev_priv ); \
449 if ( __ret ) return __ret; \
450 sarea_priv->last_dispatch = 0; \
451 r128_freelist_reset( dev ); \
455 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
456 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
457 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
460 /* ================================================================
464 #define R128_VERBOSE 0
466 #define RING_LOCALS \
467 int write, _nr; unsigned int tail_mask; volatile u32 *ring;
469 #define BEGIN_RING( n ) do { \
470 if ( R128_VERBOSE ) { \
471 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
473 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
475 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
477 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
478 ring = dev_priv->ring.start; \
479 write = dev_priv->ring.tail; \
480 tail_mask = dev_priv->ring.tail_mask; \
483 /* You can set this to zero if you want. If the card locks up, you'll
484 * need to keep this set. It works around a bug in early revs of the
485 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
486 * the ring buffer before wrapping around.
488 #define R128_BROKEN_CCE 1
490 #define ADVANCE_RING() do { \
491 if ( R128_VERBOSE ) { \
492 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
493 write, dev_priv->ring.tail ); \
495 if ( R128_BROKEN_CCE && write < 32 ) { \
496 memcpy( dev_priv->ring.end, \
497 dev_priv->ring.start, \
498 write * sizeof(u32) ); \
500 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \
502 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
503 ((dev_priv->ring.tail + _nr) & tail_mask), \
506 dev_priv->ring.tail = write; \
509 #define COMMIT_RING() do { \
510 if ( R128_VERBOSE ) { \
511 DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \
512 dev_priv->ring.tail ); \
514 DRM_MEMORYBARRIER(); \
515 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \
516 R128_READ( R128_PM4_BUFFER_DL_WPTR ); \
519 #define OUT_RING( x ) do { \
520 if ( R128_VERBOSE ) { \
521 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
522 (unsigned int)(x), write ); \
524 ring[write++] = cpu_to_le32( x ); \
525 write &= tail_mask; \
528 #endif /* __R128_DRV_H__ */