1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 * Kevin E. Martin <martin@valinux.com>
30 * Gareth Hughes <gareth@valinux.com>
31 * Michel Dänzer <daenzerm@student.ethz.ch>
37 #include <machine/endian.h>
38 #if BYTE_ORDER==LITTLE_ENDIAN
39 #define le32_to_cpu(x) x
40 #define cpu_to_le32(x) x
42 #define le32_to_cpu(x) ntohl(x)
43 #define cpu_to_le32(x) htonl(x)
45 #endif /* __FreeBSD__ */
47 #ifndef __R128_DRV_H__
48 #define __R128_DRV_H__
50 #define GET_RING_HEAD( ring ) le32_to_cpu( *(ring)->head )
51 #define SET_RING_HEAD( ring, val ) *(ring)->head = cpu_to_le32( val )
53 typedef struct drm_r128_freelist {
56 struct drm_r128_freelist *next;
57 struct drm_r128_freelist *prev;
58 } drm_r128_freelist_t;
60 typedef struct drm_r128_ring_buffer {
72 } drm_r128_ring_buffer_t;
74 typedef struct drm_r128_private {
75 drm_r128_ring_buffer_t ring;
76 drm_r128_sarea_t *sarea_priv;
82 drm_r128_freelist_t *head;
83 drm_r128_freelist_t *tail;
87 unsigned long phys_pci_gart;
89 dma_addr_t bus_pci_gart;
91 unsigned long cce_buffers_offset;
101 unsigned int front_offset;
102 unsigned int front_pitch;
103 unsigned int back_offset;
104 unsigned int back_pitch;
107 unsigned int depth_offset;
108 unsigned int depth_pitch;
109 unsigned int span_offset;
111 u32 front_pitch_offset_c;
112 u32 back_pitch_offset_c;
113 u32 depth_pitch_offset_c;
114 u32 span_pitch_offset_c;
120 drm_map_t *ring_rptr;
122 drm_map_t *agp_textures;
123 } drm_r128_private_t;
125 typedef struct drm_r128_buf_priv {
130 drm_r128_freelist_t *list_entry;
131 } drm_r128_buf_priv_t;
134 extern int r128_cce_init( DRM_OS_IOCTL );
135 extern int r128_cce_start( DRM_OS_IOCTL );
136 extern int r128_cce_stop( DRM_OS_IOCTL );
137 extern int r128_cce_reset( DRM_OS_IOCTL );
138 extern int r128_cce_idle( DRM_OS_IOCTL );
139 extern int r128_engine_reset( DRM_OS_IOCTL );
140 extern int r128_fullscreen( DRM_OS_IOCTL );
141 extern int r128_cce_buffers( DRM_OS_IOCTL );
143 extern void r128_freelist_reset( drm_device_t *dev );
144 extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
146 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
148 static __inline__ void
149 r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
151 ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
152 if ( ring->space <= 0 )
153 ring->space += ring->size;
156 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
157 extern int r128_do_cleanup_cce( drm_device_t *dev );
158 extern int r128_do_cleanup_pageflip( drm_device_t *dev );
161 extern int r128_cce_clear( DRM_OS_IOCTL );
162 extern int r128_cce_swap( DRM_OS_IOCTL );
163 extern int r128_cce_vertex( DRM_OS_IOCTL );
164 extern int r128_cce_indices( DRM_OS_IOCTL );
165 extern int r128_cce_blit( DRM_OS_IOCTL );
166 extern int r128_cce_depth( DRM_OS_IOCTL );
167 extern int r128_cce_stipple( DRM_OS_IOCTL );
168 extern int r128_cce_indirect( DRM_OS_IOCTL );
171 /* Register definitions, register access macros and drmAddMap constants
172 * for Rage 128 kernel driver.
175 #define R128_AUX_SC_CNTL 0x1660
176 # define R128_AUX1_SC_EN (1 << 0)
177 # define R128_AUX1_SC_MODE_OR (0 << 1)
178 # define R128_AUX1_SC_MODE_NAND (1 << 1)
179 # define R128_AUX2_SC_EN (1 << 2)
180 # define R128_AUX2_SC_MODE_OR (0 << 3)
181 # define R128_AUX2_SC_MODE_NAND (1 << 3)
182 # define R128_AUX3_SC_EN (1 << 4)
183 # define R128_AUX3_SC_MODE_OR (0 << 5)
184 # define R128_AUX3_SC_MODE_NAND (1 << 5)
185 #define R128_AUX1_SC_LEFT 0x1664
186 #define R128_AUX1_SC_RIGHT 0x1668
187 #define R128_AUX1_SC_TOP 0x166c
188 #define R128_AUX1_SC_BOTTOM 0x1670
189 #define R128_AUX2_SC_LEFT 0x1674
190 #define R128_AUX2_SC_RIGHT 0x1678
191 #define R128_AUX2_SC_TOP 0x167c
192 #define R128_AUX2_SC_BOTTOM 0x1680
193 #define R128_AUX3_SC_LEFT 0x1684
194 #define R128_AUX3_SC_RIGHT 0x1688
195 #define R128_AUX3_SC_TOP 0x168c
196 #define R128_AUX3_SC_BOTTOM 0x1690
198 #define R128_BRUSH_DATA0 0x1480
199 #define R128_BUS_CNTL 0x0030
200 # define R128_BUS_MASTER_DIS (1 << 6)
202 #define R128_CLOCK_CNTL_INDEX 0x0008
203 #define R128_CLOCK_CNTL_DATA 0x000c
204 # define R128_PLL_WR_EN (1 << 7)
205 #define R128_CONSTANT_COLOR_C 0x1d34
206 #define R128_CRTC_OFFSET 0x0224
207 #define R128_CRTC_OFFSET_CNTL 0x0228
208 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
210 #define R128_DP_GUI_MASTER_CNTL 0x146c
211 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
212 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
213 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
214 # define R128_GMC_BRUSH_NONE (15 << 4)
215 # define R128_GMC_DST_16BPP (4 << 8)
216 # define R128_GMC_DST_24BPP (5 << 8)
217 # define R128_GMC_DST_32BPP (6 << 8)
218 # define R128_GMC_DST_DATATYPE_SHIFT 8
219 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
220 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
221 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
222 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
223 # define R128_GMC_AUX_CLIP_DIS (1 << 29)
224 # define R128_GMC_WR_MSK_DIS (1 << 30)
225 # define R128_ROP3_S 0x00cc0000
226 # define R128_ROP3_P 0x00f00000
227 #define R128_DP_WRITE_MASK 0x16cc
228 #define R128_DST_PITCH_OFFSET_C 0x1c80
229 # define R128_DST_TILE (1 << 31)
231 #define R128_GEN_RESET_CNTL 0x00f0
232 # define R128_SOFT_RESET_GUI (1 << 0)
234 #define R128_GUI_SCRATCH_REG0 0x15e0
235 #define R128_GUI_SCRATCH_REG1 0x15e4
236 #define R128_GUI_SCRATCH_REG2 0x15e8
237 #define R128_GUI_SCRATCH_REG3 0x15ec
238 #define R128_GUI_SCRATCH_REG4 0x15f0
239 #define R128_GUI_SCRATCH_REG5 0x15f4
241 #define R128_GUI_STAT 0x1740
242 # define R128_GUI_FIFOCNT_MASK 0x0fff
243 # define R128_GUI_ACTIVE (1 << 31)
245 #define R128_MCLK_CNTL 0x000f
246 # define R128_FORCE_GCP (1 << 16)
247 # define R128_FORCE_PIPE3D_CP (1 << 17)
248 # define R128_FORCE_RCP (1 << 18)
250 #define R128_PC_GUI_CTLSTAT 0x1748
251 #define R128_PC_NGUI_CTLSTAT 0x0184
252 # define R128_PC_FLUSH_GUI (3 << 0)
253 # define R128_PC_RI_GUI (1 << 2)
254 # define R128_PC_FLUSH_ALL 0x00ff
255 # define R128_PC_BUSY (1 << 31)
257 #define R128_PCI_GART_PAGE 0x017c
258 #define R128_PRIM_TEX_CNTL_C 0x1cb0
260 #define R128_SCALE_3D_CNTL 0x1a00
261 #define R128_SEC_TEX_CNTL_C 0x1d00
262 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
263 #define R128_SETUP_CNTL 0x1bc4
264 #define R128_STEN_REF_MASK_C 0x1d40
266 #define R128_TEX_CNTL_C 0x1c9c
267 # define R128_TEX_CACHE_FLUSH (1 << 23)
269 #define R128_WAIT_UNTIL 0x1720
270 # define R128_EVENT_CRTC_OFFSET (1 << 0)
271 #define R128_WINDOW_XY_OFFSET 0x1bcc
276 #define R128_PM4_BUFFER_OFFSET 0x0700
277 #define R128_PM4_BUFFER_CNTL 0x0704
278 # define R128_PM4_MASK (15 << 28)
279 # define R128_PM4_NONPM4 (0 << 28)
280 # define R128_PM4_192PIO (1 << 28)
281 # define R128_PM4_192BM (2 << 28)
282 # define R128_PM4_128PIO_64INDBM (3 << 28)
283 # define R128_PM4_128BM_64INDBM (4 << 28)
284 # define R128_PM4_64PIO_128INDBM (5 << 28)
285 # define R128_PM4_64BM_128INDBM (6 << 28)
286 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
287 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
288 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
290 #define R128_PM4_BUFFER_WM_CNTL 0x0708
291 # define R128_WMA_SHIFT 0
292 # define R128_WMB_SHIFT 8
293 # define R128_WMC_SHIFT 16
294 # define R128_WB_WM_SHIFT 24
296 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
297 #define R128_PM4_BUFFER_DL_RPTR 0x0710
298 #define R128_PM4_BUFFER_DL_WPTR 0x0714
299 # define R128_PM4_BUFFER_DL_DONE (1 << 31)
301 #define R128_PM4_VC_FPU_SETUP 0x071c
303 #define R128_PM4_IW_INDOFF 0x0738
304 #define R128_PM4_IW_INDSIZE 0x073c
306 #define R128_PM4_STAT 0x07b8
307 # define R128_PM4_FIFOCNT_MASK 0x0fff
308 # define R128_PM4_BUSY (1 << 16)
309 # define R128_PM4_GUI_ACTIVE (1 << 31)
311 #define R128_PM4_MICROCODE_ADDR 0x07d4
312 #define R128_PM4_MICROCODE_RADDR 0x07d8
313 #define R128_PM4_MICROCODE_DATAH 0x07dc
314 #define R128_PM4_MICROCODE_DATAL 0x07e0
316 #define R128_PM4_BUFFER_ADDR 0x07f0
317 #define R128_PM4_MICRO_CNTL 0x07fc
318 # define R128_PM4_MICRO_FREERUN (1 << 30)
320 #define R128_PM4_FIFO_DATA_EVEN 0x1000
321 #define R128_PM4_FIFO_DATA_ODD 0x1004
324 /* CCE command packets
326 #define R128_CCE_PACKET0 0x00000000
327 #define R128_CCE_PACKET1 0x40000000
328 #define R128_CCE_PACKET2 0x80000000
329 #define R128_CCE_PACKET3 0xC0000000
330 # define R128_CNTL_HOSTDATA_BLT 0x00009400
331 # define R128_CNTL_PAINT_MULTI 0x00009A00
332 # define R128_CNTL_BITBLT_MULTI 0x00009B00
333 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
335 #define R128_CCE_PACKET_MASK 0xC0000000
336 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
337 #define R128_CCE_PACKET0_REG_MASK 0x000007ff
338 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff
339 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800
341 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
342 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
343 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
344 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
345 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
346 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
347 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
348 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
349 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
350 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
351 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
352 #define R128_CCE_VC_CNTL_NUM_SHIFT 16
354 #define R128_DATATYPE_CI8 2
355 #define R128_DATATYPE_ARGB1555 3
356 #define R128_DATATYPE_RGB565 4
357 #define R128_DATATYPE_RGB888 5
358 #define R128_DATATYPE_ARGB8888 6
359 #define R128_DATATYPE_RGB332 7
360 #define R128_DATATYPE_RGB8 9
361 #define R128_DATATYPE_ARGB4444 15
364 #define R128_AGP_OFFSET 0x02000000
366 #define R128_WATERMARK_L 16
367 #define R128_WATERMARK_M 8
368 #define R128_WATERMARK_N 8
369 #define R128_WATERMARK_K 128
371 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
373 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
374 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
375 #define R128_MAX_VB_AGE 0x7fffffff
376 #define R128_MAX_VB_VERTS (0xffff)
378 #define R128_RING_HIGH_MARK 128
380 #define R128_PERFORMANCE_BOXES 0
383 #define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle))
384 #define R128_ADDR(reg) (R128_BASE( reg ) + reg)
386 #define R128_DEREF(reg) *(volatile u32 *)R128_ADDR( reg )
388 #define R128_READ(reg) (_R128_READ((u32 *)R128_ADDR(reg)))
389 static inline u32 _R128_READ(u32 *addr)
391 DRM_OS_READMEMORYBARRIER;
392 return *(volatile u32 *)addr;
394 #define R128_WRITE(reg,val) \
396 DRM_OS_WRITEMEMORYBARRIER; \
397 R128_DEREF(reg) = val; \
400 #define R128_READ(reg) le32_to_cpu( R128_DEREF( reg ) )
401 #define R128_WRITE(reg,val) \
403 R128_DEREF( reg ) = cpu_to_le32( val ); \
407 #define R128_DEREF8(reg) *(volatile u8 *)R128_ADDR( reg )
409 #define R128_READ8(reg) _R128_READ8((u8 *)R128_ADDR(reg))
410 static inline u8 _R128_READ8(u8 *addr)
412 DRM_OS_READMEMORYBARRIER;
413 return *(volatile u8 *)addr;
415 #define R128_WRITE8(reg,val) \
417 DRM_OS_WRITEMEMORYBARRIER; \
418 R128_DEREF8(reg) = val; \
421 #define R128_READ8(reg) R128_DEREF8( reg )
422 #define R128_WRITE8(reg,val) do { R128_DEREF8( reg ) = val; } while (0)
425 #define R128_WRITE_PLL(addr,val) \
427 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
428 ((addr) & 0x1f) | R128_PLL_WR_EN); \
429 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
432 extern int R128_READ_PLL(drm_device_t *dev, int addr);
435 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
436 ((n) << 16) | ((reg) >> 2))
437 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
438 (((reg1) >> 2) << 11) | ((reg0) >> 2))
439 #define CCE_PACKET2() (R128_CCE_PACKET2)
440 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
444 /* ================================================================
448 #define LOCK_TEST_WITH_RETURN( dev ) \
450 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
451 dev->lock.pid != DRM_OS_CURRENTPID ) { \
452 DRM_ERROR( "%s called without lock held\n", __func__ ); \
453 return DRM_OS_ERR(EINVAL); \
457 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
459 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
460 if ( ring->space < ring->high_mark ) { \
461 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
462 r128_update_ring_snapshot( ring ); \
463 if ( ring->space >= ring->high_mark ) \
464 goto __ring_space_done; \
467 DRM_ERROR( "ring space check failed!\n" ); \
468 return DRM_OS_ERR(EBUSY); \
474 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
476 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
477 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
478 int __ret = r128_do_cce_idle( dev_priv ); \
479 if ( __ret < 0 ) return __ret; \
480 sarea_priv->last_dispatch = 0; \
481 r128_freelist_reset( dev ); \
485 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
486 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
487 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
491 /* ================================================================
495 #define r128_flush_write_combine() DRM_OS_READMEMORYBARRIER
498 #define R128_VERBOSE 0
500 #define RING_LOCALS \
501 int write; unsigned int tail_mask; volatile u32 *ring;
503 #define BEGIN_RING( n ) do { \
504 if ( R128_VERBOSE ) { \
505 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
508 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
509 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
511 dev_priv->ring.space -= (n) * sizeof(u32); \
512 ring = dev_priv->ring.start; \
513 write = dev_priv->ring.tail; \
514 tail_mask = dev_priv->ring.tail_mask; \
517 /* You can set this to zero if you want. If the card locks up, you'll
518 * need to keep this set. It works around a bug in early revs of the
519 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
520 * the ring buffer before wrapping around.
522 #define R128_BROKEN_CCE 1
524 #define ADVANCE_RING() do { \
525 if ( R128_VERBOSE ) { \
526 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
527 write, dev_priv->ring.tail ); \
529 if ( R128_BROKEN_CCE && write < 32 ) { \
530 memcpy( dev_priv->ring.end, \
531 dev_priv->ring.start, \
532 write * sizeof(u32) ); \
534 r128_flush_write_combine(); \
535 dev_priv->ring.tail = write; \
536 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \
539 #define OUT_RING( x ) do { \
540 if ( R128_VERBOSE ) { \
541 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
542 (unsigned int)(x), write ); \
544 ring[write++] = cpu_to_le32( x ); \
545 write &= tail_mask; \
548 #endif /* __R128_DRV_H__ */