sys/dev/drm/r128_state.c

   1 /* r128_state.c -- State support for r128 -*- linux-c -*-
   2  * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com */
   3 /*-
   4  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Gareth Hughes <gareth@valinux.com>
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 #include "dev/drm/drmP.h"
  33 #include "dev/drm/drm.h"
  34 #include "dev/drm/r128_drm.h"
  35 #include "dev/drm/r128_drv.h"
  36
  37 /* ================================================================
  38  * CCE hardware state programming functions
  39  */
  40
  41 static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
  42                                  drm_clip_rect_t * boxes, int count)
  43 {
  44         u32 aux_sc_cntl = 0x00000000;
  45         RING_LOCALS;
  46         DRM_DEBUG("    %s\n", __FUNCTION__);
  47
  48         BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
  49
  50         if (count >= 1) {
  51                 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
  52                 OUT_RING(boxes[0].x1);
  53                 OUT_RING(boxes[0].x2 - 1);
  54                 OUT_RING(boxes[0].y1);
  55                 OUT_RING(boxes[0].y2 - 1);
  56
  57                 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
  58         }
  59         if (count >= 2) {
  60                 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
  61                 OUT_RING(boxes[1].x1);
  62                 OUT_RING(boxes[1].x2 - 1);
  63                 OUT_RING(boxes[1].y1);
  64                 OUT_RING(boxes[1].y2 - 1);
  65
  66                 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
  67         }
  68         if (count >= 3) {
  69                 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
  70                 OUT_RING(boxes[2].x1);
  71                 OUT_RING(boxes[2].x2 - 1);
  72                 OUT_RING(boxes[2].y1);
  73                 OUT_RING(boxes[2].y2 - 1);
  74
  75                 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
  76         }
  77
  78         OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
  79         OUT_RING(aux_sc_cntl);
  80
  81         ADVANCE_RING();
  82 }
  83
  84 static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
  85 {
  86         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
  87         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
  88         RING_LOCALS;
  89         DRM_DEBUG("    %s\n", __FUNCTION__);
  90
  91         BEGIN_RING(2);
  92
  93         OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
  94         OUT_RING(ctx->scale_3d_cntl);
  95
  96         ADVANCE_RING();
  97 }
  98
  99 static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
 100 {
 101         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 102         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 103         RING_LOCALS;
 104         DRM_DEBUG("    %s\n", __FUNCTION__);
 105
 106         BEGIN_RING(13);
 107
 108         OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
 109         OUT_RING(ctx->dst_pitch_offset_c);
 110         OUT_RING(ctx->dp_gui_master_cntl_c);
 111         OUT_RING(ctx->sc_top_left_c);
 112         OUT_RING(ctx->sc_bottom_right_c);
 113         OUT_RING(ctx->z_offset_c);
 114         OUT_RING(ctx->z_pitch_c);
 115         OUT_RING(ctx->z_sten_cntl_c);
 116         OUT_RING(ctx->tex_cntl_c);
 117         OUT_RING(ctx->misc_3d_state_cntl_reg);
 118         OUT_RING(ctx->texture_clr_cmp_clr_c);
 119         OUT_RING(ctx->texture_clr_cmp_msk_c);
 120         OUT_RING(ctx->fog_color_c);
 121
 122         ADVANCE_RING();
 123 }
 124
 125 static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
 126 {
 127         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 128         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 129         RING_LOCALS;
 130         DRM_DEBUG("    %s\n", __FUNCTION__);
 131
 132         BEGIN_RING(3);
 133
 134         OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
 135         OUT_RING(ctx->setup_cntl);
 136         OUT_RING(ctx->pm4_vc_fpu_setup);
 137
 138         ADVANCE_RING();
 139 }
 140
 141 static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
 142 {
 143         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 144         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 145         RING_LOCALS;
 146         DRM_DEBUG("    %s\n", __FUNCTION__);
 147
 148         BEGIN_RING(5);
 149
 150         OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
 151         OUT_RING(ctx->dp_write_mask);
 152
 153         OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
 154         OUT_RING(ctx->sten_ref_mask_c);
 155         OUT_RING(ctx->plane_3d_mask_c);
 156
 157         ADVANCE_RING();
 158 }
 159
 160 static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
 161 {
 162         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 163         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 164         RING_LOCALS;
 165         DRM_DEBUG("    %s\n", __FUNCTION__);
 166
 167         BEGIN_RING(2);
 168
 169         OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
 170         OUT_RING(ctx->window_xy_offset);
 171
 172         ADVANCE_RING();
 173 }
 174
 175 static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
 176 {
 177         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 178         drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
 179         drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
 180         int i;
 181         RING_LOCALS;
 182         DRM_DEBUG("    %s\n", __FUNCTION__);
 183
 184         BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
 185
 186         OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
 187                              2 + R128_MAX_TEXTURE_LEVELS));
 188         OUT_RING(tex->tex_cntl);
 189         OUT_RING(tex->tex_combine_cntl);
 190         OUT_RING(ctx->tex_size_pitch_c);
 191         for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
 192                 OUT_RING(tex->tex_offset[i]);
 193         }
 194
 195         OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
 196         OUT_RING(ctx->constant_color_c);
 197         OUT_RING(tex->tex_border_color);
 198
 199         ADVANCE_RING();
 200 }
 201
 202 static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
 203 {
 204         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 205         drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
 206         int i;
 207         RING_LOCALS;
 208         DRM_DEBUG("    %s\n", __FUNCTION__);
 209
 210         BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
 211
 212         OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
 213         OUT_RING(tex->tex_cntl);
 214         OUT_RING(tex->tex_combine_cntl);
 215         for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
 216                 OUT_RING(tex->tex_offset[i]);
 217         }
 218
 219         OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
 220         OUT_RING(tex->tex_border_color);
 221
 222         ADVANCE_RING();
 223 }
 224
 225 static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv)
 226 {
 227         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 228         unsigned int dirty = sarea_priv->dirty;
 229
 230         DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
 231
 232         if (dirty & R128_UPLOAD_CORE) {
 233                 r128_emit_core(dev_priv);
 234                 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
 235         }
 236
 237         if (dirty & R128_UPLOAD_CONTEXT) {
 238                 r128_emit_context(dev_priv);
 239                 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
 240         }
 241
 242         if (dirty & R128_UPLOAD_SETUP) {
 243                 r128_emit_setup(dev_priv);
 244                 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
 245         }
 246
 247         if (dirty & R128_UPLOAD_MASKS) {
 248                 r128_emit_masks(dev_priv);
 249                 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
 250         }
 251
 252         if (dirty & R128_UPLOAD_WINDOW) {
 253                 r128_emit_window(dev_priv);
 254                 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
 255         }
 256
 257         if (dirty & R128_UPLOAD_TEX0) {
 258                 r128_emit_tex0(dev_priv);
 259                 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
 260         }
 261
 262         if (dirty & R128_UPLOAD_TEX1) {
 263                 r128_emit_tex1(dev_priv);
 264                 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
 265         }
 266
 267         /* Turn off the texture cache flushing */
 268         sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
 269
 270         sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
 271 }
 272
 273 #if R128_PERFORMANCE_BOXES
 274 /* ================================================================
 275  * Performance monitoring functions
 276  */
 277
 278 static void r128_clear_box(drm_r128_private_t * dev_priv,
 279                            int x, int y, int w, int h, int r, int g, int b)
 280 {
 281         u32 pitch, offset;
 282         u32 fb_bpp, color;
 283         RING_LOCALS;
 284
 285         switch (dev_priv->fb_bpp) {
 286         case 16:
 287                 fb_bpp = R128_GMC_DST_16BPP;
 288                 color = (((r & 0xf8) << 8) |
 289                          ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
 290                 break;
 291         case 24:
 292                 fb_bpp = R128_GMC_DST_24BPP;
 293                 color = ((r << 16) | (g << 8) | b);
 294                 break;
 295         case 32:
 296                 fb_bpp = R128_GMC_DST_32BPP;
 297                 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
 298                 break;
 299         default:
 300                 return;
 301         }
 302
 303         offset = dev_priv->back_offset;
 304         pitch = dev_priv->back_pitch >> 3;
 305
 306         BEGIN_RING(6);
 307
 308         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 309         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 310                  R128_GMC_BRUSH_SOLID_COLOR |
 311                  fb_bpp |
 312                  R128_GMC_SRC_DATATYPE_COLOR |
 313                  R128_ROP3_P |
 314                  R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
 315
 316         OUT_RING((pitch << 21) | (offset >> 5));
 317         OUT_RING(color);
 318
 319         OUT_RING((x << 16) | y);
 320         OUT_RING((w << 16) | h);
 321
 322         ADVANCE_RING();
 323 }
 324
 325 static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
 326 {
 327         if (atomic_read(&dev_priv->idle_count) == 0) {
 328                 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
 329         } else {
 330                 atomic_set(&dev_priv->idle_count, 0);
 331         }
 332 }
 333
 334 #endif
 335
 336 /* ================================================================
 337  * CCE command dispatch functions
 338  */
 339
 340 static void r128_print_dirty(const char *msg, unsigned int flags)
 341 {
 342         DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
 343                  msg,
 344                  flags,
 345                  (flags & R128_UPLOAD_CORE) ? "core, " : "",
 346                  (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
 347                  (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
 348                  (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
 349                  (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
 350                  (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
 351                  (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
 352                  (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
 353                  (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
 354 }
 355
 356 static void r128_cce_dispatch_clear(drm_device_t * dev,
 357                                     drm_r128_clear_t * clear)
 358 {
 359         drm_r128_private_t *dev_priv = dev->dev_private;
 360         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 361         int nbox = sarea_priv->nbox;
 362         drm_clip_rect_t *pbox = sarea_priv->boxes;
 363         unsigned int flags = clear->flags;
 364         int i;
 365         RING_LOCALS;
 366         DRM_DEBUG("%s\n", __FUNCTION__);
 367
 368         if (dev_priv->page_flipping && dev_priv->current_page == 1) {
 369                 unsigned int tmp = flags;
 370
 371                 flags &= ~(R128_FRONT | R128_BACK);
 372                 if (tmp & R128_FRONT)
 373                         flags |= R128_BACK;
 374                 if (tmp & R128_BACK)
 375                         flags |= R128_FRONT;
 376         }
 377
 378         for (i = 0; i < nbox; i++) {
 379                 int x = pbox[i].x1;
 380                 int y = pbox[i].y1;
 381                 int w = pbox[i].x2 - x;
 382                 int h = pbox[i].y2 - y;
 383
 384                 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
 385                           pbox[i].x1, pbox[i].y1, pbox[i].x2,
 386                           pbox[i].y2, flags);
 387
 388                 if (flags & (R128_FRONT | R128_BACK)) {
 389                         BEGIN_RING(2);
 390
 391                         OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
 392                         OUT_RING(clear->color_mask);
 393
 394                         ADVANCE_RING();
 395                 }
 396
 397                 if (flags & R128_FRONT) {
 398                         BEGIN_RING(6);
 399
 400                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 401                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 402                                  R128_GMC_BRUSH_SOLID_COLOR |
 403                                  (dev_priv->color_fmt << 8) |
 404                                  R128_GMC_SRC_DATATYPE_COLOR |
 405                                  R128_ROP3_P |
 406                                  R128_GMC_CLR_CMP_CNTL_DIS |
 407                                  R128_GMC_AUX_CLIP_DIS);
 408
 409                         OUT_RING(dev_priv->front_pitch_offset_c);
 410                         OUT_RING(clear->clear_color);
 411
 412                         OUT_RING((x << 16) | y);
 413                         OUT_RING((w << 16) | h);
 414
 415                         ADVANCE_RING();
 416                 }
 417
 418                 if (flags & R128_BACK) {
 419                         BEGIN_RING(6);
 420
 421                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 422                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 423                                  R128_GMC_BRUSH_SOLID_COLOR |
 424                                  (dev_priv->color_fmt << 8) |
 425                                  R128_GMC_SRC_DATATYPE_COLOR |
 426                                  R128_ROP3_P |
 427                                  R128_GMC_CLR_CMP_CNTL_DIS |
 428                                  R128_GMC_AUX_CLIP_DIS);
 429
 430                         OUT_RING(dev_priv->back_pitch_offset_c);
 431                         OUT_RING(clear->clear_color);
 432
 433                         OUT_RING((x << 16) | y);
 434                         OUT_RING((w << 16) | h);
 435
 436                         ADVANCE_RING();
 437                 }
 438
 439                 if (flags & R128_DEPTH) {
 440                         BEGIN_RING(6);
 441
 442                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 443                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 444                                  R128_GMC_BRUSH_SOLID_COLOR |
 445                                  (dev_priv->depth_fmt << 8) |
 446                                  R128_GMC_SRC_DATATYPE_COLOR |
 447                                  R128_ROP3_P |
 448                                  R128_GMC_CLR_CMP_CNTL_DIS |
 449                                  R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
 450
 451                         OUT_RING(dev_priv->depth_pitch_offset_c);
 452                         OUT_RING(clear->clear_depth);
 453
 454                         OUT_RING((x << 16) | y);
 455                         OUT_RING((w << 16) | h);
 456
 457                         ADVANCE_RING();
 458                 }
 459         }
 460 }
 461
 462 static void r128_cce_dispatch_swap(drm_device_t * dev)
 463 {
 464         drm_r128_private_t *dev_priv = dev->dev_private;
 465         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 466         int nbox = sarea_priv->nbox;
 467         drm_clip_rect_t *pbox = sarea_priv->boxes;
 468         int i;
 469         RING_LOCALS;
 470         DRM_DEBUG("%s\n", __FUNCTION__);
 471
 472 #if R128_PERFORMANCE_BOXES
 473         /* Do some trivial performance monitoring...
 474          */
 475         r128_cce_performance_boxes(dev_priv);
 476 #endif
 477
 478         for (i = 0; i < nbox; i++) {
 479                 int x = pbox[i].x1;
 480                 int y = pbox[i].y1;
 481                 int w = pbox[i].x2 - x;
 482                 int h = pbox[i].y2 - y;
 483
 484                 BEGIN_RING(7);
 485
 486                 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
 487                 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
 488                          R128_GMC_DST_PITCH_OFFSET_CNTL |
 489                          R128_GMC_BRUSH_NONE |
 490                          (dev_priv->color_fmt << 8) |
 491                          R128_GMC_SRC_DATATYPE_COLOR |
 492                          R128_ROP3_S |
 493                          R128_DP_SRC_SOURCE_MEMORY |
 494                          R128_GMC_CLR_CMP_CNTL_DIS |
 495                          R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
 496
 497                 /* Make this work even if front & back are flipped:
 498                  */
 499                 if (dev_priv->current_page == 0) {
 500                         OUT_RING(dev_priv->back_pitch_offset_c);
 501                         OUT_RING(dev_priv->front_pitch_offset_c);
 502                 } else {
 503                         OUT_RING(dev_priv->front_pitch_offset_c);
 504                         OUT_RING(dev_priv->back_pitch_offset_c);
 505                 }
 506
 507                 OUT_RING((x << 16) | y);
 508                 OUT_RING((x << 16) | y);
 509                 OUT_RING((w << 16) | h);
 510
 511                 ADVANCE_RING();
 512         }
 513
 514         /* Increment the frame counter.  The client-side 3D driver must
 515          * throttle the framerate by waiting for this value before
 516          * performing the swapbuffer ioctl.
 517          */
 518         dev_priv->sarea_priv->last_frame++;
 519
 520         BEGIN_RING(2);
 521
 522         OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
 523         OUT_RING(dev_priv->sarea_priv->last_frame);
 524
 525         ADVANCE_RING();
 526 }
 527
 528 static void r128_cce_dispatch_flip(drm_device_t * dev)
 529 {
 530         drm_r128_private_t *dev_priv = dev->dev_private;
 531         RING_LOCALS;
 532         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 533                   __FUNCTION__,
 534                   dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
 535
 536 #if R128_PERFORMANCE_BOXES
 537         /* Do some trivial performance monitoring...
 538          */
 539         r128_cce_performance_boxes(dev_priv);
 540 #endif
 541
 542         BEGIN_RING(4);
 543
 544         R128_WAIT_UNTIL_PAGE_FLIPPED();
 545         OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
 546
 547         if (dev_priv->current_page == 0) {
 548                 OUT_RING(dev_priv->back_offset);
 549         } else {
 550                 OUT_RING(dev_priv->front_offset);
 551         }
 552
 553         ADVANCE_RING();
 554
 555         /* Increment the frame counter.  The client-side 3D driver must
 556          * throttle the framerate by waiting for this value before
 557          * performing the swapbuffer ioctl.
 558          */
 559         dev_priv->sarea_priv->last_frame++;
 560         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
 561             1 - dev_priv->current_page;
 562
 563         BEGIN_RING(2);
 564
 565         OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
 566         OUT_RING(dev_priv->sarea_priv->last_frame);
 567
 568         ADVANCE_RING();
 569 }
 570
 571 static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
 572 {
 573         drm_r128_private_t *dev_priv = dev->dev_private;
 574         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 575         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 576         int format = sarea_priv->vc_format;
 577         int offset = buf->bus_address;
 578         int size = buf->used;
 579         int prim = buf_priv->prim;
 580         int i = 0;
 581         RING_LOCALS;
 582         DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
 583
 584         if (0)
 585                 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
 586
 587         if (buf->used) {
 588                 buf_priv->dispatched = 1;
 589
 590                 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
 591                         r128_emit_state(dev_priv);
 592                 }
 593
 594                 do {
 595                         /* Emit the next set of up to three cliprects */
 596                         if (i < sarea_priv->nbox) {
 597                                 r128_emit_clip_rects(dev_priv,
 598                                                      &sarea_priv->boxes[i],
 599                                                      sarea_priv->nbox - i);
 600                         }
 601
 602                         /* Emit the vertex buffer rendering commands */
 603                         BEGIN_RING(5);
 604
 605                         OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
 606                         OUT_RING(offset);
 607                         OUT_RING(size);
 608                         OUT_RING(format);
 609                         OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
 610                                  (size << R128_CCE_VC_CNTL_NUM_SHIFT));
 611
 612                         ADVANCE_RING();
 613
 614                         i += 3;
 615                 } while (i < sarea_priv->nbox);
 616         }
 617
 618         if (buf_priv->discard) {
 619                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 620
 621                 /* Emit the vertex buffer age */
 622                 BEGIN_RING(2);
 623
 624                 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
 625                 OUT_RING(buf_priv->age);
 626
 627                 ADVANCE_RING();
 628
 629                 buf->pending = 1;
 630                 buf->used = 0;
 631                 /* FIXME: Check dispatched field */
 632                 buf_priv->dispatched = 0;
 633         }
 634
 635         dev_priv->sarea_priv->last_dispatch++;
 636
 637         sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
 638         sarea_priv->nbox = 0;
 639 }
 640
 641 static void r128_cce_dispatch_indirect(drm_device_t * dev,
 642                                        drm_buf_t * buf, int start, int end)
 643 {
 644         drm_r128_private_t *dev_priv = dev->dev_private;
 645         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 646         RING_LOCALS;
 647         DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
 648
 649         if (start != end) {
 650                 int offset = buf->bus_address + start;
 651                 int dwords = (end - start + 3) / sizeof(u32);
 652
 653                 /* Indirect buffer data must be an even number of
 654                  * dwords, so if we've been given an odd number we must
 655                  * pad the data with a Type-2 CCE packet.
 656                  */
 657                 if (dwords & 1) {
 658                         u32 *data = (u32 *)
 659                             ((char *)dev->agp_buffer_map->handle
 660                              + buf->offset + start);
 661                         data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
 662                 }
 663
 664                 buf_priv->dispatched = 1;
 665
 666                 /* Fire off the indirect buffer */
 667                 BEGIN_RING(3);
 668
 669                 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
 670                 OUT_RING(offset);
 671                 OUT_RING(dwords);
 672
 673                 ADVANCE_RING();
 674         }
 675
 676         if (buf_priv->discard) {
 677                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 678
 679                 /* Emit the indirect buffer age */
 680                 BEGIN_RING(2);
 681
 682                 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
 683                 OUT_RING(buf_priv->age);
 684
 685                 ADVANCE_RING();
 686
 687                 buf->pending = 1;
 688                 buf->used = 0;
 689                 /* FIXME: Check dispatched field */
 690                 buf_priv->dispatched = 0;
 691         }
 692
 693         dev_priv->sarea_priv->last_dispatch++;
 694 }
 695
 696 static void r128_cce_dispatch_indices(drm_device_t * dev,
 697                                       drm_buf_t * buf,
 698                                       int start, int end, int count)
 699 {
 700         drm_r128_private_t *dev_priv = dev->dev_private;
 701         drm_r128_buf_priv_t *buf_priv = buf->dev_private;
 702         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
 703         int format = sarea_priv->vc_format;
 704         int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
 705         int prim = buf_priv->prim;
 706         u32 *data;
 707         int dwords;
 708         int i = 0;
 709         RING_LOCALS;
 710         DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
 711
 712         if (0)
 713                 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
 714
 715         if (start != end) {
 716                 buf_priv->dispatched = 1;
 717
 718                 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
 719                         r128_emit_state(dev_priv);
 720                 }
 721
 722                 dwords = (end - start + 3) / sizeof(u32);
 723
 724                 data = (u32 *) ((char *)dev->agp_buffer_map->handle
 725                                 + buf->offset + start);
 726
 727                 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
 728                                                   dwords - 2));
 729
 730                 data[1] = cpu_to_le32(offset);
 731                 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
 732                 data[3] = cpu_to_le32(format);
 733                 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
 734                                        (count << 16)));
 735
 736                 if (count & 0x1) {
 737 #ifdef __LITTLE_ENDIAN
 738                         data[dwords - 1] &= 0x0000ffff;
 739 #else
 740                         data[dwords - 1] &= 0xffff0000;
 741 #endif
 742                 }
 743
 744                 do {
 745                         /* Emit the next set of up to three cliprects */
 746                         if (i < sarea_priv->nbox) {
 747                                 r128_emit_clip_rects(dev_priv,
 748                                                      &sarea_priv->boxes[i],
 749                                                      sarea_priv->nbox - i);
 750                         }
 751
 752                         r128_cce_dispatch_indirect(dev, buf, start, end);
 753
 754                         i += 3;
 755                 } while (i < sarea_priv->nbox);
 756         }
 757
 758         if (buf_priv->discard) {
 759                 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
 760
 761                 /* Emit the vertex buffer age */
 762                 BEGIN_RING(2);
 763
 764                 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
 765                 OUT_RING(buf_priv->age);
 766
 767                 ADVANCE_RING();
 768
 769                 buf->pending = 1;
 770                 /* FIXME: Check dispatched field */
 771                 buf_priv->dispatched = 0;
 772         }
 773
 774         dev_priv->sarea_priv->last_dispatch++;
 775
 776         sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
 777         sarea_priv->nbox = 0;
 778 }
 779
 780 static int r128_cce_dispatch_blit(DRMFILE filp,
 781                                   drm_device_t * dev, drm_r128_blit_t * blit)
 782 {
 783         drm_r128_private_t *dev_priv = dev->dev_private;
 784         drm_device_dma_t *dma = dev->dma;
 785         drm_buf_t *buf;
 786         drm_r128_buf_priv_t *buf_priv;
 787         u32 *data;
 788         int dword_shift, dwords;
 789         RING_LOCALS;
 790         DRM_DEBUG("\n");
 791
 792         /* The compiler won't optimize away a division by a variable,
 793          * even if the only legal values are powers of two.  Thus, we'll
 794          * use a shift instead.
 795          */
 796         switch (blit->format) {
 797         case R128_DATATYPE_ARGB8888:
 798                 dword_shift = 0;
 799                 break;
 800         case R128_DATATYPE_ARGB1555:
 801         case R128_DATATYPE_RGB565:
 802         case R128_DATATYPE_ARGB4444:
 803         case R128_DATATYPE_YVYU422:
 804         case R128_DATATYPE_VYUY422:
 805                 dword_shift = 1;
 806                 break;
 807         case R128_DATATYPE_CI8:
 808         case R128_DATATYPE_RGB8:
 809                 dword_shift = 2;
 810                 break;
 811         default:
 812                 DRM_ERROR("invalid blit format %d\n", blit->format);
 813                 return DRM_ERR(EINVAL);
 814         }
 815
 816         /* Flush the pixel cache, and mark the contents as Read Invalid.
 817          * This ensures no pixel data gets mixed up with the texture
 818          * data from the host data blit, otherwise part of the texture
 819          * image may be corrupted.
 820          */
 821         BEGIN_RING(2);
 822
 823         OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
 824         OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
 825
 826         ADVANCE_RING();
 827
 828         /* Dispatch the indirect buffer.
 829          */
 830         buf = dma->buflist[blit->idx];
 831         buf_priv = buf->dev_private;
 832
 833         if (buf->filp != filp) {
 834                 DRM_ERROR("process %d using buffer owned by %p\n",
 835                           DRM_CURRENTPID, buf->filp);
 836                 return DRM_ERR(EINVAL);
 837         }
 838         if (buf->pending) {
 839                 DRM_ERROR("sending pending buffer %d\n", blit->idx);
 840                 return DRM_ERR(EINVAL);
 841         }
 842
 843         buf_priv->discard = 1;
 844
 845         dwords = (blit->width * blit->height) >> dword_shift;
 846
 847         data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
 848
 849         data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
 850         data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
 851                                R128_GMC_BRUSH_NONE |
 852                                (blit->format << 8) |
 853                                R128_GMC_SRC_DATATYPE_COLOR |
 854                                R128_ROP3_S |
 855                                R128_DP_SRC_SOURCE_HOST_DATA |
 856                                R128_GMC_CLR_CMP_CNTL_DIS |
 857                                R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
 858
 859         data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
 860         data[3] = cpu_to_le32(0xffffffff);
 861         data[4] = cpu_to_le32(0xffffffff);
 862         data[5] = cpu_to_le32((blit->y << 16) | blit->x);
 863         data[6] = cpu_to_le32((blit->height << 16) | blit->width);
 864         data[7] = cpu_to_le32(dwords);
 865
 866         buf->used = (dwords + 8) * sizeof(u32);
 867
 868         r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
 869
 870         /* Flush the pixel cache after the blit completes.  This ensures
 871          * the texture data is written out to memory before rendering
 872          * continues.
 873          */
 874         BEGIN_RING(2);
 875
 876         OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
 877         OUT_RING(R128_PC_FLUSH_GUI);
 878
 879         ADVANCE_RING();
 880
 881         return 0;
 882 }
 883
 884 /* ================================================================
 885  * Tiled depth buffer management
 886  *
 887  * FIXME: These should all set the destination write mask for when we
 888  * have hardware stencil support.
 889  */
 890
 891 static int r128_cce_dispatch_write_span(drm_device_t * dev,
 892                                         drm_r128_depth_t * depth)
 893 {
 894         drm_r128_private_t *dev_priv = dev->dev_private;
 895         int count, x, y;
 896         u32 *buffer;
 897         u8 *mask;
 898         int i, buffer_size, mask_size;
 899         RING_LOCALS;
 900         DRM_DEBUG("\n");
 901
 902         count = depth->n;
 903         if (count > 4096 || count <= 0)
 904                 return DRM_ERR(EMSGSIZE);
 905
 906         if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
 907                 return DRM_ERR(EFAULT);
 908         }
 909         if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
 910                 return DRM_ERR(EFAULT);
 911         }
 912
 913         buffer_size = depth->n * sizeof(u32);
 914         buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
 915         if (buffer == NULL)
 916                 return DRM_ERR(ENOMEM);
 917         if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
 918                 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 919                 return DRM_ERR(EFAULT);
 920         }
 921
 922         mask_size = depth->n * sizeof(u8);
 923         if (depth->mask) {
 924                 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
 925                 if (mask == NULL) {
 926                         drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 927                         return DRM_ERR(ENOMEM);
 928                 }
 929                 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
 930                         drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 931                         drm_free(mask, mask_size, DRM_MEM_BUFS);
 932                         return DRM_ERR(EFAULT);
 933                 }
 934
 935                 for (i = 0; i < count; i++, x++) {
 936                         if (mask[i]) {
 937                                 BEGIN_RING(6);
 938
 939                                 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 940                                 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 941                                          R128_GMC_BRUSH_SOLID_COLOR |
 942                                          (dev_priv->depth_fmt << 8) |
 943                                          R128_GMC_SRC_DATATYPE_COLOR |
 944                                          R128_ROP3_P |
 945                                          R128_GMC_CLR_CMP_CNTL_DIS |
 946                                          R128_GMC_WR_MSK_DIS);
 947
 948                                 OUT_RING(dev_priv->depth_pitch_offset_c);
 949                                 OUT_RING(buffer[i]);
 950
 951                                 OUT_RING((x << 16) | y);
 952                                 OUT_RING((1 << 16) | 1);
 953
 954                                 ADVANCE_RING();
 955                         }
 956                 }
 957
 958                 drm_free(mask, mask_size, DRM_MEM_BUFS);
 959         } else {
 960                 for (i = 0; i < count; i++, x++) {
 961                         BEGIN_RING(6);
 962
 963                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
 964                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
 965                                  R128_GMC_BRUSH_SOLID_COLOR |
 966                                  (dev_priv->depth_fmt << 8) |
 967                                  R128_GMC_SRC_DATATYPE_COLOR |
 968                                  R128_ROP3_P |
 969                                  R128_GMC_CLR_CMP_CNTL_DIS |
 970                                  R128_GMC_WR_MSK_DIS);
 971
 972                         OUT_RING(dev_priv->depth_pitch_offset_c);
 973                         OUT_RING(buffer[i]);
 974
 975                         OUT_RING((x << 16) | y);
 976                         OUT_RING((1 << 16) | 1);
 977
 978                         ADVANCE_RING();
 979                 }
 980         }
 981
 982         drm_free(buffer, buffer_size, DRM_MEM_BUFS);
 983
 984         return 0;
 985 }
 986
 987 static int r128_cce_dispatch_write_pixels(drm_device_t * dev,
 988                                           drm_r128_depth_t * depth)
 989 {
 990         drm_r128_private_t *dev_priv = dev->dev_private;
 991         int count, *x, *y;
 992         u32 *buffer;
 993         u8 *mask;
 994         int i, xbuf_size, ybuf_size, buffer_size, mask_size;
 995         RING_LOCALS;
 996         DRM_DEBUG("\n");
 997
 998         count = depth->n;
 999         if (count > 4096 || count <= 0)
1000                 return DRM_ERR(EMSGSIZE);
1001
1002         xbuf_size = count * sizeof(*x);
1003         ybuf_size = count * sizeof(*y);
1004         x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1005         if (x == NULL) {
1006                 return DRM_ERR(ENOMEM);
1007         }
1008         y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1009         if (y == NULL) {
1010                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1011                 return DRM_ERR(ENOMEM);
1012         }
1013         if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1014                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1015                 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1016                 return DRM_ERR(EFAULT);
1017         }
1018         if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
1019                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1020                 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1021                 return DRM_ERR(EFAULT);
1022         }
1023
1024         buffer_size = depth->n * sizeof(u32);
1025         buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
1026         if (buffer == NULL) {
1027                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1028                 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1029                 return DRM_ERR(ENOMEM);
1030         }
1031         if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
1032                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1033                 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1034                 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1035                 return DRM_ERR(EFAULT);
1036         }
1037
1038         if (depth->mask) {
1039                 mask_size = depth->n * sizeof(u8);
1040                 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
1041                 if (mask == NULL) {
1042                         drm_free(x, xbuf_size, DRM_MEM_BUFS);
1043                         drm_free(y, ybuf_size, DRM_MEM_BUFS);
1044                         drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1045                         return DRM_ERR(ENOMEM);
1046                 }
1047                 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
1048                         drm_free(x, xbuf_size, DRM_MEM_BUFS);
1049                         drm_free(y, ybuf_size, DRM_MEM_BUFS);
1050                         drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1051                         drm_free(mask, mask_size, DRM_MEM_BUFS);
1052                         return DRM_ERR(EFAULT);
1053                 }
1054
1055                 for (i = 0; i < count; i++) {
1056                         if (mask[i]) {
1057                                 BEGIN_RING(6);
1058
1059                                 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1060                                 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1061                                          R128_GMC_BRUSH_SOLID_COLOR |
1062                                          (dev_priv->depth_fmt << 8) |
1063                                          R128_GMC_SRC_DATATYPE_COLOR |
1064                                          R128_ROP3_P |
1065                                          R128_GMC_CLR_CMP_CNTL_DIS |
1066                                          R128_GMC_WR_MSK_DIS);
1067
1068                                 OUT_RING(dev_priv->depth_pitch_offset_c);
1069                                 OUT_RING(buffer[i]);
1070
1071                                 OUT_RING((x[i] << 16) | y[i]);
1072                                 OUT_RING((1 << 16) | 1);
1073
1074                                 ADVANCE_RING();
1075                         }
1076                 }
1077
1078                 drm_free(mask, mask_size, DRM_MEM_BUFS);
1079         } else {
1080                 for (i = 0; i < count; i++) {
1081                         BEGIN_RING(6);
1082
1083                         OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1084                         OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1085                                  R128_GMC_BRUSH_SOLID_COLOR |
1086                                  (dev_priv->depth_fmt << 8) |
1087                                  R128_GMC_SRC_DATATYPE_COLOR |
1088                                  R128_ROP3_P |
1089                                  R128_GMC_CLR_CMP_CNTL_DIS |
1090                                  R128_GMC_WR_MSK_DIS);
1091
1092                         OUT_RING(dev_priv->depth_pitch_offset_c);
1093                         OUT_RING(buffer[i]);
1094
1095                         OUT_RING((x[i] << 16) | y[i]);
1096                         OUT_RING((1 << 16) | 1);
1097
1098                         ADVANCE_RING();
1099                 }
1100         }
1101
1102         drm_free(x, xbuf_size, DRM_MEM_BUFS);
1103         drm_free(y, ybuf_size, DRM_MEM_BUFS);
1104         drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1105
1106         return 0;
1107 }
1108
1109 static int r128_cce_dispatch_read_span(drm_device_t * dev,
1110                                        drm_r128_depth_t * depth)
1111 {
1112         drm_r128_private_t *dev_priv = dev->dev_private;
1113         int count, x, y;
1114         RING_LOCALS;
1115         DRM_DEBUG("\n");
1116
1117         count = depth->n;
1118         if (count > 4096 || count <= 0)
1119                 return DRM_ERR(EMSGSIZE);
1120
1121         if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
1122                 return DRM_ERR(EFAULT);
1123         }
1124         if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
1125                 return DRM_ERR(EFAULT);
1126         }
1127
1128         BEGIN_RING(7);
1129
1130         OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1131         OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1132                  R128_GMC_DST_PITCH_OFFSET_CNTL |
1133                  R128_GMC_BRUSH_NONE |
1134                  (dev_priv->depth_fmt << 8) |
1135                  R128_GMC_SRC_DATATYPE_COLOR |
1136                  R128_ROP3_S |
1137                  R128_DP_SRC_SOURCE_MEMORY |
1138                  R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1139
1140         OUT_RING(dev_priv->depth_pitch_offset_c);
1141         OUT_RING(dev_priv->span_pitch_offset_c);
1142
1143         OUT_RING((x << 16) | y);
1144         OUT_RING((0 << 16) | 0);
1145         OUT_RING((count << 16) | 1);
1146
1147         ADVANCE_RING();
1148
1149         return 0;
1150 }
1151
1152 static int r128_cce_dispatch_read_pixels(drm_device_t * dev,
1153                                          drm_r128_depth_t * depth)
1154 {
1155         drm_r128_private_t *dev_priv = dev->dev_private;
1156         int count, *x, *y;
1157         int i, xbuf_size, ybuf_size;
1158         RING_LOCALS;
1159         DRM_DEBUG("%s\n", __FUNCTION__);
1160
1161         count = depth->n;
1162         if (count > 4096 || count <= 0)
1163                 return DRM_ERR(EMSGSIZE);
1164
1165         if (count > dev_priv->depth_pitch) {
1166                 count = dev_priv->depth_pitch;
1167         }
1168
1169         xbuf_size = count * sizeof(*x);
1170         ybuf_size = count * sizeof(*y);
1171         x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1172         if (x == NULL) {
1173                 return DRM_ERR(ENOMEM);
1174         }
1175         y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1176         if (y == NULL) {
1177                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1178                 return DRM_ERR(ENOMEM);
1179         }
1180         if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1181                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1182                 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1183                 return DRM_ERR(EFAULT);
1184         }
1185         if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
1186                 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1187                 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1188                 return DRM_ERR(EFAULT);
1189         }
1190
1191         for (i = 0; i < count; i++) {
1192                 BEGIN_RING(7);
1193
1194                 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1195                 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1196                          R128_GMC_DST_PITCH_OFFSET_CNTL |
1197                          R128_GMC_BRUSH_NONE |
1198                          (dev_priv->depth_fmt << 8) |
1199                          R128_GMC_SRC_DATATYPE_COLOR |
1200                          R128_ROP3_S |
1201                          R128_DP_SRC_SOURCE_MEMORY |
1202                          R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1203
1204                 OUT_RING(dev_priv->depth_pitch_offset_c);
1205                 OUT_RING(dev_priv->span_pitch_offset_c);
1206
1207                 OUT_RING((x[i] << 16) | y[i]);
1208                 OUT_RING((i << 16) | 0);
1209                 OUT_RING((1 << 16) | 1);
1210
1211                 ADVANCE_RING();
1212         }
1213
1214         drm_free(x, xbuf_size, DRM_MEM_BUFS);
1215         drm_free(y, ybuf_size, DRM_MEM_BUFS);
1216
1217         return 0;
1218 }
1219
1220 /* ================================================================
1221  * Polygon stipple
1222  */
1223
1224 static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1225 {
1226         drm_r128_private_t *dev_priv = dev->dev_private;
1227         int i;
1228         RING_LOCALS;
1229         DRM_DEBUG("%s\n", __FUNCTION__);
1230
1231         BEGIN_RING(33);
1232
1233         OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1234         for (i = 0; i < 32; i++) {
1235                 OUT_RING(stipple[i]);
1236         }
1237
1238         ADVANCE_RING();
1239 }
1240
1241 /* ================================================================
1242  * IOCTL functions
1243  */
1244
1245 static int r128_cce_clear(DRM_IOCTL_ARGS)
1246 {
1247         DRM_DEVICE;
1248         drm_r128_private_t *dev_priv = dev->dev_private;
1249         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1250         drm_r128_clear_t clear;
1251         DRM_DEBUG("\n");
1252
1253         LOCK_TEST_WITH_RETURN(dev, filp);
1254
1255         DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data,
1256                                  sizeof(clear));
1257
1258         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1259
1260         if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1261                 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1262
1263         r128_cce_dispatch_clear(dev, &clear);
1264         COMMIT_RING();
1265
1266         /* Make sure we restore the 3D state next time.
1267          */
1268         dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
1269
1270         return 0;
1271 }
1272
1273 static int r128_do_init_pageflip(drm_device_t * dev)
1274 {
1275         drm_r128_private_t *dev_priv = dev->dev_private;
1276         DRM_DEBUG("\n");
1277
1278         dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1279         dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1280
1281         R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1282         R128_WRITE(R128_CRTC_OFFSET_CNTL,
1283                    dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1284
1285         dev_priv->page_flipping = 1;
1286         dev_priv->current_page = 0;
1287         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1288
1289         return 0;
1290 }
1291
1292 static int r128_do_cleanup_pageflip(drm_device_t * dev)
1293 {
1294         drm_r128_private_t *dev_priv = dev->dev_private;
1295         DRM_DEBUG("\n");
1296
1297         R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1298         R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1299
1300         if (dev_priv->current_page != 0) {
1301                 r128_cce_dispatch_flip(dev);
1302                 COMMIT_RING();
1303         }
1304
1305         dev_priv->page_flipping = 0;
1306         return 0;
1307 }
1308
1309 /* Swapping and flipping are different operations, need different ioctls.
1310  * They can & should be intermixed to support multiple 3d windows.
1311  */
1312
1313 static int r128_cce_flip(DRM_IOCTL_ARGS)
1314 {
1315         DRM_DEVICE;
1316         drm_r128_private_t *dev_priv = dev->dev_private;
1317         DRM_DEBUG("%s\n", __FUNCTION__);
1318
1319         LOCK_TEST_WITH_RETURN(dev, filp);
1320
1321         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1322
1323         if (!dev_priv->page_flipping)
1324                 r128_do_init_pageflip(dev);
1325
1326         r128_cce_dispatch_flip(dev);
1327
1328         COMMIT_RING();
1329         return 0;
1330 }
1331
1332 static int r128_cce_swap(DRM_IOCTL_ARGS)
1333 {
1334         DRM_DEVICE;
1335         drm_r128_private_t *dev_priv = dev->dev_private;
1336         drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1337         DRM_DEBUG("%s\n", __FUNCTION__);
1338
1339         LOCK_TEST_WITH_RETURN(dev, filp);
1340
1341         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1342
1343         if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1344                 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1345
1346         r128_cce_dispatch_swap(dev);
1347         dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1348                                         R128_UPLOAD_MASKS);
1349
1350         COMMIT_RING();
1351         return 0;
1352 }
1353
1354 static int r128_cce_vertex(DRM_IOCTL_ARGS)
1355 {
1356         DRM_DEVICE;
1357         drm_r128_private_t *dev_priv = dev->dev_private;
1358         drm_device_dma_t *dma = dev->dma;
1359         drm_buf_t *buf;
1360         drm_r128_buf_priv_t *buf_priv;
1361         drm_r128_vertex_t vertex;
1362
1363         LOCK_TEST_WITH_RETURN(dev, filp);
1364
1365         if (!dev_priv) {
1366                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1367                 return DRM_ERR(EINVAL);
1368         }
1369
1370         DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data,
1371                                  sizeof(vertex));
1372
1373         DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1374                   DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
1375
1376         if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
1377                 DRM_ERROR("buffer index %d (of %d max)\n",
1378                           vertex.idx, dma->buf_count - 1);
1379                 return DRM_ERR(EINVAL);
1380         }
1381         if (vertex.prim < 0 ||
1382             vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1383                 DRM_ERROR("buffer prim %d\n", vertex.prim);
1384                 return DRM_ERR(EINVAL);
1385         }
1386
1387         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1388         VB_AGE_TEST_WITH_RETURN(dev_priv);
1389
1390         buf = dma->buflist[vertex.idx];
1391         buf_priv = buf->dev_private;
1392
1393         if (buf->filp != filp) {
1394                 DRM_ERROR("process %d using buffer owned by %p\n",
1395                           DRM_CURRENTPID, buf->filp);
1396                 return DRM_ERR(EINVAL);
1397         }
1398         if (buf->pending) {
1399                 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
1400                 return DRM_ERR(EINVAL);
1401         }
1402
1403         buf->used = vertex.count;
1404         buf_priv->prim = vertex.prim;
1405         buf_priv->discard = vertex.discard;
1406
1407         r128_cce_dispatch_vertex(dev, buf);
1408
1409         COMMIT_RING();
1410         return 0;
1411 }
1412
1413 static int r128_cce_indices(DRM_IOCTL_ARGS)
1414 {
1415         DRM_DEVICE;
1416         drm_r128_private_t *dev_priv = dev->dev_private;
1417         drm_device_dma_t *dma = dev->dma;
1418         drm_buf_t *buf;
1419         drm_r128_buf_priv_t *buf_priv;
1420         drm_r128_indices_t elts;
1421         int count;
1422
1423         LOCK_TEST_WITH_RETURN(dev, filp);
1424
1425         if (!dev_priv) {
1426                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1427                 return DRM_ERR(EINVAL);
1428         }
1429
1430         DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data,
1431                                  sizeof(elts));
1432
1433         DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1434                   elts.idx, elts.start, elts.end, elts.discard);
1435
1436         if (elts.idx < 0 || elts.idx >= dma->buf_count) {
1437                 DRM_ERROR("buffer index %d (of %d max)\n",
1438                           elts.idx, dma->buf_count - 1);
1439                 return DRM_ERR(EINVAL);
1440         }
1441         if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1442                 DRM_ERROR("buffer prim %d\n", elts.prim);
1443                 return DRM_ERR(EINVAL);
1444         }
1445
1446         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1447         VB_AGE_TEST_WITH_RETURN(dev_priv);
1448
1449         buf = dma->buflist[elts.idx];
1450         buf_priv = buf->dev_private;
1451
1452         if (buf->filp != filp) {
1453                 DRM_ERROR("process %d using buffer owned by %p\n",
1454                           DRM_CURRENTPID, buf->filp);
1455                 return DRM_ERR(EINVAL);
1456         }
1457         if (buf->pending) {
1458                 DRM_ERROR("sending pending buffer %d\n", elts.idx);
1459                 return DRM_ERR(EINVAL);
1460         }
1461
1462         count = (elts.end - elts.start) / sizeof(u16);
1463         elts.start -= R128_INDEX_PRIM_OFFSET;
1464
1465         if (elts.start & 0x7) {
1466                 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
1467                 return DRM_ERR(EINVAL);
1468         }
1469         if (elts.start < buf->used) {
1470                 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
1471                 return DRM_ERR(EINVAL);
1472         }
1473
1474         buf->used = elts.end;
1475         buf_priv->prim = elts.prim;
1476         buf_priv->discard = elts.discard;
1477
1478         r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count);
1479
1480         COMMIT_RING();
1481         return 0;
1482 }
1483
1484 static int r128_cce_blit(DRM_IOCTL_ARGS)
1485 {
1486         DRM_DEVICE;
1487         drm_device_dma_t *dma = dev->dma;
1488         drm_r128_private_t *dev_priv = dev->dev_private;
1489         drm_r128_blit_t blit;
1490         int ret;
1491
1492         LOCK_TEST_WITH_RETURN(dev, filp);
1493
1494         DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data,
1495                                  sizeof(blit));
1496
1497         DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx);
1498
1499         if (blit.idx < 0 || blit.idx >= dma->buf_count) {
1500                 DRM_ERROR("buffer index %d (of %d max)\n",
1501                           blit.idx, dma->buf_count - 1);
1502                 return DRM_ERR(EINVAL);
1503         }
1504
1505         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1506         VB_AGE_TEST_WITH_RETURN(dev_priv);
1507
1508         ret = r128_cce_dispatch_blit(filp, dev, &blit);
1509
1510         COMMIT_RING();
1511         return ret;
1512 }
1513
1514 static int r128_cce_depth(DRM_IOCTL_ARGS)
1515 {
1516         DRM_DEVICE;
1517         drm_r128_private_t *dev_priv = dev->dev_private;
1518         drm_r128_depth_t depth;
1519         int ret;
1520
1521         LOCK_TEST_WITH_RETURN(dev, filp);
1522
1523         DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data,
1524                                  sizeof(depth));
1525
1526         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1527
1528         ret = DRM_ERR(EINVAL);
1529         switch (depth.func) {
1530         case R128_WRITE_SPAN:
1531                 ret = r128_cce_dispatch_write_span(dev, &depth);
1532         case R128_WRITE_PIXELS:
1533                 ret = r128_cce_dispatch_write_pixels(dev, &depth);
1534         case R128_READ_SPAN:
1535                 ret = r128_cce_dispatch_read_span(dev, &depth);
1536         case R128_READ_PIXELS:
1537                 ret = r128_cce_dispatch_read_pixels(dev, &depth);
1538         }
1539
1540         COMMIT_RING();
1541         return ret;
1542 }
1543
1544 static int r128_cce_stipple(DRM_IOCTL_ARGS)
1545 {
1546         DRM_DEVICE;
1547         drm_r128_private_t *dev_priv = dev->dev_private;
1548         drm_r128_stipple_t stipple;
1549         u32 mask[32];
1550
1551         LOCK_TEST_WITH_RETURN(dev, filp);
1552
1553         DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data,
1554                                  sizeof(stipple));
1555
1556         if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
1557                 return DRM_ERR(EFAULT);
1558
1559         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1560
1561         r128_cce_dispatch_stipple(dev, mask);
1562
1563         COMMIT_RING();
1564         return 0;
1565 }
1566
1567 static int r128_cce_indirect(DRM_IOCTL_ARGS)
1568 {
1569         DRM_DEVICE;
1570         drm_r128_private_t *dev_priv = dev->dev_private;
1571         drm_device_dma_t *dma = dev->dma;
1572         drm_buf_t *buf;
1573         drm_r128_buf_priv_t *buf_priv;
1574         drm_r128_indirect_t indirect;
1575 #if 0
1576         RING_LOCALS;
1577 #endif
1578
1579         LOCK_TEST_WITH_RETURN(dev, filp);
1580
1581         if (!dev_priv) {
1582                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1583                 return DRM_ERR(EINVAL);
1584         }
1585
1586         DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data,
1587                                  sizeof(indirect));
1588
1589         DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
1590                   indirect.idx, indirect.start, indirect.end, indirect.discard);
1591
1592         if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
1593                 DRM_ERROR("buffer index %d (of %d max)\n",
1594                           indirect.idx, dma->buf_count - 1);
1595                 return DRM_ERR(EINVAL);
1596         }
1597
1598         buf = dma->buflist[indirect.idx];
1599         buf_priv = buf->dev_private;
1600
1601         if (buf->filp != filp) {
1602                 DRM_ERROR("process %d using buffer owned by %p\n",
1603                           DRM_CURRENTPID, buf->filp);
1604                 return DRM_ERR(EINVAL);
1605         }
1606         if (buf->pending) {
1607                 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
1608                 return DRM_ERR(EINVAL);
1609         }
1610
1611         if (indirect.start < buf->used) {
1612                 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1613                           indirect.start, buf->used);
1614                 return DRM_ERR(EINVAL);
1615         }
1616
1617         RING_SPACE_TEST_WITH_RETURN(dev_priv);
1618         VB_AGE_TEST_WITH_RETURN(dev_priv);
1619
1620         buf->used = indirect.end;
1621         buf_priv->discard = indirect.discard;
1622
1623 #if 0
1624         /* Wait for the 3D stream to idle before the indirect buffer
1625          * containing 2D acceleration commands is processed.
1626          */
1627         BEGIN_RING(2);
1628         RADEON_WAIT_UNTIL_3D_IDLE();
1629         ADVANCE_RING();
1630 #endif
1631
1632         /* Dispatch the indirect buffer full of commands from the
1633          * X server.  This is insecure and is thus only available to
1634          * privileged clients.
1635          */
1636         r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end);
1637
1638         COMMIT_RING();
1639         return 0;
1640 }
1641
1642 static int r128_getparam(DRM_IOCTL_ARGS)
1643 {
1644         DRM_DEVICE;
1645         drm_r128_private_t *dev_priv = dev->dev_private;
1646         drm_r128_getparam_t param;
1647         int value;
1648
1649         if (!dev_priv) {
1650                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1651                 return DRM_ERR(EINVAL);
1652         }
1653
1654         DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data,
1655                                  sizeof(param));
1656
1657         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1658
1659         switch (param.param) {
1660         case R128_PARAM_IRQ_NR:
1661                 value = dev->irq;
1662                 break;
1663         default:
1664                 return DRM_ERR(EINVAL);
1665         }
1666
1667         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1668                 DRM_ERROR("copy_to_user\n");
1669                 return DRM_ERR(EFAULT);
1670         }
1671
1672         return 0;
1673 }
1674
1675 void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1676 {
1677         if (dev->dev_private) {
1678                 drm_r128_private_t *dev_priv = dev->dev_private;
1679                 if (dev_priv->page_flipping) {
1680                         r128_do_cleanup_pageflip(dev);
1681                 }
1682         }
1683 }
1684
1685 void r128_driver_pretakedown(drm_device_t * dev)
1686 {
1687         r128_do_cleanup_cce(dev);
1688 }
1689
1690 drm_ioctl_desc_t r128_ioctls[] = {
1691         [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, 1, 1},
1692         [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, 1, 1},
1693         [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, 1, 1},
1694         [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, 1, 1},
1695         [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, 1, 0},
1696         [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, 1, 0},
1697         [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, 1, 0},
1698         [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, 1, 0},
1699         [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, 1, 0},
1700         [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, 1, 0},
1701         [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, 1, 0},
1702         [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, 1, 0},
1703         [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, 1, 0},
1704         [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, 1, 0},
1705         [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, 1, 0},
1706         [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, 1, 1},
1707         [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, 1, 0},
1708 };
1709
1710 int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);