sys/dev/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*-
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #include "dev/drm/radeon.h"
  34 #include "dev/drm/drmP.h"
  35 #include "dev/drm/drm.h"
  36 #include "dev/drm/radeon_drm.h"
  37 #include "dev/drm/radeon_drv.h"
  38
  39 #define RADEON_FIFO_DEBUG       0
  40
  41
  42 /* CP microcode (from ATI) */
  43 static u32 R200_cp_microcode[][2] = {
  44         { 0x21007000, 0000000000 },
  45         { 0x20007000, 0000000000 },
  46         { 0x000000ab, 0x00000004 },
  47         { 0x000000af, 0x00000004 },
  48         { 0x66544a49, 0000000000 },
  49         { 0x49494174, 0000000000 },
  50         { 0x54517d83, 0000000000 },
  51         { 0x498d8b64, 0000000000 },
  52         { 0x49494949, 0000000000 },
  53         { 0x49da493c, 0000000000 },
  54         { 0x49989898, 0000000000 },
  55         { 0xd34949d5, 0000000000 },
  56         { 0x9dc90e11, 0000000000 },
  57         { 0xce9b9b9b, 0000000000 },
  58         { 0x000f0000, 0x00000016 },
  59         { 0x352e232c, 0000000000 },
  60         { 0x00000013, 0x00000004 },
  61         { 0x000f0000, 0x00000016 },
  62         { 0x352e272c, 0000000000 },
  63         { 0x000f0001, 0x00000016 },
  64         { 0x3239362f, 0000000000 },
  65         { 0x000077ef, 0x00000002 },
  66         { 0x00061000, 0x00000002 },
  67         { 0x00000020, 0x0000001a },
  68         { 0x00004000, 0x0000001e },
  69         { 0x00061000, 0x00000002 },
  70         { 0x00000020, 0x0000001a },
  71         { 0x00004000, 0x0000001e },
  72         { 0x00061000, 0x00000002 },
  73         { 0x00000020, 0x0000001a },
  74         { 0x00004000, 0x0000001e },
  75         { 0x00000016, 0x00000004 },
  76         { 0x0003802a, 0x00000002 },
  77         { 0x040067e0, 0x00000002 },
  78         { 0x00000016, 0x00000004 },
  79         { 0x000077e0, 0x00000002 },
  80         { 0x00065000, 0x00000002 },
  81         { 0x000037e1, 0x00000002 },
  82         { 0x040067e1, 0x00000006 },
  83         { 0x000077e0, 0x00000002 },
  84         { 0x000077e1, 0x00000002 },
  85         { 0x000077e1, 0x00000006 },
  86         { 0xffffffff, 0000000000 },
  87         { 0x10000000, 0000000000 },
  88         { 0x0003802a, 0x00000002 },
  89         { 0x040067e0, 0x00000006 },
  90         { 0x00007675, 0x00000002 },
  91         { 0x00007676, 0x00000002 },
  92         { 0x00007677, 0x00000002 },
  93         { 0x00007678, 0x00000006 },
  94         { 0x0003802b, 0x00000002 },
  95         { 0x04002676, 0x00000002 },
  96         { 0x00007677, 0x00000002 },
  97         { 0x00007678, 0x00000006 },
  98         { 0x0000002e, 0x00000018 },
  99         { 0x0000002e, 0x00000018 },
 100         { 0000000000, 0x00000006 },
 101         { 0x0000002f, 0x00000018 },
 102         { 0x0000002f, 0x00000018 },
 103         { 0000000000, 0x00000006 },
 104         { 0x01605000, 0x00000002 },
 105         { 0x00065000, 0x00000002 },
 106         { 0x00098000, 0x00000002 },
 107         { 0x00061000, 0x00000002 },
 108         { 0x64c0603d, 0x00000004 },
 109         { 0x00080000, 0x00000016 },
 110         { 0000000000, 0000000000 },
 111         { 0x0400251d, 0x00000002 },
 112         { 0x00007580, 0x00000002 },
 113         { 0x00067581, 0x00000002 },
 114         { 0x04002580, 0x00000002 },
 115         { 0x00067581, 0x00000002 },
 116         { 0x00000046, 0x00000004 },
 117         { 0x00005000, 0000000000 },
 118         { 0x00061000, 0x00000002 },
 119         { 0x0000750e, 0x00000002 },
 120         { 0x00019000, 0x00000002 },
 121         { 0x00011055, 0x00000014 },
 122         { 0x00000055, 0x00000012 },
 123         { 0x0400250f, 0x00000002 },
 124         { 0x0000504a, 0x00000004 },
 125         { 0x00007565, 0x00000002 },
 126         { 0x00007566, 0x00000002 },
 127         { 0x00000051, 0x00000004 },
 128         { 0x01e655b4, 0x00000002 },
 129         { 0x4401b0dc, 0x00000002 },
 130         { 0x01c110dc, 0x00000002 },
 131         { 0x2666705d, 0x00000018 },
 132         { 0x040c2565, 0x00000002 },
 133         { 0x0000005d, 0x00000018 },
 134         { 0x04002564, 0x00000002 },
 135         { 0x00007566, 0x00000002 },
 136         { 0x00000054, 0x00000004 },
 137         { 0x00401060, 0x00000008 },
 138         { 0x00101000, 0x00000002 },
 139         { 0x000d80ff, 0x00000002 },
 140         { 0x00800063, 0x00000008 },
 141         { 0x000f9000, 0x00000002 },
 142         { 0x000e00ff, 0x00000002 },
 143         { 0000000000, 0x00000006 },
 144         { 0x00000080, 0x00000018 },
 145         { 0x00000054, 0x00000004 },
 146         { 0x00007576, 0x00000002 },
 147         { 0x00065000, 0x00000002 },
 148         { 0x00009000, 0x00000002 },
 149         { 0x00041000, 0x00000002 },
 150         { 0x0c00350e, 0x00000002 },
 151         { 0x00049000, 0x00000002 },
 152         { 0x00051000, 0x00000002 },
 153         { 0x01e785f8, 0x00000002 },
 154         { 0x00200000, 0x00000002 },
 155         { 0x00600073, 0x0000000c },
 156         { 0x00007563, 0x00000002 },
 157         { 0x006075f0, 0x00000021 },
 158         { 0x20007068, 0x00000004 },
 159         { 0x00005068, 0x00000004 },
 160         { 0x00007576, 0x00000002 },
 161         { 0x00007577, 0x00000002 },
 162         { 0x0000750e, 0x00000002 },
 163         { 0x0000750f, 0x00000002 },
 164         { 0x00a05000, 0x00000002 },
 165         { 0x00600076, 0x0000000c },
 166         { 0x006075f0, 0x00000021 },
 167         { 0x000075f8, 0x00000002 },
 168         { 0x00000076, 0x00000004 },
 169         { 0x000a750e, 0x00000002 },
 170         { 0x0020750f, 0x00000002 },
 171         { 0x00600079, 0x00000004 },
 172         { 0x00007570, 0x00000002 },
 173         { 0x00007571, 0x00000002 },
 174         { 0x00007572, 0x00000006 },
 175         { 0x00005000, 0x00000002 },
 176         { 0x00a05000, 0x00000002 },
 177         { 0x00007568, 0x00000002 },
 178         { 0x00061000, 0x00000002 },
 179         { 0x00000084, 0x0000000c },
 180         { 0x00058000, 0x00000002 },
 181         { 0x0c607562, 0x00000002 },
 182         { 0x00000086, 0x00000004 },
 183         { 0x00600085, 0x00000004 },
 184         { 0x400070dd, 0000000000 },
 185         { 0x000380dd, 0x00000002 },
 186         { 0x00000093, 0x0000001c },
 187         { 0x00065095, 0x00000018 },
 188         { 0x040025bb, 0x00000002 },
 189         { 0x00061096, 0x00000018 },
 190         { 0x040075bc, 0000000000 },
 191         { 0x000075bb, 0x00000002 },
 192         { 0x000075bc, 0000000000 },
 193         { 0x00090000, 0x00000006 },
 194         { 0x00090000, 0x00000002 },
 195         { 0x000d8002, 0x00000006 },
 196         { 0x00005000, 0x00000002 },
 197         { 0x00007821, 0x00000002 },
 198         { 0x00007800, 0000000000 },
 199         { 0x00007821, 0x00000002 },
 200         { 0x00007800, 0000000000 },
 201         { 0x01665000, 0x00000002 },
 202         { 0x000a0000, 0x00000002 },
 203         { 0x000671cc, 0x00000002 },
 204         { 0x0286f1cd, 0x00000002 },
 205         { 0x000000a3, 0x00000010 },
 206         { 0x21007000, 0000000000 },
 207         { 0x000000aa, 0x0000001c },
 208         { 0x00065000, 0x00000002 },
 209         { 0x000a0000, 0x00000002 },
 210         { 0x00061000, 0x00000002 },
 211         { 0x000b0000, 0x00000002 },
 212         { 0x38067000, 0x00000002 },
 213         { 0x000a00a6, 0x00000004 },
 214         { 0x20007000, 0000000000 },
 215         { 0x01200000, 0x00000002 },
 216         { 0x20077000, 0x00000002 },
 217         { 0x01200000, 0x00000002 },
 218         { 0x20007000, 0000000000 },
 219         { 0x00061000, 0x00000002 },
 220         { 0x0120751b, 0x00000002 },
 221         { 0x8040750a, 0x00000002 },
 222         { 0x8040750b, 0x00000002 },
 223         { 0x00110000, 0x00000002 },
 224         { 0x000380dd, 0x00000002 },
 225         { 0x000000bd, 0x0000001c },
 226         { 0x00061096, 0x00000018 },
 227         { 0x844075bd, 0x00000002 },
 228         { 0x00061095, 0x00000018 },
 229         { 0x840075bb, 0x00000002 },
 230         { 0x00061096, 0x00000018 },
 231         { 0x844075bc, 0x00000002 },
 232         { 0x000000c0, 0x00000004 },
 233         { 0x804075bd, 0x00000002 },
 234         { 0x800075bb, 0x00000002 },
 235         { 0x804075bc, 0x00000002 },
 236         { 0x00108000, 0x00000002 },
 237         { 0x01400000, 0x00000002 },
 238         { 0x006000c4, 0x0000000c },
 239         { 0x20c07000, 0x00000020 },
 240         { 0x000000c6, 0x00000012 },
 241         { 0x00800000, 0x00000006 },
 242         { 0x0080751d, 0x00000006 },
 243         { 0x000025bb, 0x00000002 },
 244         { 0x000040c0, 0x00000004 },
 245         { 0x0000775c, 0x00000002 },
 246         { 0x00a05000, 0x00000002 },
 247         { 0x00661000, 0x00000002 },
 248         { 0x0460275d, 0x00000020 },
 249         { 0x00004000, 0000000000 },
 250         { 0x00007999, 0x00000002 },
 251         { 0x00a05000, 0x00000002 },
 252         { 0x00661000, 0x00000002 },
 253         { 0x0460299b, 0x00000020 },
 254         { 0x00004000, 0000000000 },
 255         { 0x01e00830, 0x00000002 },
 256         { 0x21007000, 0000000000 },
 257         { 0x00005000, 0x00000002 },
 258         { 0x00038042, 0x00000002 },
 259         { 0x040025e0, 0x00000002 },
 260         { 0x000075e1, 0000000000 },
 261         { 0x00000001, 0000000000 },
 262         { 0x000380d9, 0x00000002 },
 263         { 0x04007394, 0000000000 },
 264         { 0000000000, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299         { 0000000000, 0000000000 },
 300 };
 301
 302
 303 static u32 radeon_cp_microcode[][2] = {
 304         { 0x21007000, 0000000000 },
 305         { 0x20007000, 0000000000 },
 306         { 0x000000b4, 0x00000004 },
 307         { 0x000000b8, 0x00000004 },
 308         { 0x6f5b4d4c, 0000000000 },
 309         { 0x4c4c427f, 0000000000 },
 310         { 0x5b568a92, 0000000000 },
 311         { 0x4ca09c6d, 0000000000 },
 312         { 0xad4c4c4c, 0000000000 },
 313         { 0x4ce1af3d, 0000000000 },
 314         { 0xd8afafaf, 0000000000 },
 315         { 0xd64c4cdc, 0000000000 },
 316         { 0x4cd10d10, 0000000000 },
 317         { 0x000f0000, 0x00000016 },
 318         { 0x362f242d, 0000000000 },
 319         { 0x00000012, 0x00000004 },
 320         { 0x000f0000, 0x00000016 },
 321         { 0x362f282d, 0000000000 },
 322         { 0x000380e7, 0x00000002 },
 323         { 0x04002c97, 0x00000002 },
 324         { 0x000f0001, 0x00000016 },
 325         { 0x333a3730, 0000000000 },
 326         { 0x000077ef, 0x00000002 },
 327         { 0x00061000, 0x00000002 },
 328         { 0x00000021, 0x0000001a },
 329         { 0x00004000, 0x0000001e },
 330         { 0x00061000, 0x00000002 },
 331         { 0x00000021, 0x0000001a },
 332         { 0x00004000, 0x0000001e },
 333         { 0x00061000, 0x00000002 },
 334         { 0x00000021, 0x0000001a },
 335         { 0x00004000, 0x0000001e },
 336         { 0x00000017, 0x00000004 },
 337         { 0x0003802b, 0x00000002 },
 338         { 0x040067e0, 0x00000002 },
 339         { 0x00000017, 0x00000004 },
 340         { 0x000077e0, 0x00000002 },
 341         { 0x00065000, 0x00000002 },
 342         { 0x000037e1, 0x00000002 },
 343         { 0x040067e1, 0x00000006 },
 344         { 0x000077e0, 0x00000002 },
 345         { 0x000077e1, 0x00000002 },
 346         { 0x000077e1, 0x00000006 },
 347         { 0xffffffff, 0000000000 },
 348         { 0x10000000, 0000000000 },
 349         { 0x0003802b, 0x00000002 },
 350         { 0x040067e0, 0x00000006 },
 351         { 0x00007675, 0x00000002 },
 352         { 0x00007676, 0x00000002 },
 353         { 0x00007677, 0x00000002 },
 354         { 0x00007678, 0x00000006 },
 355         { 0x0003802c, 0x00000002 },
 356         { 0x04002676, 0x00000002 },
 357         { 0x00007677, 0x00000002 },
 358         { 0x00007678, 0x00000006 },
 359         { 0x0000002f, 0x00000018 },
 360         { 0x0000002f, 0x00000018 },
 361         { 0000000000, 0x00000006 },
 362         { 0x00000030, 0x00000018 },
 363         { 0x00000030, 0x00000018 },
 364         { 0000000000, 0x00000006 },
 365         { 0x01605000, 0x00000002 },
 366         { 0x00065000, 0x00000002 },
 367         { 0x00098000, 0x00000002 },
 368         { 0x00061000, 0x00000002 },
 369         { 0x64c0603e, 0x00000004 },
 370         { 0x000380e6, 0x00000002 },
 371         { 0x040025c5, 0x00000002 },
 372         { 0x00080000, 0x00000016 },
 373         { 0000000000, 0000000000 },
 374         { 0x0400251d, 0x00000002 },
 375         { 0x00007580, 0x00000002 },
 376         { 0x00067581, 0x00000002 },
 377         { 0x04002580, 0x00000002 },
 378         { 0x00067581, 0x00000002 },
 379         { 0x00000049, 0x00000004 },
 380         { 0x00005000, 0000000000 },
 381         { 0x000380e6, 0x00000002 },
 382         { 0x040025c5, 0x00000002 },
 383         { 0x00061000, 0x00000002 },
 384         { 0x0000750e, 0x00000002 },
 385         { 0x00019000, 0x00000002 },
 386         { 0x00011055, 0x00000014 },
 387         { 0x00000055, 0x00000012 },
 388         { 0x0400250f, 0x00000002 },
 389         { 0x0000504f, 0x00000004 },
 390         { 0x000380e6, 0x00000002 },
 391         { 0x040025c5, 0x00000002 },
 392         { 0x00007565, 0x00000002 },
 393         { 0x00007566, 0x00000002 },
 394         { 0x00000058, 0x00000004 },
 395         { 0x000380e6, 0x00000002 },
 396         { 0x040025c5, 0x00000002 },
 397         { 0x01e655b4, 0x00000002 },
 398         { 0x4401b0e4, 0x00000002 },
 399         { 0x01c110e4, 0x00000002 },
 400         { 0x26667066, 0x00000018 },
 401         { 0x040c2565, 0x00000002 },
 402         { 0x00000066, 0x00000018 },
 403         { 0x04002564, 0x00000002 },
 404         { 0x00007566, 0x00000002 },
 405         { 0x0000005d, 0x00000004 },
 406         { 0x00401069, 0x00000008 },
 407         { 0x00101000, 0x00000002 },
 408         { 0x000d80ff, 0x00000002 },
 409         { 0x0080006c, 0x00000008 },
 410         { 0x000f9000, 0x00000002 },
 411         { 0x000e00ff, 0x00000002 },
 412         { 0000000000, 0x00000006 },
 413         { 0x0000008f, 0x00000018 },
 414         { 0x0000005b, 0x00000004 },
 415         { 0x000380e6, 0x00000002 },
 416         { 0x040025c5, 0x00000002 },
 417         { 0x00007576, 0x00000002 },
 418         { 0x00065000, 0x00000002 },
 419         { 0x00009000, 0x00000002 },
 420         { 0x00041000, 0x00000002 },
 421         { 0x0c00350e, 0x00000002 },
 422         { 0x00049000, 0x00000002 },
 423         { 0x00051000, 0x00000002 },
 424         { 0x01e785f8, 0x00000002 },
 425         { 0x00200000, 0x00000002 },
 426         { 0x0060007e, 0x0000000c },
 427         { 0x00007563, 0x00000002 },
 428         { 0x006075f0, 0x00000021 },
 429         { 0x20007073, 0x00000004 },
 430         { 0x00005073, 0x00000004 },
 431         { 0x000380e6, 0x00000002 },
 432         { 0x040025c5, 0x00000002 },
 433         { 0x00007576, 0x00000002 },
 434         { 0x00007577, 0x00000002 },
 435         { 0x0000750e, 0x00000002 },
 436         { 0x0000750f, 0x00000002 },
 437         { 0x00a05000, 0x00000002 },
 438         { 0x00600083, 0x0000000c },
 439         { 0x006075f0, 0x00000021 },
 440         { 0x000075f8, 0x00000002 },
 441         { 0x00000083, 0x00000004 },
 442         { 0x000a750e, 0x00000002 },
 443         { 0x000380e6, 0x00000002 },
 444         { 0x040025c5, 0x00000002 },
 445         { 0x0020750f, 0x00000002 },
 446         { 0x00600086, 0x00000004 },
 447         { 0x00007570, 0x00000002 },
 448         { 0x00007571, 0x00000002 },
 449         { 0x00007572, 0x00000006 },
 450         { 0x000380e6, 0x00000002 },
 451         { 0x040025c5, 0x00000002 },
 452         { 0x00005000, 0x00000002 },
 453         { 0x00a05000, 0x00000002 },
 454         { 0x00007568, 0x00000002 },
 455         { 0x00061000, 0x00000002 },
 456         { 0x00000095, 0x0000000c },
 457         { 0x00058000, 0x00000002 },
 458         { 0x0c607562, 0x00000002 },
 459         { 0x00000097, 0x00000004 },
 460         { 0x000380e6, 0x00000002 },
 461         { 0x040025c5, 0x00000002 },
 462         { 0x00600096, 0x00000004 },
 463         { 0x400070e5, 0000000000 },
 464         { 0x000380e6, 0x00000002 },
 465         { 0x040025c5, 0x00000002 },
 466         { 0x000380e5, 0x00000002 },
 467         { 0x000000a8, 0x0000001c },
 468         { 0x000650aa, 0x00000018 },
 469         { 0x040025bb, 0x00000002 },
 470         { 0x000610ab, 0x00000018 },
 471         { 0x040075bc, 0000000000 },
 472         { 0x000075bb, 0x00000002 },
 473         { 0x000075bc, 0000000000 },
 474         { 0x00090000, 0x00000006 },
 475         { 0x00090000, 0x00000002 },
 476         { 0x000d8002, 0x00000006 },
 477         { 0x00007832, 0x00000002 },
 478         { 0x00005000, 0x00000002 },
 479         { 0x000380e7, 0x00000002 },
 480         { 0x04002c97, 0x00000002 },
 481         { 0x00007820, 0x00000002 },
 482         { 0x00007821, 0x00000002 },
 483         { 0x00007800, 0000000000 },
 484         { 0x01200000, 0x00000002 },
 485         { 0x20077000, 0x00000002 },
 486         { 0x01200000, 0x00000002 },
 487         { 0x20007000, 0x00000002 },
 488         { 0x00061000, 0x00000002 },
 489         { 0x0120751b, 0x00000002 },
 490         { 0x8040750a, 0x00000002 },
 491         { 0x8040750b, 0x00000002 },
 492         { 0x00110000, 0x00000002 },
 493         { 0x000380e5, 0x00000002 },
 494         { 0x000000c6, 0x0000001c },
 495         { 0x000610ab, 0x00000018 },
 496         { 0x844075bd, 0x00000002 },
 497         { 0x000610aa, 0x00000018 },
 498         { 0x840075bb, 0x00000002 },
 499         { 0x000610ab, 0x00000018 },
 500         { 0x844075bc, 0x00000002 },
 501         { 0x000000c9, 0x00000004 },
 502         { 0x804075bd, 0x00000002 },
 503         { 0x800075bb, 0x00000002 },
 504         { 0x804075bc, 0x00000002 },
 505         { 0x00108000, 0x00000002 },
 506         { 0x01400000, 0x00000002 },
 507         { 0x006000cd, 0x0000000c },
 508         { 0x20c07000, 0x00000020 },
 509         { 0x000000cf, 0x00000012 },
 510         { 0x00800000, 0x00000006 },
 511         { 0x0080751d, 0x00000006 },
 512         { 0000000000, 0000000000 },
 513         { 0x0000775c, 0x00000002 },
 514         { 0x00a05000, 0x00000002 },
 515         { 0x00661000, 0x00000002 },
 516         { 0x0460275d, 0x00000020 },
 517         { 0x00004000, 0000000000 },
 518         { 0x01e00830, 0x00000002 },
 519         { 0x21007000, 0000000000 },
 520         { 0x6464614d, 0000000000 },
 521         { 0x69687420, 0000000000 },
 522         { 0x00000073, 0000000000 },
 523         { 0000000000, 0000000000 },
 524         { 0x00005000, 0x00000002 },
 525         { 0x000380d0, 0x00000002 },
 526         { 0x040025e0, 0x00000002 },
 527         { 0x000075e1, 0000000000 },
 528         { 0x00000001, 0000000000 },
 529         { 0x000380e0, 0x00000002 },
 530         { 0x04002394, 0x00000002 },
 531         { 0x00005000, 0000000000 },
 532         { 0000000000, 0000000000 },
 533         { 0000000000, 0000000000 },
 534         { 0x00000008, 0000000000 },
 535         { 0x00000004, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557         { 0000000000, 0000000000 },
 558         { 0000000000, 0000000000 },
 559         { 0000000000, 0000000000 },
 560 };
 561
 562
 563 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 564 {
 565         drm_radeon_private_t *dev_priv = dev->dev_private;
 566
 567         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 568         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 569 }
 570
 571 #if RADEON_FIFO_DEBUG
 572 static void radeon_status( drm_radeon_private_t *dev_priv )
 573 {
 574         printk( "%s:\n", __FUNCTION__ );
 575         printk( "RBBM_STATUS = 0x%08x\n",
 576                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 577         printk( "CP_RB_RTPR = 0x%08x\n",
 578                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 579         printk( "CP_RB_WTPR = 0x%08x\n",
 580                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 581         printk( "AIC_CNTL = 0x%08x\n",
 582                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 583         printk( "AIC_STAT = 0x%08x\n",
 584                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 585         printk( "AIC_PT_BASE = 0x%08x\n",
 586                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 587         printk( "TLB_ADDR = 0x%08x\n",
 588                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 589         printk( "TLB_DATA = 0x%08x\n",
 590                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 591 }
 592 #endif
 593
 594
 595 /* ================================================================
 596  * Engine, FIFO control
 597  */
 598
 599 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 600 {
 601         u32 tmp;
 602         int i;
 603
 604         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 605
 606         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 607         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 608         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 609
 610         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 611                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 612                        & RADEON_RB2D_DC_BUSY) ) {
 613                         return 0;
 614                 }
 615                 DRM_UDELAY( 1 );
 616         }
 617
 618 #if RADEON_FIFO_DEBUG
 619         DRM_ERROR( "failed!\n" );
 620         radeon_status( dev_priv );
 621 #endif
 622         return DRM_ERR(EBUSY);
 623 }
 624
 625 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 626                                     int entries )
 627 {
 628         int i;
 629
 630         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 631
 632         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 633                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 634                               & RADEON_RBBM_FIFOCNT_MASK );
 635                 if ( slots >= entries ) return 0;
 636                 DRM_UDELAY( 1 );
 637         }
 638
 639 #if RADEON_FIFO_DEBUG
 640         DRM_ERROR( "failed!\n" );
 641         radeon_status( dev_priv );
 642 #endif
 643         return DRM_ERR(EBUSY);
 644 }
 645
 646 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 647 {
 648         int i, ret;
 649
 650         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 651
 652         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 653         if ( ret ) return ret;
 654
 655         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 656                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 657                        & RADEON_RBBM_ACTIVE) ) {
 658                         radeon_do_pixcache_flush( dev_priv );
 659                         return 0;
 660                 }
 661                 DRM_UDELAY( 1 );
 662         }
 663
 664 #if RADEON_FIFO_DEBUG
 665         DRM_ERROR( "failed!\n" );
 666         radeon_status( dev_priv );
 667 #endif
 668         return DRM_ERR(EBUSY);
 669 }
 670
 671
 672 /* ================================================================
 673  * CP control, initialization
 674  */
 675
 676 /* Load the microcode for the CP */
 677 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 678 {
 679         int i;
 680         DRM_DEBUG( "\n" );
 681
 682         radeon_do_wait_for_idle( dev_priv );
 683
 684         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 685
 686         if (dev_priv->is_r200)
 687         {
 688                 DRM_INFO("Loading R200 Microcode\n");
 689                 for ( i = 0 ; i < 256 ; i++ )
 690                 {
 691                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 692                                       R200_cp_microcode[i][1] );
 693                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 694                                       R200_cp_microcode[i][0] );
 695                 }
 696         }
 697         else
 698         {
 699                 for ( i = 0 ; i < 256 ; i++ ) {
 700                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 701                                       radeon_cp_microcode[i][1] );
 702                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 703                                       radeon_cp_microcode[i][0] );
 704                 }
 705         }
 706 }
 707
 708 /* Flush any pending commands to the CP.  This should only be used just
 709  * prior to a wait for idle, as it informs the engine that the command
 710  * stream is ending.
 711  */
 712 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 713 {
 714         DRM_DEBUG( "\n" );
 715 #if 0
 716         u32 tmp;
 717
 718         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 719         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 720 #endif
 721 }
 722
 723 /* Wait for the CP to go idle.
 724  */
 725 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 726 {
 727         RING_LOCALS;
 728         DRM_DEBUG( "\n" );
 729
 730         BEGIN_RING( 6 );
 731
 732         RADEON_PURGE_CACHE();
 733         RADEON_PURGE_ZCACHE();
 734         RADEON_WAIT_UNTIL_IDLE();
 735
 736         ADVANCE_RING();
 737         COMMIT_RING();
 738
 739         return radeon_do_wait_for_idle( dev_priv );
 740 }
 741
 742 /* Start the Command Processor.
 743  */
 744 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 745 {
 746         RING_LOCALS;
 747         DRM_DEBUG( "\n" );
 748
 749         radeon_do_wait_for_idle( dev_priv );
 750
 751         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
 752
 753         dev_priv->cp_running = 1;
 754
 755         BEGIN_RING( 6 );
 756
 757         RADEON_PURGE_CACHE();
 758         RADEON_PURGE_ZCACHE();
 759         RADEON_WAIT_UNTIL_IDLE();
 760
 761         ADVANCE_RING();
 762         COMMIT_RING();
 763 }
 764
 765 /* Reset the Command Processor.  This will not flush any pending
 766  * commands, so you must wait for the CP command stream to complete
 767  * before calling this routine.
 768  */
 769 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 770 {
 771         u32 cur_read_ptr;
 772         DRM_DEBUG( "\n" );
 773
 774         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 775         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 776         SET_RING_HEAD( dev_priv, cur_read_ptr );
 777         dev_priv->ring.tail = cur_read_ptr;
 778 }
 779
 780 /* Stop the Command Processor.  This will not flush any pending
 781  * commands, so you must flush the command stream and wait for the CP
 782  * to go idle before calling this routine.
 783  */
 784 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
 785 {
 786         DRM_DEBUG( "\n" );
 787
 788         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
 789
 790         dev_priv->cp_running = 0;
 791 }
 792
 793 /* Reset the engine.  This will stop the CP if it is running.
 794  */
 795 static int radeon_do_engine_reset( drm_device_t *dev )
 796 {
 797         drm_radeon_private_t *dev_priv = dev->dev_private;
 798         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 799         DRM_DEBUG( "\n" );
 800
 801         radeon_do_pixcache_flush( dev_priv );
 802
 803         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
 804         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
 805
 806         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
 807                                               RADEON_FORCEON_MCLKA |
 808                                               RADEON_FORCEON_MCLKB |
 809                                               RADEON_FORCEON_YCLKA |
 810                                               RADEON_FORCEON_YCLKB |
 811                                               RADEON_FORCEON_MC |
 812                                               RADEON_FORCEON_AIC ) );
 813
 814         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
 815
 816         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
 817                                                 RADEON_SOFT_RESET_CP |
 818                                                 RADEON_SOFT_RESET_HI |
 819                                                 RADEON_SOFT_RESET_SE |
 820                                                 RADEON_SOFT_RESET_RE |
 821                                                 RADEON_SOFT_RESET_PP |
 822                                                 RADEON_SOFT_RESET_E2 |
 823                                                 RADEON_SOFT_RESET_RB ) );
 824         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 825         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
 826                                                 ~( RADEON_SOFT_RESET_CP |
 827                                                    RADEON_SOFT_RESET_HI |
 828                                                    RADEON_SOFT_RESET_SE |
 829                                                    RADEON_SOFT_RESET_RE |
 830                                                    RADEON_SOFT_RESET_PP |
 831                                                    RADEON_SOFT_RESET_E2 |
 832                                                    RADEON_SOFT_RESET_RB ) ) );
 833         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 834
 835
 836         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
 837         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
 838         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
 839
 840         /* Reset the CP ring */
 841         radeon_do_cp_reset( dev_priv );
 842
 843         /* The CP is no longer running after an engine reset */
 844         dev_priv->cp_running = 0;
 845
 846         /* Reset any pending vertex, indirect buffers */
 847         radeon_freelist_reset( dev );
 848
 849         return 0;
 850 }
 851
 852 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 853                                         drm_radeon_private_t *dev_priv )
 854 {
 855         u32 ring_start, cur_read_ptr;
 856         u32 tmp;
 857
 858         /* Initialize the memory controller */
 859         RADEON_WRITE( RADEON_MC_FB_LOCATION,
 860                       ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
 861                     | ( dev_priv->fb_location >> 16 ) );
 862
 863 #if __REALLY_HAVE_AGP
 864         if ( !dev_priv->is_pci ) {
 865                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
 866                               (((dev_priv->gart_vm_start - 1 +
 867                                  dev_priv->gart_size) & 0xffff0000) |
 868                                (dev_priv->gart_vm_start >> 16)) );
 869
 870                 ring_start = (dev_priv->cp_ring->offset
 871                               - dev->agp->base
 872                               + dev_priv->gart_vm_start);
 873        } else
 874 #endif
 875                 ring_start = (dev_priv->cp_ring->offset
 876                               - dev->sg->handle
 877                               + dev_priv->gart_vm_start);
 878
 879         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
 880
 881         /* Set the write pointer delay */
 882         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
 883
 884         /* Initialize the ring buffer's read and write pointers */
 885         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 886         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 887         SET_RING_HEAD( dev_priv, cur_read_ptr );
 888         dev_priv->ring.tail = cur_read_ptr;
 889
 890 #if __REALLY_HAVE_AGP
 891         if ( !dev_priv->is_pci ) {
 892                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 893                               dev_priv->ring_rptr->offset
 894                               - dev->agp->base
 895                               + dev_priv->gart_vm_start);
 896         } else
 897 #endif
 898         {
 899                 drm_sg_mem_t *entry = dev->sg;
 900                 unsigned long tmp_ofs, page_ofs;
 901
 902                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 903                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 904
 905                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 906                              entry->busaddr[page_ofs]);
 907                 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
 908                            (unsigned long) entry->busaddr[page_ofs],
 909                            entry->handle + tmp_ofs );
 910         }
 911
 912         /* Initialize the scratch register pointer.  This will cause
 913          * the scratch register values to be written out to memory
 914          * whenever they are updated.
 915          *
 916          * We simply put this behind the ring read pointer, this works
 917          * with PCI GART as well as (whatever kind of) AGP GART
 918          */
 919         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
 920                                          + RADEON_SCRATCH_REG_OFFSET );
 921
 922         dev_priv->scratch = ((__volatile__ u32 *)
 923                              dev_priv->ring_rptr->handle +
 924                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 925
 926         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
 927
 928         /* Writeback doesn't seem to work everywhere, test it first */
 929         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
 930         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
 931
 932         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
 933                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
 934                         break;
 935                 DRM_UDELAY( 1 );
 936         }
 937
 938         if ( tmp < dev_priv->usec_timeout ) {
 939                 dev_priv->writeback_works = 1;
 940                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
 941         } else {
 942                 dev_priv->writeback_works = 0;
 943                 DRM_DEBUG( "writeback test failed\n" );
 944         }
 945
 946         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 947         RADEON_WRITE( RADEON_LAST_FRAME_REG,
 948                       dev_priv->sarea_priv->last_frame );
 949
 950         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 951         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
 952                       dev_priv->sarea_priv->last_dispatch );
 953
 954         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 955         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
 956                       dev_priv->sarea_priv->last_clear );
 957
 958         /* Set ring buffer size */
 959 #ifdef __BIG_ENDIAN
 960         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
 961 #else
 962         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
 963 #endif
 964
 965         radeon_do_wait_for_idle( dev_priv );
 966
 967         /* Turn on bus mastering */
 968         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
 969         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
 970
 971         /* Sync everything up */
 972         RADEON_WRITE( RADEON_ISYNC_CNTL,
 973                       (RADEON_ISYNC_ANY2D_IDLE3D |
 974                        RADEON_ISYNC_ANY3D_IDLE2D |
 975                        RADEON_ISYNC_WAIT_IDLEGUI |
 976                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
 977 }
 978
 979 /* Enable or disable PCI GART on the chip */
 980 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
 981 {
 982         u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
 983
 984         if ( on ) {
 985                 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
 986
 987                 /* set PCI GART page-table base address
 988                  */
 989                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
 990
 991                 /* set address range for PCI address translate
 992                  */
 993                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
 994                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 995                                                   + dev_priv->gart_size - 1);
 996
 997                 /* Turn off AGP aperture -- is this required for PCI GART?
 998                  */
 999                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1000                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1001         } else {
1002                 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1003         }
1004 }
1005
1006 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1007 {
1008         drm_radeon_private_t *dev_priv;
1009         DRM_DEBUG( "\n" );
1010
1011         dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
1012         if ( dev_priv == NULL )
1013                 return DRM_ERR(ENOMEM);
1014
1015         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
1016
1017         dev_priv->is_pci = init->is_pci;
1018
1019         if ( dev_priv->is_pci && !dev->sg ) {
1020                 DRM_ERROR( "PCI GART memory not allocated!\n" );
1021                 dev->dev_private = (void *)dev_priv;
1022                 radeon_do_cleanup_cp(dev);
1023                 return DRM_ERR(EINVAL);
1024         }
1025
1026         dev_priv->usec_timeout = init->usec_timeout;
1027         if ( dev_priv->usec_timeout < 1 ||
1028              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1029                 DRM_DEBUG( "TIMEOUT problem!\n" );
1030                 dev->dev_private = (void *)dev_priv;
1031                 radeon_do_cleanup_cp(dev);
1032                 return DRM_ERR(EINVAL);
1033         }
1034
1035         dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1036         dev_priv->do_boxes = 0;
1037         dev_priv->cp_mode = init->cp_mode;
1038
1039         /* We don't support anything other than bus-mastering ring mode,
1040          * but the ring can be in either AGP or PCI space for the ring
1041          * read pointer.
1042          */
1043         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1044              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1045                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1046                 dev->dev_private = (void *)dev_priv;
1047                 radeon_do_cleanup_cp(dev);
1048                 return DRM_ERR(EINVAL);
1049         }
1050
1051         switch ( init->fb_bpp ) {
1052         case 16:
1053                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1054                 break;
1055         case 32:
1056         default:
1057                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1058                 break;
1059         }
1060         dev_priv->front_offset  = init->front_offset;
1061         dev_priv->front_pitch   = init->front_pitch;
1062         dev_priv->back_offset   = init->back_offset;
1063         dev_priv->back_pitch    = init->back_pitch;
1064
1065         switch ( init->depth_bpp ) {
1066         case 16:
1067                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1068                 break;
1069         case 32:
1070         default:
1071                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1072                 break;
1073         }
1074         dev_priv->depth_offset  = init->depth_offset;
1075         dev_priv->depth_pitch   = init->depth_pitch;
1076
1077         /* Hardware state for depth clears.  Remove this if/when we no
1078          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1079          * all values to prevent unwanted 3D state from slipping through
1080          * and screwing with the clear operation.
1081          */
1082         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1083                                            (dev_priv->color_fmt << 10) |
1084                                            (1<<15));
1085
1086         dev_priv->depth_clear.rb3d_zstencilcntl =
1087                 (dev_priv->depth_fmt |
1088                  RADEON_Z_TEST_ALWAYS |
1089                  RADEON_STENCIL_TEST_ALWAYS |
1090                  RADEON_STENCIL_S_FAIL_REPLACE |
1091                  RADEON_STENCIL_ZPASS_REPLACE |
1092                  RADEON_STENCIL_ZFAIL_REPLACE |
1093                  RADEON_Z_WRITE_ENABLE);
1094
1095         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1096                                          RADEON_BFACE_SOLID |
1097                                          RADEON_FFACE_SOLID |
1098                                          RADEON_FLAT_SHADE_VTX_LAST |
1099                                          RADEON_DIFFUSE_SHADE_FLAT |
1100                                          RADEON_ALPHA_SHADE_FLAT |
1101                                          RADEON_SPECULAR_SHADE_FLAT |
1102                                          RADEON_FOG_SHADE_FLAT |
1103                                          RADEON_VTX_PIX_CENTER_OGL |
1104                                          RADEON_ROUND_MODE_TRUNC |
1105                                          RADEON_ROUND_PREC_8TH_PIX);
1106
1107         DRM_GETSAREA();
1108
1109         dev_priv->fb_offset = init->fb_offset;
1110         dev_priv->mmio_offset = init->mmio_offset;
1111         dev_priv->ring_offset = init->ring_offset;
1112         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1113         dev_priv->buffers_offset = init->buffers_offset;
1114         dev_priv->gart_textures_offset = init->gart_textures_offset;
1115
1116         if(!dev_priv->sarea) {
1117                 DRM_ERROR("could not find sarea!\n");
1118                 dev->dev_private = (void *)dev_priv;
1119                 radeon_do_cleanup_cp(dev);
1120                 return DRM_ERR(EINVAL);
1121         }
1122
1123         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1124         if(!dev_priv->mmio) {
1125                 DRM_ERROR("could not find mmio region!\n");
1126                 dev->dev_private = (void *)dev_priv;
1127                 radeon_do_cleanup_cp(dev);
1128                 return DRM_ERR(EINVAL);
1129         }
1130         DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1131         if(!dev_priv->cp_ring) {
1132                 DRM_ERROR("could not find cp ring region!\n");
1133                 dev->dev_private = (void *)dev_priv;
1134                 radeon_do_cleanup_cp(dev);
1135                 return DRM_ERR(EINVAL);
1136         }
1137         DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1138         if(!dev_priv->ring_rptr) {
1139                 DRM_ERROR("could not find ring read pointer!\n");
1140                 dev->dev_private = (void *)dev_priv;
1141                 radeon_do_cleanup_cp(dev);
1142                 return DRM_ERR(EINVAL);
1143         }
1144         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1145         if(!dev_priv->buffers) {
1146                 DRM_ERROR("could not find dma buffer region!\n");
1147                 dev->dev_private = (void *)dev_priv;
1148                 radeon_do_cleanup_cp(dev);
1149                 return DRM_ERR(EINVAL);
1150         }
1151
1152         if ( init->gart_textures_offset ) {
1153                 DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
1154                 if ( !dev_priv->gart_textures ) {
1155                         DRM_ERROR("could not find GART texture region!\n");
1156                         dev->dev_private = (void *)dev_priv;
1157                         radeon_do_cleanup_cp(dev);
1158                         return DRM_ERR(EINVAL);
1159                 }
1160         }
1161
1162         dev_priv->sarea_priv =
1163                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1164                                        init->sarea_priv_offset);
1165
1166 #if __REALLY_HAVE_AGP
1167         if ( !dev_priv->is_pci ) {
1168                 DRM_IOREMAP( dev_priv->cp_ring, dev );
1169                 DRM_IOREMAP( dev_priv->ring_rptr, dev );
1170                 DRM_IOREMAP( dev_priv->buffers, dev );
1171                 if(!dev_priv->cp_ring->handle ||
1172                    !dev_priv->ring_rptr->handle ||
1173                    !dev_priv->buffers->handle) {
1174                         DRM_ERROR("could not find ioremap agp regions!\n");
1175                         dev->dev_private = (void *)dev_priv;
1176                         radeon_do_cleanup_cp(dev);
1177                         return DRM_ERR(EINVAL);
1178                 }
1179         } else
1180 #endif
1181         {
1182                 dev_priv->cp_ring->handle =
1183                         (void *)dev_priv->cp_ring->offset;
1184                 dev_priv->ring_rptr->handle =
1185                         (void *)dev_priv->ring_rptr->offset;
1186                 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1187
1188                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1189                            dev_priv->cp_ring->handle );
1190                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1191                            dev_priv->ring_rptr->handle );
1192                 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1193                            dev_priv->buffers->handle );
1194         }
1195
1196         dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1197                                 & 0xffff ) << 16;
1198
1199         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1200                                         ( ( dev_priv->front_offset
1201                                           + dev_priv->fb_location ) >> 10 ) );
1202
1203         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1204                                        ( ( dev_priv->back_offset
1205                                          + dev_priv->fb_location ) >> 10 ) );
1206
1207         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1208                                         ( ( dev_priv->depth_offset
1209                                           + dev_priv->fb_location ) >> 10 ) );
1210
1211
1212         dev_priv->gart_size = init->gart_size;
1213         dev_priv->gart_vm_start = dev_priv->fb_location
1214                                 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1215
1216 #if __REALLY_HAVE_AGP
1217         if ( !dev_priv->is_pci )
1218                 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
1219                                                 - dev->agp->base
1220                                                 + dev_priv->gart_vm_start);
1221         else
1222 #endif
1223                 dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
1224                                                 - dev->sg->handle
1225                                                 + dev_priv->gart_vm_start);
1226
1227         DRM_DEBUG( "dev_priv->gart_size %d\n",
1228                    dev_priv->gart_size );
1229         DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1230                    dev_priv->gart_vm_start );
1231         DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1232                    dev_priv->gart_buffers_offset );
1233
1234         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1235         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1236                               + init->ring_size / sizeof(u32));
1237         dev_priv->ring.size = init->ring_size;
1238         dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1239
1240         dev_priv->ring.tail_mask =
1241                 (dev_priv->ring.size / sizeof(u32)) - 1;
1242
1243         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1244
1245 #if __REALLY_HAVE_AGP
1246         if ( !dev_priv->is_pci ) {
1247                 /* Turn off PCI GART */
1248                 radeon_set_pcigart( dev_priv, 0 );
1249         } else
1250 #endif
1251         {
1252                 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1253                                             &dev_priv->bus_pci_gart)) {
1254                         DRM_ERROR( "failed to init PCI GART!\n" );
1255                         dev->dev_private = (void *)dev_priv;
1256                         radeon_do_cleanup_cp(dev);
1257                         return DRM_ERR(ENOMEM);
1258                 }
1259
1260                 /* Turn on PCI GART */
1261                 radeon_set_pcigart( dev_priv, 1 );
1262         }
1263
1264         radeon_cp_load_microcode( dev_priv );
1265         radeon_cp_init_ring_buffer( dev, dev_priv );
1266
1267         dev_priv->last_buf = 0;
1268
1269         dev->dev_private = (void *)dev_priv;
1270
1271         radeon_do_engine_reset( dev );
1272
1273         return 0;
1274 }
1275
1276 int radeon_do_cleanup_cp( drm_device_t *dev )
1277 {
1278         DRM_DEBUG( "\n" );
1279
1280 #if __HAVE_IRQ
1281         /* Make sure interrupts are disabled here because the uninstall ioctl
1282          * may not have been called from userspace and after dev_private
1283          * is freed, it's too late.
1284          */
1285         if ( dev->irq_enabled ) DRM(irq_uninstall)(dev);
1286 #endif
1287
1288         if ( dev->dev_private ) {
1289                 drm_radeon_private_t *dev_priv = dev->dev_private;
1290
1291 #if __REALLY_HAVE_AGP
1292                 if ( !dev_priv->is_pci ) {
1293                         if ( dev_priv->cp_ring != NULL )
1294                                 DRM_IOREMAPFREE( dev_priv->cp_ring, dev );
1295                         if ( dev_priv->ring_rptr != NULL )
1296                                 DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
1297                         if ( dev_priv->buffers != NULL )
1298                                 DRM_IOREMAPFREE( dev_priv->buffers, dev );
1299                 } else
1300 #endif
1301                 {
1302                         if (!DRM(ati_pcigart_cleanup)( dev,
1303                                                 dev_priv->phys_pci_gart,
1304                                                 dev_priv->bus_pci_gart ))
1305                                 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1306                 }
1307
1308                 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1309                            DRM_MEM_DRIVER );
1310                 dev->dev_private = NULL;
1311         }
1312
1313         return 0;
1314 }
1315
1316 /* This code will reinit the Radeon CP hardware after a resume from disc.
1317  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1318  * here we make sure that all Radeon hardware initialisation is re-done without
1319  * affecting running applications.
1320  *
1321  * Charl P. Botha <http://cpbotha.net>
1322  */
1323 static int radeon_do_resume_cp( drm_device_t *dev )
1324 {
1325         drm_radeon_private_t *dev_priv = dev->dev_private;
1326
1327         if ( !dev_priv ) {
1328                 DRM_ERROR( "Called with no initialization\n" );
1329                 return DRM_ERR( EINVAL );
1330         }
1331
1332         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1333
1334 #if __REALLY_HAVE_AGP
1335         if ( !dev_priv->is_pci ) {
1336                 /* Turn off PCI GART */
1337                 radeon_set_pcigart( dev_priv, 0 );
1338         } else
1339 #endif
1340         {
1341                 /* Turn on PCI GART */
1342                 radeon_set_pcigart( dev_priv, 1 );
1343         }
1344
1345         radeon_cp_load_microcode( dev_priv );
1346         radeon_cp_init_ring_buffer( dev, dev_priv );
1347
1348         radeon_do_engine_reset( dev );
1349
1350         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1351
1352         return 0;
1353 }
1354
1355
1356 int radeon_cp_init( DRM_IOCTL_ARGS )
1357 {
1358         DRM_DEVICE;
1359         drm_radeon_init_t init;
1360
1361         LOCK_TEST_WITH_RETURN( dev, filp );
1362
1363         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1364
1365         switch ( init.func ) {
1366         case RADEON_INIT_CP:
1367         case RADEON_INIT_R200_CP:
1368                 return radeon_do_init_cp( dev, &init );
1369         case RADEON_CLEANUP_CP:
1370                 return radeon_do_cleanup_cp( dev );
1371         }
1372
1373         return DRM_ERR(EINVAL);
1374 }
1375
1376 int radeon_cp_start( DRM_IOCTL_ARGS )
1377 {
1378         DRM_DEVICE;
1379         drm_radeon_private_t *dev_priv = dev->dev_private;
1380         DRM_DEBUG( "\n" );
1381
1382         LOCK_TEST_WITH_RETURN( dev, filp );
1383
1384         if ( dev_priv->cp_running ) {
1385                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1386                 return 0;
1387         }
1388         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1389                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1390                            __FUNCTION__, dev_priv->cp_mode );
1391                 return 0;
1392         }
1393
1394         radeon_do_cp_start( dev_priv );
1395
1396         return 0;
1397 }
1398
1399 /* Stop the CP.  The engine must have been idled before calling this
1400  * routine.
1401  */
1402 int radeon_cp_stop( DRM_IOCTL_ARGS )
1403 {
1404         DRM_DEVICE;
1405         drm_radeon_private_t *dev_priv = dev->dev_private;
1406         drm_radeon_cp_stop_t stop;
1407         int ret;
1408         DRM_DEBUG( "\n" );
1409
1410         LOCK_TEST_WITH_RETURN( dev, filp );
1411
1412         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1413
1414         if (!dev_priv->cp_running)
1415                 return 0;
1416
1417         /* Flush any pending CP commands.  This ensures any outstanding
1418          * commands are exectuted by the engine before we turn it off.
1419          */
1420         if ( stop.flush ) {
1421                 radeon_do_cp_flush( dev_priv );
1422         }
1423
1424         /* If we fail to make the engine go idle, we return an error
1425          * code so that the DRM ioctl wrapper can try again.
1426          */
1427         if ( stop.idle ) {
1428                 ret = radeon_do_cp_idle( dev_priv );
1429                 if ( ret ) return ret;
1430         }
1431
1432         /* Finally, we can turn off the CP.  If the engine isn't idle,
1433          * we will get some dropped triangles as they won't be fully
1434          * rendered before the CP is shut down.
1435          */
1436         radeon_do_cp_stop( dev_priv );
1437
1438         /* Reset the engine */
1439         radeon_do_engine_reset( dev );
1440
1441         return 0;
1442 }
1443
1444
1445 void radeon_do_release( drm_device_t *dev )
1446 {
1447         drm_radeon_private_t *dev_priv = dev->dev_private;
1448         int ret;
1449
1450         if (dev_priv) {
1451                 if (dev_priv->cp_running) {
1452                         /* Stop the cp */
1453                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1454                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1455 #ifdef __linux__
1456                                 schedule();
1457 #else
1458                                 tsleep(&ret, PZERO, "rdnrel", 1);
1459 #endif
1460                         }
1461                         radeon_do_cp_stop( dev_priv );
1462                         radeon_do_engine_reset( dev );
1463                 }
1464
1465                 /* Disable *all* interrupts */
1466                 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1467
1468                 /* Free memory heap structures */
1469                 radeon_mem_takedown( &(dev_priv->gart_heap) );
1470                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1471
1472                 /* deallocate kernel resources */
1473                 radeon_do_cleanup_cp( dev );
1474         }
1475 }
1476
1477 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1478  */
1479 int radeon_cp_reset( DRM_IOCTL_ARGS )
1480 {
1481         DRM_DEVICE;
1482         drm_radeon_private_t *dev_priv = dev->dev_private;
1483         DRM_DEBUG( "\n" );
1484
1485         LOCK_TEST_WITH_RETURN( dev, filp );
1486
1487         if ( !dev_priv ) {
1488                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1489                 return DRM_ERR(EINVAL);
1490         }
1491
1492         radeon_do_cp_reset( dev_priv );
1493
1494         /* The CP is no longer running after an engine reset */
1495         dev_priv->cp_running = 0;
1496
1497         return 0;
1498 }
1499
1500 int radeon_cp_idle( DRM_IOCTL_ARGS )
1501 {
1502         DRM_DEVICE;
1503         drm_radeon_private_t *dev_priv = dev->dev_private;
1504         DRM_DEBUG( "\n" );
1505
1506         LOCK_TEST_WITH_RETURN( dev, filp );
1507
1508         return radeon_do_cp_idle( dev_priv );
1509 }
1510
1511 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1512  */
1513 int radeon_cp_resume( DRM_IOCTL_ARGS )
1514 {
1515         DRM_DEVICE;
1516
1517         return radeon_do_resume_cp(dev);
1518 }
1519
1520
1521 int radeon_engine_reset( DRM_IOCTL_ARGS )
1522 {
1523         DRM_DEVICE;
1524         DRM_DEBUG( "\n" );
1525
1526         LOCK_TEST_WITH_RETURN( dev, filp );
1527
1528         return radeon_do_engine_reset( dev );
1529 }
1530
1531
1532 /* ================================================================
1533  * Fullscreen mode
1534  */
1535
1536 /* KW: Deprecated to say the least:
1537  */
1538 int radeon_fullscreen( DRM_IOCTL_ARGS )
1539 {
1540         return 0;
1541 }
1542
1543
1544 /* ================================================================
1545  * Freelist management
1546  */
1547
1548 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1549  *   bufs until freelist code is used.  Note this hides a problem with
1550  *   the scratch register * (used to keep track of last buffer
1551  *   completed) being written to before * the last buffer has actually
1552  *   completed rendering.
1553  *
1554  * KW:  It's also a good way to find free buffers quickly.
1555  *
1556  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1557  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1558  * we essentially have to do this, else old clients will break.
1559  *
1560  * However, it does leave open a potential deadlock where all the
1561  * buffers are held by other clients, which can't release them because
1562  * they can't get the lock.
1563  */
1564
1565 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1566 {
1567         drm_device_dma_t *dma = dev->dma;
1568         drm_radeon_private_t *dev_priv = dev->dev_private;
1569         drm_radeon_buf_priv_t *buf_priv;
1570         drm_buf_t *buf;
1571         int i, t;
1572         int start;
1573
1574         if ( ++dev_priv->last_buf >= dma->buf_count )
1575                 dev_priv->last_buf = 0;
1576
1577         start = dev_priv->last_buf;
1578
1579         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1580                 u32 done_age = GET_SCRATCH( 1 );
1581                 DRM_DEBUG("done_age = %d\n",done_age);
1582                 for ( i = start ; i < dma->buf_count ; i++ ) {
1583                         buf = dma->buflist[i];
1584                         buf_priv = buf->dev_private;
1585                         if ( buf->filp == 0 || (buf->pending &&
1586                                                buf_priv->age <= done_age) ) {
1587                                 dev_priv->stats.requested_bufs++;
1588                                 buf->pending = 0;
1589                                 return buf;
1590                         }
1591                         start = 0;
1592                 }
1593
1594                 if (t) {
1595                         DRM_UDELAY( 1 );
1596                         dev_priv->stats.freelist_loops++;
1597                 }
1598         }
1599
1600         DRM_DEBUG( "returning NULL!\n" );
1601         return NULL;
1602 }
1603 #if 0
1604 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1605 {
1606         drm_device_dma_t *dma = dev->dma;
1607         drm_radeon_private_t *dev_priv = dev->dev_private;
1608         drm_radeon_buf_priv_t *buf_priv;
1609         drm_buf_t *buf;
1610         int i, t;
1611         int start;
1612         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1613
1614         if ( ++dev_priv->last_buf >= dma->buf_count )
1615                 dev_priv->last_buf = 0;
1616
1617         start = dev_priv->last_buf;
1618         dev_priv->stats.freelist_loops++;
1619
1620         for ( t = 0 ; t < 2 ; t++ ) {
1621                 for ( i = start ; i < dma->buf_count ; i++ ) {
1622                         buf = dma->buflist[i];
1623                         buf_priv = buf->dev_private;
1624                         if ( buf->filp == 0 || (buf->pending &&
1625                                                buf_priv->age <= done_age) ) {
1626                                 dev_priv->stats.requested_bufs++;
1627                                 buf->pending = 0;
1628                                 return buf;
1629                         }
1630                 }
1631                 start = 0;
1632         }
1633
1634         return NULL;
1635 }
1636 #endif
1637
1638 void radeon_freelist_reset( drm_device_t *dev )
1639 {
1640         drm_device_dma_t *dma = dev->dma;
1641         drm_radeon_private_t *dev_priv = dev->dev_private;
1642         int i;
1643
1644         dev_priv->last_buf = 0;
1645         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1646                 drm_buf_t *buf = dma->buflist[i];
1647                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1648                 buf_priv->age = 0;
1649         }
1650 }
1651
1652
1653 /* ================================================================
1654  * CP command submission
1655  */
1656
1657 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1658 {
1659         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1660         int i;
1661         u32 last_head = GET_RING_HEAD( dev_priv );
1662
1663         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1664                 u32 head = GET_RING_HEAD( dev_priv );
1665
1666                 ring->space = (head - ring->tail) * sizeof(u32);
1667                 if ( ring->space <= 0 )
1668                         ring->space += ring->size;
1669                 if ( ring->space > n )
1670                         return 0;
1671
1672                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1673
1674                 if (head != last_head)
1675                         i = 0;
1676                 last_head = head;
1677
1678                 DRM_UDELAY( 1 );
1679         }
1680
1681         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1682 #if RADEON_FIFO_DEBUG
1683         radeon_status( dev_priv );
1684         DRM_ERROR( "failed!\n" );
1685 #endif
1686         return DRM_ERR(EBUSY);
1687 }
1688
1689 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1690 {
1691         int i;
1692         drm_buf_t *buf;
1693
1694         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1695                 buf = radeon_freelist_get( dev );
1696                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1697
1698                 buf->filp = filp;
1699
1700                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1701                                    sizeof(buf->idx) ) )
1702                         return DRM_ERR(EFAULT);
1703                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1704                                    sizeof(buf->total) ) )
1705                         return DRM_ERR(EFAULT);
1706
1707                 d->granted_count++;
1708         }
1709         return 0;
1710 }
1711
1712 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1713 {
1714         DRM_DEVICE;
1715         drm_device_dma_t *dma = dev->dma;
1716         int ret = 0;
1717         drm_dma_t d;
1718
1719         LOCK_TEST_WITH_RETURN( dev, filp );
1720
1721         DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1722
1723         /* Please don't send us buffers.
1724          */
1725         if ( d.send_count != 0 ) {
1726                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1727                            DRM_CURRENTPID, d.send_count );
1728                 return DRM_ERR(EINVAL);
1729         }
1730
1731         /* We'll send you buffers.
1732          */
1733         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1734                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1735                            DRM_CURRENTPID, d.request_count, dma->buf_count );
1736                 return DRM_ERR(EINVAL);
1737         }
1738
1739         d.granted_count = 0;
1740
1741         if ( d.request_count ) {
1742                 ret = radeon_cp_get_buffers( filp, dev, &d );
1743         }
1744
1745         DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1746
1747         return ret;
1748 }