sys/dev/drm/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*-
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #include "dev/drm/drmP.h"
  34 #include "dev/drm/drm.h"
  35 #include "dev/drm/radeon_drm.h"
  36 #include "dev/drm/radeon_drv.h"
  37
  38 #define RADEON_FIFO_DEBUG       0
  39
  40 static int radeon_do_cleanup_cp(drm_device_t * dev);
  41
  42 /* CP microcode (from ATI) */
  43 static u32 R200_cp_microcode[][2] = {
  44         {0x21007000, 0000000000},
  45         {0x20007000, 0000000000},
  46         {0x000000ab, 0x00000004},
  47         {0x000000af, 0x00000004},
  48         {0x66544a49, 0000000000},
  49         {0x49494174, 0000000000},
  50         {0x54517d83, 0000000000},
  51         {0x498d8b64, 0000000000},
  52         {0x49494949, 0000000000},
  53         {0x49da493c, 0000000000},
  54         {0x49989898, 0000000000},
  55         {0xd34949d5, 0000000000},
  56         {0x9dc90e11, 0000000000},
  57         {0xce9b9b9b, 0000000000},
  58         {0x000f0000, 0x00000016},
  59         {0x352e232c, 0000000000},
  60         {0x00000013, 0x00000004},
  61         {0x000f0000, 0x00000016},
  62         {0x352e272c, 0000000000},
  63         {0x000f0001, 0x00000016},
  64         {0x3239362f, 0000000000},
  65         {0x000077ef, 0x00000002},
  66         {0x00061000, 0x00000002},
  67         {0x00000020, 0x0000001a},
  68         {0x00004000, 0x0000001e},
  69         {0x00061000, 0x00000002},
  70         {0x00000020, 0x0000001a},
  71         {0x00004000, 0x0000001e},
  72         {0x00061000, 0x00000002},
  73         {0x00000020, 0x0000001a},
  74         {0x00004000, 0x0000001e},
  75         {0x00000016, 0x00000004},
  76         {0x0003802a, 0x00000002},
  77         {0x040067e0, 0x00000002},
  78         {0x00000016, 0x00000004},
  79         {0x000077e0, 0x00000002},
  80         {0x00065000, 0x00000002},
  81         {0x000037e1, 0x00000002},
  82         {0x040067e1, 0x00000006},
  83         {0x000077e0, 0x00000002},
  84         {0x000077e1, 0x00000002},
  85         {0x000077e1, 0x00000006},
  86         {0xffffffff, 0000000000},
  87         {0x10000000, 0000000000},
  88         {0x0003802a, 0x00000002},
  89         {0x040067e0, 0x00000006},
  90         {0x00007675, 0x00000002},
  91         {0x00007676, 0x00000002},
  92         {0x00007677, 0x00000002},
  93         {0x00007678, 0x00000006},
  94         {0x0003802b, 0x00000002},
  95         {0x04002676, 0x00000002},
  96         {0x00007677, 0x00000002},
  97         {0x00007678, 0x00000006},
  98         {0x0000002e, 0x00000018},
  99         {0x0000002e, 0x00000018},
 100         {0000000000, 0x00000006},
 101         {0x0000002f, 0x00000018},
 102         {0x0000002f, 0x00000018},
 103         {0000000000, 0x00000006},
 104         {0x01605000, 0x00000002},
 105         {0x00065000, 0x00000002},
 106         {0x00098000, 0x00000002},
 107         {0x00061000, 0x00000002},
 108         {0x64c0603d, 0x00000004},
 109         {0x00080000, 0x00000016},
 110         {0000000000, 0000000000},
 111         {0x0400251d, 0x00000002},
 112         {0x00007580, 0x00000002},
 113         {0x00067581, 0x00000002},
 114         {0x04002580, 0x00000002},
 115         {0x00067581, 0x00000002},
 116         {0x00000046, 0x00000004},
 117         {0x00005000, 0000000000},
 118         {0x00061000, 0x00000002},
 119         {0x0000750e, 0x00000002},
 120         {0x00019000, 0x00000002},
 121         {0x00011055, 0x00000014},
 122         {0x00000055, 0x00000012},
 123         {0x0400250f, 0x00000002},
 124         {0x0000504a, 0x00000004},
 125         {0x00007565, 0x00000002},
 126         {0x00007566, 0x00000002},
 127         {0x00000051, 0x00000004},
 128         {0x01e655b4, 0x00000002},
 129         {0x4401b0dc, 0x00000002},
 130         {0x01c110dc, 0x00000002},
 131         {0x2666705d, 0x00000018},
 132         {0x040c2565, 0x00000002},
 133         {0x0000005d, 0x00000018},
 134         {0x04002564, 0x00000002},
 135         {0x00007566, 0x00000002},
 136         {0x00000054, 0x00000004},
 137         {0x00401060, 0x00000008},
 138         {0x00101000, 0x00000002},
 139         {0x000d80ff, 0x00000002},
 140         {0x00800063, 0x00000008},
 141         {0x000f9000, 0x00000002},
 142         {0x000e00ff, 0x00000002},
 143         {0000000000, 0x00000006},
 144         {0x00000080, 0x00000018},
 145         {0x00000054, 0x00000004},
 146         {0x00007576, 0x00000002},
 147         {0x00065000, 0x00000002},
 148         {0x00009000, 0x00000002},
 149         {0x00041000, 0x00000002},
 150         {0x0c00350e, 0x00000002},
 151         {0x00049000, 0x00000002},
 152         {0x00051000, 0x00000002},
 153         {0x01e785f8, 0x00000002},
 154         {0x00200000, 0x00000002},
 155         {0x00600073, 0x0000000c},
 156         {0x00007563, 0x00000002},
 157         {0x006075f0, 0x00000021},
 158         {0x20007068, 0x00000004},
 159         {0x00005068, 0x00000004},
 160         {0x00007576, 0x00000002},
 161         {0x00007577, 0x00000002},
 162         {0x0000750e, 0x00000002},
 163         {0x0000750f, 0x00000002},
 164         {0x00a05000, 0x00000002},
 165         {0x00600076, 0x0000000c},
 166         {0x006075f0, 0x00000021},
 167         {0x000075f8, 0x00000002},
 168         {0x00000076, 0x00000004},
 169         {0x000a750e, 0x00000002},
 170         {0x0020750f, 0x00000002},
 171         {0x00600079, 0x00000004},
 172         {0x00007570, 0x00000002},
 173         {0x00007571, 0x00000002},
 174         {0x00007572, 0x00000006},
 175         {0x00005000, 0x00000002},
 176         {0x00a05000, 0x00000002},
 177         {0x00007568, 0x00000002},
 178         {0x00061000, 0x00000002},
 179         {0x00000084, 0x0000000c},
 180         {0x00058000, 0x00000002},
 181         {0x0c607562, 0x00000002},
 182         {0x00000086, 0x00000004},
 183         {0x00600085, 0x00000004},
 184         {0x400070dd, 0000000000},
 185         {0x000380dd, 0x00000002},
 186         {0x00000093, 0x0000001c},
 187         {0x00065095, 0x00000018},
 188         {0x040025bb, 0x00000002},
 189         {0x00061096, 0x00000018},
 190         {0x040075bc, 0000000000},
 191         {0x000075bb, 0x00000002},
 192         {0x000075bc, 0000000000},
 193         {0x00090000, 0x00000006},
 194         {0x00090000, 0x00000002},
 195         {0x000d8002, 0x00000006},
 196         {0x00005000, 0x00000002},
 197         {0x00007821, 0x00000002},
 198         {0x00007800, 0000000000},
 199         {0x00007821, 0x00000002},
 200         {0x00007800, 0000000000},
 201         {0x01665000, 0x00000002},
 202         {0x000a0000, 0x00000002},
 203         {0x000671cc, 0x00000002},
 204         {0x0286f1cd, 0x00000002},
 205         {0x000000a3, 0x00000010},
 206         {0x21007000, 0000000000},
 207         {0x000000aa, 0x0000001c},
 208         {0x00065000, 0x00000002},
 209         {0x000a0000, 0x00000002},
 210         {0x00061000, 0x00000002},
 211         {0x000b0000, 0x00000002},
 212         {0x38067000, 0x00000002},
 213         {0x000a00a6, 0x00000004},
 214         {0x20007000, 0000000000},
 215         {0x01200000, 0x00000002},
 216         {0x20077000, 0x00000002},
 217         {0x01200000, 0x00000002},
 218         {0x20007000, 0000000000},
 219         {0x00061000, 0x00000002},
 220         {0x0120751b, 0x00000002},
 221         {0x8040750a, 0x00000002},
 222         {0x8040750b, 0x00000002},
 223         {0x00110000, 0x00000002},
 224         {0x000380dd, 0x00000002},
 225         {0x000000bd, 0x0000001c},
 226         {0x00061096, 0x00000018},
 227         {0x844075bd, 0x00000002},
 228         {0x00061095, 0x00000018},
 229         {0x840075bb, 0x00000002},
 230         {0x00061096, 0x00000018},
 231         {0x844075bc, 0x00000002},
 232         {0x000000c0, 0x00000004},
 233         {0x804075bd, 0x00000002},
 234         {0x800075bb, 0x00000002},
 235         {0x804075bc, 0x00000002},
 236         {0x00108000, 0x00000002},
 237         {0x01400000, 0x00000002},
 238         {0x006000c4, 0x0000000c},
 239         {0x20c07000, 0x00000020},
 240         {0x000000c6, 0x00000012},
 241         {0x00800000, 0x00000006},
 242         {0x0080751d, 0x00000006},
 243         {0x000025bb, 0x00000002},
 244         {0x000040c0, 0x00000004},
 245         {0x0000775c, 0x00000002},
 246         {0x00a05000, 0x00000002},
 247         {0x00661000, 0x00000002},
 248         {0x0460275d, 0x00000020},
 249         {0x00004000, 0000000000},
 250         {0x00007999, 0x00000002},
 251         {0x00a05000, 0x00000002},
 252         {0x00661000, 0x00000002},
 253         {0x0460299b, 0x00000020},
 254         {0x00004000, 0000000000},
 255         {0x01e00830, 0x00000002},
 256         {0x21007000, 0000000000},
 257         {0x00005000, 0x00000002},
 258         {0x00038042, 0x00000002},
 259         {0x040025e0, 0x00000002},
 260         {0x000075e1, 0000000000},
 261         {0x00000001, 0000000000},
 262         {0x000380d9, 0x00000002},
 263         {0x04007394, 0000000000},
 264         {0000000000, 0000000000},
 265         {0000000000, 0000000000},
 266         {0000000000, 0000000000},
 267         {0000000000, 0000000000},
 268         {0000000000, 0000000000},
 269         {0000000000, 0000000000},
 270         {0000000000, 0000000000},
 271         {0000000000, 0000000000},
 272         {0000000000, 0000000000},
 273         {0000000000, 0000000000},
 274         {0000000000, 0000000000},
 275         {0000000000, 0000000000},
 276         {0000000000, 0000000000},
 277         {0000000000, 0000000000},
 278         {0000000000, 0000000000},
 279         {0000000000, 0000000000},
 280         {0000000000, 0000000000},
 281         {0000000000, 0000000000},
 282         {0000000000, 0000000000},
 283         {0000000000, 0000000000},
 284         {0000000000, 0000000000},
 285         {0000000000, 0000000000},
 286         {0000000000, 0000000000},
 287         {0000000000, 0000000000},
 288         {0000000000, 0000000000},
 289         {0000000000, 0000000000},
 290         {0000000000, 0000000000},
 291         {0000000000, 0000000000},
 292         {0000000000, 0000000000},
 293         {0000000000, 0000000000},
 294         {0000000000, 0000000000},
 295         {0000000000, 0000000000},
 296         {0000000000, 0000000000},
 297         {0000000000, 0000000000},
 298         {0000000000, 0000000000},
 299         {0000000000, 0000000000},
 300 };
 301
 302 static u32 radeon_cp_microcode[][2] = {
 303         {0x21007000, 0000000000},
 304         {0x20007000, 0000000000},
 305         {0x000000b4, 0x00000004},
 306         {0x000000b8, 0x00000004},
 307         {0x6f5b4d4c, 0000000000},
 308         {0x4c4c427f, 0000000000},
 309         {0x5b568a92, 0000000000},
 310         {0x4ca09c6d, 0000000000},
 311         {0xad4c4c4c, 0000000000},
 312         {0x4ce1af3d, 0000000000},
 313         {0xd8afafaf, 0000000000},
 314         {0xd64c4cdc, 0000000000},
 315         {0x4cd10d10, 0000000000},
 316         {0x000f0000, 0x00000016},
 317         {0x362f242d, 0000000000},
 318         {0x00000012, 0x00000004},
 319         {0x000f0000, 0x00000016},
 320         {0x362f282d, 0000000000},
 321         {0x000380e7, 0x00000002},
 322         {0x04002c97, 0x00000002},
 323         {0x000f0001, 0x00000016},
 324         {0x333a3730, 0000000000},
 325         {0x000077ef, 0x00000002},
 326         {0x00061000, 0x00000002},
 327         {0x00000021, 0x0000001a},
 328         {0x00004000, 0x0000001e},
 329         {0x00061000, 0x00000002},
 330         {0x00000021, 0x0000001a},
 331         {0x00004000, 0x0000001e},
 332         {0x00061000, 0x00000002},
 333         {0x00000021, 0x0000001a},
 334         {0x00004000, 0x0000001e},
 335         {0x00000017, 0x00000004},
 336         {0x0003802b, 0x00000002},
 337         {0x040067e0, 0x00000002},
 338         {0x00000017, 0x00000004},
 339         {0x000077e0, 0x00000002},
 340         {0x00065000, 0x00000002},
 341         {0x000037e1, 0x00000002},
 342         {0x040067e1, 0x00000006},
 343         {0x000077e0, 0x00000002},
 344         {0x000077e1, 0x00000002},
 345         {0x000077e1, 0x00000006},
 346         {0xffffffff, 0000000000},
 347         {0x10000000, 0000000000},
 348         {0x0003802b, 0x00000002},
 349         {0x040067e0, 0x00000006},
 350         {0x00007675, 0x00000002},
 351         {0x00007676, 0x00000002},
 352         {0x00007677, 0x00000002},
 353         {0x00007678, 0x00000006},
 354         {0x0003802c, 0x00000002},
 355         {0x04002676, 0x00000002},
 356         {0x00007677, 0x00000002},
 357         {0x00007678, 0x00000006},
 358         {0x0000002f, 0x00000018},
 359         {0x0000002f, 0x00000018},
 360         {0000000000, 0x00000006},
 361         {0x00000030, 0x00000018},
 362         {0x00000030, 0x00000018},
 363         {0000000000, 0x00000006},
 364         {0x01605000, 0x00000002},
 365         {0x00065000, 0x00000002},
 366         {0x00098000, 0x00000002},
 367         {0x00061000, 0x00000002},
 368         {0x64c0603e, 0x00000004},
 369         {0x000380e6, 0x00000002},
 370         {0x040025c5, 0x00000002},
 371         {0x00080000, 0x00000016},
 372         {0000000000, 0000000000},
 373         {0x0400251d, 0x00000002},
 374         {0x00007580, 0x00000002},
 375         {0x00067581, 0x00000002},
 376         {0x04002580, 0x00000002},
 377         {0x00067581, 0x00000002},
 378         {0x00000049, 0x00000004},
 379         {0x00005000, 0000000000},
 380         {0x000380e6, 0x00000002},
 381         {0x040025c5, 0x00000002},
 382         {0x00061000, 0x00000002},
 383         {0x0000750e, 0x00000002},
 384         {0x00019000, 0x00000002},
 385         {0x00011055, 0x00000014},
 386         {0x00000055, 0x00000012},
 387         {0x0400250f, 0x00000002},
 388         {0x0000504f, 0x00000004},
 389         {0x000380e6, 0x00000002},
 390         {0x040025c5, 0x00000002},
 391         {0x00007565, 0x00000002},
 392         {0x00007566, 0x00000002},
 393         {0x00000058, 0x00000004},
 394         {0x000380e6, 0x00000002},
 395         {0x040025c5, 0x00000002},
 396         {0x01e655b4, 0x00000002},
 397         {0x4401b0e4, 0x00000002},
 398         {0x01c110e4, 0x00000002},
 399         {0x26667066, 0x00000018},
 400         {0x040c2565, 0x00000002},
 401         {0x00000066, 0x00000018},
 402         {0x04002564, 0x00000002},
 403         {0x00007566, 0x00000002},
 404         {0x0000005d, 0x00000004},
 405         {0x00401069, 0x00000008},
 406         {0x00101000, 0x00000002},
 407         {0x000d80ff, 0x00000002},
 408         {0x0080006c, 0x00000008},
 409         {0x000f9000, 0x00000002},
 410         {0x000e00ff, 0x00000002},
 411         {0000000000, 0x00000006},
 412         {0x0000008f, 0x00000018},
 413         {0x0000005b, 0x00000004},
 414         {0x000380e6, 0x00000002},
 415         {0x040025c5, 0x00000002},
 416         {0x00007576, 0x00000002},
 417         {0x00065000, 0x00000002},
 418         {0x00009000, 0x00000002},
 419         {0x00041000, 0x00000002},
 420         {0x0c00350e, 0x00000002},
 421         {0x00049000, 0x00000002},
 422         {0x00051000, 0x00000002},
 423         {0x01e785f8, 0x00000002},
 424         {0x00200000, 0x00000002},
 425         {0x0060007e, 0x0000000c},
 426         {0x00007563, 0x00000002},
 427         {0x006075f0, 0x00000021},
 428         {0x20007073, 0x00000004},
 429         {0x00005073, 0x00000004},
 430         {0x000380e6, 0x00000002},
 431         {0x040025c5, 0x00000002},
 432         {0x00007576, 0x00000002},
 433         {0x00007577, 0x00000002},
 434         {0x0000750e, 0x00000002},
 435         {0x0000750f, 0x00000002},
 436         {0x00a05000, 0x00000002},
 437         {0x00600083, 0x0000000c},
 438         {0x006075f0, 0x00000021},
 439         {0x000075f8, 0x00000002},
 440         {0x00000083, 0x00000004},
 441         {0x000a750e, 0x00000002},
 442         {0x000380e6, 0x00000002},
 443         {0x040025c5, 0x00000002},
 444         {0x0020750f, 0x00000002},
 445         {0x00600086, 0x00000004},
 446         {0x00007570, 0x00000002},
 447         {0x00007571, 0x00000002},
 448         {0x00007572, 0x00000006},
 449         {0x000380e6, 0x00000002},
 450         {0x040025c5, 0x00000002},
 451         {0x00005000, 0x00000002},
 452         {0x00a05000, 0x00000002},
 453         {0x00007568, 0x00000002},
 454         {0x00061000, 0x00000002},
 455         {0x00000095, 0x0000000c},
 456         {0x00058000, 0x00000002},
 457         {0x0c607562, 0x00000002},
 458         {0x00000097, 0x00000004},
 459         {0x000380e6, 0x00000002},
 460         {0x040025c5, 0x00000002},
 461         {0x00600096, 0x00000004},
 462         {0x400070e5, 0000000000},
 463         {0x000380e6, 0x00000002},
 464         {0x040025c5, 0x00000002},
 465         {0x000380e5, 0x00000002},
 466         {0x000000a8, 0x0000001c},
 467         {0x000650aa, 0x00000018},
 468         {0x040025bb, 0x00000002},
 469         {0x000610ab, 0x00000018},
 470         {0x040075bc, 0000000000},
 471         {0x000075bb, 0x00000002},
 472         {0x000075bc, 0000000000},
 473         {0x00090000, 0x00000006},
 474         {0x00090000, 0x00000002},
 475         {0x000d8002, 0x00000006},
 476         {0x00007832, 0x00000002},
 477         {0x00005000, 0x00000002},
 478         {0x000380e7, 0x00000002},
 479         {0x04002c97, 0x00000002},
 480         {0x00007820, 0x00000002},
 481         {0x00007821, 0x00000002},
 482         {0x00007800, 0000000000},
 483         {0x01200000, 0x00000002},
 484         {0x20077000, 0x00000002},
 485         {0x01200000, 0x00000002},
 486         {0x20007000, 0x00000002},
 487         {0x00061000, 0x00000002},
 488         {0x0120751b, 0x00000002},
 489         {0x8040750a, 0x00000002},
 490         {0x8040750b, 0x00000002},
 491         {0x00110000, 0x00000002},
 492         {0x000380e5, 0x00000002},
 493         {0x000000c6, 0x0000001c},
 494         {0x000610ab, 0x00000018},
 495         {0x844075bd, 0x00000002},
 496         {0x000610aa, 0x00000018},
 497         {0x840075bb, 0x00000002},
 498         {0x000610ab, 0x00000018},
 499         {0x844075bc, 0x00000002},
 500         {0x000000c9, 0x00000004},
 501         {0x804075bd, 0x00000002},
 502         {0x800075bb, 0x00000002},
 503         {0x804075bc, 0x00000002},
 504         {0x00108000, 0x00000002},
 505         {0x01400000, 0x00000002},
 506         {0x006000cd, 0x0000000c},
 507         {0x20c07000, 0x00000020},
 508         {0x000000cf, 0x00000012},
 509         {0x00800000, 0x00000006},
 510         {0x0080751d, 0x00000006},
 511         {0000000000, 0000000000},
 512         {0x0000775c, 0x00000002},
 513         {0x00a05000, 0x00000002},
 514         {0x00661000, 0x00000002},
 515         {0x0460275d, 0x00000020},
 516         {0x00004000, 0000000000},
 517         {0x01e00830, 0x00000002},
 518         {0x21007000, 0000000000},
 519         {0x6464614d, 0000000000},
 520         {0x69687420, 0000000000},
 521         {0x00000073, 0000000000},
 522         {0000000000, 0000000000},
 523         {0x00005000, 0x00000002},
 524         {0x000380d0, 0x00000002},
 525         {0x040025e0, 0x00000002},
 526         {0x000075e1, 0000000000},
 527         {0x00000001, 0000000000},
 528         {0x000380e0, 0x00000002},
 529         {0x04002394, 0x00000002},
 530         {0x00005000, 0000000000},
 531         {0000000000, 0000000000},
 532         {0000000000, 0000000000},
 533         {0x00000008, 0000000000},
 534         {0x00000004, 0000000000},
 535         {0000000000, 0000000000},
 536         {0000000000, 0000000000},
 537         {0000000000, 0000000000},
 538         {0000000000, 0000000000},
 539         {0000000000, 0000000000},
 540         {0000000000, 0000000000},
 541         {0000000000, 0000000000},
 542         {0000000000, 0000000000},
 543         {0000000000, 0000000000},
 544         {0000000000, 0000000000},
 545         {0000000000, 0000000000},
 546         {0000000000, 0000000000},
 547         {0000000000, 0000000000},
 548         {0000000000, 0000000000},
 549         {0000000000, 0000000000},
 550         {0000000000, 0000000000},
 551         {0000000000, 0000000000},
 552         {0000000000, 0000000000},
 553         {0000000000, 0000000000},
 554         {0000000000, 0000000000},
 555         {0000000000, 0000000000},
 556         {0000000000, 0000000000},
 557         {0000000000, 0000000000},
 558         {0000000000, 0000000000},
 559 };
 560
 561 static u32 R300_cp_microcode[][2] = {
 562         { 0x4200e000, 0000000000 },
 563         { 0x4000e000, 0000000000 },
 564         { 0x000000af, 0x00000008 },
 565         { 0x000000b3, 0x00000008 },
 566         { 0x6c5a504f, 0000000000 },
 567         { 0x4f4f497a, 0000000000 },
 568         { 0x5a578288, 0000000000 },
 569         { 0x4f91906a, 0000000000 },
 570         { 0x4f4f4f4f, 0000000000 },
 571         { 0x4fe24f44, 0000000000 },
 572         { 0x4f9c9c9c, 0000000000 },
 573         { 0xdc4f4fde, 0000000000 },
 574         { 0xa1cd4f4f, 0000000000 },
 575         { 0xd29d9d9d, 0000000000 },
 576         { 0x4f0f9fd7, 0000000000 },
 577         { 0x000ca000, 0x00000004 },
 578         { 0x000d0012, 0x00000038 },
 579         { 0x0000e8b4, 0x00000004 },
 580         { 0x000d0014, 0x00000038 },
 581         { 0x0000e8b6, 0x00000004 },
 582         { 0x000d0016, 0x00000038 },
 583         { 0x0000e854, 0x00000004 },
 584         { 0x000d0018, 0x00000038 },
 585         { 0x0000e855, 0x00000004 },
 586         { 0x000d001a, 0x00000038 },
 587         { 0x0000e856, 0x00000004 },
 588         { 0x000d001c, 0x00000038 },
 589         { 0x0000e857, 0x00000004 },
 590         { 0x000d001e, 0x00000038 },
 591         { 0x0000e824, 0x00000004 },
 592         { 0x000d0020, 0x00000038 },
 593         { 0x0000e825, 0x00000004 },
 594         { 0x000d0022, 0x00000038 },
 595         { 0x0000e830, 0x00000004 },
 596         { 0x000d0024, 0x00000038 },
 597         { 0x0000f0c0, 0x00000004 },
 598         { 0x000d0026, 0x00000038 },
 599         { 0x0000f0c1, 0x00000004 },
 600         { 0x000d0028, 0x00000038 },
 601         { 0x0000f041, 0x00000004 },
 602         { 0x000d002a, 0x00000038 },
 603         { 0x0000f184, 0x00000004 },
 604         { 0x000d002c, 0x00000038 },
 605         { 0x0000f185, 0x00000004 },
 606         { 0x000d002e, 0x00000038 },
 607         { 0x0000f186, 0x00000004 },
 608         { 0x000d0030, 0x00000038 },
 609         { 0x0000f187, 0x00000004 },
 610         { 0x000d0032, 0x00000038 },
 611         { 0x0000f180, 0x00000004 },
 612         { 0x000d0034, 0x00000038 },
 613         { 0x0000f393, 0x00000004 },
 614         { 0x000d0036, 0x00000038 },
 615         { 0x0000f38a, 0x00000004 },
 616         { 0x000d0038, 0x00000038 },
 617         { 0x0000f38e, 0x00000004 },
 618         { 0x0000e821, 0x00000004 },
 619         { 0x0140a000, 0x00000004 },
 620         { 0x00000043, 0x00000018 },
 621         { 0x00cce800, 0x00000004 },
 622         { 0x001b0001, 0x00000004 },
 623         { 0x08004800, 0x00000004 },
 624         { 0x001b0001, 0x00000004 },
 625         { 0x08004800, 0x00000004 },
 626         { 0x001b0001, 0x00000004 },
 627         { 0x08004800, 0x00000004 },
 628         { 0x0000003a, 0x00000008 },
 629         { 0x0000a000, 0000000000 },
 630         { 0x02c0a000, 0x00000004 },
 631         { 0x000ca000, 0x00000004 },
 632         { 0x00130000, 0x00000004 },
 633         { 0x000c2000, 0x00000004 },
 634         { 0xc980c045, 0x00000008 },
 635         { 0x2000451d, 0x00000004 },
 636         { 0x0000e580, 0x00000004 },
 637         { 0x000ce581, 0x00000004 },
 638         { 0x08004580, 0x00000004 },
 639         { 0x000ce581, 0x00000004 },
 640         { 0x0000004c, 0x00000008 },
 641         { 0x0000a000, 0000000000 },
 642         { 0x000c2000, 0x00000004 },
 643         { 0x0000e50e, 0x00000004 },
 644         { 0x00032000, 0x00000004 },
 645         { 0x00022056, 0x00000028 },
 646         { 0x00000056, 0x00000024 },
 647         { 0x0800450f, 0x00000004 },
 648         { 0x0000a050, 0x00000008 },
 649         { 0x0000e565, 0x00000004 },
 650         { 0x0000e566, 0x00000004 },
 651         { 0x00000057, 0x00000008 },
 652         { 0x03cca5b4, 0x00000004 },
 653         { 0x05432000, 0x00000004 },
 654         { 0x00022000, 0x00000004 },
 655         { 0x4ccce063, 0x00000030 },
 656         { 0x08274565, 0x00000004 },
 657         { 0x00000063, 0x00000030 },
 658         { 0x08004564, 0x00000004 },
 659         { 0x0000e566, 0x00000004 },
 660         { 0x0000005a, 0x00000008 },
 661         { 0x00802066, 0x00000010 },
 662         { 0x00202000, 0x00000004 },
 663         { 0x001b00ff, 0x00000004 },
 664         { 0x01000069, 0x00000010 },
 665         { 0x001f2000, 0x00000004 },
 666         { 0x001c00ff, 0x00000004 },
 667         { 0000000000, 0x0000000c },
 668         { 0x00000085, 0x00000030 },
 669         { 0x0000005a, 0x00000008 },
 670         { 0x0000e576, 0x00000004 },
 671         { 0x000ca000, 0x00000004 },
 672         { 0x00012000, 0x00000004 },
 673         { 0x00082000, 0x00000004 },
 674         { 0x1800650e, 0x00000004 },
 675         { 0x00092000, 0x00000004 },
 676         { 0x000a2000, 0x00000004 },
 677         { 0x000f0000, 0x00000004 },
 678         { 0x00400000, 0x00000004 },
 679         { 0x00000079, 0x00000018 },
 680         { 0x0000e563, 0x00000004 },
 681         { 0x00c0e5f9, 0x000000c2 },
 682         { 0x0000006e, 0x00000008 },
 683         { 0x0000a06e, 0x00000008 },
 684         { 0x0000e576, 0x00000004 },
 685         { 0x0000e577, 0x00000004 },
 686         { 0x0000e50e, 0x00000004 },
 687         { 0x0000e50f, 0x00000004 },
 688         { 0x0140a000, 0x00000004 },
 689         { 0x0000007c, 0x00000018 },
 690         { 0x00c0e5f9, 0x000000c2 },
 691         { 0x0000007c, 0x00000008 },
 692         { 0x0014e50e, 0x00000004 },
 693         { 0x0040e50f, 0x00000004 },
 694         { 0x00c0007f, 0x00000008 },
 695         { 0x0000e570, 0x00000004 },
 696         { 0x0000e571, 0x00000004 },
 697         { 0x0000e572, 0x0000000c },
 698         { 0x0000a000, 0x00000004 },
 699         { 0x0140a000, 0x00000004 },
 700         { 0x0000e568, 0x00000004 },
 701         { 0x000c2000, 0x00000004 },
 702         { 0x00000089, 0x00000018 },
 703         { 0x000b0000, 0x00000004 },
 704         { 0x18c0e562, 0x00000004 },
 705         { 0x0000008b, 0x00000008 },
 706         { 0x00c0008a, 0x00000008 },
 707         { 0x000700e4, 0x00000004 },
 708         { 0x00000097, 0x00000038 },
 709         { 0x000ca099, 0x00000030 },
 710         { 0x080045bb, 0x00000004 },
 711         { 0x000c209a, 0x00000030 },
 712         { 0x0800e5bc, 0000000000 },
 713         { 0x0000e5bb, 0x00000004 },
 714         { 0x0000e5bc, 0000000000 },
 715         { 0x00120000, 0x0000000c },
 716         { 0x00120000, 0x00000004 },
 717         { 0x001b0002, 0x0000000c },
 718         { 0x0000a000, 0x00000004 },
 719         { 0x0000e821, 0x00000004 },
 720         { 0x0000e800, 0000000000 },
 721         { 0x0000e821, 0x00000004 },
 722         { 0x0000e82e, 0000000000 },
 723         { 0x02cca000, 0x00000004 },
 724         { 0x00140000, 0x00000004 },
 725         { 0x000ce1cc, 0x00000004 },
 726         { 0x050de1cd, 0x00000004 },
 727         { 0x000000a7, 0x00000020 },
 728         { 0x4200e000, 0000000000 },
 729         { 0x000000ae, 0x00000038 },
 730         { 0x000ca000, 0x00000004 },
 731         { 0x00140000, 0x00000004 },
 732         { 0x000c2000, 0x00000004 },
 733         { 0x00160000, 0x00000004 },
 734         { 0x700ce000, 0x00000004 },
 735         { 0x001400aa, 0x00000008 },
 736         { 0x4000e000, 0000000000 },
 737         { 0x02400000, 0x00000004 },
 738         { 0x400ee000, 0x00000004 },
 739         { 0x02400000, 0x00000004 },
 740         { 0x4000e000, 0000000000 },
 741         { 0x000c2000, 0x00000004 },
 742         { 0x0240e51b, 0x00000004 },
 743         { 0x0080e50a, 0x00000005 },
 744         { 0x0080e50b, 0x00000005 },
 745         { 0x00220000, 0x00000004 },
 746         { 0x000700e4, 0x00000004 },
 747         { 0x000000c1, 0x00000038 },
 748         { 0x000c209a, 0x00000030 },
 749         { 0x0880e5bd, 0x00000005 },
 750         { 0x000c2099, 0x00000030 },
 751         { 0x0800e5bb, 0x00000005 },
 752         { 0x000c209a, 0x00000030 },
 753         { 0x0880e5bc, 0x00000005 },
 754         { 0x000000c4, 0x00000008 },
 755         { 0x0080e5bd, 0x00000005 },
 756         { 0x0000e5bb, 0x00000005 },
 757         { 0x0080e5bc, 0x00000005 },
 758         { 0x00210000, 0x00000004 },
 759         { 0x02800000, 0x00000004 },
 760         { 0x00c000c8, 0x00000018 },
 761         { 0x4180e000, 0x00000040 },
 762         { 0x000000ca, 0x00000024 },
 763         { 0x01000000, 0x0000000c },
 764         { 0x0100e51d, 0x0000000c },
 765         { 0x000045bb, 0x00000004 },
 766         { 0x000080c4, 0x00000008 },
 767         { 0x0000f3ce, 0x00000004 },
 768         { 0x0140a000, 0x00000004 },
 769         { 0x00cc2000, 0x00000004 },
 770         { 0x08c053cf, 0x00000040 },
 771         { 0x00008000, 0000000000 },
 772         { 0x0000f3d2, 0x00000004 },
 773         { 0x0140a000, 0x00000004 },
 774         { 0x00cc2000, 0x00000004 },
 775         { 0x08c053d3, 0x00000040 },
 776         { 0x00008000, 0000000000 },
 777         { 0x0000f39d, 0x00000004 },
 778         { 0x0140a000, 0x00000004 },
 779         { 0x00cc2000, 0x00000004 },
 780         { 0x08c0539e, 0x00000040 },
 781         { 0x00008000, 0000000000 },
 782         { 0x03c00830, 0x00000004 },
 783         { 0x4200e000, 0000000000 },
 784         { 0x0000a000, 0x00000004 },
 785         { 0x200045e0, 0x00000004 },
 786         { 0x0000e5e1, 0000000000 },
 787         { 0x00000001, 0000000000 },
 788         { 0x000700e1, 0x00000004 },
 789         { 0x0800e394, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816         { 0000000000, 0000000000 },
 817         { 0000000000, 0000000000 },
 818 };
 819
 820 static int RADEON_READ_PLL(drm_device_t * dev, int addr)
 821 {
 822         drm_radeon_private_t *dev_priv = dev->dev_private;
 823
 824         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 825         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 826 }
 827
 828 #if RADEON_FIFO_DEBUG
 829 static void radeon_status(drm_radeon_private_t * dev_priv)
 830 {
 831         printk("%s:\n", __FUNCTION__);
 832         printk("RBBM_STATUS = 0x%08x\n",
 833                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 834         printk("CP_RB_RTPR = 0x%08x\n",
 835                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 836         printk("CP_RB_WTPR = 0x%08x\n",
 837                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 838         printk("AIC_CNTL = 0x%08x\n",
 839                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 840         printk("AIC_STAT = 0x%08x\n",
 841                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 842         printk("AIC_PT_BASE = 0x%08x\n",
 843                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 844         printk("TLB_ADDR = 0x%08x\n",
 845                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 846         printk("TLB_DATA = 0x%08x\n",
 847                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 848 }
 849 #endif
 850
 851 /* ================================================================
 852  * Engine, FIFO control
 853  */
 854
 855 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 856 {
 857         u32 tmp;
 858         int i;
 859
 860         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 861
 862         tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
 863         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 864         RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
 865
 866         for (i = 0; i < dev_priv->usec_timeout; i++) {
 867                 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
 868                       & RADEON_RB2D_DC_BUSY)) {
 869                         return 0;
 870                 }
 871                 DRM_UDELAY(1);
 872         }
 873
 874 #if RADEON_FIFO_DEBUG
 875         DRM_ERROR("failed!\n");
 876         radeon_status(dev_priv);
 877 #endif
 878         return DRM_ERR(EBUSY);
 879 }
 880
 881 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 882 {
 883         int i;
 884
 885         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 886
 887         for (i = 0; i < dev_priv->usec_timeout; i++) {
 888                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 889                              & RADEON_RBBM_FIFOCNT_MASK);
 890                 if (slots >= entries)
 891                         return 0;
 892                 DRM_UDELAY(1);
 893         }
 894
 895 #if RADEON_FIFO_DEBUG
 896         DRM_ERROR("failed!\n");
 897         radeon_status(dev_priv);
 898 #endif
 899         return DRM_ERR(EBUSY);
 900 }
 901
 902 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 903 {
 904         int i, ret;
 905
 906         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 907
 908         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 909         if (ret)
 910                 return ret;
 911
 912         for (i = 0; i < dev_priv->usec_timeout; i++) {
 913                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 914                       & RADEON_RBBM_ACTIVE)) {
 915                         radeon_do_pixcache_flush(dev_priv);
 916                         return 0;
 917                 }
 918                 DRM_UDELAY(1);
 919         }
 920
 921 #if RADEON_FIFO_DEBUG
 922         DRM_ERROR("failed!\n");
 923         radeon_status(dev_priv);
 924 #endif
 925         return DRM_ERR(EBUSY);
 926 }
 927
 928 /* ================================================================
 929  * CP control, initialization
 930  */
 931
 932 /* Load the microcode for the CP */
 933 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 934 {
 935         int i;
 936         DRM_DEBUG("\n");
 937
 938         radeon_do_wait_for_idle(dev_priv);
 939
 940         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 941
 942         if (dev_priv->microcode_version==UCODE_R200) {
 943                 DRM_INFO("Loading R200 Microcode\n");
 944                 for (i = 0; i < 256; i++) {
 945                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 946                                      R200_cp_microcode[i][1]);
 947                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 948                                      R200_cp_microcode[i][0]);
 949                 }
 950         } else if (dev_priv->microcode_version==UCODE_R300) {
 951                 DRM_INFO("Loading R300 Microcode\n");
 952                 for ( i = 0 ; i < 256 ; i++ ) {
 953                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 954                                       R300_cp_microcode[i][1] );
 955                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 956                                       R300_cp_microcode[i][0] );
 957                 }
 958         } else {
 959                 for (i = 0; i < 256; i++) {
 960                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 961                                      radeon_cp_microcode[i][1]);
 962                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 963                                      radeon_cp_microcode[i][0]);
 964                 }
 965         }
 966 }
 967
 968 /* Flush any pending commands to the CP.  This should only be used just
 969  * prior to a wait for idle, as it informs the engine that the command
 970  * stream is ending.
 971  */
 972 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 973 {
 974         DRM_DEBUG("\n");
 975 #if 0
 976         u32 tmp;
 977
 978         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 979         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 980 #endif
 981 }
 982
 983 /* Wait for the CP to go idle.
 984  */
 985 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 986 {
 987         RING_LOCALS;
 988         DRM_DEBUG("\n");
 989
 990         BEGIN_RING(6);
 991
 992         RADEON_PURGE_CACHE();
 993         RADEON_PURGE_ZCACHE();
 994         RADEON_WAIT_UNTIL_IDLE();
 995
 996         ADVANCE_RING();
 997         COMMIT_RING();
 998
 999         return radeon_do_wait_for_idle(dev_priv);
1000 }
1001
1002 /* Start the Command Processor.
1003  */
1004 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1005 {
1006         RING_LOCALS;
1007         DRM_DEBUG("\n");
1008
1009         radeon_do_wait_for_idle(dev_priv);
1010
1011         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1012
1013         dev_priv->cp_running = 1;
1014
1015         BEGIN_RING(6);
1016
1017         RADEON_PURGE_CACHE();
1018         RADEON_PURGE_ZCACHE();
1019         RADEON_WAIT_UNTIL_IDLE();
1020
1021         ADVANCE_RING();
1022         COMMIT_RING();
1023 }
1024
1025 /* Reset the Command Processor.  This will not flush any pending
1026  * commands, so you must wait for the CP command stream to complete
1027  * before calling this routine.
1028  */
1029 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1030 {
1031         u32 cur_read_ptr;
1032         DRM_DEBUG("\n");
1033
1034         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1035         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1036         SET_RING_HEAD(dev_priv, cur_read_ptr);
1037         dev_priv->ring.tail = cur_read_ptr;
1038 }
1039
1040 /* Stop the Command Processor.  This will not flush any pending
1041  * commands, so you must flush the command stream and wait for the CP
1042  * to go idle before calling this routine.
1043  */
1044 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1045 {
1046         DRM_DEBUG("\n");
1047
1048         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1049
1050         dev_priv->cp_running = 0;
1051 }
1052
1053 /* Reset the engine.  This will stop the CP if it is running.
1054  */
1055 static int radeon_do_engine_reset(drm_device_t * dev)
1056 {
1057         drm_radeon_private_t *dev_priv = dev->dev_private;
1058         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1059         DRM_DEBUG("\n");
1060
1061         radeon_do_pixcache_flush(dev_priv);
1062
1063         clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1064         mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1065
1066         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1067                                             RADEON_FORCEON_MCLKA |
1068                                             RADEON_FORCEON_MCLKB |
1069                                             RADEON_FORCEON_YCLKA |
1070                                             RADEON_FORCEON_YCLKB |
1071                                             RADEON_FORCEON_MC |
1072                                             RADEON_FORCEON_AIC));
1073
1074         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1075
1076         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1077                                               RADEON_SOFT_RESET_CP |
1078                                               RADEON_SOFT_RESET_HI |
1079                                               RADEON_SOFT_RESET_SE |
1080                                               RADEON_SOFT_RESET_RE |
1081                                               RADEON_SOFT_RESET_PP |
1082                                               RADEON_SOFT_RESET_E2 |
1083                                               RADEON_SOFT_RESET_RB));
1084         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1085         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1086                                               ~(RADEON_SOFT_RESET_CP |
1087                                                 RADEON_SOFT_RESET_HI |
1088                                                 RADEON_SOFT_RESET_SE |
1089                                                 RADEON_SOFT_RESET_RE |
1090                                                 RADEON_SOFT_RESET_PP |
1091                                                 RADEON_SOFT_RESET_E2 |
1092                                                 RADEON_SOFT_RESET_RB)));
1093         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1094
1095         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1096         RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1097         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1098
1099         /* Reset the CP ring */
1100         radeon_do_cp_reset(dev_priv);
1101
1102         /* The CP is no longer running after an engine reset */
1103         dev_priv->cp_running = 0;
1104
1105         /* Reset any pending vertex, indirect buffers */
1106         radeon_freelist_reset(dev);
1107
1108         return 0;
1109 }
1110
1111 static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1112                                        drm_radeon_private_t * dev_priv)
1113 {
1114         u32 ring_start, cur_read_ptr;
1115         u32 tmp;
1116
1117         /* Initialize the memory controller */
1118         RADEON_WRITE(RADEON_MC_FB_LOCATION,
1119                      ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1120                      | (dev_priv->fb_location >> 16));
1121
1122 #if __OS_HAS_AGP
1123         if (dev_priv->flags & CHIP_IS_AGP) {
1124                 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1125                              (((dev_priv->gart_vm_start - 1 +
1126                                 dev_priv->gart_size) & 0xffff0000) |
1127                               (dev_priv->gart_vm_start >> 16)));
1128
1129                 ring_start = (dev_priv->cp_ring->offset
1130                               - dev->agp->base + dev_priv->gart_vm_start);
1131         } else
1132 #endif
1133                 ring_start = (dev_priv->cp_ring->offset
1134                               - dev->sg->handle + dev_priv->gart_vm_start);
1135
1136         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1137
1138         /* Set the write pointer delay */
1139         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1140
1141         /* Initialize the ring buffer's read and write pointers */
1142         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1143         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1144         SET_RING_HEAD(dev_priv, cur_read_ptr);
1145         dev_priv->ring.tail = cur_read_ptr;
1146
1147 #if __OS_HAS_AGP
1148         if (dev_priv->flags & CHIP_IS_AGP) {
1149                 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1150                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1151                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1152                              dev_priv->ring_rptr->offset
1153                              - dev->agp->base + dev_priv->gart_vm_start);
1154         } else
1155 #endif
1156         {
1157                 drm_sg_mem_t *entry = dev->sg;
1158                 unsigned long tmp_ofs, page_ofs;
1159
1160                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1161                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1162
1163                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1164                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1165                           (unsigned long)entry->busaddr[page_ofs],
1166                           entry->handle + tmp_ofs);
1167         }
1168
1169         /* Initialize the scratch register pointer.  This will cause
1170          * the scratch register values to be written out to memory
1171          * whenever they are updated.
1172          *
1173          * We simply put this behind the ring read pointer, this works
1174          * with PCI GART as well as (whatever kind of) AGP GART
1175          */
1176         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1177                      + RADEON_SCRATCH_REG_OFFSET);
1178
1179         dev_priv->scratch = ((__volatile__ u32 *)
1180                              dev_priv->ring_rptr->handle +
1181                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1182
1183         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1184
1185         /* Writeback doesn't seem to work everywhere, test it first */
1186         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1187         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1188
1189         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1190                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1191                     0xdeadbeef)
1192                         break;
1193                 DRM_UDELAY(1);
1194         }
1195
1196         if (tmp < dev_priv->usec_timeout) {
1197                 dev_priv->writeback_works = 1;
1198                 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1199         } else {
1200                 dev_priv->writeback_works = 0;
1201                 DRM_DEBUG("writeback test failed\n");
1202         }
1203
1204         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1205         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1206
1207         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1208         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1209                      dev_priv->sarea_priv->last_dispatch);
1210
1211         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1212         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1213
1214         /* Set ring buffer size */
1215 #ifdef __BIG_ENDIAN
1216         RADEON_WRITE(RADEON_CP_RB_CNTL,
1217                      dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1218 #else
1219         RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1220 #endif
1221
1222         radeon_do_wait_for_idle(dev_priv);
1223
1224         /* Turn on bus mastering */
1225         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1226         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1227
1228         /* Sync everything up */
1229         RADEON_WRITE(RADEON_ISYNC_CNTL,
1230                      (RADEON_ISYNC_ANY2D_IDLE3D |
1231                       RADEON_ISYNC_ANY3D_IDLE2D |
1232                       RADEON_ISYNC_WAIT_IDLEGUI |
1233                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1234 }
1235
1236 /* Enable or disable PCI GART on the chip */
1237 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1238 {
1239         u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
1240
1241         if (on) {
1242                 RADEON_WRITE(RADEON_AIC_CNTL,
1243                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1244
1245                 /* set PCI GART page-table base address
1246                  */
1247                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart);
1248
1249                 /* set address range for PCI address translate
1250                  */
1251                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1252                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1253                              + dev_priv->gart_size - 1);
1254
1255                 /* Turn off AGP aperture -- is this required for PCI GART?
1256                  */
1257                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1258                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1259         } else {
1260                 RADEON_WRITE(RADEON_AIC_CNTL,
1261                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1262         }
1263 }
1264
1265 static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1266 {
1267         drm_radeon_private_t *dev_priv = dev->dev_private;
1268         DRM_DEBUG("\n");
1269
1270         if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
1271                 DRM_ERROR("PCI GART memory not allocated!\n");
1272                 radeon_do_cleanup_cp(dev);
1273                 return DRM_ERR(EINVAL);
1274         }
1275
1276         dev_priv->usec_timeout = init->usec_timeout;
1277         if (dev_priv->usec_timeout < 1 ||
1278             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1279                 DRM_DEBUG("TIMEOUT problem!\n");
1280                 radeon_do_cleanup_cp(dev);
1281                 return DRM_ERR(EINVAL);
1282         }
1283
1284         switch(init->func) {
1285         case RADEON_INIT_R200_CP:
1286                 dev_priv->microcode_version=UCODE_R200;
1287                 break;
1288         case RADEON_INIT_R300_CP:
1289                 dev_priv->microcode_version=UCODE_R300;
1290                 break;
1291         default:
1292                 dev_priv->microcode_version=UCODE_R100;
1293                 break;
1294         }
1295
1296         dev_priv->do_boxes = 0;
1297         dev_priv->cp_mode = init->cp_mode;
1298
1299         /* We don't support anything other than bus-mastering ring mode,
1300          * but the ring can be in either AGP or PCI space for the ring
1301          * read pointer.
1302          */
1303         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1304             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1305                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1306                 radeon_do_cleanup_cp(dev);
1307                 return DRM_ERR(EINVAL);
1308         }
1309
1310         switch (init->fb_bpp) {
1311         case 16:
1312                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1313                 break;
1314         case 32:
1315         default:
1316                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1317                 break;
1318         }
1319         dev_priv->front_offset = init->front_offset;
1320         dev_priv->front_pitch = init->front_pitch;
1321         dev_priv->back_offset = init->back_offset;
1322         dev_priv->back_pitch = init->back_pitch;
1323
1324         switch (init->depth_bpp) {
1325         case 16:
1326                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1327                 break;
1328         case 32:
1329         default:
1330                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1331                 break;
1332         }
1333         dev_priv->depth_offset = init->depth_offset;
1334         dev_priv->depth_pitch = init->depth_pitch;
1335
1336         /* Hardware state for depth clears.  Remove this if/when we no
1337          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1338          * all values to prevent unwanted 3D state from slipping through
1339          * and screwing with the clear operation.
1340          */
1341         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1342                                            (dev_priv->color_fmt << 10) |
1343                                            (dev_priv->microcode_version == UCODE_R100 ?
1344                                                 RADEON_ZBLOCK16 : 0));
1345
1346         dev_priv->depth_clear.rb3d_zstencilcntl =
1347             (dev_priv->depth_fmt |
1348              RADEON_Z_TEST_ALWAYS |
1349              RADEON_STENCIL_TEST_ALWAYS |
1350              RADEON_STENCIL_S_FAIL_REPLACE |
1351              RADEON_STENCIL_ZPASS_REPLACE |
1352              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1353
1354         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1355                                          RADEON_BFACE_SOLID |
1356                                          RADEON_FFACE_SOLID |
1357                                          RADEON_FLAT_SHADE_VTX_LAST |
1358                                          RADEON_DIFFUSE_SHADE_FLAT |
1359                                          RADEON_ALPHA_SHADE_FLAT |
1360                                          RADEON_SPECULAR_SHADE_FLAT |
1361                                          RADEON_FOG_SHADE_FLAT |
1362                                          RADEON_VTX_PIX_CENTER_OGL |
1363                                          RADEON_ROUND_MODE_TRUNC |
1364                                          RADEON_ROUND_PREC_8TH_PIX);
1365
1366         DRM_GETSAREA();
1367
1368         dev_priv->fb_offset = init->fb_offset;
1369         dev_priv->mmio_offset = init->mmio_offset;
1370         dev_priv->ring_offset = init->ring_offset;
1371         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1372         dev_priv->buffers_offset = init->buffers_offset;
1373         dev_priv->gart_textures_offset = init->gart_textures_offset;
1374
1375         if (!dev_priv->sarea) {
1376                 DRM_ERROR("could not find sarea!\n");
1377                 radeon_do_cleanup_cp(dev);
1378                 return DRM_ERR(EINVAL);
1379         }
1380
1381         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1382         if (!dev_priv->mmio) {
1383                 DRM_ERROR("could not find mmio region!\n");
1384                 radeon_do_cleanup_cp(dev);
1385                 return DRM_ERR(EINVAL);
1386         }
1387         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1388         if (!dev_priv->cp_ring) {
1389                 DRM_ERROR("could not find cp ring region!\n");
1390                 radeon_do_cleanup_cp(dev);
1391                 return DRM_ERR(EINVAL);
1392         }
1393         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1394         if (!dev_priv->ring_rptr) {
1395                 DRM_ERROR("could not find ring read pointer!\n");
1396                 radeon_do_cleanup_cp(dev);
1397                 return DRM_ERR(EINVAL);
1398         }
1399         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1400         if (!dev->agp_buffer_map) {
1401                 DRM_ERROR("could not find dma buffer region!\n");
1402                 radeon_do_cleanup_cp(dev);
1403                 return DRM_ERR(EINVAL);
1404         }
1405
1406         if (init->gart_textures_offset) {
1407                 dev_priv->gart_textures =
1408                     drm_core_findmap(dev, init->gart_textures_offset);
1409                 if (!dev_priv->gart_textures) {
1410                         DRM_ERROR("could not find GART texture region!\n");
1411                         radeon_do_cleanup_cp(dev);
1412                         return DRM_ERR(EINVAL);
1413                 }
1414         }
1415
1416         dev_priv->sarea_priv =
1417             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1418                                     init->sarea_priv_offset);
1419
1420 #if __OS_HAS_AGP
1421         if (dev_priv->flags & CHIP_IS_AGP) {
1422                 drm_core_ioremap(dev_priv->cp_ring, dev);
1423                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1424                 drm_core_ioremap(dev->agp_buffer_map, dev);
1425                 if (!dev_priv->cp_ring->handle ||
1426                     !dev_priv->ring_rptr->handle ||
1427                     !dev->agp_buffer_map->handle) {
1428                         DRM_ERROR("could not find ioremap agp regions!\n");
1429                         radeon_do_cleanup_cp(dev);
1430                         return DRM_ERR(EINVAL);
1431                 }
1432         } else
1433 #endif
1434         {
1435                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1436                 dev_priv->ring_rptr->handle =
1437                     (void *)dev_priv->ring_rptr->offset;
1438                 dev->agp_buffer_map->handle =
1439                     (void *)dev->agp_buffer_map->offset;
1440
1441                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1442                           dev_priv->cp_ring->handle);
1443                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1444                           dev_priv->ring_rptr->handle);
1445                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1446                           dev->agp_buffer_map->handle);
1447         }
1448
1449         dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1450                                  & 0xffff) << 16;
1451
1452         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1453                                         ((dev_priv->front_offset
1454                                           + dev_priv->fb_location) >> 10));
1455
1456         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1457                                        ((dev_priv->back_offset
1458                                          + dev_priv->fb_location) >> 10));
1459
1460         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1461                                         ((dev_priv->depth_offset
1462                                           + dev_priv->fb_location) >> 10));
1463
1464         dev_priv->gart_size = init->gart_size;
1465         dev_priv->gart_vm_start = dev_priv->fb_location
1466             + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1467
1468 #if __OS_HAS_AGP
1469         if (dev_priv->flags & CHIP_IS_AGP)
1470                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1471                                                  - dev->agp->base
1472                                                  + dev_priv->gart_vm_start);
1473         else
1474 #endif
1475                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1476                                                  - dev->sg->handle
1477                                                  + dev_priv->gart_vm_start);
1478
1479         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1480         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1481         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1482                   dev_priv->gart_buffers_offset);
1483
1484         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1485         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1486                               + init->ring_size / sizeof(u32));
1487         dev_priv->ring.size = init->ring_size;
1488         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1489
1490         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1491
1492         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1493
1494 #if __OS_HAS_AGP
1495         if (dev_priv->flags & CHIP_IS_AGP) {
1496                 /* Turn off PCI GART */
1497                 radeon_set_pcigart(dev_priv, 0);
1498         } else
1499 #endif
1500         {
1501                 if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
1502                                           &dev_priv->bus_pci_gart)) {
1503                         DRM_ERROR("failed to init PCI GART!\n");
1504                         radeon_do_cleanup_cp(dev);
1505                         return DRM_ERR(ENOMEM);
1506                 }
1507
1508                 /* Turn on PCI GART */
1509                 radeon_set_pcigart(dev_priv, 1);
1510         }
1511
1512         radeon_cp_load_microcode(dev_priv);
1513         radeon_cp_init_ring_buffer(dev, dev_priv);
1514
1515         dev_priv->last_buf = 0;
1516
1517         radeon_do_engine_reset(dev);
1518
1519         return 0;
1520 }
1521
1522 static int radeon_do_cleanup_cp(drm_device_t * dev)
1523 {
1524         drm_radeon_private_t *dev_priv = dev->dev_private;
1525         DRM_DEBUG("\n");
1526
1527         /* Make sure interrupts are disabled here because the uninstall ioctl
1528          * may not have been called from userspace and after dev_private
1529          * is freed, it's too late.
1530          */
1531         if (dev->irq_enabled)
1532                 drm_irq_uninstall(dev);
1533
1534 #if __OS_HAS_AGP
1535         if (dev_priv->flags & CHIP_IS_AGP) {
1536                 if (dev_priv->cp_ring != NULL) {
1537                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1538                         dev_priv->cp_ring = NULL;
1539                 }
1540                 if (dev_priv->ring_rptr != NULL) {
1541                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1542                         dev_priv->ring_rptr = NULL;
1543                 }
1544                 if (dev->agp_buffer_map != NULL) {
1545                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1546                         dev->agp_buffer_map = NULL;
1547                 }
1548         } else
1549 #endif
1550         {
1551                 if (!drm_ati_pcigart_cleanup(dev,
1552                                              dev_priv->phys_pci_gart,
1553                                              dev_priv->bus_pci_gart))
1554                         DRM_ERROR("failed to cleanup PCI GART!\n");
1555         }
1556         /* only clear to the start of flags */
1557         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1558
1559         return 0;
1560 }
1561
1562 /* This code will reinit the Radeon CP hardware after a resume from disc.
1563  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1564  * here we make sure that all Radeon hardware initialisation is re-done without
1565  * affecting running applications.
1566  *
1567  * Charl P. Botha <http://cpbotha.net>
1568  */
1569 static int radeon_do_resume_cp(drm_device_t * dev)
1570 {
1571         drm_radeon_private_t *dev_priv = dev->dev_private;
1572
1573         if (!dev_priv) {
1574                 DRM_ERROR("Called with no initialization\n");
1575                 return DRM_ERR(EINVAL);
1576         }
1577
1578         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1579
1580 #if __OS_HAS_AGP
1581         if (dev_priv->flags & CHIP_IS_AGP) {
1582                 /* Turn off PCI GART */
1583                 radeon_set_pcigart(dev_priv, 0);
1584         } else
1585 #endif
1586         {
1587                 /* Turn on PCI GART */
1588                 radeon_set_pcigart(dev_priv, 1);
1589         }
1590
1591         radeon_cp_load_microcode(dev_priv);
1592         radeon_cp_init_ring_buffer(dev, dev_priv);
1593
1594         radeon_do_engine_reset(dev);
1595
1596         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1597
1598         return 0;
1599 }
1600
1601 int radeon_cp_init(DRM_IOCTL_ARGS)
1602 {
1603         DRM_DEVICE;
1604         drm_radeon_init_t init;
1605
1606         LOCK_TEST_WITH_RETURN(dev, filp);
1607
1608         DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1609                                  sizeof(init));
1610
1611         switch (init.func) {
1612         case RADEON_INIT_CP:
1613         case RADEON_INIT_R200_CP:
1614         case RADEON_INIT_R300_CP:
1615                 return radeon_do_init_cp(dev, &init);
1616         case RADEON_CLEANUP_CP:
1617                 return radeon_do_cleanup_cp(dev);
1618         }
1619
1620         return DRM_ERR(EINVAL);
1621 }
1622
1623 int radeon_cp_start(DRM_IOCTL_ARGS)
1624 {
1625         DRM_DEVICE;
1626         drm_radeon_private_t *dev_priv = dev->dev_private;
1627         DRM_DEBUG("\n");
1628
1629         LOCK_TEST_WITH_RETURN(dev, filp);
1630
1631         if (dev_priv->cp_running) {
1632                 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1633                 return 0;
1634         }
1635         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1636                 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1637                           __FUNCTION__, dev_priv->cp_mode);
1638                 return 0;
1639         }
1640
1641         radeon_do_cp_start(dev_priv);
1642
1643         return 0;
1644 }
1645
1646 /* Stop the CP.  The engine must have been idled before calling this
1647  * routine.
1648  */
1649 int radeon_cp_stop(DRM_IOCTL_ARGS)
1650 {
1651         DRM_DEVICE;
1652         drm_radeon_private_t *dev_priv = dev->dev_private;
1653         drm_radeon_cp_stop_t stop;
1654         int ret;
1655         DRM_DEBUG("\n");
1656
1657         LOCK_TEST_WITH_RETURN(dev, filp);
1658
1659         DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1660                                  sizeof(stop));
1661
1662         if (!dev_priv->cp_running)
1663                 return 0;
1664
1665         /* Flush any pending CP commands.  This ensures any outstanding
1666          * commands are exectuted by the engine before we turn it off.
1667          */
1668         if (stop.flush) {
1669                 radeon_do_cp_flush(dev_priv);
1670         }
1671
1672         /* If we fail to make the engine go idle, we return an error
1673          * code so that the DRM ioctl wrapper can try again.
1674          */
1675         if (stop.idle) {
1676                 ret = radeon_do_cp_idle(dev_priv);
1677                 if (ret)
1678                         return ret;
1679         }
1680
1681         /* Finally, we can turn off the CP.  If the engine isn't idle,
1682          * we will get some dropped triangles as they won't be fully
1683          * rendered before the CP is shut down.
1684          */
1685         radeon_do_cp_stop(dev_priv);
1686
1687         /* Reset the engine */
1688         radeon_do_engine_reset(dev);
1689
1690         return 0;
1691 }
1692
1693 void radeon_do_release(drm_device_t * dev)
1694 {
1695         drm_radeon_private_t *dev_priv = dev->dev_private;
1696         int i, ret;
1697
1698         if (dev_priv) {
1699
1700                 if (dev_priv->cp_running) {
1701                         /* Stop the cp */
1702                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1703                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1704 #ifdef __linux__
1705                                 schedule();
1706 #else
1707                                 tsleep(&ret, PZERO, "rdnrel", 1);
1708 #endif
1709                         }
1710                         radeon_do_cp_stop(dev_priv);
1711                         radeon_do_engine_reset(dev);
1712                 }
1713
1714                 /* Disable *all* interrupts */
1715                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1716                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1717
1718                 if (dev_priv->mmio) {/* remove all surfaces */
1719                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1720                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1721                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1722                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1723                         }
1724                 }
1725
1726                 /* Free memory heap structures */
1727                 radeon_mem_takedown(&(dev_priv->gart_heap));
1728                 radeon_mem_takedown(&(dev_priv->fb_heap));
1729
1730                 /* deallocate kernel resources */
1731                 radeon_do_cleanup_cp(dev);
1732         }
1733 }
1734
1735 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1736  */
1737 int radeon_cp_reset(DRM_IOCTL_ARGS)
1738 {
1739         DRM_DEVICE;
1740         drm_radeon_private_t *dev_priv = dev->dev_private;
1741         DRM_DEBUG("\n");
1742
1743         LOCK_TEST_WITH_RETURN(dev, filp);
1744
1745         if (!dev_priv) {
1746                 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1747                 return DRM_ERR(EINVAL);
1748         }
1749
1750         radeon_do_cp_reset(dev_priv);
1751
1752         /* The CP is no longer running after an engine reset */
1753         dev_priv->cp_running = 0;
1754
1755         return 0;
1756 }
1757
1758 int radeon_cp_idle(DRM_IOCTL_ARGS)
1759 {
1760         DRM_DEVICE;
1761         drm_radeon_private_t *dev_priv = dev->dev_private;
1762         DRM_DEBUG("\n");
1763
1764         LOCK_TEST_WITH_RETURN(dev, filp);
1765
1766         return radeon_do_cp_idle(dev_priv);
1767 }
1768
1769 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1770  */
1771 int radeon_cp_resume(DRM_IOCTL_ARGS)
1772 {
1773         DRM_DEVICE;
1774
1775         return radeon_do_resume_cp(dev);
1776 }
1777
1778 int radeon_engine_reset(DRM_IOCTL_ARGS)
1779 {
1780         DRM_DEVICE;
1781         DRM_DEBUG("\n");
1782
1783         LOCK_TEST_WITH_RETURN(dev, filp);
1784
1785         return radeon_do_engine_reset(dev);
1786 }
1787
1788 /* ================================================================
1789  * Fullscreen mode
1790  */
1791
1792 /* KW: Deprecated to say the least:
1793  */
1794 int radeon_fullscreen(DRM_IOCTL_ARGS)
1795 {
1796         return 0;
1797 }
1798
1799 /* ================================================================
1800  * Freelist management
1801  */
1802
1803 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1804  *   bufs until freelist code is used.  Note this hides a problem with
1805  *   the scratch register * (used to keep track of last buffer
1806  *   completed) being written to before * the last buffer has actually
1807  *   completed rendering.
1808  *
1809  * KW:  It's also a good way to find free buffers quickly.
1810  *
1811  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1812  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1813  * we essentially have to do this, else old clients will break.
1814  *
1815  * However, it does leave open a potential deadlock where all the
1816  * buffers are held by other clients, which can't release them because
1817  * they can't get the lock.
1818  */
1819
1820 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1821 {
1822         drm_device_dma_t *dma = dev->dma;
1823         drm_radeon_private_t *dev_priv = dev->dev_private;
1824         drm_radeon_buf_priv_t *buf_priv;
1825         drm_buf_t *buf;
1826         int i, t;
1827         int start;
1828
1829         if (++dev_priv->last_buf >= dma->buf_count)
1830                 dev_priv->last_buf = 0;
1831
1832         start = dev_priv->last_buf;
1833
1834         for (t = 0; t < dev_priv->usec_timeout; t++) {
1835                 u32 done_age = GET_SCRATCH(1);
1836                 DRM_DEBUG("done_age = %d\n", done_age);
1837                 for (i = start; i < dma->buf_count; i++) {
1838                         buf = dma->buflist[i];
1839                         buf_priv = buf->dev_private;
1840                         if (buf->filp == 0 || (buf->pending &&
1841                                                buf_priv->age <= done_age)) {
1842                                 dev_priv->stats.requested_bufs++;
1843                                 buf->pending = 0;
1844                                 return buf;
1845                         }
1846                         start = 0;
1847                 }
1848
1849                 if (t) {
1850                         DRM_UDELAY(1);
1851                         dev_priv->stats.freelist_loops++;
1852                 }
1853         }
1854
1855         DRM_DEBUG("returning NULL!\n");
1856         return NULL;
1857 }
1858
1859 #if 0
1860 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1861 {
1862         drm_device_dma_t *dma = dev->dma;
1863         drm_radeon_private_t *dev_priv = dev->dev_private;
1864         drm_radeon_buf_priv_t *buf_priv;
1865         drm_buf_t *buf;
1866         int i, t;
1867         int start;
1868         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1869
1870         if (++dev_priv->last_buf >= dma->buf_count)
1871                 dev_priv->last_buf = 0;
1872
1873         start = dev_priv->last_buf;
1874         dev_priv->stats.freelist_loops++;
1875
1876         for (t = 0; t < 2; t++) {
1877                 for (i = start; i < dma->buf_count; i++) {
1878                         buf = dma->buflist[i];
1879                         buf_priv = buf->dev_private;
1880                         if (buf->filp == 0 || (buf->pending &&
1881                                                buf_priv->age <= done_age)) {
1882                                 dev_priv->stats.requested_bufs++;
1883                                 buf->pending = 0;
1884                                 return buf;
1885                         }
1886                 }
1887                 start = 0;
1888         }
1889
1890         return NULL;
1891 }
1892 #endif
1893
1894 void radeon_freelist_reset(drm_device_t * dev)
1895 {
1896         drm_device_dma_t *dma = dev->dma;
1897         drm_radeon_private_t *dev_priv = dev->dev_private;
1898         int i;
1899
1900         dev_priv->last_buf = 0;
1901         for (i = 0; i < dma->buf_count; i++) {
1902                 drm_buf_t *buf = dma->buflist[i];
1903                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1904                 buf_priv->age = 0;
1905         }
1906 }
1907
1908 /* ================================================================
1909  * CP command submission
1910  */
1911
1912 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1913 {
1914         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1915         int i;
1916         u32 last_head = GET_RING_HEAD(dev_priv);
1917
1918         for (i = 0; i < dev_priv->usec_timeout; i++) {
1919                 u32 head = GET_RING_HEAD(dev_priv);
1920
1921                 ring->space = (head - ring->tail) * sizeof(u32);
1922                 if (ring->space <= 0)
1923                         ring->space += ring->size;
1924                 if (ring->space > n)
1925                         return 0;
1926
1927                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1928
1929                 if (head != last_head)
1930                         i = 0;
1931                 last_head = head;
1932
1933                 DRM_UDELAY(1);
1934         }
1935
1936         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1937 #if RADEON_FIFO_DEBUG
1938         radeon_status(dev_priv);
1939         DRM_ERROR("failed!\n");
1940 #endif
1941         return DRM_ERR(EBUSY);
1942 }
1943
1944 static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
1945                                  drm_dma_t * d)
1946 {
1947         int i;
1948         drm_buf_t *buf;
1949
1950         for (i = d->granted_count; i < d->request_count; i++) {
1951                 buf = radeon_freelist_get(dev);
1952                 if (!buf)
1953                         return DRM_ERR(EBUSY);  /* NOTE: broken client */
1954
1955                 buf->filp = filp;
1956
1957                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1958                                      sizeof(buf->idx)))
1959                         return DRM_ERR(EFAULT);
1960                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1961                                      sizeof(buf->total)))
1962                         return DRM_ERR(EFAULT);
1963
1964                 d->granted_count++;
1965         }
1966         return 0;
1967 }
1968
1969 int radeon_cp_buffers(DRM_IOCTL_ARGS)
1970 {
1971         DRM_DEVICE;
1972         drm_device_dma_t *dma = dev->dma;
1973         int ret = 0;
1974         drm_dma_t __user *argp = (void __user *)data;
1975         drm_dma_t d;
1976
1977         LOCK_TEST_WITH_RETURN(dev, filp);
1978
1979         DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1980
1981         /* Please don't send us buffers.
1982          */
1983         if (d.send_count != 0) {
1984                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1985                           DRM_CURRENTPID, d.send_count);
1986                 return DRM_ERR(EINVAL);
1987         }
1988
1989         /* We'll send you buffers.
1990          */
1991         if (d.request_count < 0 || d.request_count > dma->buf_count) {
1992                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1993                           DRM_CURRENTPID, d.request_count, dma->buf_count);
1994                 return DRM_ERR(EINVAL);
1995         }
1996
1997         d.granted_count = 0;
1998
1999         if (d.request_count) {
2000                 ret = radeon_cp_get_buffers(filp, dev, &d);
2001         }
2002
2003         DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2004
2005         return ret;
2006 }
2007
2008 /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
2009 int radeon_preinit(struct drm_device *dev, unsigned long flags)
2010 {
2011         drm_radeon_private_t *dev_priv;
2012         int ret = 0;
2013
2014         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2015         if (dev_priv == NULL)
2016                 return DRM_ERR(ENOMEM);
2017
2018         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2019         dev->dev_private = (void *)dev_priv;
2020         dev_priv->flags = flags;
2021
2022         switch (flags & CHIP_FAMILY_MASK) {
2023         case CHIP_R100:
2024         case CHIP_RV200:
2025         case CHIP_R200:
2026         case CHIP_R300:
2027                 dev_priv->flags |= CHIP_HAS_HIERZ;
2028                 break;
2029         default:
2030         /* all other chips have no hierarchical z buffer */
2031                 break;
2032         }
2033
2034         ret = drm_initmap(dev, drm_get_resource_start(dev, 2),
2035                           drm_get_resource_len(dev, 2), 2, _DRM_REGISTERS, 0);
2036         if (ret != 0)
2037                 return ret;
2038
2039         ret = drm_initmap(dev, drm_get_resource_start(dev, 0),
2040                           drm_get_resource_len(dev, 0), 0, _DRM_FRAME_BUFFER,
2041                           _DRM_WRITE_COMBINING);
2042         if (ret != 0)
2043                 return ret;
2044
2045         /* The original method of detecting AGP is known to not work correctly,
2046          * according to Mike Harris.  The solution is to walk the capabilities
2047          * list, which should be done in drm_device_is_agp().
2048          */
2049         if (drm_device_is_agp(dev))
2050                 dev_priv->flags |= CHIP_IS_AGP;
2051
2052         DRM_DEBUG("%s card detected\n",
2053                   ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2054
2055 #if defined(__linux__)
2056         /* Check if we need a reset */
2057         if (!
2058             (dev_priv->mmio =
2059              drm_core_findmap(dev, pci_resource_start(dev->pdev, 2))))
2060                 return DRM_ERR(ENOMEM);
2061
2062         ret = radeon_create_i2c_busses(dev);
2063 #endif
2064         return ret;
2065 }
2066
2067 int radeon_postcleanup(struct drm_device *dev)
2068 {
2069         drm_radeon_private_t *dev_priv = dev->dev_private;
2070
2071         DRM_DEBUG("\n");
2072 #if defined(__linux__)
2073         radeon_delete_i2c_busses(dev);
2074 #endif
2075         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2076
2077         dev->dev_private = NULL;
2078         return 0;
2079 }