1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #ifndef __RADEON_DRM_H__
37 #define __RADEON_DRM_H__
39 /* WARNING: If you change any of these defines, make sure to change the
40 * defines in the X server file (radeon_sarea.h)
42 #ifndef __RADEON_SAREA_DEFINES__
43 #define __RADEON_SAREA_DEFINES__
45 /* Old style state flags, required for sarea interface (1.1 and 1.2
46 * clears) and 1.2 drm_vertex2 ioctl.
48 #define RADEON_UPLOAD_CONTEXT 0x00000001
49 #define RADEON_UPLOAD_VERTFMT 0x00000002
50 #define RADEON_UPLOAD_LINE 0x00000004
51 #define RADEON_UPLOAD_BUMPMAP 0x00000008
52 #define RADEON_UPLOAD_MASKS 0x00000010
53 #define RADEON_UPLOAD_VIEWPORT 0x00000020
54 #define RADEON_UPLOAD_SETUP 0x00000040
55 #define RADEON_UPLOAD_TCL 0x00000080
56 #define RADEON_UPLOAD_MISC 0x00000100
57 #define RADEON_UPLOAD_TEX0 0x00000200
58 #define RADEON_UPLOAD_TEX1 0x00000400
59 #define RADEON_UPLOAD_TEX2 0x00000800
60 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000
61 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000
62 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000
63 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
64 #define RADEON_REQUIRE_QUIESCENCE 0x00010000
65 #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
66 #define RADEON_UPLOAD_ALL 0x003effff
67 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
69 /* New style per-packet identifiers for use in cmd_buffer ioctl with
70 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
71 * state bits and the packet size:
73 #define RADEON_EMIT_PP_MISC 0 /* context/7 */
74 #define RADEON_EMIT_PP_CNTL 1 /* context/3 */
75 #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
76 #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
77 #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
78 #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
79 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
80 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
81 #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
82 #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
83 #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
84 #define RADEON_EMIT_RE_MISC 11 /* misc/1 */
85 #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
86 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
87 #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
88 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
89 #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
90 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
91 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
92 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
93 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
94 #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
95 #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
96 #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
97 #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
98 #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
99 #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
100 #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
101 #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
102 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
103 #define R200_EMIT_TFACTOR_0 30 /* tf/7 */
104 #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
105 #define R200_EMIT_VAP_CTL 32 /* vap/1 */
106 #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
107 #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
108 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
109 #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
110 #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
111 #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
112 #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
113 #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
114 #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
115 #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
116 #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
117 #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
118 #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
119 #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
120 #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
121 #define R200_EMIT_VTE_CNTL 48 /* vte/1 */
122 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
123 #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
124 #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
125 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
126 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
127 #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
128 #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
129 #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
130 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
131 #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
132 #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
133 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
134 #define R200_EMIT_PP_CUBIC_FACES_0 61
135 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62
136 #define R200_EMIT_PP_CUBIC_FACES_1 63
137 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64
138 #define R200_EMIT_PP_CUBIC_FACES_2 65
139 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66
140 #define R200_EMIT_PP_CUBIC_FACES_3 67
141 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68
142 #define R200_EMIT_PP_CUBIC_FACES_4 69
143 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70
144 #define R200_EMIT_PP_CUBIC_FACES_5 71
145 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72
146 #define RADEON_EMIT_PP_TEX_SIZE_0 73
147 #define RADEON_EMIT_PP_TEX_SIZE_1 74
148 #define RADEON_EMIT_PP_TEX_SIZE_2 75
149 #define R200_EMIT_RB3D_BLENDCOLOR 76
150 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
151 #define RADEON_EMIT_PP_CUBIC_FACES_0 78
152 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
153 #define RADEON_EMIT_PP_CUBIC_FACES_1 80
154 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
155 #define RADEON_EMIT_PP_CUBIC_FACES_2 82
156 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
157 #define R200_EMIT_PP_TRI_PERF_CNTL 84
158 #define R200_EMIT_PP_AFS_0 85
159 #define R200_EMIT_PP_AFS_1 86
160 #define R200_EMIT_ATF_TFACTOR 87
161 #define R200_EMIT_PP_TXCTLALL_0 88
162 #define R200_EMIT_PP_TXCTLALL_1 89
163 #define R200_EMIT_PP_TXCTLALL_2 90
164 #define R200_EMIT_PP_TXCTLALL_3 91
165 #define R200_EMIT_PP_TXCTLALL_4 92
166 #define R200_EMIT_PP_TXCTLALL_5 93
167 #define RADEON_MAX_STATE_PACKETS 94
169 /* Commands understood by cmd_buffer ioctl. More can be added but
170 * obviously these can't be removed or changed:
172 #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
173 #define RADEON_CMD_SCALARS 2 /* emit scalar data */
174 #define RADEON_CMD_VECTORS 3 /* emit vector data */
175 #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
176 #define RADEON_CMD_PACKET3 5 /* emit hw packet */
177 #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
178 #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
179 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
180 * doesn't make the cpu wait, just
181 * the graphics hardware */
186 unsigned char cmd_type, pad0, pad1, pad2;
189 unsigned char cmd_type, packet_id, pad0, pad1;
192 unsigned char cmd_type, offset, stride, count;
195 unsigned char cmd_type, offset, stride, count;
198 unsigned char cmd_type, buf_idx, pad0, pad1;
201 unsigned char cmd_type, flags, pad0, pad1;
203 } drm_radeon_cmd_header_t;
205 #define RADEON_WAIT_2D 0x1
206 #define RADEON_WAIT_3D 0x2
208 /* Allowed parameters for R300_CMD_PACKET3
210 #define R300_CMD_PACKET3_CLEAR 0
211 #define R300_CMD_PACKET3_RAW 1
213 /* Commands understood by cmd_buffer ioctl for R300.
214 * The interface has not been stabilized, so some of these may be removed
215 * and eventually reordered before stabilization.
217 #define R300_CMD_PACKET0 1
218 #define R300_CMD_VPU 2 /* emit vertex program upload */
219 #define R300_CMD_PACKET3 3 /* emit a packet3 */
220 #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
221 #define R300_CMD_CP_DELAY 5
222 #define R300_CMD_DMA_DISCARD 6
223 #define R300_CMD_WAIT 7
224 # define R300_WAIT_2D 0x1
225 # define R300_WAIT_3D 0x2
226 # define R300_WAIT_2D_CLEAN 0x3
227 # define R300_WAIT_3D_CLEAN 0x4
232 unsigned char cmd_type, pad0, pad1, pad2;
235 unsigned char cmd_type, count, reglo, reghi;
238 unsigned char cmd_type, count, adrlo, adrhi;
241 unsigned char cmd_type, packet, pad0, pad1;
244 unsigned char cmd_type, packet;
245 unsigned short count; /* amount of packet2 to emit */
248 unsigned char cmd_type, buf_idx, pad0, pad1;
251 unsigned char cmd_type, flags, pad0, pad1;
253 } drm_r300_cmd_header_t;
255 #define RADEON_FRONT 0x1
256 #define RADEON_BACK 0x2
257 #define RADEON_DEPTH 0x4
258 #define RADEON_STENCIL 0x8
259 #define RADEON_CLEAR_FASTZ 0x80000000
260 #define RADEON_USE_HIERZ 0x40000000
261 #define RADEON_USE_COMP_ZBUF 0x20000000
265 #define RADEON_POINTS 0x1
266 #define RADEON_LINES 0x2
267 #define RADEON_LINE_STRIP 0x3
268 #define RADEON_TRIANGLES 0x4
269 #define RADEON_TRIANGLE_FAN 0x5
270 #define RADEON_TRIANGLE_STRIP 0x6
272 /* Vertex/indirect buffer size
274 #define RADEON_BUFFER_SIZE 65536
276 /* Byte offsets for indirect buffer data
278 #define RADEON_INDEX_PRIM_OFFSET 20
280 #define RADEON_SCRATCH_REG_OFFSET 32
282 #define RADEON_NR_SAREA_CLIPRECTS 12
284 /* There are 2 heaps (local/GART). Each region within a heap is a
285 * minimum of 64k, and there are at most 64 of them per heap.
287 #define RADEON_LOCAL_TEX_HEAP 0
288 #define RADEON_GART_TEX_HEAP 1
289 #define RADEON_NR_TEX_HEAPS 2
290 #define RADEON_NR_TEX_REGIONS 64
291 #define RADEON_LOG_TEX_GRANULARITY 16
293 #define RADEON_MAX_TEXTURE_LEVELS 12
294 #define RADEON_MAX_TEXTURE_UNITS 3
296 #define RADEON_MAX_SURFACES 8
298 /* Blits have strict offset rules. All blit offset must be aligned on
299 * a 1K-byte boundary.
301 #define RADEON_OFFSET_SHIFT 10
302 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
303 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
305 #endif /* __RADEON_SAREA_DEFINES__ */
312 } radeon_color_regs_t;
316 unsigned int pp_misc; /* 0x1c14 */
317 unsigned int pp_fog_color;
318 unsigned int re_solid_color;
319 unsigned int rb3d_blendcntl;
320 unsigned int rb3d_depthoffset;
321 unsigned int rb3d_depthpitch;
322 unsigned int rb3d_zstencilcntl;
324 unsigned int pp_cntl; /* 0x1c38 */
325 unsigned int rb3d_cntl;
326 unsigned int rb3d_coloroffset;
327 unsigned int re_width_height;
328 unsigned int rb3d_colorpitch;
329 unsigned int se_cntl;
331 /* Vertex format state */
332 unsigned int se_coord_fmt; /* 0x1c50 */
335 unsigned int re_line_pattern; /* 0x1cd0 */
336 unsigned int re_line_state;
338 unsigned int se_line_width; /* 0x1db8 */
341 unsigned int pp_lum_matrix; /* 0x1d00 */
343 unsigned int pp_rot_matrix_0; /* 0x1d58 */
344 unsigned int pp_rot_matrix_1;
347 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
348 unsigned int rb3d_ropcntl;
349 unsigned int rb3d_planemask;
352 unsigned int se_vport_xscale; /* 0x1d98 */
353 unsigned int se_vport_xoffset;
354 unsigned int se_vport_yscale;
355 unsigned int se_vport_yoffset;
356 unsigned int se_vport_zscale;
357 unsigned int se_vport_zoffset;
360 unsigned int se_cntl_status; /* 0x2140 */
363 unsigned int re_top_left; /* 0x26c0 */
364 unsigned int re_misc;
365 } drm_radeon_context_regs_t;
369 unsigned int se_zbias_factor; /* 0x1dac */
370 unsigned int se_zbias_constant;
371 } drm_radeon_context2_regs_t;
373 /* Setup registers for each texture unit
376 unsigned int pp_txfilter;
377 unsigned int pp_txformat;
378 unsigned int pp_txoffset;
379 unsigned int pp_txcblend;
380 unsigned int pp_txablend;
381 unsigned int pp_tfactor;
382 unsigned int pp_border_color;
383 } drm_radeon_texture_regs_t;
389 unsigned int stateidx:8;
390 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
391 unsigned int vc_format; /* vertex format */
395 drm_radeon_context_regs_t context;
396 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
397 drm_radeon_context2_regs_t context2;
399 } drm_radeon_state_t;
402 /* The channel for communication of state information to the
403 * kernel on firing a vertex buffer with either of the
404 * obsoleted vertex/index ioctls.
406 drm_radeon_context_regs_t context_state;
407 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
409 unsigned int vertsize;
410 unsigned int vc_format;
412 /* The current cliprects, or a subset thereof.
414 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
417 /* Counters for client-side throttling of rendering clients.
419 unsigned int last_frame;
420 unsigned int last_dispatch;
421 unsigned int last_clear;
423 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
425 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
427 int pfState; /* number of 3d windows (0,1,2ormore) */
428 int pfCurrentPage; /* which buffer is being displayed? */
429 int crtc2_base; /* CRTC2 frame offset */
430 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
431 } drm_radeon_sarea_t;
433 /* WARNING: If you change any of these defines, make sure to change the
434 * defines in the Xserver file (xf86drmRadeon.h)
436 * KW: actually it's illegal to change any of this (backwards compatibility).
439 /* Radeon specific ioctls
440 * The device specific ioctl range is 0x40 to 0x79.
442 #define DRM_RADEON_CP_INIT 0x00
443 #define DRM_RADEON_CP_START 0x01
444 #define DRM_RADEON_CP_STOP 0x02
445 #define DRM_RADEON_CP_RESET 0x03
446 #define DRM_RADEON_CP_IDLE 0x04
447 #define DRM_RADEON_RESET 0x05
448 #define DRM_RADEON_FULLSCREEN 0x06
449 #define DRM_RADEON_SWAP 0x07
450 #define DRM_RADEON_CLEAR 0x08
451 #define DRM_RADEON_VERTEX 0x09
452 #define DRM_RADEON_INDICES 0x0A
453 #define DRM_RADEON_NOT_USED
454 #define DRM_RADEON_STIPPLE 0x0C
455 #define DRM_RADEON_INDIRECT 0x0D
456 #define DRM_RADEON_TEXTURE 0x0E
457 #define DRM_RADEON_VERTEX2 0x0F
458 #define DRM_RADEON_CMDBUF 0x10
459 #define DRM_RADEON_GETPARAM 0x11
460 #define DRM_RADEON_FLIP 0x12
461 #define DRM_RADEON_ALLOC 0x13
462 #define DRM_RADEON_FREE 0x14
463 #define DRM_RADEON_INIT_HEAP 0x15
464 #define DRM_RADEON_IRQ_EMIT 0x16
465 #define DRM_RADEON_IRQ_WAIT 0x17
466 #define DRM_RADEON_CP_RESUME 0x18
467 #define DRM_RADEON_SETPARAM 0x19
468 #define DRM_RADEON_SURF_ALLOC 0x1a
469 #define DRM_RADEON_SURF_FREE 0x1b
471 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
472 #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
473 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
474 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
475 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
476 #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
477 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
478 #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
479 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
480 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
481 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
482 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
483 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
484 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
485 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
486 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
487 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
488 #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
489 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
490 #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
491 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
492 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
493 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
494 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
495 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
496 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
497 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
499 typedef struct drm_radeon_init {
501 RADEON_INIT_CP = 0x01,
502 RADEON_CLEANUP_CP = 0x02,
503 RADEON_INIT_R200_CP = 0x03,
504 RADEON_INIT_R300_CP = 0x04
506 unsigned long sarea_priv_offset;
507 int is_pci; /* for overriding only */
514 unsigned int front_offset, front_pitch;
515 unsigned int back_offset, back_pitch;
516 unsigned int depth_bpp;
517 unsigned int depth_offset, depth_pitch;
519 unsigned long fb_offset DEPRECATED; /* deprecated, driver asks hardware */
520 unsigned long mmio_offset DEPRECATED; /* deprecated, driver asks hardware */
521 unsigned long ring_offset;
522 unsigned long ring_rptr_offset;
523 unsigned long buffers_offset;
524 unsigned long gart_textures_offset;
527 typedef struct drm_radeon_cp_stop {
530 } drm_radeon_cp_stop_t;
532 typedef struct drm_radeon_fullscreen {
534 RADEON_INIT_FULLSCREEN = 0x01,
535 RADEON_CLEANUP_FULLSCREEN = 0x02
537 } drm_radeon_fullscreen_t;
543 #define CLEAR_DEPTH 4
545 typedef union drm_radeon_clear_rect {
548 } drm_radeon_clear_rect_t;
550 typedef struct drm_radeon_clear {
552 unsigned int clear_color;
553 unsigned int clear_depth;
554 unsigned int color_mask;
555 unsigned int depth_mask; /* misnamed field: should be stencil */
556 drm_radeon_clear_rect_t __user *depth_boxes;
557 } drm_radeon_clear_t;
559 typedef struct drm_radeon_vertex {
561 int idx; /* Index of vertex buffer */
562 int count; /* Number of vertices in buffer */
563 int discard; /* Client finished with buffer? */
564 } drm_radeon_vertex_t;
566 typedef struct drm_radeon_indices {
571 int discard; /* Client finished with buffer? */
572 } drm_radeon_indices_t;
574 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
575 * - allows multiple primitives and state changes in a single ioctl
576 * - supports driver change to emit native primitives
578 typedef struct drm_radeon_vertex2 {
579 int idx; /* Index of vertex buffer */
580 int discard; /* Client finished with buffer? */
582 drm_radeon_state_t __user *state;
584 drm_radeon_prim_t __user *prim;
585 } drm_radeon_vertex2_t;
587 /* v1.3 - obsoletes drm_radeon_vertex2
588 * - allows arbitarily large cliprect list
589 * - allows updating of tcl packet, vector and scalar state
590 * - allows memory-efficient description of state updates
591 * - allows state to be emitted without a primitive
592 * (for clears, ctx switches)
593 * - allows more than one dma buffer to be referenced per ioctl
594 * - supports tcl driver
595 * - may be extended in future versions with new cmd types, packets
597 typedef struct drm_radeon_cmd_buffer {
601 drm_clip_rect_t __user *boxes;
602 } drm_radeon_cmd_buffer_t;
604 typedef struct drm_radeon_tex_image {
605 unsigned int x, y; /* Blit coordinates */
606 unsigned int width, height;
607 const void __user *data;
608 } drm_radeon_tex_image_t;
610 typedef struct drm_radeon_texture {
614 int width; /* Texture image coordinates */
616 drm_radeon_tex_image_t __user *image;
617 } drm_radeon_texture_t;
619 typedef struct drm_radeon_stipple {
620 unsigned int __user *mask;
621 } drm_radeon_stipple_t;
623 typedef struct drm_radeon_indirect {
628 } drm_radeon_indirect_t;
630 /* 1.3: An ioctl to get parameters that aren't available to the 3d
631 * client any other way.
633 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
634 #define RADEON_PARAM_LAST_FRAME 2
635 #define RADEON_PARAM_LAST_DISPATCH 3
636 #define RADEON_PARAM_LAST_CLEAR 4
637 /* Added with DRM version 1.6. */
638 #define RADEON_PARAM_IRQ_NR 5
639 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
640 /* Added with DRM version 1.8. */
641 #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
642 #define RADEON_PARAM_STATUS_HANDLE 8
643 #define RADEON_PARAM_SAREA_HANDLE 9
644 #define RADEON_PARAM_GART_TEX_HANDLE 10
645 #define RADEON_PARAM_SCRATCH_OFFSET 11
647 typedef struct drm_radeon_getparam {
650 } drm_radeon_getparam_t;
652 /* 1.6: Set up a memory manager for regions of shared memory:
654 #define RADEON_MEM_REGION_GART 1
655 #define RADEON_MEM_REGION_FB 2
657 typedef struct drm_radeon_mem_alloc {
661 int __user *region_offset; /* offset from start of fb or GART */
662 } drm_radeon_mem_alloc_t;
664 typedef struct drm_radeon_mem_free {
667 } drm_radeon_mem_free_t;
669 typedef struct drm_radeon_mem_init_heap {
673 } drm_radeon_mem_init_heap_t;
675 /* 1.6: Userspace can request & wait on irq's:
677 typedef struct drm_radeon_irq_emit {
679 } drm_radeon_irq_emit_t;
681 typedef struct drm_radeon_irq_wait {
683 } drm_radeon_irq_wait_t;
685 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
686 * the card's address space, via a new generic ioctl to set parameters
689 typedef struct drm_radeon_setparam {
692 } drm_radeon_setparam_t;
694 #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
695 #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
696 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
698 /* 1.14: Clients can allocate/free a surface
700 typedef struct drm_radeon_surface_alloc {
701 unsigned int address;
704 } drm_radeon_surface_alloc_t;
706 typedef struct drm_radeon_surface_free {
707 unsigned int address;
708 } drm_radeon_surface_free_t;