1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #ifndef __RADEON_DRV_H__
35 #define __RADEON_DRV_H__
37 /* General customization:
40 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
42 #define DRIVER_NAME "radeon"
43 #define DRIVER_DESC "ATI Radeon"
44 #define DRIVER_DATE "20050911"
49 * 1.2 - Add vertex2 ioctl (keith)
50 * - Add stencil capability to clear ioctl (gareth, keith)
51 * - Increase MAX_TEXTURE_LEVELS (brian)
52 * 1.3 - Add cmdbuf ioctl (keith)
53 * - Add support for new radeon packets (keith)
54 * - Add getparam ioctl (keith)
55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
56 * 1.4 - Add scratch registers to get_param ioctl.
57 * 1.5 - Add r200 packets to cmdbuf ioctl
58 * - Add r200 function to init ioctl
59 * - Add 'scalar2' instruction to cmdbuf
60 * 1.6 - Add static GART memory manager
61 * Add irq handler (won't be turned on unless X server knows to)
62 * Add irq ioctls and irq_active getparam.
63 * Add wait command for cmdbuf ioctl
64 * Add GART offset query for getparam
65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
66 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
70 * Add 'GET' queries for starting additional clients on different VT's.
71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
72 * Add texture rectangle support for r100.
73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
74 * clients use to tell the DRM where they think the framebuffer is
75 * located in the card's address space
76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
77 * and GL_EXT_blend_[func|equation]_separate on r200
78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
79 * (No 3D support yet - just microcode loading).
80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
81 * - Add hyperz support, add hyperz flags to clear ioctl.
82 * 1.14- Add support for color tiling
83 * - Add R100/R200 surface allocation/free support
84 * 1.15- Add support for texture micro tiling
85 * - Add support for r100 cube maps
86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
87 * texture filtering on r200
88 * 1.17- Add initial support for R300 (3D).
89 * 1.18- Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1,
90 R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs)
91 and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
92 * 1.19- Add support for gart table in FB memory and PCIE r300
95 #define DRIVER_MAJOR 1
96 #define DRIVER_MINOR 19
97 #define DRIVER_PATCHLEVEL 0
118 enum radeon_cp_microcode_version {
127 enum radeon_chip_flags {
128 CHIP_FAMILY_MASK = 0x0000ffffUL,
129 CHIP_FLAGS_MASK = 0xffff0000UL,
130 CHIP_IS_MOBILITY = 0x00010000UL,
131 CHIP_IS_IGP = 0x00020000UL,
132 CHIP_SINGLE_CRTC = 0x00040000UL,
133 CHIP_IS_AGP = 0x00080000UL,
134 CHIP_HAS_HIERZ = 0x00100000UL,
135 CHIP_IS_PCIE = 0x00200000UL,
138 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
139 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
141 typedef struct drm_radeon_freelist {
144 struct drm_radeon_freelist *next;
145 struct drm_radeon_freelist *prev;
146 } drm_radeon_freelist_t;
148 typedef struct drm_radeon_ring_buffer {
159 } drm_radeon_ring_buffer_t;
161 typedef struct drm_radeon_depth_clear_t {
163 u32 rb3d_zstencilcntl;
165 } drm_radeon_depth_clear_t;
167 struct drm_radeon_driver_file_fields {
168 int64_t radeon_fb_delta;
172 struct mem_block *next;
173 struct mem_block *prev;
176 DRMFILE filp; /* 0: free, -1: heap, other: real files */
179 struct radeon_surface {
186 struct radeon_virt_surface {
194 typedef struct drm_radeon_private {
196 drm_radeon_ring_buffer_t ring;
197 drm_radeon_sarea_t *sarea_priv;
203 unsigned long gart_buffers_offset;
208 drm_radeon_freelist_t *head;
209 drm_radeon_freelist_t *tail;
211 volatile u32 *scratch;
216 int microcode_version;
220 int freelist_timeouts;
223 int last_frame_reads;
224 int last_clear_reads;
234 unsigned int front_offset;
235 unsigned int front_pitch;
236 unsigned int back_offset;
237 unsigned int back_pitch;
240 unsigned int depth_offset;
241 unsigned int depth_pitch;
243 u32 front_pitch_offset;
244 u32 back_pitch_offset;
245 u32 depth_pitch_offset;
247 drm_radeon_depth_clear_t depth_clear;
249 unsigned long ring_offset;
250 unsigned long ring_rptr_offset;
251 unsigned long buffers_offset;
252 unsigned long gart_textures_offset;
254 drm_local_map_t *sarea;
255 drm_local_map_t *mmio;
256 drm_local_map_t *cp_ring;
257 drm_local_map_t *ring_rptr;
258 drm_local_map_t *gart_textures;
260 struct mem_block *gart_heap;
261 struct mem_block *fb_heap;
264 wait_queue_head_t swi_queue;
265 atomic_t swi_emitted;
267 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
268 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
270 unsigned long pcigart_offset;
271 drm_ati_pcigart_info gart_info;
272 /* starting from here on, data is preserved accross an open */
273 uint32_t flags; /* see radeon_chip_flags */
275 } drm_radeon_private_t;
277 typedef struct drm_radeon_buf_priv {
279 } drm_radeon_buf_priv_t;
281 extern int radeon_no_wb;
282 extern drm_ioctl_desc_t radeon_ioctls[];
283 extern int radeon_max_ioctl;
286 extern int radeon_cp_init(DRM_IOCTL_ARGS);
287 extern int radeon_cp_start(DRM_IOCTL_ARGS);
288 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
289 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
290 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
291 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
292 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
293 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
294 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
296 extern void radeon_freelist_reset(drm_device_t * dev);
297 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
299 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
301 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
303 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
304 extern int radeon_mem_free(DRM_IOCTL_ARGS);
305 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
306 extern void radeon_mem_takedown(struct mem_block **heap);
307 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
310 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
311 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
313 extern void radeon_do_release(drm_device_t * dev);
314 extern int radeon_driver_vblank_wait(drm_device_t * dev,
315 unsigned int *sequence);
316 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
317 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
318 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
319 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
321 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
322 extern int radeon_driver_unload(struct drm_device *dev);
323 extern int radeon_driver_firstopen(struct drm_device *dev);
324 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
325 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
326 extern void radeon_driver_lastclose(drm_device_t * dev);
327 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
328 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
332 extern void r300_init_reg_flags(void);
334 extern int r300_do_cp_cmdbuf( drm_device_t* dev,
336 drm_file_t* filp_priv,
337 drm_radeon_cmd_buffer_t* cmdbuf );
339 /* Flags for stats.boxes
341 #define RADEON_BOX_DMA_IDLE 0x1
342 #define RADEON_BOX_RING_FULL 0x2
343 #define RADEON_BOX_FLIP 0x4
344 #define RADEON_BOX_WAIT_IDLE 0x8
345 #define RADEON_BOX_TEXTURE_LOAD 0x10
347 /* Register definitions, register access macros and drmAddMap constants
348 * for Radeon kernel driver.
350 #define RADEON_AGP_COMMAND 0x0f60
351 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
352 # define RADEON_AGP_ENABLE (1<<8)
354 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
355 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
356 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
357 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
358 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
359 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
360 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
362 #define RADEON_BUS_CNTL 0x0030
363 # define RADEON_BUS_MASTER_DIS (1 << 6)
365 #define RADEON_CLOCK_CNTL_DATA 0x000c
366 # define RADEON_PLL_WR_EN (1 << 7)
367 #define RADEON_CLOCK_CNTL_INDEX 0x0008
368 #define RADEON_CONFIG_APER_SIZE 0x0108
369 #define RADEON_CRTC_OFFSET 0x0224
370 #define RADEON_CRTC_OFFSET_CNTL 0x0228
371 # define RADEON_CRTC_TILE_EN (1 << 15)
372 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
373 #define RADEON_CRTC2_OFFSET 0x0324
374 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
376 #define RADEON_PCIE_INDEX 0x0030
377 #define RADEON_PCIE_DATA 0x0034
378 #define RADEON_PCIE_TX_GART_CNTL 0x10
379 # define RADEON_PCIE_TX_GART_EN (1 << 0)
380 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
381 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
382 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
383 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
384 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
385 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
386 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
387 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
388 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
389 #define RADEON_PCIE_TX_GART_BASE 0x13
390 #define RADEON_PCIE_TX_GART_START_LO 0x14
391 #define RADEON_PCIE_TX_GART_START_HI 0x15
392 #define RADEON_PCIE_TX_GART_END_LO 0x16
393 #define RADEON_PCIE_TX_GART_END_HI 0x17
395 #define RADEON_MPP_TB_CONFIG 0x01c0
396 #define RADEON_MEM_CNTL 0x0140
397 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
398 #define RADEON_AGP_BASE 0x0170
400 #define RADEON_RB3D_COLOROFFSET 0x1c40
401 #define RADEON_RB3D_COLORPITCH 0x1c48
403 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
404 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
405 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
406 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
407 # define RADEON_GMC_BRUSH_NONE (15 << 4)
408 # define RADEON_GMC_DST_16BPP (4 << 8)
409 # define RADEON_GMC_DST_24BPP (5 << 8)
410 # define RADEON_GMC_DST_32BPP (6 << 8)
411 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
412 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
413 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
414 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
415 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
416 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
417 # define RADEON_ROP3_S 0x00cc0000
418 # define RADEON_ROP3_P 0x00f00000
419 #define RADEON_DP_WRITE_MASK 0x16cc
420 #define RADEON_DST_PITCH_OFFSET 0x142c
421 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
422 # define RADEON_DST_TILE_LINEAR (0 << 30)
423 # define RADEON_DST_TILE_MACRO (1 << 30)
424 # define RADEON_DST_TILE_MICRO (2 << 30)
425 # define RADEON_DST_TILE_BOTH (3 << 30)
427 #define RADEON_SCRATCH_REG0 0x15e0
428 #define RADEON_SCRATCH_REG1 0x15e4
429 #define RADEON_SCRATCH_REG2 0x15e8
430 #define RADEON_SCRATCH_REG3 0x15ec
431 #define RADEON_SCRATCH_REG4 0x15f0
432 #define RADEON_SCRATCH_REG5 0x15f4
433 #define RADEON_SCRATCH_UMSK 0x0770
434 #define RADEON_SCRATCH_ADDR 0x0774
436 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
438 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
439 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
440 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
442 #define RADEON_GEN_INT_CNTL 0x0040
443 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
444 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
445 # define RADEON_SW_INT_ENABLE (1 << 25)
447 #define RADEON_GEN_INT_STATUS 0x0044
448 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
449 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
450 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
451 # define RADEON_SW_INT_TEST (1 << 25)
452 # define RADEON_SW_INT_TEST_ACK (1 << 25)
453 # define RADEON_SW_INT_FIRE (1 << 26)
455 #define RADEON_HOST_PATH_CNTL 0x0130
456 # define RADEON_HDP_SOFT_RESET (1 << 26)
457 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
458 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
460 #define RADEON_ISYNC_CNTL 0x1724
461 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
462 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
463 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
464 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
465 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
466 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
468 #define RADEON_RBBM_GUICNTL 0x172c
469 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
470 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
471 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
472 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
474 #define RADEON_MC_AGP_LOCATION 0x014c
475 #define RADEON_MC_FB_LOCATION 0x0148
476 #define RADEON_MCLK_CNTL 0x0012
477 # define RADEON_FORCEON_MCLKA (1 << 16)
478 # define RADEON_FORCEON_MCLKB (1 << 17)
479 # define RADEON_FORCEON_YCLKA (1 << 18)
480 # define RADEON_FORCEON_YCLKB (1 << 19)
481 # define RADEON_FORCEON_MC (1 << 20)
482 # define RADEON_FORCEON_AIC (1 << 21)
484 #define RADEON_PP_BORDER_COLOR_0 0x1d40
485 #define RADEON_PP_BORDER_COLOR_1 0x1d44
486 #define RADEON_PP_BORDER_COLOR_2 0x1d48
487 #define RADEON_PP_CNTL 0x1c38
488 # define RADEON_SCISSOR_ENABLE (1 << 1)
489 #define RADEON_PP_LUM_MATRIX 0x1d00
490 #define RADEON_PP_MISC 0x1c14
491 #define RADEON_PP_ROT_MATRIX_0 0x1d58
492 #define RADEON_PP_TXFILTER_0 0x1c54
493 #define RADEON_PP_TXOFFSET_0 0x1c5c
494 #define RADEON_PP_TXFILTER_1 0x1c6c
495 #define RADEON_PP_TXFILTER_2 0x1c84
497 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
498 # define RADEON_RB2D_DC_FLUSH (3 << 0)
499 # define RADEON_RB2D_DC_FREE (3 << 2)
500 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
501 # define RADEON_RB2D_DC_BUSY (1 << 31)
502 #define RADEON_RB3D_CNTL 0x1c3c
503 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
504 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
505 # define RADEON_DITHER_ENABLE (1 << 2)
506 # define RADEON_ROUND_ENABLE (1 << 3)
507 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
508 # define RADEON_DITHER_INIT (1 << 5)
509 # define RADEON_ROP_ENABLE (1 << 6)
510 # define RADEON_STENCIL_ENABLE (1 << 7)
511 # define RADEON_Z_ENABLE (1 << 8)
512 # define RADEON_ZBLOCK16 (1 << 15)
513 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
514 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
515 #define RADEON_RB3D_DEPTHPITCH 0x1c28
516 #define RADEON_RB3D_PLANEMASK 0x1d84
517 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
518 #define RADEON_RB3D_ZCACHE_MODE 0x3250
519 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
520 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
521 # define RADEON_RB3D_ZC_FREE (1 << 2)
522 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
523 # define RADEON_RB3D_ZC_BUSY (1 << 31)
524 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
525 # define RADEON_Z_TEST_MASK (7 << 4)
526 # define RADEON_Z_TEST_ALWAYS (7 << 4)
527 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
528 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
529 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
530 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
531 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
532 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
533 # define RADEON_FORCE_Z_DIRTY (1 << 29)
534 # define RADEON_Z_WRITE_ENABLE (1 << 30)
535 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
536 #define RADEON_RBBM_SOFT_RESET 0x00f0
537 # define RADEON_SOFT_RESET_CP (1 << 0)
538 # define RADEON_SOFT_RESET_HI (1 << 1)
539 # define RADEON_SOFT_RESET_SE (1 << 2)
540 # define RADEON_SOFT_RESET_RE (1 << 3)
541 # define RADEON_SOFT_RESET_PP (1 << 4)
542 # define RADEON_SOFT_RESET_E2 (1 << 5)
543 # define RADEON_SOFT_RESET_RB (1 << 6)
544 # define RADEON_SOFT_RESET_HDP (1 << 7)
545 #define RADEON_RBBM_STATUS 0x0e40
546 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
547 # define RADEON_RBBM_ACTIVE (1 << 31)
548 #define RADEON_RE_LINE_PATTERN 0x1cd0
549 #define RADEON_RE_MISC 0x26c4
550 #define RADEON_RE_TOP_LEFT 0x26c0
551 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
552 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
553 #define RADEON_RE_STIPPLE_DATA 0x1ccc
555 #define RADEON_SCISSOR_TL_0 0x1cd8
556 #define RADEON_SCISSOR_BR_0 0x1cdc
557 #define RADEON_SCISSOR_TL_1 0x1ce0
558 #define RADEON_SCISSOR_BR_1 0x1ce4
559 #define RADEON_SCISSOR_TL_2 0x1ce8
560 #define RADEON_SCISSOR_BR_2 0x1cec
561 #define RADEON_SE_COORD_FMT 0x1c50
562 #define RADEON_SE_CNTL 0x1c4c
563 # define RADEON_FFACE_CULL_CW (0 << 0)
564 # define RADEON_BFACE_SOLID (3 << 1)
565 # define RADEON_FFACE_SOLID (3 << 3)
566 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
567 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
568 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
569 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
570 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
571 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
572 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
573 # define RADEON_FOG_SHADE_FLAT (1 << 14)
574 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
575 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
576 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
577 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
578 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
579 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
580 #define RADEON_SE_CNTL_STATUS 0x2140
581 #define RADEON_SE_LINE_WIDTH 0x1db8
582 #define RADEON_SE_VPORT_XSCALE 0x1d98
583 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
584 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
585 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
586 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
587 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
588 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
589 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
590 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
591 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
592 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
593 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
594 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
595 #define RADEON_SURFACE_CNTL 0x0b00
596 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
597 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
598 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
599 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
600 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
601 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
602 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
603 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
604 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
605 #define RADEON_SURFACE0_INFO 0x0b0c
606 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
607 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
608 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
609 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
610 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
611 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
612 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
613 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
614 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
615 #define RADEON_SURFACE1_INFO 0x0b1c
616 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
617 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
618 #define RADEON_SURFACE2_INFO 0x0b2c
619 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
620 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
621 #define RADEON_SURFACE3_INFO 0x0b3c
622 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
623 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
624 #define RADEON_SURFACE4_INFO 0x0b4c
625 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
626 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
627 #define RADEON_SURFACE5_INFO 0x0b5c
628 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
629 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
630 #define RADEON_SURFACE6_INFO 0x0b6c
631 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
632 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
633 #define RADEON_SURFACE7_INFO 0x0b7c
634 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
635 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
636 #define RADEON_SW_SEMAPHORE 0x013c
638 #define RADEON_WAIT_UNTIL 0x1720
639 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
640 # define RADEON_WAIT_2D_IDLE (1 << 14)
641 # define RADEON_WAIT_3D_IDLE (1 << 15)
642 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
643 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
644 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
646 #define RADEON_RB3D_ZMASKOFFSET 0x3234
647 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
648 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
649 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
652 #define RADEON_CP_ME_RAM_ADDR 0x07d4
653 #define RADEON_CP_ME_RAM_RADDR 0x07d8
654 #define RADEON_CP_ME_RAM_DATAH 0x07dc
655 #define RADEON_CP_ME_RAM_DATAL 0x07e0
657 #define RADEON_CP_RB_BASE 0x0700
658 #define RADEON_CP_RB_CNTL 0x0704
659 # define RADEON_BUF_SWAP_32BIT (2 << 16)
660 #define RADEON_CP_RB_RPTR_ADDR 0x070c
661 #define RADEON_CP_RB_RPTR 0x0710
662 #define RADEON_CP_RB_WPTR 0x0714
664 #define RADEON_CP_RB_WPTR_DELAY 0x0718
665 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
666 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
668 #define RADEON_CP_IB_BASE 0x0738
670 #define RADEON_CP_CSQ_CNTL 0x0740
671 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
672 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
673 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
674 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
675 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
676 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
677 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
679 #define RADEON_AIC_CNTL 0x01d0
680 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
681 #define RADEON_AIC_STAT 0x01d4
682 #define RADEON_AIC_PT_BASE 0x01d8
683 #define RADEON_AIC_LO_ADDR 0x01dc
684 #define RADEON_AIC_HI_ADDR 0x01e0
685 #define RADEON_AIC_TLB_ADDR 0x01e4
686 #define RADEON_AIC_TLB_DATA 0x01e8
688 /* CP command packets */
689 #define RADEON_CP_PACKET0 0x00000000
690 # define RADEON_ONE_REG_WR (1 << 15)
691 #define RADEON_CP_PACKET1 0x40000000
692 #define RADEON_CP_PACKET2 0x80000000
693 #define RADEON_CP_PACKET3 0xC0000000
694 # define RADEON_CP_NOP 0x00001000
695 # define RADEON_CP_NEXT_CHAR 0x00001900
696 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
697 # define RADEON_CP_SET_SCISSORS 0x00001E00
698 /* GEN_INDX_PRIM is unsupported starting with R300 */
699 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
700 # define RADEON_WAIT_FOR_IDLE 0x00002600
701 # define RADEON_3D_DRAW_VBUF 0x00002800
702 # define RADEON_3D_DRAW_IMMD 0x00002900
703 # define RADEON_3D_DRAW_INDX 0x00002A00
704 # define RADEON_CP_LOAD_PALETTE 0x00002C00
705 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
706 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
707 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
708 # define RADEON_3D_CLEAR_ZMASK 0x00003200
709 # define RADEON_CP_INDX_BUFFER 0x00003300
710 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
711 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
712 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
713 # define RADEON_3D_CLEAR_HIZ 0x00003700
714 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
715 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
716 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
717 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
718 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
720 #define RADEON_CP_PACKET_MASK 0xC0000000
721 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
722 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
723 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
724 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
726 #define RADEON_VTX_Z_PRESENT (1 << 31)
727 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
729 #define RADEON_PRIM_TYPE_NONE (0 << 0)
730 #define RADEON_PRIM_TYPE_POINT (1 << 0)
731 #define RADEON_PRIM_TYPE_LINE (2 << 0)
732 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
733 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
734 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
735 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
736 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
737 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
738 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
739 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
740 #define RADEON_PRIM_TYPE_MASK 0xf
741 #define RADEON_PRIM_WALK_IND (1 << 4)
742 #define RADEON_PRIM_WALK_LIST (2 << 4)
743 #define RADEON_PRIM_WALK_RING (3 << 4)
744 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
745 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
746 #define RADEON_MAOS_ENABLE (1 << 7)
747 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
748 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
749 #define RADEON_NUM_VERTICES_SHIFT 16
751 #define RADEON_COLOR_FORMAT_CI8 2
752 #define RADEON_COLOR_FORMAT_ARGB1555 3
753 #define RADEON_COLOR_FORMAT_RGB565 4
754 #define RADEON_COLOR_FORMAT_ARGB8888 6
755 #define RADEON_COLOR_FORMAT_RGB332 7
756 #define RADEON_COLOR_FORMAT_RGB8 9
757 #define RADEON_COLOR_FORMAT_ARGB4444 15
759 #define RADEON_TXFORMAT_I8 0
760 #define RADEON_TXFORMAT_AI88 1
761 #define RADEON_TXFORMAT_RGB332 2
762 #define RADEON_TXFORMAT_ARGB1555 3
763 #define RADEON_TXFORMAT_RGB565 4
764 #define RADEON_TXFORMAT_ARGB4444 5
765 #define RADEON_TXFORMAT_ARGB8888 6
766 #define RADEON_TXFORMAT_RGBA8888 7
767 #define RADEON_TXFORMAT_Y8 8
768 #define RADEON_TXFORMAT_VYUY422 10
769 #define RADEON_TXFORMAT_YVYU422 11
770 #define RADEON_TXFORMAT_DXT1 12
771 #define RADEON_TXFORMAT_DXT23 14
772 #define RADEON_TXFORMAT_DXT45 15
774 #define R200_PP_TXCBLEND_0 0x2f00
775 #define R200_PP_TXCBLEND_1 0x2f10
776 #define R200_PP_TXCBLEND_2 0x2f20
777 #define R200_PP_TXCBLEND_3 0x2f30
778 #define R200_PP_TXCBLEND_4 0x2f40
779 #define R200_PP_TXCBLEND_5 0x2f50
780 #define R200_PP_TXCBLEND_6 0x2f60
781 #define R200_PP_TXCBLEND_7 0x2f70
782 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
783 #define R200_PP_TFACTOR_0 0x2ee0
784 #define R200_SE_VTX_FMT_0 0x2088
785 #define R200_SE_VAP_CNTL 0x2080
786 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
787 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
788 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
789 #define R200_PP_TXFILTER_5 0x2ca0
790 #define R200_PP_TXFILTER_4 0x2c80
791 #define R200_PP_TXFILTER_3 0x2c60
792 #define R200_PP_TXFILTER_2 0x2c40
793 #define R200_PP_TXFILTER_1 0x2c20
794 #define R200_PP_TXFILTER_0 0x2c00
795 #define R200_PP_TXOFFSET_5 0x2d78
796 #define R200_PP_TXOFFSET_4 0x2d60
797 #define R200_PP_TXOFFSET_3 0x2d48
798 #define R200_PP_TXOFFSET_2 0x2d30
799 #define R200_PP_TXOFFSET_1 0x2d18
800 #define R200_PP_TXOFFSET_0 0x2d00
802 #define R200_PP_CUBIC_FACES_0 0x2c18
803 #define R200_PP_CUBIC_FACES_1 0x2c38
804 #define R200_PP_CUBIC_FACES_2 0x2c58
805 #define R200_PP_CUBIC_FACES_3 0x2c78
806 #define R200_PP_CUBIC_FACES_4 0x2c98
807 #define R200_PP_CUBIC_FACES_5 0x2cb8
808 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
809 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
810 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
811 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
812 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
813 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
814 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
815 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
816 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
817 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
818 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
819 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
820 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
821 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
822 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
823 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
824 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
825 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
826 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
827 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
828 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
829 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
830 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
831 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
832 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
833 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
834 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
835 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
836 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
837 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
839 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
840 #define R200_SE_VTE_CNTL 0x20b0
841 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
842 #define R200_PP_TAM_DEBUG3 0x2d9c
843 #define R200_PP_CNTL_X 0x2cc4
844 #define R200_SE_VAP_CNTL_STATUS 0x2140
845 #define R200_RE_SCISSOR_TL_0 0x1cd8
846 #define R200_RE_SCISSOR_TL_1 0x1ce0
847 #define R200_RE_SCISSOR_TL_2 0x1ce8
848 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
849 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
850 #define R200_SE_VTX_STATE_CNTL 0x2180
851 #define R200_RE_POINTSIZE 0x2648
852 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
854 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
855 #define RADEON_PP_TEX_SIZE_1 0x1d0c
856 #define RADEON_PP_TEX_SIZE_2 0x1d14
858 #define RADEON_PP_CUBIC_FACES_0 0x1d24
859 #define RADEON_PP_CUBIC_FACES_1 0x1d28
860 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
861 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
862 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
863 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
865 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
866 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
867 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
868 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
869 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
870 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
871 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
872 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
873 #define R200_3D_DRAW_IMMD_2 0xC0003500
874 #define R200_SE_VTX_FMT_1 0x208c
875 #define R200_RE_CNTL 0x1c50
877 #define R200_RB3D_BLENDCOLOR 0x3218
879 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
881 #define R200_PP_TRI_PERF 0x2cf8
883 #define R200_PP_AFS_0 0x2f80
884 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
886 /* MPEG settings from VHA code */
887 #define RADEON_VHA_SETTO16_1 0x2694
888 #define RADEON_VHA_SETTO16_2 0x2680
889 #define RADEON_VHA_SETTO0_1 0x1840
890 #define RADEON_VHA_FB_OFFSET 0x19e4
891 #define RADEON_VHA_SETTO1AND70S 0x19d8
892 #define RADEON_VHA_DST_PITCH 0x1408
894 // set as reference header
895 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
896 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
897 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
898 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
899 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
900 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
901 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
902 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
903 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
904 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
905 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
906 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
907 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
908 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
909 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
910 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
911 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
912 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
917 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
919 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
920 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
921 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
922 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
923 #define RADEON_LAST_DISPATCH 1
925 #define RADEON_MAX_VB_AGE 0x7fffffff
926 #define RADEON_MAX_VB_VERTS (0xffff)
928 #define RADEON_RING_HIGH_MARK 128
930 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
932 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
933 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
934 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
935 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
937 #define RADEON_WRITE_PLL( addr, val ) \
939 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
940 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
941 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
944 #define RADEON_WRITE_PCIE( addr, val ) \
946 RADEON_WRITE8( RADEON_PCIE_INDEX, \
948 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
951 #define CP_PACKET0( reg, n ) \
952 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
953 #define CP_PACKET0_TABLE( reg, n ) \
954 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
955 #define CP_PACKET1( reg0, reg1 ) \
956 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
957 #define CP_PACKET2() \
959 #define CP_PACKET3( pkt, n ) \
960 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
962 /* ================================================================
963 * Engine control helper macros
966 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
967 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
968 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
969 RADEON_WAIT_HOST_IDLECLEAN) ); \
972 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
973 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
974 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
975 RADEON_WAIT_HOST_IDLECLEAN) ); \
978 #define RADEON_WAIT_UNTIL_IDLE() do { \
979 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
980 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
981 RADEON_WAIT_3D_IDLECLEAN | \
982 RADEON_WAIT_HOST_IDLECLEAN) ); \
985 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
986 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
987 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
990 #define RADEON_FLUSH_CACHE() do { \
991 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
992 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
995 #define RADEON_PURGE_CACHE() do { \
996 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
997 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
1000 #define RADEON_FLUSH_ZCACHE() do { \
1001 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1002 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1005 #define RADEON_PURGE_ZCACHE() do { \
1006 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1007 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1010 /* ================================================================
1011 * Misc helper macros
1014 /* Perfbox functionality only.
1016 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1018 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1019 u32 head = GET_RING_HEAD( dev_priv ); \
1020 if (head == dev_priv->ring.tail) \
1021 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1025 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1027 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1028 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1029 int __ret = radeon_do_cp_idle( dev_priv ); \
1030 if ( __ret ) return __ret; \
1031 sarea_priv->last_dispatch = 0; \
1032 radeon_freelist_reset( dev ); \
1036 #define RADEON_DISPATCH_AGE( age ) do { \
1037 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1041 #define RADEON_FRAME_AGE( age ) do { \
1042 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1046 #define RADEON_CLEAR_AGE( age ) do { \
1047 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1051 /* ================================================================
1055 #define RADEON_VERBOSE 0
1057 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1059 #define BEGIN_RING( n ) do { \
1060 if ( RADEON_VERBOSE ) { \
1061 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1062 n, __FUNCTION__ ); \
1064 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1066 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1068 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1069 ring = dev_priv->ring.start; \
1070 write = dev_priv->ring.tail; \
1071 mask = dev_priv->ring.tail_mask; \
1074 #define ADVANCE_RING() do { \
1075 if ( RADEON_VERBOSE ) { \
1076 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1077 write, dev_priv->ring.tail ); \
1079 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1081 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1082 ((dev_priv->ring.tail + _nr) & mask), \
1085 dev_priv->ring.tail = write; \
1088 #define COMMIT_RING() do { \
1089 /* Flush writes to ring */ \
1090 DRM_MEMORYBARRIER(); \
1091 GET_RING_HEAD( dev_priv ); \
1092 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1093 /* read from PCI bus to ensure correct posting */ \
1094 RADEON_READ( RADEON_CP_RB_RPTR ); \
1097 #define OUT_RING( x ) do { \
1098 if ( RADEON_VERBOSE ) { \
1099 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1100 (unsigned int)(x), write ); \
1102 ring[write++] = (x); \
1106 #define OUT_RING_REG( reg, val ) do { \
1107 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1111 #define OUT_RING_TABLE( tab, sz ) do { \
1113 int *_tab = (int *)(tab); \
1115 if (write + _size > mask) { \
1116 int _i = (mask+1) - write; \
1119 *(int *)(ring + write) = *_tab++; \
1126 while (_size > 0) { \
1127 *(ring + write) = *_tab++; \
1134 #endif /* __RADEON_DRV_H__ */