sys/dev/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*-
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 #include "dev/drm/drmP.h"
  36 #include "dev/drm/drm.h"
  37 #include "dev/drm/radeon_drm.h"
  38 #include "dev/drm/radeon_drv.h"
  39
  40 /* Interrupts - Used for device synchronization and flushing in the
  41  * following circumstances:
  42  *
  43  * - Exclusive FB access with hw idle:
  44  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
  45  *
  46  * - Frame throttling, NV_fence:
  47  *    - Drop marker irq's into command stream ahead of time.
  48  *    - Wait on irq's with lock *not held*
  49  *    - Check each for termination condition
  50  *
  51  * - Internally in cp_getbuffer, etc:
  52  *    - as above, but wait with lock held???
  53  *
  54  * NOTE: These functions are misleadingly named -- the irq's aren't
  55  * tied to dma at all, this is just a hangover from dri prehistory.
  56  */
  57
  58 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
  59 {
  60         drm_device_t *dev = (drm_device_t *) arg;
  61         drm_radeon_private_t *dev_priv =
  62             (drm_radeon_private_t *) dev->dev_private;
  63         u32 stat;
  64
  65         /* Only consider the bits we're interested in - others could be used
  66          * outside the DRM
  67          */
  68         stat = RADEON_READ(RADEON_GEN_INT_STATUS)
  69             & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
  70         if (!stat)
  71                 return IRQ_NONE;
  72
  73         /* SW interrupt */
  74         if (stat & RADEON_SW_INT_TEST) {
  75                 DRM_WAKEUP(&dev_priv->swi_queue);
  76         }
  77
  78         /* VBLANK interrupt */
  79         if (stat & RADEON_CRTC_VBLANK_STAT) {
  80                 atomic_inc(&dev->vbl_received);
  81                 DRM_WAKEUP(&dev->vbl_queue);
  82                 drm_vbl_send_signals(dev);
  83         }
  84
  85         /* Acknowledge interrupts we handle */
  86         RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
  87         return IRQ_HANDLED;
  88 }
  89
  90 static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv)
  91 {
  92         u32 tmp = RADEON_READ(RADEON_GEN_INT_STATUS)
  93             & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
  94         if (tmp)
  95                 RADEON_WRITE(RADEON_GEN_INT_STATUS, tmp);
  96 }
  97
  98 static int radeon_emit_irq(drm_device_t * dev)
  99 {
 100         drm_radeon_private_t *dev_priv = dev->dev_private;
 101         unsigned int ret;
 102         RING_LOCALS;
 103
 104         atomic_inc(&dev_priv->swi_emitted);
 105         ret = atomic_read(&dev_priv->swi_emitted);
 106
 107         BEGIN_RING(4);
 108         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 109         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 110         ADVANCE_RING();
 111         COMMIT_RING();
 112
 113         return ret;
 114 }
 115
 116 static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
 117 {
 118         drm_radeon_private_t *dev_priv =
 119             (drm_radeon_private_t *) dev->dev_private;
 120         int ret = 0;
 121
 122         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 123                 return 0;
 124
 125         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 126
 127         /* This is a hack to work around mysterious freezes on certain
 128          * systems:
 129          */
 130         radeon_acknowledge_irqs(dev_priv);
 131
 132         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 133                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 134
 135         return ret;
 136 }
 137
 138 int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
 139 {
 140         drm_radeon_private_t *dev_priv =
 141             (drm_radeon_private_t *) dev->dev_private;
 142         unsigned int cur_vblank;
 143         int ret = 0;
 144
 145         if (!dev_priv) {
 146                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 147                 return DRM_ERR(EINVAL);
 148         }
 149
 150         radeon_acknowledge_irqs(dev_priv);
 151
 152         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 153
 154         /* Assume that the user has missed the current sequence number
 155          * by about a day rather than she wants to wait for years
 156          * using vertical blanks...
 157          */
 158         DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
 159                     (((cur_vblank = atomic_read(&dev->vbl_received))
 160                       - *sequence) <= (1 << 23)));
 161
 162         *sequence = cur_vblank;
 163
 164         return ret;
 165 }
 166
 167 /* Needs the lock as it touches the ring.
 168  */
 169 int radeon_irq_emit(DRM_IOCTL_ARGS)
 170 {
 171         DRM_DEVICE;
 172         drm_radeon_private_t *dev_priv = dev->dev_private;
 173         drm_radeon_irq_emit_t emit;
 174         int result;
 175
 176         LOCK_TEST_WITH_RETURN(dev, filp);
 177
 178         if (!dev_priv) {
 179                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 180                 return DRM_ERR(EINVAL);
 181         }
 182
 183         DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data,
 184                                  sizeof(emit));
 185
 186         result = radeon_emit_irq(dev);
 187
 188         if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
 189                 DRM_ERROR("copy_to_user\n");
 190                 return DRM_ERR(EFAULT);
 191         }
 192
 193         return 0;
 194 }
 195
 196 /* Doesn't need the hardware lock.
 197  */
 198 int radeon_irq_wait(DRM_IOCTL_ARGS)
 199 {
 200         DRM_DEVICE;
 201         drm_radeon_private_t *dev_priv = dev->dev_private;
 202         drm_radeon_irq_wait_t irqwait;
 203
 204         if (!dev_priv) {
 205                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 206                 return DRM_ERR(EINVAL);
 207         }
 208
 209         DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data,
 210                                  sizeof(irqwait));
 211
 212         return radeon_wait_irq(dev, irqwait.irq_seq);
 213 }
 214
 215 /* drm_dma.h hooks
 216 */
 217 void radeon_driver_irq_preinstall(drm_device_t * dev)
 218 {
 219         drm_radeon_private_t *dev_priv =
 220             (drm_radeon_private_t *) dev->dev_private;
 221
 222         /* Disable *all* interrupts */
 223         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 224
 225         /* Clear bits if they're already high */
 226         radeon_acknowledge_irqs(dev_priv);
 227 }
 228
 229 void radeon_driver_irq_postinstall(drm_device_t * dev)
 230 {
 231         drm_radeon_private_t *dev_priv =
 232             (drm_radeon_private_t *) dev->dev_private;
 233
 234         atomic_set(&dev_priv->swi_emitted, 0);
 235         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 236
 237         /* Turn on SW and VBL ints */
 238         RADEON_WRITE(RADEON_GEN_INT_CNTL,
 239                      RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
 240 }
 241
 242 void radeon_driver_irq_uninstall(drm_device_t * dev)
 243 {
 244         drm_radeon_private_t *dev_priv =
 245             (drm_radeon_private_t *) dev->dev_private;
 246         if (!dev_priv)
 247                 return;
 248
 249         /* Disable *all* interrupts */
 250         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 251 }