1 /* radeon_state.c -- State support for Radeon -*- linux-c -*-
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
33 #define __NO_VERSION__
34 #include <linux/delay.h>
35 #endif /* __linux__ */
36 #include "dev/drm/radeon.h"
37 #include "dev/drm/drmP.h"
38 #include "dev/drm/radeon_drm.h"
39 #include "dev/drm/radeon_drv.h"
40 #include "dev/drm/drm.h"
43 /* ================================================================
44 * CP hardware state programming functions
47 static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
48 drm_clip_rect_t *box )
52 DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n",
53 box->x1, box->y1, box->x2, box->y2 );
57 OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
58 OUT_RING( (box->y1 << 16) | box->x1 );
60 OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
61 OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
66 static __inline__ void radeon_emit_context( drm_radeon_private_t *dev_priv )
68 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
69 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
71 DRM_DEBUG( " %s\n", __func__ );
75 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
76 OUT_RING( ctx->pp_misc );
77 OUT_RING( ctx->pp_fog_color );
78 OUT_RING( ctx->re_solid_color );
79 OUT_RING( ctx->rb3d_blendcntl );
80 OUT_RING( ctx->rb3d_depthoffset );
81 OUT_RING( ctx->rb3d_depthpitch );
82 OUT_RING( ctx->rb3d_zstencilcntl );
84 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
85 OUT_RING( ctx->pp_cntl );
86 OUT_RING( ctx->rb3d_cntl );
87 OUT_RING( ctx->rb3d_coloroffset );
89 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
90 OUT_RING( ctx->rb3d_colorpitch );
95 static __inline__ void radeon_emit_vertfmt( drm_radeon_private_t *dev_priv )
97 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
98 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
100 DRM_DEBUG( " %s\n", __func__ );
104 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
105 OUT_RING( ctx->se_coord_fmt );
110 static __inline__ void radeon_emit_line( drm_radeon_private_t *dev_priv )
112 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
113 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
115 DRM_DEBUG( " %s\n", __func__ );
119 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
120 OUT_RING( ctx->re_line_pattern );
121 OUT_RING( ctx->re_line_state );
123 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
124 OUT_RING( ctx->se_line_width );
129 static __inline__ void radeon_emit_bumpmap( drm_radeon_private_t *dev_priv )
131 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
132 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
134 DRM_DEBUG( " %s\n", __func__ );
138 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
139 OUT_RING( ctx->pp_lum_matrix );
141 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
142 OUT_RING( ctx->pp_rot_matrix_0 );
143 OUT_RING( ctx->pp_rot_matrix_1 );
148 static __inline__ void radeon_emit_masks( drm_radeon_private_t *dev_priv )
150 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
151 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
153 DRM_DEBUG( " %s\n", __func__ );
157 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
158 OUT_RING( ctx->rb3d_stencilrefmask );
159 OUT_RING( ctx->rb3d_ropcntl );
160 OUT_RING( ctx->rb3d_planemask );
165 static __inline__ void radeon_emit_viewport( drm_radeon_private_t *dev_priv )
167 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
168 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
170 DRM_DEBUG( " %s\n", __func__ );
174 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
175 OUT_RING( ctx->se_vport_xscale );
176 OUT_RING( ctx->se_vport_xoffset );
177 OUT_RING( ctx->se_vport_yscale );
178 OUT_RING( ctx->se_vport_yoffset );
179 OUT_RING( ctx->se_vport_zscale );
180 OUT_RING( ctx->se_vport_zoffset );
185 static __inline__ void radeon_emit_setup( drm_radeon_private_t *dev_priv )
187 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
188 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
190 DRM_DEBUG( " %s\n", __func__ );
194 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
195 OUT_RING( ctx->se_cntl );
196 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
197 OUT_RING( ctx->se_cntl_status );
202 static __inline__ void radeon_emit_tcl( drm_radeon_private_t *dev_priv )
205 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
208 DRM_DEBUG( " %s\n", __func__ );
212 OUT_RING( CP_PACKET0( RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 27 ) );
213 OUT_RING( ctx->se_tcl_material_emmissive.red );
214 OUT_RING( ctx->se_tcl_material_emmissive.green );
215 OUT_RING( ctx->se_tcl_material_emmissive.blue );
216 OUT_RING( ctx->se_tcl_material_emmissive.alpha );
217 OUT_RING( ctx->se_tcl_material_ambient.red );
218 OUT_RING( ctx->se_tcl_material_ambient.green );
219 OUT_RING( ctx->se_tcl_material_ambient.blue );
220 OUT_RING( ctx->se_tcl_material_ambient.alpha );
221 OUT_RING( ctx->se_tcl_material_diffuse.red );
222 OUT_RING( ctx->se_tcl_material_diffuse.green );
223 OUT_RING( ctx->se_tcl_material_diffuse.blue );
224 OUT_RING( ctx->se_tcl_material_diffuse.alpha );
225 OUT_RING( ctx->se_tcl_material_specular.red );
226 OUT_RING( ctx->se_tcl_material_specular.green );
227 OUT_RING( ctx->se_tcl_material_specular.blue );
228 OUT_RING( ctx->se_tcl_material_specular.alpha );
229 OUT_RING( ctx->se_tcl_shininess );
230 OUT_RING( ctx->se_tcl_output_vtx_fmt );
231 OUT_RING( ctx->se_tcl_output_vtx_sel );
232 OUT_RING( ctx->se_tcl_matrix_select_0 );
233 OUT_RING( ctx->se_tcl_matrix_select_1 );
234 OUT_RING( ctx->se_tcl_ucp_vert_blend_ctl );
235 OUT_RING( ctx->se_tcl_texture_proc_ctl );
236 OUT_RING( ctx->se_tcl_light_model_ctl );
237 for ( i = 0 ; i < 4 ; i++ ) {
238 OUT_RING( ctx->se_tcl_per_light_ctl[i] );
243 DRM_ERROR( "TCL not enabled!\n" );
247 static __inline__ void radeon_emit_misc( drm_radeon_private_t *dev_priv )
249 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
250 drm_radeon_context_regs_t *ctx = &sarea_priv->context_state;
252 DRM_DEBUG( " %s\n", __func__ );
256 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
257 OUT_RING( ctx->re_misc );
262 static __inline__ void radeon_emit_tex0( drm_radeon_private_t *dev_priv )
264 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
265 drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[0];
267 DRM_DEBUG( " %s: offset=0x%x\n", __func__, tex->pp_txoffset );
271 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
272 OUT_RING( tex->pp_txfilter );
273 OUT_RING( tex->pp_txformat );
274 OUT_RING( tex->pp_txoffset );
275 OUT_RING( tex->pp_txcblend );
276 OUT_RING( tex->pp_txablend );
277 OUT_RING( tex->pp_tfactor );
279 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
280 OUT_RING( tex->pp_border_color );
285 static __inline__ void radeon_emit_tex1( drm_radeon_private_t *dev_priv )
287 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
288 drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[1];
290 DRM_DEBUG( " %s: offset=0x%x\n", __func__, tex->pp_txoffset );
294 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
295 OUT_RING( tex->pp_txfilter );
296 OUT_RING( tex->pp_txformat );
297 OUT_RING( tex->pp_txoffset );
298 OUT_RING( tex->pp_txcblend );
299 OUT_RING( tex->pp_txablend );
300 OUT_RING( tex->pp_tfactor );
302 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
303 OUT_RING( tex->pp_border_color );
308 static __inline__ void radeon_emit_tex2( drm_radeon_private_t *dev_priv )
310 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
311 drm_radeon_texture_regs_t *tex = &sarea_priv->tex_state[2];
313 DRM_DEBUG( " %s\n", __func__ );
317 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
318 OUT_RING( tex->pp_txfilter );
319 OUT_RING( tex->pp_txformat );
320 OUT_RING( tex->pp_txoffset );
321 OUT_RING( tex->pp_txcblend );
322 OUT_RING( tex->pp_txablend );
323 OUT_RING( tex->pp_tfactor );
325 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
326 OUT_RING( tex->pp_border_color );
331 static __inline__ void radeon_emit_state( drm_radeon_private_t *dev_priv )
333 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
334 unsigned int dirty = sarea_priv->dirty;
336 DRM_DEBUG( "%s: dirty=0x%08x\n", __func__, dirty );
338 if ( dirty & RADEON_UPLOAD_CONTEXT ) {
339 radeon_emit_context( dev_priv );
340 sarea_priv->dirty &= ~RADEON_UPLOAD_CONTEXT;
343 if ( dirty & RADEON_UPLOAD_VERTFMT ) {
344 radeon_emit_vertfmt( dev_priv );
345 sarea_priv->dirty &= ~RADEON_UPLOAD_VERTFMT;
348 if ( dirty & RADEON_UPLOAD_LINE ) {
349 radeon_emit_line( dev_priv );
350 sarea_priv->dirty &= ~RADEON_UPLOAD_LINE;
353 if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
354 radeon_emit_bumpmap( dev_priv );
355 sarea_priv->dirty &= ~RADEON_UPLOAD_BUMPMAP;
358 if ( dirty & RADEON_UPLOAD_MASKS ) {
359 radeon_emit_masks( dev_priv );
360 sarea_priv->dirty &= ~RADEON_UPLOAD_MASKS;
363 if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
364 radeon_emit_viewport( dev_priv );
365 sarea_priv->dirty &= ~RADEON_UPLOAD_VIEWPORT;
368 if ( dirty & RADEON_UPLOAD_SETUP ) {
369 radeon_emit_setup( dev_priv );
370 sarea_priv->dirty &= ~RADEON_UPLOAD_SETUP;
373 if ( dirty & RADEON_UPLOAD_TCL ) {
375 radeon_emit_tcl( dev_priv );
377 sarea_priv->dirty &= ~RADEON_UPLOAD_TCL;
380 if ( dirty & RADEON_UPLOAD_MISC ) {
381 radeon_emit_misc( dev_priv );
382 sarea_priv->dirty &= ~RADEON_UPLOAD_MISC;
385 if ( dirty & RADEON_UPLOAD_TEX0 ) {
386 radeon_emit_tex0( dev_priv );
387 sarea_priv->dirty &= ~RADEON_UPLOAD_TEX0;
390 if ( dirty & RADEON_UPLOAD_TEX1 ) {
391 radeon_emit_tex1( dev_priv );
392 sarea_priv->dirty &= ~RADEON_UPLOAD_TEX1;
395 if ( dirty & RADEON_UPLOAD_TEX2 ) {
397 radeon_emit_tex2( dev_priv );
399 sarea_priv->dirty &= ~RADEON_UPLOAD_TEX2;
402 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
403 RADEON_UPLOAD_TEX1IMAGES |
404 RADEON_UPLOAD_TEX2IMAGES |
405 RADEON_REQUIRE_QUIESCENCE);
409 #if RADEON_PERFORMANCE_BOXES
410 /* ================================================================
411 * Performance monitoring functions
414 static void radeon_clear_box( drm_radeon_private_t *dev_priv,
415 int x, int y, int w, int h,
416 int r, int g, int b )
422 switch ( dev_priv->color_fmt ) {
423 case RADEON_COLOR_FORMAT_RGB565:
424 color = (((r & 0xf8) << 8) |
428 case RADEON_COLOR_FORMAT_ARGB8888:
430 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
434 offset = dev_priv->back_offset;
435 pitch = dev_priv->back_pitch >> 3;
439 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
440 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
441 RADEON_GMC_BRUSH_SOLID_COLOR |
442 (dev_priv->color_fmt << 8) |
443 RADEON_GMC_SRC_DATATYPE_COLOR |
445 RADEON_GMC_CLR_CMP_CNTL_DIS );
447 OUT_RING( (pitch << 22) | (offset >> 5) );
450 OUT_RING( (x << 16) | y );
451 OUT_RING( (w << 16) | h );
456 static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
458 if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
459 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
461 atomic_set( &dev_priv->idle_count, 0 );
468 /* ================================================================
469 * CP command dispatch functions
472 static void radeon_print_dirty( const char *msg, unsigned int flags )
474 DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
477 (flags & RADEON_UPLOAD_CONTEXT) ? "context, " : "",
478 (flags & RADEON_UPLOAD_VERTFMT) ? "vertfmt, " : "",
479 (flags & RADEON_UPLOAD_LINE) ? "line, " : "",
480 (flags & RADEON_UPLOAD_BUMPMAP) ? "bumpmap, " : "",
481 (flags & RADEON_UPLOAD_MASKS) ? "masks, " : "",
482 (flags & RADEON_UPLOAD_VIEWPORT) ? "viewport, " : "",
483 (flags & RADEON_UPLOAD_SETUP) ? "setup, " : "",
484 (flags & RADEON_UPLOAD_TCL) ? "tcl, " : "",
485 (flags & RADEON_UPLOAD_MISC) ? "misc, " : "",
486 (flags & RADEON_UPLOAD_TEX0) ? "tex0, " : "",
487 (flags & RADEON_UPLOAD_TEX1) ? "tex1, " : "",
488 (flags & RADEON_UPLOAD_TEX2) ? "tex2, " : "",
489 (flags & RADEON_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
490 (flags & RADEON_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
493 static void radeon_cp_dispatch_clear( drm_device_t *dev,
494 drm_radeon_clear_t *clear,
495 drm_radeon_clear_rect_t *depth_boxes )
497 drm_radeon_private_t *dev_priv = dev->dev_private;
498 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
499 int nbox = sarea_priv->nbox;
500 drm_clip_rect_t *pbox = sarea_priv->boxes;
501 unsigned int flags = clear->flags;
504 DRM_DEBUG( "%s\n", __func__ );
506 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
507 unsigned int tmp = flags;
509 flags &= ~(RADEON_FRONT | RADEON_BACK);
510 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
511 if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT;
514 for ( i = 0 ; i < nbox ; i++ ) {
517 int w = pbox[i].x2 - x;
518 int h = pbox[i].y2 - y;
520 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
523 if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
526 /* Ensure the 3D stream is idle before doing a
527 * 2D fill to clear the front or back buffer.
529 RADEON_WAIT_UNTIL_3D_IDLE();
531 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
532 OUT_RING( clear->color_mask );
536 /* Make sure we restore the 3D state next time.
538 dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
539 RADEON_UPLOAD_MASKS);
542 if ( flags & RADEON_FRONT ) {
545 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
546 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
547 RADEON_GMC_BRUSH_SOLID_COLOR |
548 (dev_priv->color_fmt << 8) |
549 RADEON_GMC_SRC_DATATYPE_COLOR |
551 RADEON_GMC_CLR_CMP_CNTL_DIS );
553 OUT_RING( dev_priv->front_pitch_offset );
554 OUT_RING( clear->clear_color );
556 OUT_RING( (x << 16) | y );
557 OUT_RING( (w << 16) | h );
562 if ( flags & RADEON_BACK ) {
565 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
566 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
567 RADEON_GMC_BRUSH_SOLID_COLOR |
568 (dev_priv->color_fmt << 8) |
569 RADEON_GMC_SRC_DATATYPE_COLOR |
571 RADEON_GMC_CLR_CMP_CNTL_DIS );
573 OUT_RING( dev_priv->back_pitch_offset );
574 OUT_RING( clear->clear_color );
576 OUT_RING( (x << 16) | y );
577 OUT_RING( (w << 16) | h );
583 if ( flags & RADEON_DEPTH ) {
584 drm_radeon_depth_clear_t *depth_clear =
585 &dev_priv->depth_clear;
587 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
588 radeon_emit_state( dev_priv );
591 /* FIXME: Render a rectangle to clear the depth
592 * buffer. So much for those "fast Z clears"...
596 RADEON_WAIT_UNTIL_2D_IDLE();
598 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
599 OUT_RING( 0x00000000 );
600 OUT_RING( depth_clear->rb3d_cntl );
601 OUT_RING( CP_PACKET0( RADEON_RB3D_ZSTENCILCNTL, 0 ) );
602 OUT_RING( depth_clear->rb3d_zstencilcntl );
603 OUT_RING( CP_PACKET0( RADEON_RB3D_PLANEMASK, 0 ) );
604 OUT_RING( 0x00000000 );
605 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
606 OUT_RING( depth_clear->se_cntl );
608 OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
609 OUT_RING( RADEON_VTX_Z_PRESENT );
610 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
611 RADEON_PRIM_WALK_RING |
613 RADEON_VTX_FMT_RADEON_MODE |
614 (3 << RADEON_NUM_VERTICES_SHIFT)) );
616 OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
617 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
618 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
620 OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
621 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
622 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
624 OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
625 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
626 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
630 /* Make sure we restore the 3D state next time.
632 dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
633 RADEON_UPLOAD_SETUP |
634 RADEON_UPLOAD_MASKS);
638 /* Increment the clear counter. The client-side 3D driver must
639 * wait on this value before performing the clear ioctl. We
640 * need this because the card's so damned fast...
642 dev_priv->sarea_priv->last_clear++;
646 RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
647 RADEON_WAIT_UNTIL_IDLE();
652 static void radeon_cp_dispatch_swap( drm_device_t *dev )
654 drm_radeon_private_t *dev_priv = dev->dev_private;
655 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
656 int nbox = sarea_priv->nbox;
657 drm_clip_rect_t *pbox = sarea_priv->boxes;
660 DRM_DEBUG( "%s\n", __func__ );
662 #if RADEON_PERFORMANCE_BOXES
663 /* Do some trivial performance monitoring...
665 radeon_cp_performance_boxes( dev_priv );
668 /* Wait for the 3D stream to idle before dispatching the bitblt.
669 * This will prevent data corruption between the two streams.
673 RADEON_WAIT_UNTIL_3D_IDLE();
677 for ( i = 0 ; i < nbox ; i++ ) {
680 int w = pbox[i].x2 - x;
681 int h = pbox[i].y2 - y;
683 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
688 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
689 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
690 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
691 RADEON_GMC_BRUSH_NONE |
692 (dev_priv->color_fmt << 8) |
693 RADEON_GMC_SRC_DATATYPE_COLOR |
695 RADEON_DP_SRC_SOURCE_MEMORY |
696 RADEON_GMC_CLR_CMP_CNTL_DIS |
697 RADEON_GMC_WR_MSK_DIS );
699 OUT_RING( dev_priv->back_pitch_offset );
700 OUT_RING( dev_priv->front_pitch_offset );
702 OUT_RING( (x << 16) | y );
703 OUT_RING( (x << 16) | y );
704 OUT_RING( (w << 16) | h );
709 /* Increment the frame counter. The client-side 3D driver must
710 * throttle the framerate by waiting for this value before
711 * performing the swapbuffer ioctl.
713 dev_priv->sarea_priv->last_frame++;
717 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
718 RADEON_WAIT_UNTIL_2D_IDLE();
723 static void radeon_cp_dispatch_flip( drm_device_t *dev )
725 drm_radeon_private_t *dev_priv = dev->dev_private;
727 DRM_DEBUG( "%s: page=%d\n", __func__, dev_priv->current_page );
729 #if RADEON_PERFORMANCE_BOXES
730 /* Do some trivial performance monitoring...
732 radeon_cp_performance_boxes( dev_priv );
737 RADEON_WAIT_UNTIL_3D_IDLE();
738 RADEON_WAIT_UNTIL_PAGE_FLIPPED();
740 OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
742 if ( dev_priv->current_page == 0 ) {
743 OUT_RING( dev_priv->back_offset );
744 dev_priv->current_page = 1;
746 OUT_RING( dev_priv->front_offset );
747 dev_priv->current_page = 0;
752 /* Increment the frame counter. The client-side 3D driver must
753 * throttle the framerate by waiting for this value before
754 * performing the swapbuffer ioctl.
756 dev_priv->sarea_priv->last_frame++;
760 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
765 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
768 drm_radeon_private_t *dev_priv = dev->dev_private;
769 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
770 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
771 int format = sarea_priv->vc_format;
772 int offset = dev_priv->agp_buffers_offset + buf->offset;
773 int size = buf->used;
774 int prim = buf_priv->prim;
777 DRM_DEBUG( "%s: nbox=%d\n", __func__, sarea_priv->nbox );
780 radeon_print_dirty( "dispatch_vertex", sarea_priv->dirty );
783 buf_priv->dispatched = 1;
785 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
786 radeon_emit_state( dev_priv );
790 /* Emit the next set of up to three cliprects */
791 if ( i < sarea_priv->nbox ) {
792 radeon_emit_clip_rect( dev_priv,
793 &sarea_priv->boxes[i] );
796 /* Emit the vertex buffer rendering commands */
799 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
803 OUT_RING( prim | RADEON_PRIM_WALK_LIST |
804 RADEON_COLOR_ORDER_RGBA |
805 RADEON_VTX_FMT_RADEON_MODE |
806 (size << RADEON_NUM_VERTICES_SHIFT) );
811 } while ( i < sarea_priv->nbox );
814 if ( buf_priv->discard ) {
815 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
817 /* Emit the vertex buffer age */
819 RADEON_DISPATCH_AGE( buf_priv->age );
824 /* FIXME: Check dispatched field */
825 buf_priv->dispatched = 0;
828 dev_priv->sarea_priv->last_dispatch++;
830 sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS;
831 sarea_priv->nbox = 0;
835 static void radeon_cp_dispatch_indirect( drm_device_t *dev,
839 drm_radeon_private_t *dev_priv = dev->dev_private;
840 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
842 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
843 buf->idx, start, end );
845 if ( start != end ) {
846 int offset = (dev_priv->agp_buffers_offset
847 + buf->offset + start);
848 int dwords = (end - start + 3) / sizeof(u32);
850 /* Indirect buffer data must be an even number of
851 * dwords, so if we've been given an odd number we must
852 * pad the data with a Type-2 CP packet.
856 ((char *)dev_priv->buffers->handle
857 + buf->offset + start);
858 data[dwords++] = RADEON_CP_PACKET2;
861 buf_priv->dispatched = 1;
863 /* Fire off the indirect buffer */
866 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
873 if ( buf_priv->discard ) {
874 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
876 /* Emit the indirect buffer age */
878 RADEON_DISPATCH_AGE( buf_priv->age );
883 /* FIXME: Check dispatched field */
884 buf_priv->dispatched = 0;
887 dev_priv->sarea_priv->last_dispatch++;
890 static void radeon_cp_dispatch_indices( drm_device_t *dev,
895 drm_radeon_private_t *dev_priv = dev->dev_private;
896 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
897 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
898 int format = sarea_priv->vc_format;
899 int offset = dev_priv->agp_buffers_offset;
900 int prim = buf_priv->prim;
905 DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
908 radeon_print_dirty( "dispatch_indices", sarea_priv->dirty );
910 if ( start != end ) {
911 buf_priv->dispatched = 1;
913 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
914 radeon_emit_state( dev_priv );
917 dwords = (end - start + 3) / sizeof(u32);
919 data = (u32 *)((char *)dev_priv->buffers->handle
920 + buf->offset + start);
922 data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
925 data[2] = RADEON_MAX_VB_VERTS;
927 data[4] = (prim | RADEON_PRIM_WALK_IND |
928 RADEON_COLOR_ORDER_RGBA |
929 RADEON_VTX_FMT_RADEON_MODE |
930 (count << RADEON_NUM_VERTICES_SHIFT) );
933 data[dwords-1] &= 0x0000ffff;
937 /* Emit the next set of up to three cliprects */
938 if ( i < sarea_priv->nbox ) {
939 radeon_emit_clip_rect( dev_priv,
940 &sarea_priv->boxes[i] );
943 radeon_cp_dispatch_indirect( dev, buf, start, end );
946 } while ( i < sarea_priv->nbox );
949 if ( buf_priv->discard ) {
950 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
952 /* Emit the vertex buffer age */
954 RADEON_DISPATCH_AGE( buf_priv->age );
958 /* FIXME: Check dispatched field */
959 buf_priv->dispatched = 0;
962 dev_priv->sarea_priv->last_dispatch++;
964 sarea_priv->dirty &= ~RADEON_UPLOAD_CLIPRECTS;
965 sarea_priv->nbox = 0;
968 #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
970 static int radeon_cp_dispatch_texture( drm_device_t *dev,
971 drm_radeon_texture_t *tex,
972 drm_radeon_tex_image_t *image, int pid )
974 drm_radeon_private_t *dev_priv = dev->dev_private;
976 drm_radeon_buf_priv_t *buf_priv;
980 int size, dwords, tex_width, blit_width;
985 /* FIXME: Be smarter about this...
987 buf = radeon_freelist_get( dev );
988 if ( !buf ) return DRM_OS_ERR(EAGAIN);
990 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
991 tex->offset >> 10, tex->pitch, tex->format,
992 image->x, image->y, image->width, image->height );
994 buf_priv = buf->dev_private;
996 /* The compiler won't optimize away a division by a variable,
997 * even if the only legal values are powers of two. Thus, we'll
998 * use a shift instead.
1000 switch ( tex->format ) {
1001 case RADEON_TXFORMAT_ARGB8888:
1002 case RADEON_TXFORMAT_RGBA8888:
1003 format = RADEON_COLOR_FORMAT_ARGB8888;
1004 tex_width = tex->width * 4;
1005 blit_width = image->width * 4;
1007 case RADEON_TXFORMAT_AI88:
1008 case RADEON_TXFORMAT_ARGB1555:
1009 case RADEON_TXFORMAT_RGB565:
1010 case RADEON_TXFORMAT_ARGB4444:
1011 format = RADEON_COLOR_FORMAT_RGB565;
1012 tex_width = tex->width * 2;
1013 blit_width = image->width * 2;
1015 case RADEON_TXFORMAT_I8:
1016 case RADEON_TXFORMAT_RGB332:
1017 format = RADEON_COLOR_FORMAT_CI8;
1018 tex_width = tex->width * 1;
1019 blit_width = image->width * 1;
1022 DRM_ERROR( "invalid texture format %d\n", tex->format );
1023 return DRM_OS_ERR(EINVAL);
1026 DRM_DEBUG( " tex=%dx%d blit=%d\n",
1027 tex_width, tex->height, blit_width );
1029 /* Flush the pixel cache. This ensures no pixel data gets mixed
1030 * up with the texture data from the host data blit, otherwise
1031 * part of the texture image may be corrupted.
1035 RADEON_FLUSH_CACHE();
1036 RADEON_WAIT_UNTIL_IDLE();
1040 /* Make a copy of the parameters in case we have to update them
1041 * for a multi-pass texture blit.
1044 height = image->height;
1047 size = height * blit_width;
1049 if ( size > RADEON_MAX_TEXTURE_SIZE ) {
1050 /* Texture image is too large, do a multipass upload */
1053 /* Adjust the blit size to fit the indirect buffer */
1054 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1055 size = height * blit_width;
1057 /* Update the input parameters for next time */
1059 image->height -= height;
1060 image->data = (const char *)image->data + size;
1062 if ( DRM_OS_COPYTOUSR( tex->image, image, sizeof(*image) ) ) {
1063 DRM_ERROR( "EFAULT on tex->image\n" );
1064 return DRM_OS_ERR(EFAULT);
1066 } else if ( size < 4 && size > 0 ) {
1072 /* Dispatch the indirect buffer.
1074 buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
1076 buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
1077 buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1078 RADEON_GMC_BRUSH_NONE |
1080 RADEON_GMC_SRC_DATATYPE_COLOR |
1082 RADEON_DP_SRC_SOURCE_HOST_DATA |
1083 RADEON_GMC_CLR_CMP_CNTL_DIS |
1084 RADEON_GMC_WR_MSK_DIS);
1086 buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
1087 buffer[3] = 0xffffffff;
1088 buffer[4] = 0xffffffff;
1089 buffer[5] = (y << 16) | image->x;
1090 buffer[6] = (height << 16) | image->width;
1095 if ( tex_width >= 32 ) {
1096 /* Texture image width is larger than the minimum, so we
1097 * can upload it directly.
1099 if ( DRM_OS_COPYFROMUSR( buffer, data, dwords * sizeof(u32) ) ) {
1100 DRM_ERROR( "EFAULT on data, %d dwords\n", dwords );
1101 return DRM_OS_ERR(EFAULT);
1104 /* Texture image width is less than the minimum, so we
1105 * need to pad out each image scanline to the minimum
1108 for ( i = 0 ; i < tex->height ; i++ ) {
1109 if ( DRM_OS_COPYFROMUSR( buffer, data, tex_width ) ) {
1110 DRM_ERROR( "EFAULT on pad, %d bytes\n",
1112 return DRM_OS_ERR(EFAULT);
1120 buf->used = (dwords + 8) * sizeof(u32);
1121 buf_priv->discard = 1;
1123 radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
1125 /* Flush the pixel cache after the blit completes. This ensures
1126 * the texture data is written out to memory before rendering
1131 RADEON_FLUSH_CACHE();
1132 RADEON_WAIT_UNTIL_2D_IDLE();
1139 static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1141 drm_radeon_private_t *dev_priv = dev->dev_private;
1144 DRM_DEBUG( "%s\n", __func__ );
1148 OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
1149 OUT_RING( 0x00000000 );
1151 OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
1152 for ( i = 0 ; i < 32 ; i++ ) {
1153 OUT_RING( stipple[i] );
1160 /* ================================================================
1164 int radeon_cp_clear( DRM_OS_IOCTL )
1167 drm_radeon_private_t *dev_priv = dev->dev_private;
1168 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1169 drm_radeon_clear_t clear;
1170 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1171 DRM_DEBUG( "%s\n", __func__ );
1173 LOCK_TEST_WITH_RETURN( dev );
1175 DRM_OS_KRNFROMUSR( clear, (drm_radeon_clear_t *) data,
1178 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1180 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1181 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1183 if ( DRM_OS_COPYFROMUSR( &depth_boxes, clear.depth_boxes,
1184 sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
1185 return DRM_OS_ERR(EFAULT);
1187 radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
1192 int radeon_cp_swap( DRM_OS_IOCTL )
1195 drm_radeon_private_t *dev_priv = dev->dev_private;
1196 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1197 DRM_DEBUG( "%s\n", __func__ );
1199 LOCK_TEST_WITH_RETURN( dev );
1201 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1203 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1204 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1206 if ( !dev_priv->page_flipping ) {
1207 radeon_cp_dispatch_swap( dev );
1208 dev_priv->sarea_priv->dirty |= (RADEON_UPLOAD_CONTEXT |
1209 RADEON_UPLOAD_MASKS);
1211 radeon_cp_dispatch_flip( dev );
1217 int radeon_cp_vertex( DRM_OS_IOCTL )
1220 drm_radeon_private_t *dev_priv = dev->dev_private;
1221 drm_device_dma_t *dma = dev->dma;
1223 drm_radeon_buf_priv_t *buf_priv;
1224 drm_radeon_vertex_t vertex;
1226 LOCK_TEST_WITH_RETURN( dev );
1229 DRM_ERROR( "%s called with no initialization\n", __func__ );
1230 return DRM_OS_ERR(EINVAL);
1233 DRM_OS_KRNFROMUSR( vertex, (drm_radeon_vertex_t *) data,
1236 DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
1237 __func__, DRM_OS_CURRENTPID,
1238 vertex.idx, vertex.count, vertex.discard );
1240 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1241 DRM_ERROR( "buffer index %d (of %d max)\n",
1242 vertex.idx, dma->buf_count - 1 );
1243 return DRM_OS_ERR(EINVAL);
1245 if ( vertex.prim < 0 ||
1246 vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1247 DRM_ERROR( "buffer prim %d\n", vertex.prim );
1248 return DRM_OS_ERR(EINVAL);
1251 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1252 VB_AGE_TEST_WITH_RETURN( dev_priv );
1254 buf = dma->buflist[vertex.idx];
1255 buf_priv = buf->dev_private;
1257 if ( buf->pid != DRM_OS_CURRENTPID ) {
1258 DRM_ERROR( "process %d using buffer owned by %d\n",
1259 DRM_OS_CURRENTPID, buf->pid );
1260 return DRM_OS_ERR(EINVAL);
1262 if ( buf->pending ) {
1263 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1264 return DRM_OS_ERR(EINVAL);
1267 buf->used = vertex.count;
1268 buf_priv->prim = vertex.prim;
1269 buf_priv->discard = vertex.discard;
1271 radeon_cp_dispatch_vertex( dev, buf );
1276 int radeon_cp_indices( DRM_OS_IOCTL )
1279 drm_radeon_private_t *dev_priv = dev->dev_private;
1280 drm_device_dma_t *dma = dev->dma;
1282 drm_radeon_buf_priv_t *buf_priv;
1283 drm_radeon_indices_t elts;
1286 LOCK_TEST_WITH_RETURN( dev );
1289 DRM_ERROR( "%s called with no initialization\n", __func__ );
1290 return DRM_OS_ERR(EINVAL);
1293 DRM_OS_KRNFROMUSR( elts, (drm_radeon_indices_t *) data,
1296 DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n",
1297 __func__, DRM_OS_CURRENTPID,
1298 elts.idx, elts.start, elts.end, elts.discard );
1300 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
1301 DRM_ERROR( "buffer index %d (of %d max)\n",
1302 elts.idx, dma->buf_count - 1 );
1303 return DRM_OS_ERR(EINVAL);
1305 if ( elts.prim < 0 ||
1306 elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1307 DRM_ERROR( "buffer prim %d\n", elts.prim );
1308 return DRM_OS_ERR(EINVAL);
1311 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1312 VB_AGE_TEST_WITH_RETURN( dev_priv );
1314 buf = dma->buflist[elts.idx];
1315 buf_priv = buf->dev_private;
1317 if ( buf->pid != DRM_OS_CURRENTPID ) {
1318 DRM_ERROR( "process %d using buffer owned by %d\n",
1319 DRM_OS_CURRENTPID, buf->pid );
1320 return DRM_OS_ERR(EINVAL);
1322 if ( buf->pending ) {
1323 DRM_ERROR( "sending pending buffer %d\n", elts.idx );
1324 return DRM_OS_ERR(EINVAL);
1327 count = (elts.end - elts.start) / sizeof(u16);
1328 elts.start -= RADEON_INDEX_PRIM_OFFSET;
1330 if ( elts.start & 0x7 ) {
1331 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
1332 return DRM_OS_ERR(EINVAL);
1334 if ( elts.start < buf->used ) {
1335 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
1336 return DRM_OS_ERR(EINVAL);
1339 buf->used = elts.end;
1340 buf_priv->prim = elts.prim;
1341 buf_priv->discard = elts.discard;
1343 radeon_cp_dispatch_indices( dev, buf, elts.start, elts.end, count );
1348 int radeon_cp_texture( DRM_OS_IOCTL )
1351 drm_radeon_private_t *dev_priv = dev->dev_private;
1352 drm_radeon_texture_t tex;
1353 drm_radeon_tex_image_t image;
1355 LOCK_TEST_WITH_RETURN( dev );
1357 DRM_OS_KRNFROMUSR( tex, (drm_radeon_texture_t *) data, sizeof(tex) );
1359 if ( tex.image == NULL ) {
1360 DRM_ERROR( "null texture image!\n" );
1361 return DRM_OS_ERR(EINVAL);
1364 if ( DRM_OS_COPYFROMUSR( &image,
1365 (drm_radeon_tex_image_t *)tex.image,
1367 return DRM_OS_ERR(EFAULT);
1369 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1370 VB_AGE_TEST_WITH_RETURN( dev_priv );
1372 return radeon_cp_dispatch_texture( dev, &tex, &image, DRM_OS_CURRENTPID );
1375 int radeon_cp_stipple( DRM_OS_IOCTL )
1378 drm_radeon_private_t *dev_priv = dev->dev_private;
1379 drm_radeon_stipple_t stipple;
1382 LOCK_TEST_WITH_RETURN( dev );
1384 DRM_OS_KRNFROMUSR( stipple, (drm_radeon_stipple_t *) data,
1387 if ( DRM_OS_COPYFROMUSR( &mask, stipple.mask, 32 * sizeof(u32) ) )
1388 return DRM_OS_ERR(EFAULT);
1390 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1392 radeon_cp_dispatch_stipple( dev, mask );
1397 int radeon_cp_indirect( DRM_OS_IOCTL )
1400 drm_radeon_private_t *dev_priv = dev->dev_private;
1401 drm_device_dma_t *dma = dev->dma;
1403 drm_radeon_buf_priv_t *buf_priv;
1404 drm_radeon_indirect_t indirect;
1407 LOCK_TEST_WITH_RETURN( dev );
1410 DRM_ERROR( "%s called with no initialization\n", __func__ );
1411 return DRM_OS_ERR(EINVAL);
1414 DRM_OS_KRNFROMUSR( indirect, (drm_radeon_indirect_t *) data,
1417 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
1418 indirect.idx, indirect.start,
1419 indirect.end, indirect.discard );
1421 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
1422 DRM_ERROR( "buffer index %d (of %d max)\n",
1423 indirect.idx, dma->buf_count - 1 );
1424 return DRM_OS_ERR(EINVAL);
1427 buf = dma->buflist[indirect.idx];
1428 buf_priv = buf->dev_private;
1430 if ( buf->pid != DRM_OS_CURRENTPID ) {
1431 DRM_ERROR( "process %d using buffer owned by %d\n",
1432 DRM_OS_CURRENTPID, buf->pid );
1433 return DRM_OS_ERR(EINVAL);
1435 if ( buf->pending ) {
1436 DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
1437 return DRM_OS_ERR(EINVAL);
1440 if ( indirect.start < buf->used ) {
1441 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
1442 indirect.start, buf->used );
1443 return DRM_OS_ERR(EINVAL);
1446 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1447 VB_AGE_TEST_WITH_RETURN( dev_priv );
1449 buf->used = indirect.end;
1450 buf_priv->discard = indirect.discard;
1452 /* Wait for the 3D stream to idle before the indirect buffer
1453 * containing 2D acceleration commands is processed.
1457 RADEON_WAIT_UNTIL_3D_IDLE();
1461 /* Dispatch the indirect buffer full of commands from the
1462 * X server. This is insecure and is thus only available to
1463 * privileged clients.
1465 radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );