1 /* savage_state.c -- State and drawing support for Savage
3 * Copyright 2004 Felix Kuehling
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 #include "dev/drm/drmP.h"
29 #include "dev/drm/savage_drm.h"
30 #include "dev/drm/savage_drv.h"
32 void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,
33 const drm_clip_rect_t *pbox)
35 uint32_t scstart = dev_priv->state.s3d.new_scstart;
36 uint32_t scend = dev_priv->state.s3d.new_scend;
37 scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) |
38 ((uint32_t)pbox->x1 & 0x000007ff) |
39 (((uint32_t)pbox->y1 << 16) & 0x07ff0000);
40 scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
41 (((uint32_t)pbox->x2-1) & 0x000007ff) |
42 ((((uint32_t)pbox->y2-1) << 16) & 0x07ff0000);
43 if (scstart != dev_priv->state.s3d.scstart ||
44 scend != dev_priv->state.s3d.scend) {
47 DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D);
48 DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2);
51 dev_priv->state.s3d.scstart = scstart;
52 dev_priv->state.s3d.scend = scend;
53 dev_priv->waiting = 1;
58 void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
59 const drm_clip_rect_t *pbox)
61 uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0;
62 uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1;
63 drawctrl0 = (drawctrl0 & ~SAVAGE_SCISSOR_MASK_S4) |
64 ((uint32_t)pbox->x1 & 0x000007ff) |
65 (((uint32_t)pbox->y1 << 12) & 0x00fff000);
66 drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) |
67 (((uint32_t)pbox->x2-1) & 0x000007ff) |
68 ((((uint32_t)pbox->y2-1) << 12) & 0x00fff000);
69 if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||
70 drawctrl1 != dev_priv->state.s4.drawctrl1) {
73 DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D);
74 DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2);
77 dev_priv->state.s4.drawctrl0 = drawctrl0;
78 dev_priv->state.s4.drawctrl1 = drawctrl1;
79 dev_priv->waiting = 1;
84 static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit,
87 if ((addr & 6) != 2) { /* reserved bits */
88 DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr);
89 return DRM_ERR(EINVAL);
91 if (!(addr & 1)) { /* local */
93 if (addr < dev_priv->texture_offset ||
94 addr >= dev_priv->texture_offset+dev_priv->texture_size) {
96 ("bad texAddr%d %08x (local addr out of range)\n",
98 return DRM_ERR(EINVAL);
101 if (!dev_priv->agp_textures) {
102 DRM_ERROR("bad texAddr%d %08x (AGP not available)\n",
104 return DRM_ERR(EINVAL);
107 if (addr < dev_priv->agp_textures->offset ||
108 addr >= (dev_priv->agp_textures->offset +
109 dev_priv->agp_textures->size)) {
111 ("bad texAddr%d %08x (AGP addr out of range)\n",
113 return DRM_ERR(EINVAL);
119 #define SAVE_STATE(reg,where) \
120 if(start <= reg && start+count > reg) \
121 dev_priv->state.where = regs[reg - start]
122 #define SAVE_STATE_MASK(reg,where,mask) do { \
123 if(start <= reg && start+count > reg) { \
125 tmp = regs[reg - start]; \
126 dev_priv->state.where = (tmp & (mask)) | \
127 (dev_priv->state.where & ~(mask)); \
130 static int savage_verify_state_s3d(drm_savage_private_t *dev_priv,
131 unsigned int start, unsigned int count,
132 const uint32_t *regs)
134 if (start < SAVAGE_TEXPALADDR_S3D ||
135 start+count-1 > SAVAGE_DESTTEXRWWATERMARK_S3D) {
136 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
137 start, start+count-1);
138 return DRM_ERR(EINVAL);
141 SAVE_STATE_MASK(SAVAGE_SCSTART_S3D, s3d.new_scstart,
142 ~SAVAGE_SCISSOR_MASK_S3D);
143 SAVE_STATE_MASK(SAVAGE_SCEND_S3D, s3d.new_scend,
144 ~SAVAGE_SCISSOR_MASK_S3D);
146 /* if any texture regs were changed ... */
147 if (start <= SAVAGE_TEXCTRL_S3D &&
148 start+count > SAVAGE_TEXPALADDR_S3D) {
149 /* ... check texture state */
150 SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl);
151 SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr);
152 if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK)
153 return savage_verify_texaddr(dev_priv, 0,
154 dev_priv->state.s3d.texaddr);
160 static int savage_verify_state_s4(drm_savage_private_t *dev_priv,
161 unsigned int start, unsigned int count,
162 const uint32_t *regs)
166 if (start < SAVAGE_DRAWLOCALCTRL_S4 ||
167 start+count-1 > SAVAGE_TEXBLENDCOLOR_S4) {
168 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
169 start, start+count-1);
170 return DRM_ERR(EINVAL);
173 SAVE_STATE_MASK(SAVAGE_DRAWCTRL0_S4, s4.new_drawctrl0,
174 ~SAVAGE_SCISSOR_MASK_S4);
175 SAVE_STATE_MASK(SAVAGE_DRAWCTRL1_S4, s4.new_drawctrl1,
176 ~SAVAGE_SCISSOR_MASK_S4);
178 /* if any texture regs were changed ... */
179 if (start <= SAVAGE_TEXDESCR_S4 &&
180 start + count > SAVAGE_TEXPALADDR_S4) {
181 /* ... check texture state */
182 SAVE_STATE(SAVAGE_TEXDESCR_S4, s4.texdescr);
183 SAVE_STATE(SAVAGE_TEXADDR0_S4, s4.texaddr0);
184 SAVE_STATE(SAVAGE_TEXADDR1_S4, s4.texaddr1);
185 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK)
186 ret |= savage_verify_texaddr(dev_priv, 0,
187 dev_priv->state.s4.texaddr0);
188 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK)
189 ret |= savage_verify_texaddr(dev_priv, 1,
190 dev_priv->state.s4.texaddr1);
196 #undef SAVE_STATE_MASK
198 static int savage_dispatch_state(drm_savage_private_t *dev_priv,
199 const drm_savage_cmd_header_t *cmd_header,
200 const uint32_t *regs)
202 unsigned int count = cmd_header->state.count;
203 unsigned int start = cmd_header->state.start;
204 unsigned int count2 = 0;
205 unsigned int bci_size;
212 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
213 ret = savage_verify_state_s3d(dev_priv, start, count, regs);
216 /* scissor regs are emitted in savage_dispatch_draw */
217 if (start < SAVAGE_SCSTART_S3D) {
218 if (start+count > SAVAGE_SCEND_S3D+1)
219 count2 = count - (SAVAGE_SCEND_S3D+1 - start);
220 if (start+count > SAVAGE_SCSTART_S3D)
221 count = SAVAGE_SCSTART_S3D - start;
222 } else if (start <= SAVAGE_SCEND_S3D) {
223 if (start+count > SAVAGE_SCEND_S3D+1) {
224 count -= SAVAGE_SCEND_S3D+1 - start;
225 start = SAVAGE_SCEND_S3D+1;
230 ret = savage_verify_state_s4(dev_priv, start, count, regs);
233 /* scissor regs are emitted in savage_dispatch_draw */
234 if (start < SAVAGE_DRAWCTRL0_S4) {
235 if (start+count > SAVAGE_DRAWCTRL1_S4+1)
237 (SAVAGE_DRAWCTRL1_S4 + 1 - start);
238 if (start+count > SAVAGE_DRAWCTRL0_S4)
239 count = SAVAGE_DRAWCTRL0_S4 - start;
240 } else if (start <= SAVAGE_DRAWCTRL1_S4) {
241 if (start+count > SAVAGE_DRAWCTRL1_S4+1) {
242 count -= SAVAGE_DRAWCTRL1_S4+1 - start;
243 start = SAVAGE_DRAWCTRL1_S4+1;
249 bci_size = count + (count+254)/255 + count2 + (count2+254)/255;
251 if (cmd_header->state.global) {
252 BEGIN_DMA(bci_size+1);
253 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
254 dev_priv->waiting = 1;
261 unsigned int n = count < 255 ? count : 255;
262 DMA_SET_REGISTERS(start, n);
279 static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
280 const drm_savage_cmd_header_t *cmd_header,
281 const drm_buf_t *dmabuf)
283 unsigned char reorder = 0;
284 unsigned int prim = cmd_header->prim.prim;
285 unsigned int skip = cmd_header->prim.skip;
286 unsigned int n = cmd_header->prim.count;
287 unsigned int start = cmd_header->prim.start;
292 DRM_ERROR("called without dma buffers!\n");
293 return DRM_ERR(EINVAL);
300 case SAVAGE_PRIM_TRILIST_201:
302 prim = SAVAGE_PRIM_TRILIST;
303 case SAVAGE_PRIM_TRILIST:
305 DRM_ERROR("wrong number of vertices %u in TRILIST\n",
307 return DRM_ERR(EINVAL);
310 case SAVAGE_PRIM_TRISTRIP:
311 case SAVAGE_PRIM_TRIFAN:
314 ("wrong number of vertices %u in TRIFAN/STRIP\n",
316 return DRM_ERR(EINVAL);
320 DRM_ERROR("invalid primitive type %u\n", prim);
321 return DRM_ERR(EINVAL);
324 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
326 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
327 return DRM_ERR(EINVAL);
330 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) -
331 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) -
332 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1);
333 if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) {
334 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
335 return DRM_ERR(EINVAL);
338 DRM_ERROR("TRILIST_201 used on Savage4 hardware\n");
339 return DRM_ERR(EINVAL);
343 if (start + n > dmabuf->total/32) {
344 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
345 start, start + n - 1, dmabuf->total/32);
346 return DRM_ERR(EINVAL);
349 /* Vertex DMA doesn't work with command DMA at the same time,
350 * so we use BCI_... to submit commands here. Flush buffered
351 * faked DMA first. */
354 if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {
356 BCI_SET_REGISTERS(SAVAGE_VERTBUFADDR, 1);
357 BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);
358 dev_priv->state.common.vbaddr = dmabuf->bus_address;
360 if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {
361 /* Workaround for what looks like a hardware bug. If a
362 * WAIT_3D_IDLE was emitted some time before the
363 * indexed drawing command then the engine will lock
364 * up. There are two known workarounds:
365 * WAIT_IDLE_EMPTY or emit at least 63 NOPs. */
367 for (i = 0; i < 63; ++i)
368 BCI_WRITE(BCI_CMD_WAIT);
369 dev_priv->waiting = 0;
374 /* Can emit up to 255 indices (85 triangles) at once. */
375 unsigned int count = n > 255 ? 255 : n;
377 /* Need to reorder indices for correct flat
378 * shading while preserving the clock sense
379 * for correct culling. Only on Savage3D. */
380 int reorder[3] = {-1, -1, -1};
381 reorder[start%3] = 2;
383 BEGIN_BCI((count+1+1)/2);
384 BCI_DRAW_INDICES_S3D(count, prim, start+2);
386 for (i = start+1; i+1 < start+count; i += 2)
387 BCI_WRITE((i + reorder[i % 3]) |
389 reorder[(i + 1) % 3]) << 16));
391 BCI_WRITE(i + reorder[i%3]);
392 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
393 BEGIN_BCI((count+1+1)/2);
394 BCI_DRAW_INDICES_S3D(count, prim, start);
396 for (i = start+1; i+1 < start+count; i += 2)
397 BCI_WRITE(i | ((i+1) << 16));
401 BEGIN_BCI((count+2+1)/2);
402 BCI_DRAW_INDICES_S4(count, prim, skip);
404 for (i = start; i+1 < start+count; i += 2)
405 BCI_WRITE(i | ((i+1) << 16));
413 prim |= BCI_CMD_DRAW_CONT;
419 static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
420 const drm_savage_cmd_header_t *cmd_header,
421 const uint32_t *vtxbuf, unsigned int vb_size,
422 unsigned int vb_stride)
424 unsigned char reorder = 0;
425 unsigned int prim = cmd_header->prim.prim;
426 unsigned int skip = cmd_header->prim.skip;
427 unsigned int n = cmd_header->prim.count;
428 unsigned int start = cmd_header->prim.start;
429 unsigned int vtx_size;
437 case SAVAGE_PRIM_TRILIST_201:
439 prim = SAVAGE_PRIM_TRILIST;
440 case SAVAGE_PRIM_TRILIST:
442 DRM_ERROR("wrong number of vertices %u in TRILIST\n",
444 return DRM_ERR(EINVAL);
447 case SAVAGE_PRIM_TRISTRIP:
448 case SAVAGE_PRIM_TRIFAN:
451 ("wrong number of vertices %u in TRIFAN/STRIP\n",
453 return DRM_ERR(EINVAL);
457 DRM_ERROR("invalid primitive type %u\n", prim);
458 return DRM_ERR(EINVAL);
461 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
462 if (skip > SAVAGE_SKIP_ALL_S3D) {
463 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
464 return DRM_ERR(EINVAL);
466 vtx_size = 8; /* full vertex */
468 if (skip > SAVAGE_SKIP_ALL_S4) {
469 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
470 return DRM_ERR(EINVAL);
472 vtx_size = 10; /* full vertex */
475 vtx_size -= (skip & 1) + (skip >> 1 & 1) +
476 (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) +
477 (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1);
479 if (vtx_size > vb_stride) {
480 DRM_ERROR("vertex size greater than vb stride (%u > %u)\n",
481 vtx_size, vb_stride);
482 return DRM_ERR(EINVAL);
485 if (start + n > vb_size / (vb_stride*4)) {
486 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
487 start, start + n - 1, vb_size / (vb_stride*4));
488 return DRM_ERR(EINVAL);
493 /* Can emit up to 255 vertices (85 triangles) at once. */
494 unsigned int count = n > 255 ? 255 : n;
496 /* Need to reorder vertices for correct flat
497 * shading while preserving the clock sense
498 * for correct culling. Only on Savage3D. */
499 int reorder[3] = {-1, -1, -1};
500 reorder[start%3] = 2;
502 BEGIN_DMA(count*vtx_size+1);
503 DMA_DRAW_PRIMITIVE(count, prim, skip);
505 for (i = start; i < start+count; ++i) {
506 unsigned int j = i + reorder[i % 3];
507 DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
512 BEGIN_DMA(count*vtx_size+1);
513 DMA_DRAW_PRIMITIVE(count, prim, skip);
515 if (vb_stride == vtx_size) {
516 DMA_COPY(&vtxbuf[vb_stride*start],
519 for (i = start; i < start+count; ++i) {
520 DMA_COPY(&vtxbuf[vb_stride*i],
531 prim |= BCI_CMD_DRAW_CONT;
537 static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
538 const drm_savage_cmd_header_t *cmd_header,
540 const drm_buf_t *dmabuf)
542 unsigned char reorder = 0;
543 unsigned int prim = cmd_header->idx.prim;
544 unsigned int skip = cmd_header->idx.skip;
545 unsigned int n = cmd_header->idx.count;
550 DRM_ERROR("called without dma buffers!\n");
551 return DRM_ERR(EINVAL);
558 case SAVAGE_PRIM_TRILIST_201:
560 prim = SAVAGE_PRIM_TRILIST;
561 case SAVAGE_PRIM_TRILIST:
563 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
564 return DRM_ERR(EINVAL);
567 case SAVAGE_PRIM_TRISTRIP:
568 case SAVAGE_PRIM_TRIFAN:
571 ("wrong number of indices %u in TRIFAN/STRIP\n", n);
572 return DRM_ERR(EINVAL);
576 DRM_ERROR("invalid primitive type %u\n", prim);
577 return DRM_ERR(EINVAL);
580 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
582 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
583 return DRM_ERR(EINVAL);
586 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) -
587 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) -
588 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1);
589 if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) {
590 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
591 return DRM_ERR(EINVAL);
594 DRM_ERROR("TRILIST_201 used on Savage4 hardware\n");
595 return DRM_ERR(EINVAL);
599 /* Vertex DMA doesn't work with command DMA at the same time,
600 * so we use BCI_... to submit commands here. Flush buffered
601 * faked DMA first. */
604 if (dmabuf->bus_address != dev_priv->state.common.vbaddr) {
606 BCI_SET_REGISTERS(SAVAGE_VERTBUFADDR, 1);
607 BCI_WRITE(dmabuf->bus_address | dev_priv->dma_type);
608 dev_priv->state.common.vbaddr = dmabuf->bus_address;
610 if (S3_SAVAGE3D_SERIES(dev_priv->chipset) && dev_priv->waiting) {
611 /* Workaround for what looks like a hardware bug. If a
612 * WAIT_3D_IDLE was emitted some time before the
613 * indexed drawing command then the engine will lock
614 * up. There are two known workarounds:
615 * WAIT_IDLE_EMPTY or emit at least 63 NOPs. */
617 for (i = 0; i < 63; ++i)
618 BCI_WRITE(BCI_CMD_WAIT);
619 dev_priv->waiting = 0;
624 /* Can emit up to 255 indices (85 triangles) at once. */
625 unsigned int count = n > 255 ? 255 : n;
628 for (i = 0; i < count; ++i) {
629 if (idx[i] > dmabuf->total/32) {
630 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
631 i, idx[i], dmabuf->total/32);
632 return DRM_ERR(EINVAL);
637 /* Need to reorder indices for correct flat
638 * shading while preserving the clock sense
639 * for correct culling. Only on Savage3D. */
640 int reorder[3] = {2, -1, -1};
642 BEGIN_BCI((count+1+1)/2);
643 BCI_DRAW_INDICES_S3D(count, prim, idx[2]);
645 for (i = 1; i+1 < count; i += 2)
646 BCI_WRITE(idx[i + reorder[i % 3]] |
648 reorder[(i + 1) % 3]] << 16));
650 BCI_WRITE(idx[i + reorder[i%3]]);
651 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
652 BEGIN_BCI((count+1+1)/2);
653 BCI_DRAW_INDICES_S3D(count, prim, idx[0]);
655 for (i = 1; i+1 < count; i += 2)
656 BCI_WRITE(idx[i] | (idx[i+1] << 16));
660 BEGIN_BCI((count+2+1)/2);
661 BCI_DRAW_INDICES_S4(count, prim, skip);
663 for (i = 0; i+1 < count; i += 2)
664 BCI_WRITE(idx[i] | (idx[i+1] << 16));
672 prim |= BCI_CMD_DRAW_CONT;
678 static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
679 const drm_savage_cmd_header_t *cmd_header,
681 const uint32_t *vtxbuf,
682 unsigned int vb_size, unsigned int vb_stride)
684 unsigned char reorder = 0;
685 unsigned int prim = cmd_header->idx.prim;
686 unsigned int skip = cmd_header->idx.skip;
687 unsigned int n = cmd_header->idx.count;
688 unsigned int vtx_size;
696 case SAVAGE_PRIM_TRILIST_201:
698 prim = SAVAGE_PRIM_TRILIST;
699 case SAVAGE_PRIM_TRILIST:
701 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
702 return DRM_ERR(EINVAL);
705 case SAVAGE_PRIM_TRISTRIP:
706 case SAVAGE_PRIM_TRIFAN:
709 ("wrong number of indices %u in TRIFAN/STRIP\n", n);
710 return DRM_ERR(EINVAL);
714 DRM_ERROR("invalid primitive type %u\n", prim);
715 return DRM_ERR(EINVAL);
718 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
719 if (skip > SAVAGE_SKIP_ALL_S3D) {
720 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
721 return DRM_ERR(EINVAL);
723 vtx_size = 8; /* full vertex */
725 if (skip > SAVAGE_SKIP_ALL_S4) {
726 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
727 return DRM_ERR(EINVAL);
729 vtx_size = 10; /* full vertex */
732 vtx_size -= (skip & 1) + (skip >> 1 & 1) +
733 (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) +
734 (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1);
736 if (vtx_size > vb_stride) {
737 DRM_ERROR("vertex size greater than vb stride (%u > %u)\n",
738 vtx_size, vb_stride);
739 return DRM_ERR(EINVAL);
744 /* Can emit up to 255 vertices (85 triangles) at once. */
745 unsigned int count = n > 255 ? 255 : n;
748 for (i = 0; i < count; ++i) {
749 if (idx[i] > vb_size / (vb_stride*4)) {
750 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
751 i, idx[i], vb_size / (vb_stride*4));
752 return DRM_ERR(EINVAL);
757 /* Need to reorder vertices for correct flat
758 * shading while preserving the clock sense
759 * for correct culling. Only on Savage3D. */
760 int reorder[3] = {2, -1, -1};
762 BEGIN_DMA(count*vtx_size+1);
763 DMA_DRAW_PRIMITIVE(count, prim, skip);
765 for (i = 0; i < count; ++i) {
766 unsigned int j = idx[i + reorder[i % 3]];
767 DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
772 BEGIN_DMA(count*vtx_size+1);
773 DMA_DRAW_PRIMITIVE(count, prim, skip);
775 for (i = 0; i < count; ++i) {
776 unsigned int j = idx[i];
777 DMA_COPY(&vtxbuf[vb_stride*j], vtx_size);
786 prim |= BCI_CMD_DRAW_CONT;
792 static int savage_dispatch_clear(drm_savage_private_t *dev_priv,
793 const drm_savage_cmd_header_t *cmd_header,
794 const drm_savage_cmd_header_t *data,
796 const drm_clip_rect_t *boxes)
798 unsigned int flags = cmd_header->clear0.flags;
799 unsigned int clear_cmd;
800 unsigned int i, nbufs;
806 clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
807 BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW;
808 BCI_CMD_SET_ROP(clear_cmd,0xCC);
810 nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) +
811 ((flags & SAVAGE_BACK) ? 1 : 0) + ((flags & SAVAGE_DEPTH) ? 1 : 0);
815 if (data->clear1.mask != 0xffffffff) {
818 DMA_SET_REGISTERS(SAVAGE_BITPLANEWTMASK, 1);
819 DMA_WRITE(data->clear1.mask);
822 for (i = 0; i < nbox; ++i) {
823 unsigned int x, y, w, h;
826 x = boxes[i].x1, y = boxes[i].y1;
827 w = boxes[i].x2 - boxes[i].x1;
828 h = boxes[i].y2 - boxes[i].y1;
830 for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) {
833 DMA_WRITE(clear_cmd);
836 DMA_WRITE(dev_priv->front_offset);
837 DMA_WRITE(dev_priv->front_bd);
840 DMA_WRITE(dev_priv->back_offset);
841 DMA_WRITE(dev_priv->back_bd);
844 DMA_WRITE(dev_priv->depth_offset);
845 DMA_WRITE(dev_priv->depth_bd);
848 DMA_WRITE(data->clear1.value);
849 DMA_WRITE(BCI_X_Y(x, y));
850 DMA_WRITE(BCI_W_H(w, h));
854 if (data->clear1.mask != 0xffffffff) {
857 DMA_SET_REGISTERS(SAVAGE_BITPLANEWTMASK, 1);
858 DMA_WRITE(0xffffffff);
865 static int savage_dispatch_swap(drm_savage_private_t *dev_priv,
866 unsigned int nbox, const drm_clip_rect_t *boxes)
868 unsigned int swap_cmd;
875 swap_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
876 BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD;
877 BCI_CMD_SET_ROP(swap_cmd,0xCC);
879 for (i = 0; i < nbox; ++i) {
882 DMA_WRITE(dev_priv->back_offset);
883 DMA_WRITE(dev_priv->back_bd);
884 DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
885 DMA_WRITE(BCI_X_Y(boxes[i].x1, boxes[i].y1));
886 DMA_WRITE(BCI_W_H(boxes[i].x2-boxes[i].x1,
887 boxes[i].y2-boxes[i].y1));
894 static int savage_dispatch_draw(drm_savage_private_t *dev_priv,
895 const drm_savage_cmd_header_t *start,
896 const drm_savage_cmd_header_t *end,
897 const drm_buf_t *dmabuf,
898 const unsigned int *vtxbuf,
899 unsigned int vb_size, unsigned int vb_stride,
901 const drm_clip_rect_t *boxes)
906 for (i = 0; i < nbox; ++i) {
907 const drm_savage_cmd_header_t *cmdbuf;
908 dev_priv->emit_clip_rect(dev_priv, &boxes[i]);
911 while (cmdbuf < end) {
912 drm_savage_cmd_header_t cmd_header;
913 cmd_header = *cmdbuf;
915 switch (cmd_header.cmd.cmd) {
916 case SAVAGE_CMD_DMA_PRIM:
917 ret = savage_dispatch_dma_prim(
918 dev_priv, &cmd_header, dmabuf);
920 case SAVAGE_CMD_VB_PRIM:
921 ret = savage_dispatch_vb_prim(
922 dev_priv, &cmd_header,
923 vtxbuf, vb_size, vb_stride);
925 case SAVAGE_CMD_DMA_IDX:
926 j = (cmd_header.idx.count + 3) / 4;
927 /* j was check in savage_bci_cmdbuf */
928 ret = savage_dispatch_dma_idx(dev_priv,
929 &cmd_header, (const uint16_t *)cmdbuf,
933 case SAVAGE_CMD_VB_IDX:
934 j = (cmd_header.idx.count + 3) / 4;
935 /* j was check in savage_bci_cmdbuf */
936 ret = savage_dispatch_vb_idx(dev_priv,
937 &cmd_header, (const uint16_t *)cmdbuf,
938 (const uint32_t *)vtxbuf, vb_size,
943 /* What's the best return code? EFAULT? */
944 DRM_ERROR("IMPLEMENTATION ERROR: "
945 "non-drawing-command %d\n",
947 return DRM_ERR(EINVAL);
958 int savage_bci_cmdbuf(DRM_IOCTL_ARGS)
961 drm_savage_private_t *dev_priv = dev->dev_private;
962 drm_device_dma_t *dma = dev->dma;
964 drm_savage_cmdbuf_t cmdbuf;
965 drm_savage_cmd_header_t *kcmd_addr = NULL;
966 drm_savage_cmd_header_t *first_draw_cmd;
967 unsigned int *kvb_addr = NULL;
968 drm_clip_rect_t *kbox_addr = NULL;
974 LOCK_TEST_WITH_RETURN(dev, filp);
976 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *)data,
979 if (dma && dma->buflist) {
980 if (cmdbuf.dma_idx > dma->buf_count) {
982 ("vertex buffer index %u out of range (0-%u)\n",
983 cmdbuf.dma_idx, dma->buf_count-1);
984 return DRM_ERR(EINVAL);
986 dmabuf = dma->buflist[cmdbuf.dma_idx];
991 /* Copy the user buffers into kernel temporary areas. This hasn't been
992 * a performance loss compared to VERIFYAREA_READ/
993 * COPY_FROM_USER_UNCHECKED when done in other drivers, and is correct
994 * for locking on FreeBSD.
997 kcmd_addr = drm_alloc(cmdbuf.size * 8, DRM_MEM_DRIVER);
998 if (kcmd_addr == NULL)
1001 if (DRM_COPY_FROM_USER(kcmd_addr, cmdbuf.cmd_addr,
1004 drm_free(kcmd_addr, cmdbuf.size * 8, DRM_MEM_DRIVER);
1005 return DRM_ERR(EFAULT);
1007 cmdbuf.cmd_addr = kcmd_addr;
1009 if (cmdbuf.vb_size) {
1010 kvb_addr = drm_alloc(cmdbuf.vb_size, DRM_MEM_DRIVER);
1011 if (kvb_addr == NULL) {
1012 ret = DRM_ERR(ENOMEM);
1016 if (DRM_COPY_FROM_USER(kvb_addr, cmdbuf.vb_addr,
1018 ret = DRM_ERR(EFAULT);
1021 cmdbuf.vb_addr = kvb_addr;
1024 kbox_addr = drm_alloc(cmdbuf.nbox * sizeof(drm_clip_rect_t),
1026 if (kbox_addr == NULL) {
1027 ret = DRM_ERR(ENOMEM);
1031 if (DRM_COPY_FROM_USER(kbox_addr, cmdbuf.box_addr,
1032 cmdbuf.nbox * sizeof(drm_clip_rect_t))) {
1033 ret = DRM_ERR(EFAULT);
1036 cmdbuf.box_addr = kbox_addr;
1039 /* Make sure writes to DMA buffers are finished before sending
1040 * DMA commands to the graphics hardware. */
1041 DRM_MEMORYBARRIER();
1043 /* Coming from user space. Don't know if the Xserver has
1044 * emitted wait commands. Assuming the worst. */
1045 dev_priv->waiting = 1;
1048 first_draw_cmd = NULL;
1049 while (i < cmdbuf.size) {
1050 drm_savage_cmd_header_t cmd_header;
1051 cmd_header = *(drm_savage_cmd_header_t *)cmdbuf.cmd_addr;
1055 /* Group drawing commands with same state to minimize
1056 * iterations over clip rects. */
1058 switch (cmd_header.cmd.cmd) {
1059 case SAVAGE_CMD_DMA_IDX:
1060 case SAVAGE_CMD_VB_IDX:
1061 j = (cmd_header.idx.count + 3) / 4;
1062 if (i + j > cmdbuf.size) {
1063 DRM_ERROR("indexed drawing command extends "
1064 "beyond end of command buffer\n");
1066 return DRM_ERR(EINVAL);
1069 case SAVAGE_CMD_DMA_PRIM:
1070 case SAVAGE_CMD_VB_PRIM:
1071 if (!first_draw_cmd)
1072 first_draw_cmd = cmdbuf.cmd_addr-1;
1073 cmdbuf.cmd_addr += j;
1077 if (first_draw_cmd) {
1078 ret = savage_dispatch_draw (
1079 dev_priv, first_draw_cmd,
1081 dmabuf, cmdbuf.vb_addr, cmdbuf.vb_size,
1083 cmdbuf.nbox, cmdbuf.box_addr);
1086 first_draw_cmd = NULL;
1092 switch (cmd_header.cmd.cmd) {
1093 case SAVAGE_CMD_STATE:
1094 j = (cmd_header.state.count + 1) / 2;
1095 if (i + j > cmdbuf.size) {
1096 DRM_ERROR("command SAVAGE_CMD_STATE extends "
1097 "beyond end of command buffer\n");
1099 ret = DRM_ERR(EINVAL);
1102 ret = savage_dispatch_state(dev_priv, &cmd_header,
1103 (const uint32_t *)cmdbuf.cmd_addr);
1104 cmdbuf.cmd_addr += j;
1107 case SAVAGE_CMD_CLEAR:
1108 if (i + 1 > cmdbuf.size) {
1109 DRM_ERROR("command SAVAGE_CMD_CLEAR extends "
1110 "beyond end of command buffer\n");
1112 ret = DRM_ERR(EINVAL);
1115 ret = savage_dispatch_clear(dev_priv, &cmd_header,
1117 cmdbuf.nbox, cmdbuf.box_addr);
1121 case SAVAGE_CMD_SWAP:
1122 ret = savage_dispatch_swap(dev_priv, cmdbuf.nbox,
1126 DRM_ERROR("invalid command 0x%x\n", cmd_header.cmd.cmd);
1128 ret = DRM_ERR(EINVAL);
1138 if (first_draw_cmd) {
1139 ret = savage_dispatch_draw (
1140 dev_priv, first_draw_cmd, cmdbuf.cmd_addr, dmabuf,
1141 cmdbuf.vb_addr, cmdbuf.vb_size, cmdbuf.vb_stride,
1142 cmdbuf.nbox, cmdbuf.box_addr);
1151 if (dmabuf && cmdbuf.discard) {
1152 drm_savage_buf_priv_t *buf_priv = dmabuf->dev_private;
1154 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1155 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1156 savage_freelist_put(dev, dmabuf);
1160 /* If we didn't need to allocate them, these'll be NULL */
1161 drm_free(kcmd_addr, cmdbuf.size * 8, DRM_MEM_DRIVER);
1162 drm_free(kvb_addr, cmdbuf.vb_size, DRM_MEM_DRIVER);
1163 drm_free(kbox_addr, cmdbuf.nbox * sizeof(drm_clip_rect_t),