2 * Copyright 2004 The Unichrome Project. All Rights Reserved.
3 * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
24 * Author: Thomas Hellstrom 2004, 2005.
25 * This code was written using docs obtained under NDA from VIA Inc.
27 * Don't run this code directly on an AGP buffer. Due to cache problems it will
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include "dev/drm/via_3d_reg.h"
35 #include "dev/drm/drmP.h"
36 #include "dev/drm/drm.h"
37 #include "dev/drm/via_drm.h"
38 #include "dev/drm/via_verifier.h"
39 #include "dev/drm/via_drv.h"
54 check_for_header2_err,
55 check_for_header1_err,
59 check_z_buffer_addr_mode,
60 check_destination_addr0,
61 check_destination_addr1,
62 check_destination_addr_mode,
74 check_texture_addr_mode,
75 check_for_vertex_count,
76 check_number_texunits,
81 * Associates each hazard above with a possible multi-command
82 * sequence. For example an address that is split over multiple
83 * commands and that needs to be checked at the first command
84 * that does not include any part of the address.
87 static drm_via_sequence_t seqs[] = {
120 static hz_init_t init_table1[] = {
121 {0xf2, check_for_header2_err},
122 {0xf0, check_for_header1_err},
123 {0xee, check_for_fire},
124 {0xcc, check_for_dummy},
125 {0xdd, check_for_dd},
127 {0x10, check_z_buffer_addr0},
128 {0x11, check_z_buffer_addr1},
129 {0x12, check_z_buffer_addr_mode},
147 {0x40, check_destination_addr0},
148 {0x41, check_destination_addr1},
149 {0x42, check_destination_addr_mode},
168 {0x7D, check_for_vertex_count}
171 static hz_init_t init_table2[] = {
172 {0xf2, check_for_header2_err},
173 {0xf0, check_for_header1_err},
174 {0xee, check_for_fire},
175 {0xcc, check_for_dummy},
176 {0x00, check_texture_addr0},
177 {0x01, check_texture_addr0},
178 {0x02, check_texture_addr0},
179 {0x03, check_texture_addr0},
180 {0x04, check_texture_addr0},
181 {0x05, check_texture_addr0},
182 {0x06, check_texture_addr0},
183 {0x07, check_texture_addr0},
184 {0x08, check_texture_addr0},
185 {0x09, check_texture_addr0},
186 {0x20, check_texture_addr1},
187 {0x21, check_texture_addr1},
188 {0x22, check_texture_addr1},
189 {0x23, check_texture_addr4},
190 {0x2B, check_texture_addr3},
191 {0x2C, check_texture_addr3},
192 {0x2D, check_texture_addr3},
193 {0x2E, check_texture_addr3},
194 {0x2F, check_texture_addr3},
195 {0x30, check_texture_addr3},
196 {0x31, check_texture_addr3},
197 {0x32, check_texture_addr3},
198 {0x33, check_texture_addr3},
199 {0x34, check_texture_addr3},
200 {0x4B, check_texture_addr5},
201 {0x4C, check_texture_addr6},
202 {0x51, check_texture_addr7},
203 {0x52, check_texture_addr8},
204 {0x77, check_texture_addr2},
208 {0x7B, check_texture_addr_mode},
229 static hz_init_t init_table3[] = {
230 {0xf2, check_for_header2_err},
231 {0xf0, check_for_header1_err},
232 {0xcc, check_for_dummy},
233 {0x00, check_number_texunits}
236 static hazard_t table1[256];
237 static hazard_t table2[256];
238 static hazard_t table3[256];
240 static __inline__ int
241 eat_words(const uint32_t ** buf, const uint32_t * buf_end, unsigned num_words)
243 if ((buf_end - *buf) >= num_words) {
247 DRM_ERROR("Illegal termination of DMA command buffer\n");
252 * Partially stolen from drm_memory.h
255 static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t *seq,
256 unsigned long offset,
258 struct drm_device * dev)
260 drm_local_map_t *map = seq->map_cache;
262 if (map && map->offset <= offset
263 && (offset + size) <= (map->offset + map->size)) {
267 TAILQ_FOREACH(map, &dev->maplist, link) {
268 if (map->offset <= offset
269 && (offset + size) <= (map->offset + map->size)
270 && !(map->flags & _DRM_RESTRICTED)
271 && (map->type == _DRM_AGP)) {
272 seq->map_cache = map;
280 * Require that all AGP texture levels reside in the same AGP map which should
281 * be mappable by the client. This is not a big restriction.
282 * FIXME: To actually enforce this security policy strictly, drm_rmmap
283 * would have to wait for dma quiescent before removing an AGP map.
284 * The via_drm_lookup_agp_map call in reality seems to take
285 * very little CPU time.
288 static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq)
290 switch (cur_seq->unfinished) {
292 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
295 DRM_DEBUG("Destination start address is 0x%x\n",
299 if (cur_seq->agp_texture) {
301 cur_seq->tex_level_lo[cur_seq->texture];
302 unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
303 unsigned long lo = ~0, hi = 0, tmp;
304 uint32_t *addr, *pitch, *height, tex;
314 &(cur_seq->t_addr[tex = cur_seq->texture][start]);
315 pitch = &(cur_seq->pitch[tex][start]);
316 height = &(cur_seq->height[tex][start]);
317 npot = cur_seq->tex_npot[tex];
318 for (i = start; i <= end; ++i) {
323 tmp += (*height++ * *pitch++);
325 tmp += (*height++ << *pitch++);
330 if (!via_drm_lookup_agp_map
331 (cur_seq, lo, hi - lo, cur_seq->dev)) {
333 ("AGP texture is not in allowed map\n");
341 cur_seq->unfinished = no_sequence;
345 static __inline__ int
346 investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t * cur_seq)
348 register uint32_t tmp, *tmp_addr;
350 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
352 if ((ret = finish_current_sequence(cur_seq)))
357 case check_for_header2:
358 if (cmd == HALCYON_HEADER2)
361 case check_for_header1:
362 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
365 case check_for_header2_err:
366 if (cmd == HALCYON_HEADER2)
368 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
370 case check_for_header1_err:
371 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
373 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
376 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD)
378 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
380 case check_for_dummy:
383 DRM_ERROR("Illegal DMA HC_DUMMY command\n");
386 if (0xdddddddd == cmd)
388 DRM_ERROR("Illegal DMA 0xdddddddd command\n");
390 case check_z_buffer_addr0:
391 cur_seq->unfinished = z_address;
392 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
395 case check_z_buffer_addr1:
396 cur_seq->unfinished = z_address;
397 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
398 ((cmd & 0xFF) << 24);
400 case check_z_buffer_addr_mode:
401 cur_seq->unfinished = z_address;
402 if ((cmd & 0x0000C000) == 0)
404 DRM_ERROR("Attempt to place Z buffer in system memory\n");
406 case check_destination_addr0:
407 cur_seq->unfinished = dest_address;
408 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
411 case check_destination_addr1:
412 cur_seq->unfinished = dest_address;
413 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
414 ((cmd & 0xFF) << 24);
416 case check_destination_addr_mode:
417 cur_seq->unfinished = dest_address;
418 if ((cmd & 0x0000C000) == 0)
421 ("Attempt to place 3D drawing buffer in system memory\n");
423 case check_texture_addr0:
424 cur_seq->unfinished = tex_address;
426 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
427 *tmp_addr = (*tmp_addr & 0xFF000000) | (cmd & 0x00FFFFFF);
429 case check_texture_addr1:
430 cur_seq->unfinished = tex_address;
431 tmp = ((cmd >> 24) - 0x20);
433 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
434 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
436 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF00) << 16);
438 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF0000) << 8);
440 case check_texture_addr2:
441 cur_seq->unfinished = tex_address;
442 cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F;
443 cur_seq->tex_level_hi[tmp] = (cmd & 0xFC0) >> 6;
445 case check_texture_addr3:
446 cur_seq->unfinished = tex_address;
447 tmp = ((cmd >> 24) - HC_SubA_HTXnL0Pit);
449 (cmd & HC_HTXnEnPit_MASK)) {
450 cur_seq->pitch[cur_seq->texture][tmp] =
451 (cmd & HC_HTXnLnPit_MASK);
452 cur_seq->tex_npot[cur_seq->texture] = 1;
454 cur_seq->pitch[cur_seq->texture][tmp] =
455 (cmd & HC_HTXnLnPitE_MASK) >> HC_HTXnLnPitE_SHIFT;
456 cur_seq->tex_npot[cur_seq->texture] = 0;
457 if (cmd & 0x000FFFFF) {
459 ("Unimplemented texture level 0 pitch mode.\n");
464 case check_texture_addr4:
465 cur_seq->unfinished = tex_address;
466 tmp_addr = &cur_seq->t_addr[cur_seq->texture][9];
467 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
469 case check_texture_addr5:
470 case check_texture_addr6:
471 cur_seq->unfinished = tex_address;
473 * Texture width. We don't care since we have the pitch.
476 case check_texture_addr7:
477 cur_seq->unfinished = tex_address;
478 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
479 tmp_addr[5] = 1 << ((cmd & 0x00F00000) >> 20);
480 tmp_addr[4] = 1 << ((cmd & 0x000F0000) >> 16);
481 tmp_addr[3] = 1 << ((cmd & 0x0000F000) >> 12);
482 tmp_addr[2] = 1 << ((cmd & 0x00000F00) >> 8);
483 tmp_addr[1] = 1 << ((cmd & 0x000000F0) >> 4);
484 tmp_addr[0] = 1 << (cmd & 0x0000000F);
486 case check_texture_addr8:
487 cur_seq->unfinished = tex_address;
488 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
489 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
490 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
491 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
492 tmp_addr[6] = 1 << (cmd & 0x0000000F);
494 case check_texture_addr_mode:
495 cur_seq->unfinished = tex_address;
496 if (2 == (tmp = cmd & 0x00000003)) {
498 ("Attempt to fetch texture from system memory.\n");
501 cur_seq->agp_texture = (tmp == 3);
502 cur_seq->tex_palette_size[cur_seq->texture] =
503 (cmd >> 16) & 0x000000007;
505 case check_for_vertex_count:
506 cur_seq->vertex_count = cmd & 0x0000FFFF;
508 case check_number_texunits:
509 cur_seq->multitex = (cmd >> 3) & 1;
512 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
518 static __inline__ int
519 via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end,
520 drm_via_state_t * cur_seq)
522 drm_via_private_t *dev_priv =
523 (drm_via_private_t *) cur_seq->dev->dev_private;
524 uint32_t a_fire, bcmd, dw_count;
527 const uint32_t *buf = *buffer;
529 while (buf < buf_end) {
531 if ((buf_end - buf) < 2) {
533 ("Unexpected termination of primitive list.\n");
537 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB)
540 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) {
541 DRM_ERROR("Expected Vertex List A command, got 0x%x\n",
547 *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK |
551 * How many dwords per vertex ?
554 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) {
555 DRM_ERROR("Illegal B command vertex data for AGP.\n");
562 dw_count += (cur_seq->multitex) ? 2 : 1;
564 dw_count += (cur_seq->multitex) ? 2 : 1;
567 if (bcmd & (1 << 10))
569 if (bcmd & (1 << 11))
571 if (bcmd & (1 << 12))
573 if (bcmd & (1 << 13))
575 if (bcmd & (1 << 14))
578 while (buf < buf_end) {
579 if (*buf == a_fire) {
580 if (dev_priv->num_fire_offsets >=
582 DRM_ERROR("Fire offset buffer full.\n");
586 dev_priv->fire_offsets[dev_priv->
587 num_fire_offsets++] =
591 if (buf < buf_end && *buf == a_fire)
595 if ((*buf == HALCYON_HEADER2) ||
596 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) {
597 DRM_ERROR("Missing Vertex Fire command, "
598 "Stray Vertex Fire command or verifier "
603 if ((ret = eat_words(&buf, buf_end, dw_count)))
606 if (buf >= buf_end && !have_fire) {
607 DRM_ERROR("Missing Vertex Fire command or verifier "
612 if (cur_seq->agp && ((buf - cur_seq->buf_start) & 0x01)) {
613 DRM_ERROR("AGP Primitive list end misaligned.\n");
622 static __inline__ verifier_state_t
623 via_check_header2(uint32_t const **buffer, const uint32_t * buf_end,
624 drm_via_state_t * hc_state)
629 const uint32_t *buf = *buffer;
630 const hazard_t *hz_table;
632 if ((buf_end - buf) < 2) {
634 ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
638 cmd = (*buf++ & 0xFFFF0000) >> 16;
641 case HC_ParaType_CmdVdata:
642 if (via_check_prim_list(&buf, buf_end, hc_state))
645 return state_command;
646 case HC_ParaType_NotTex:
649 case HC_ParaType_Tex:
650 hc_state->texture = 0;
653 case (HC_ParaType_Tex | (HC_SubType_Tex1 << 8)):
654 hc_state->texture = 1;
657 case (HC_ParaType_Tex | (HC_SubType_TexGeneral << 8)):
660 case HC_ParaType_Auto:
661 if (eat_words(&buf, buf_end, 2))
664 return state_command;
665 case (HC_ParaType_Palette | (HC_SubType_Stipple << 8)):
666 if (eat_words(&buf, buf_end, 32))
669 return state_command;
670 case (HC_ParaType_Palette | (HC_SubType_TexPalette0 << 8)):
671 case (HC_ParaType_Palette | (HC_SubType_TexPalette1 << 8)):
672 DRM_ERROR("Texture palettes are rejected because of "
673 "lack of info how to determine their size.\n");
675 case (HC_ParaType_Palette | (HC_SubType_FogTable << 8)):
676 DRM_ERROR("Fog factor palettes are rejected because of "
677 "lack of info how to determine their size.\n");
682 * There are some unimplemented HC_ParaTypes here, that
683 * need to be implemented if the Mesa driver is extended.
686 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
687 "DMA subcommand: 0x%x. Previous dword: 0x%x\n",
693 while (buf < buf_end) {
695 if ((hz = hz_table[cmd >> 24])) {
696 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
703 } else if (hc_state->unfinished &&
704 finish_current_sequence(hc_state)) {
708 if (hc_state->unfinished && finish_current_sequence(hc_state)) {
712 return state_command;
715 static __inline__ verifier_state_t
716 via_parse_header2(drm_via_private_t * dev_priv, uint32_t const **buffer,
717 const uint32_t * buf_end, int *fire_count)
720 const uint32_t *buf = *buffer;
721 const uint32_t *next_fire;
724 next_fire = dev_priv->fire_offsets[*fire_count];
726 cmd = (*buf & 0xFFFF0000) >> 16;
727 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
729 case HC_ParaType_CmdVdata:
730 while ((buf < buf_end) &&
731 (*fire_count < dev_priv->num_fire_offsets) &&
732 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
733 while (buf <= next_fire) {
734 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
735 (burst & 63), *buf++);
739 && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
742 if (++(*fire_count) < dev_priv->num_fire_offsets)
743 next_fire = dev_priv->fire_offsets[*fire_count];
747 while (buf < buf_end) {
749 if (*buf == HC_HEADER2 ||
750 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 ||
751 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 ||
752 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
755 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
756 (burst & 63), *buf++);
761 return state_command;
764 static __inline__ int verify_mmio_address(uint32_t address)
766 if ((address > 0x3FF) && (address < 0xC00)) {
767 DRM_ERROR("Invalid VIDEO DMA command. "
768 "Attempt to access 3D- or command burst area.\n");
770 } else if ((address > 0xCFF) && (address < 0x1300)) {
771 DRM_ERROR("Invalid VIDEO DMA command. "
772 "Attempt to access PCI DMA area.\n");
774 } else if (address > 0x13FF) {
775 DRM_ERROR("Invalid VIDEO DMA command. "
776 "Attempt to access VGA registers.\n");
782 static __inline__ int
783 verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end,
786 const uint32_t *buf = *buffer;
788 if (buf_end - buf < dwords) {
789 DRM_ERROR("Illegal termination of video command.\n");
794 DRM_ERROR("Illegal video command tail.\n");
802 static __inline__ verifier_state_t
803 via_check_header1(uint32_t const **buffer, const uint32_t * buf_end)
806 const uint32_t *buf = *buffer;
807 verifier_state_t ret = state_command;
809 while (buf < buf_end) {
811 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
812 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
813 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
815 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
816 "Attempt to access 3D- or command burst area.\n");
819 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
820 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
822 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
823 "Attempt to access VGA registers.\n");
834 static __inline__ verifier_state_t
835 via_parse_header1(drm_via_private_t * dev_priv, uint32_t const **buffer,
836 const uint32_t * buf_end)
838 register uint32_t cmd;
839 const uint32_t *buf = *buffer;
841 while (buf < buf_end) {
843 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
845 VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
849 return state_command;
852 static __inline__ verifier_state_t
853 via_check_vheader5(uint32_t const **buffer, const uint32_t * buf_end)
856 const uint32_t *buf = *buffer;
858 if (buf_end - buf < 4) {
859 DRM_ERROR("Illegal termination of video header5 command\n");
863 data = *buf++ & ~VIA_VIDEOMASK;
864 if (verify_mmio_address(data))
868 if (*buf++ != 0x00F50000) {
869 DRM_ERROR("Illegal header5 header data\n");
872 if (*buf++ != 0x00000000) {
873 DRM_ERROR("Illegal header5 header data\n");
876 if (eat_words(&buf, buf_end, data))
878 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
881 return state_command;
885 static __inline__ verifier_state_t
886 via_parse_vheader5(drm_via_private_t * dev_priv, uint32_t const **buffer,
887 const uint32_t * buf_end)
889 uint32_t addr, count, i;
890 const uint32_t *buf = *buffer;
892 addr = *buf++ & ~VIA_VIDEOMASK;
896 VIA_WRITE(addr, *buf++);
899 buf += 4 - (count & 3);
901 return state_command;
904 static __inline__ verifier_state_t
905 via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end)
908 const uint32_t *buf = *buffer;
911 if (buf_end - buf < 4) {
912 DRM_ERROR("Illegal termination of video header6 command\n");
917 if (*buf++ != 0x00F60000) {
918 DRM_ERROR("Illegal header6 header data\n");
921 if (*buf++ != 0x00000000) {
922 DRM_ERROR("Illegal header6 header data\n");
925 if ((buf_end - buf) < (data << 1)) {
926 DRM_ERROR("Illegal termination of video header6 command\n");
929 for (i = 0; i < data; ++i) {
930 if (verify_mmio_address(*buf++))
935 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
938 return state_command;
941 static __inline__ verifier_state_t
942 via_parse_vheader6(drm_via_private_t * dev_priv, uint32_t const **buffer,
943 const uint32_t * buf_end)
946 uint32_t addr, count, i;
947 const uint32_t *buf = *buffer;
953 VIA_WRITE(addr, *buf++);
957 buf += 4 - (count & 3);
959 return state_command;
963 via_verify_command_stream(const uint32_t * buf, unsigned int size,
964 struct drm_device * dev, int agp)
967 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
968 drm_via_state_t *hc_state = &dev_priv->hc_state;
969 drm_via_state_t saved_state = *hc_state;
971 const uint32_t *buf_end = buf + (size >> 2);
972 verifier_state_t state = state_command;
976 cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A ||
977 dev_priv->chipset == VIA_DX9_0);
979 supported_3d = dev_priv->chipset != VIA_DX9_0;
982 hc_state->unfinished = no_sequence;
983 hc_state->map_cache = NULL;
985 hc_state->buf_start = buf;
986 dev_priv->num_fire_offsets = 0;
988 while (buf < buf_end) {
992 state = via_check_header2(&buf, buf_end, hc_state);
995 state = via_check_header1(&buf, buf_end);
998 state = via_check_vheader5(&buf, buf_end);
1000 case state_vheader6:
1001 state = via_check_vheader6(&buf, buf_end);
1004 if ((HALCYON_HEADER2 == (cmd = *buf)) &&
1006 state = state_header2;
1007 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1008 state = state_header1;
1010 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1011 state = state_vheader5;
1013 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1014 state = state_vheader6;
1015 else if ((cmd == HALCYON_HEADER2) && !supported_3d) {
1016 DRM_ERROR("Accelerated 3D is not supported on this chipset yet.\n");
1017 state = state_error;
1020 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1022 state = state_error;
1027 *hc_state = saved_state;
1031 if (state == state_error) {
1032 *hc_state = saved_state;
1039 via_parse_command_stream(struct drm_device * dev, const uint32_t * buf,
1043 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
1045 const uint32_t *buf_end = buf + (size >> 2);
1046 verifier_state_t state = state_command;
1049 while (buf < buf_end) {
1054 via_parse_header2(dev_priv, &buf, buf_end,
1058 state = via_parse_header1(dev_priv, &buf, buf_end);
1060 case state_vheader5:
1061 state = via_parse_vheader5(dev_priv, &buf, buf_end);
1063 case state_vheader6:
1064 state = via_parse_vheader6(dev_priv, &buf, buf_end);
1067 if (HALCYON_HEADER2 == (cmd = *buf))
1068 state = state_header2;
1069 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1070 state = state_header1;
1071 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1072 state = state_vheader5;
1073 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1074 state = state_vheader6;
1077 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1079 state = state_error;
1087 if (state == state_error) {
1094 setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
1098 for (i = 0; i < 256; ++i) {
1099 table[i] = forbidden_command;
1102 for (i = 0; i < size; ++i) {
1103 table[init_table[i].code] = init_table[i].hz;
1107 void via_init_command_verifier(void)
1109 setup_hazard_table(init_table1, table1,
1110 sizeof(init_table1) / sizeof(hz_init_t));
1111 setup_hazard_table(init_table2, table2,
1112 sizeof(init_table2) / sizeof(hz_init_t));
1113 setup_hazard_table(init_table3, table3,
1114 sizeof(init_table3) / sizeof(hz_init_t));