2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __DRM_EDID_H__
24 #define __DRM_EDID_H__
26 #define EDID_LENGTH 128
39 } __attribute__((packed));
41 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
42 #define EDID_TIMING_ASPECT_SHIFT 6
43 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
46 #define EDID_TIMING_VFREQ_SHIFT 0
47 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
50 u8 hsize; /* need to multiply by 8 then add 248 */
52 } __attribute__((packed));
54 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
55 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
56 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
57 #define DRM_EDID_PT_STEREO (1 << 5)
58 #define DRM_EDID_PT_INTERLACED (1 << 7)
60 /* If detailed data is pixel timing */
61 struct detailed_pixel_timing {
69 u8 hsync_pulse_width_lo;
70 u8 vsync_offset_pulse_width_lo;
71 u8 hsync_vsync_offset_pulse_width_hi;
74 u8 width_height_mm_hi;
78 } __attribute__((packed));
80 /* If it's not pixel timing, it'll be one of the below */
81 struct detailed_data_string {
83 } __attribute__((packed));
85 struct detailed_data_monitor_range {
90 u8 pixel_clock_mhz; /* need to multiply by 10 */
95 u8 hfreq_start_khz; /* need to multiply by 2 */
96 u8 c; /* need to divide by 2 */
99 u8 j; /* need to divide by 2 */
100 } __attribute__((packed)) gtf2;
103 u8 data1; /* high 6 bits: extra clock resolution */
104 u8 data2; /* plus low 2 of above: max hactive */
105 u8 supported_aspects;
106 u8 flags; /* preferred aspect and blanking support */
107 u8 supported_scalings;
108 u8 preferred_refresh;
109 } __attribute__((packed)) cvt;
111 } __attribute__((packed));
113 struct detailed_data_wpindex {
114 u8 white_yx_lo; /* Lower 2 bits each */
117 u8 gamma; /* need to divide by 100 then add 1 */
118 } __attribute__((packed));
120 struct detailed_data_color_point {
125 } __attribute__((packed));
129 } __attribute__((packed));
131 struct detailed_non_pixel {
133 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
134 fb=color point data, fa=standard timing data,
135 f9=undefined, f8=mfg. reserved */
138 struct detailed_data_string str;
139 struct detailed_data_monitor_range range;
140 struct detailed_data_wpindex color;
141 struct std_timing timings[6];
142 struct cvt_timing cvt[4];
144 } __attribute__((packed));
146 #define EDID_DETAIL_EST_TIMINGS 0xf7
147 #define EDID_DETAIL_CVT_3BYTE 0xf8
148 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
149 #define EDID_DETAIL_STD_MODES 0xfa
150 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
151 #define EDID_DETAIL_MONITOR_NAME 0xfc
152 #define EDID_DETAIL_MONITOR_RANGE 0xfd
153 #define EDID_DETAIL_MONITOR_STRING 0xfe
154 #define EDID_DETAIL_MONITOR_SERIAL 0xff
156 struct detailed_timing {
157 __le16 pixel_clock; /* need to multiply by 10 KHz */
159 struct detailed_pixel_timing pixel_data;
160 struct detailed_non_pixel other_data;
162 } __attribute__((packed));
164 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
165 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
166 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
167 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
168 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
169 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
170 #define DRM_EDID_INPUT_DIGITAL (1 << 7)
171 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
172 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
173 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
174 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
175 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
176 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
177 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
178 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
179 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
180 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
181 #define DRM_EDID_DIGITAL_TYPE_DVI (1)
182 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
183 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
184 #define DRM_EDID_DIGITAL_TYPE_MDDI (4)
185 #define DRM_EDID_DIGITAL_TYPE_DP (5)
187 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
188 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
189 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
191 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
193 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
194 #define DRM_EDID_FEATURE_RGB (0 << 3)
195 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
196 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
197 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
199 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
200 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
201 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
205 /* Vendor & product info */
208 u32 serial; /* FIXME: byte order */
220 /* Color characteristics */
231 /* Est. timings and mfg rsvd timings*/
232 struct est_timings established_timings;
233 /* Standard timings 1-8*/
234 struct std_timing standard_timings[8];
235 /* Detailing timings 1-4 */
236 struct detailed_timing detailed_timings[4];
237 /* Number of 128 byte ext. blocks */
241 } __attribute__((packed));
243 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
246 struct drm_connector;
247 struct drm_display_mode;
248 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
249 int drm_av_sync_delay(struct drm_connector *connector,
250 struct drm_display_mode *mode);
251 struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
252 struct drm_display_mode *mode);
253 int drm_load_edid_firmware(struct drm_connector *connector);
255 #endif /* __DRM_EDID_H__ */