2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
34 * register definitions for the i82807aa.
36 * Documentation on this chipset can be found in datasheet #29069001 at
41 * VCH Revision & GMBus Base Addr
44 # define VR00_BASE_ADDRESS_MASK 0x007f
47 * Functionality Enable
52 * Enable the panel fitter
54 # define VR01_PANEL_FIT_ENABLE (1 << 3)
56 * Enables the LCD display.
58 * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
60 # define VR01_LCD_ENABLE (1 << 2)
61 /** Enables the DVO repeater. */
62 # define VR01_DVO_BYPASS_ENABLE (1 << 1)
63 /** Enables the DVO clock */
64 # define VR01_DVO_ENABLE (1 << 0)
67 * LCD Interface Format
70 /** Enables LVDS output instead of CMOS */
71 # define VR10_LVDS_ENABLE (1 << 4)
72 /** Enables 18-bit LVDS output. */
73 # define VR10_INTERFACE_1X18 (0 << 2)
74 /** Enables 24-bit LVDS or CMOS output */
75 # define VR10_INTERFACE_1X24 (1 << 2)
76 /** Enables 2x18-bit LVDS or CMOS output. */
77 # define VR10_INTERFACE_2X18 (2 << 2)
78 /** Enables 2x24-bit LVDS output */
79 # define VR10_INTERFACE_2X24 (3 << 2)
82 * VR20 LCD Horizontal Display Size
87 * LCD Vertical Display Size
92 * Panel power down status
95 /** Read only bit indicating that the panel is not in a safe poweroff state. */
96 # define VR30_PANEL_ON (1 << 15)
99 # define VR40_STALL_ENABLE (1 << 13)
100 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
101 # define VR40_ENHANCED_PANEL_FITTING (1 << 11)
102 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
103 # define VR40_AUTO_RATIO_ENABLE (1 << 9)
104 # define VR40_CLOCK_GATING_ENABLE (1 << 8)
107 * Panel Fitting Vertical Ratio
108 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
113 * Panel Fitting Horizontal Ratio
114 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
119 * Horizontal Image Size
138 /* Graphics BIOS scratch 0
141 # define VR8E_PANEL_TYPE_MASK (0xf << 0)
142 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
143 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
144 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
146 /* Graphics BIOS scratch 1
149 # define VR8F_VCH_PRESENT (1 << 0)
150 # define VR8F_DISPLAY_CONN (1 << 1)
151 # define VR8F_POWER_MASK (0x3c)
152 # define VR8F_POWER_POS (2)
158 uint16_t width, height;
162 static void ivch_dump_regs(struct intel_dvo_device *dvo);
165 * Reads a register on the ivch.
167 * Each of the 256 registers are 16 bits long.
169 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
171 struct ivch_priv *priv = dvo->dev_priv;
172 device_t adapter = dvo->i2c_bus;
176 struct iic_msg msgs[] = {
178 .slave = dvo->slave_addr << 1,
184 .flags = I2C_M_NOSTART,
189 .slave = dvo->slave_addr << 1,
190 .flags = I2C_M_RD | I2C_M_NOSTART,
198 if (-iicbus_transfer(adapter, msgs, 3) == 0) {
199 *data = (in_buf[1] << 8) | in_buf[0];
204 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
206 addr, device_get_nameunit(adapter), dvo->slave_addr);
211 /** Writes a 16-bit register on the ivch */
212 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
214 struct ivch_priv *priv = dvo->dev_priv;
215 device_t adapter = dvo->i2c_bus;
217 struct iic_msg msg = {
218 .slave = dvo->slave_addr << 1,
225 out_buf[1] = data & 0xff;
226 out_buf[2] = data >> 8;
228 if (-iicbus_transfer(adapter, &msg, 1) == 0)
232 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
233 addr, device_get_nameunit(adapter), dvo->slave_addr);
239 /** Probes the given bus and slave address for an ivch */
240 static bool ivch_init(struct intel_dvo_device *dvo,
243 struct ivch_priv *priv;
246 priv = malloc(sizeof(struct ivch_priv), DRM_MEM_KMS, M_NOWAIT | M_ZERO);
250 dvo->i2c_bus = adapter;
251 dvo->dev_priv = priv;
254 if (!ivch_read(dvo, VR00, &temp))
258 /* Since the identification bits are probably zeroes, which doesn't seem
259 * very unique, check that the value in the base address field matches
260 * the address it's responding on.
262 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
263 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
265 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
269 ivch_read(dvo, VR20, &priv->width);
270 ivch_read(dvo, VR21, &priv->height);
275 free(priv, DRM_MEM_KMS);
279 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
281 return connector_status_connected;
284 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
285 struct drm_display_mode *mode)
287 if (mode->clock > 112000)
288 return MODE_CLOCK_HIGH;
293 /** Sets the power state of the panel connected to the ivch */
294 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
297 uint16_t vr01, vr30, backlight;
299 /* Set the new power state of the panel. */
300 if (!ivch_read(dvo, VR01, &vr01))
307 ivch_write(dvo, VR80, backlight);
310 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
312 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
314 ivch_write(dvo, VR01, vr01);
316 /* Wait for the panel to make its state transition */
317 for (i = 0; i < 100; i++) {
318 if (!ivch_read(dvo, VR30, &vr30))
321 if (((vr30 & VR30_PANEL_ON) != 0) == enable)
325 /* wait some more; vch may fail to resync sometimes without this */
329 static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
333 /* Set the new power state of the panel. */
334 if (!ivch_read(dvo, VR01, &vr01))
337 if (vr01 & VR01_LCD_ENABLE)
343 static void ivch_mode_set(struct intel_dvo_device *dvo,
344 struct drm_display_mode *mode,
345 struct drm_display_mode *adjusted_mode)
351 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
352 VR40_HORIZONTAL_INTERP_ENABLE);
354 if (mode->hdisplay != adjusted_mode->hdisplay ||
355 mode->vdisplay != adjusted_mode->vdisplay) {
356 uint16_t x_ratio, y_ratio;
358 vr01 |= VR01_PANEL_FIT_ENABLE;
359 vr40 |= VR40_CLOCK_GATING_ENABLE;
360 x_ratio = (((mode->hdisplay - 1) << 16) /
361 (adjusted_mode->hdisplay - 1)) >> 2;
362 y_ratio = (((mode->vdisplay - 1) << 16) /
363 (adjusted_mode->vdisplay - 1)) >> 2;
364 ivch_write(dvo, VR42, x_ratio);
365 ivch_write(dvo, VR41, y_ratio);
367 vr01 &= ~VR01_PANEL_FIT_ENABLE;
368 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
370 vr40 &= ~VR40_AUTO_RATIO_ENABLE;
372 ivch_write(dvo, VR01, vr01);
373 ivch_write(dvo, VR40, vr40);
378 static void ivch_dump_regs(struct intel_dvo_device *dvo)
382 ivch_read(dvo, VR00, &val);
383 DRM_LOG_KMS("VR00: 0x%04x\n", val);
384 ivch_read(dvo, VR01, &val);
385 DRM_LOG_KMS("VR01: 0x%04x\n", val);
386 ivch_read(dvo, VR30, &val);
387 DRM_LOG_KMS("VR30: 0x%04x\n", val);
388 ivch_read(dvo, VR40, &val);
389 DRM_LOG_KMS("VR40: 0x%04x\n", val);
392 ivch_read(dvo, VR80, &val);
393 DRM_LOG_KMS("VR80: 0x%04x\n", val);
394 ivch_read(dvo, VR81, &val);
395 DRM_LOG_KMS("VR81: 0x%04x\n", val);
396 ivch_read(dvo, VR82, &val);
397 DRM_LOG_KMS("VR82: 0x%04x\n", val);
398 ivch_read(dvo, VR83, &val);
399 DRM_LOG_KMS("VR83: 0x%04x\n", val);
400 ivch_read(dvo, VR84, &val);
401 DRM_LOG_KMS("VR84: 0x%04x\n", val);
402 ivch_read(dvo, VR85, &val);
403 DRM_LOG_KMS("VR85: 0x%04x\n", val);
404 ivch_read(dvo, VR86, &val);
405 DRM_LOG_KMS("VR86: 0x%04x\n", val);
406 ivch_read(dvo, VR87, &val);
407 DRM_LOG_KMS("VR87: 0x%04x\n", val);
408 ivch_read(dvo, VR88, &val);
409 DRM_LOG_KMS("VR88: 0x%04x\n", val);
411 /* Scratch register 0 - AIM Panel type */
412 ivch_read(dvo, VR8E, &val);
413 DRM_LOG_KMS("VR8E: 0x%04x\n", val);
415 /* Scratch register 1 - Status register */
416 ivch_read(dvo, VR8F, &val);
417 DRM_LOG_KMS("VR8F: 0x%04x\n", val);
420 static void ivch_destroy(struct intel_dvo_device *dvo)
422 struct ivch_priv *priv = dvo->dev_priv;
425 free(priv, DRM_MEM_KMS);
426 dvo->dev_priv = NULL;
430 struct intel_dvo_dev_ops ivch_ops = {
433 .get_hw_state = ivch_get_hw_state,
434 .mode_valid = ivch_mode_valid,
435 .mode_set = ivch_mode_set,
436 .detect = ivch_detect,
437 .dump_regs = ivch_dump_regs,
438 .destroy = ivch_destroy,