2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 #include <sys/cdefs.h>
55 __FBSDID("$FreeBSD$");
57 #include <dev/drm2/drmP.h>
58 #include <dev/drm2/i915/i915_drm.h>
59 #include <dev/drm2/i915/i915_drv.h>
60 #include <dev/drm2/i915/intel_drv.h>
62 #include <sys/resourcevar.h>
63 #include <sys/sched.h>
64 #include <sys/sf_buf.h>
67 #include <vm/vm_pageout.h>
69 #include <machine/md_var.h>
71 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
72 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
73 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
75 bool map_and_fenceable,
77 static int i915_gem_phys_pwrite(struct drm_device *dev,
78 struct drm_i915_gem_object *obj,
79 struct drm_i915_gem_pwrite *args,
80 struct drm_file *file);
82 static void i915_gem_write_fence(struct drm_device *dev, int reg,
83 struct drm_i915_gem_object *obj);
84 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
85 struct drm_i915_fence_reg *fence,
88 static void i915_gem_inactive_shrink(void *);
89 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
90 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
91 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
93 static int i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
94 off_t start, off_t end);
96 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex,
99 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
100 long i915_gem_wired_pages_cnt;
102 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
104 if (obj->tiling_mode)
105 i915_gem_release_mmap(obj);
107 /* As we do not have an associated fence register, we will force
108 * a tiling change if we ever need to acquire one.
110 obj->fence_dirty = false;
111 obj->fence_reg = I915_FENCE_REG_NONE;
114 /* some bookkeeping */
115 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
118 dev_priv->mm.object_count++;
119 dev_priv->mm.object_memory += size;
122 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
125 dev_priv->mm.object_count--;
126 dev_priv->mm.object_memory -= size;
130 i915_gem_wait_for_error(struct drm_device *dev)
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct completion *x = &dev_priv->error_completion;
136 if (!atomic_read(&dev_priv->mm.wedged))
140 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
141 * userspace. If it takes that long something really bad is going on and
142 * we should simply try to bail out and fail as gracefully as possible.
144 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
146 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
148 } else if (ret < 0) {
152 if (atomic_read(&dev_priv->mm.wedged)) {
153 /* GPU is hung, bump the completion count to account for
154 * the token we just consumed so that we never hit zero and
155 * end up waiting upon a subsequent completion event that
160 mtx_unlock(&x->lock);
165 int i915_mutex_lock_interruptible(struct drm_device *dev)
169 ret = i915_gem_wait_for_error(dev);
174 * interruptible shall it be. might indeed be if dev_lock is
177 ret = sx_xlock_sig(&dev->dev_struct_lock);
181 WARN_ON(i915_verify_lists(dev));
186 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
188 return obj->gtt_space && !obj->active;
192 i915_gem_init_ioctl(struct drm_device *dev, void *data,
193 struct drm_file *file)
195 struct drm_i915_gem_init *args = data;
197 if (drm_core_check_feature(dev, DRIVER_MODESET))
200 if (args->gtt_start >= args->gtt_end ||
201 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
204 /* GEM with user mode setting was never supported on ilk and later. */
205 if (INTEL_INFO(dev)->gen >= 5)
209 * XXXKIB. The second-time initialization should be guarded
213 i915_gem_init_global_gtt(dev, args->gtt_start,
214 args->gtt_end, args->gtt_end);
221 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
222 struct drm_file *file)
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 struct drm_i915_gem_get_aperture *args = data;
226 struct drm_i915_gem_object *obj;
231 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
233 pinned += obj->gtt_space->size;
236 args->aper_size = dev_priv->mm.gtt_total;
237 args->aper_available_size = args->aper_size - pinned;
243 i915_gem_create(struct drm_file *file,
244 struct drm_device *dev,
248 struct drm_i915_gem_object *obj;
252 size = roundup(size, PAGE_SIZE);
256 /* Allocate the new object */
257 obj = i915_gem_alloc_object(dev, size);
261 ret = drm_gem_handle_create(file, &obj->base, &handle);
263 drm_gem_object_release(&obj->base);
264 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
265 free(obj, DRM_I915_GEM);
269 /* drop reference from allocate - handle holds it now */
270 drm_gem_object_unreference(&obj->base);
271 CTR2(KTR_DRM, "object_create %p %x", obj, size);
278 i915_gem_dumb_create(struct drm_file *file,
279 struct drm_device *dev,
280 struct drm_mode_create_dumb *args)
282 /* have to work out size/pitch and return them */
283 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
284 args->size = args->pitch * args->height;
285 return i915_gem_create(file, dev,
286 args->size, &args->handle);
289 int i915_gem_dumb_destroy(struct drm_file *file,
290 struct drm_device *dev,
293 return drm_gem_handle_delete(file, handle);
297 * Creates a new mm object and returns a handle to it.
300 i915_gem_create_ioctl(struct drm_device *dev, void *data,
301 struct drm_file *file)
303 struct drm_i915_gem_create *args = data;
305 return i915_gem_create(file, dev,
306 args->size, &args->handle);
309 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
311 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
314 obj->tiling_mode != I915_TILING_NONE;
318 __copy_to_user_swizzled(char __user *cpu_vaddr,
319 const char *gpu_vaddr, int gpu_offset,
322 int ret, cpu_offset = 0;
325 int cacheline_end = roundup2(gpu_offset + 1, 64);
326 int this_length = min(cacheline_end - gpu_offset, length);
327 int swizzled_gpu_offset = gpu_offset ^ 64;
329 ret = __copy_to_user(cpu_vaddr + cpu_offset,
330 gpu_vaddr + swizzled_gpu_offset,
335 cpu_offset += this_length;
336 gpu_offset += this_length;
337 length -= this_length;
344 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
345 const char __user *cpu_vaddr,
348 int ret, cpu_offset = 0;
351 int cacheline_end = roundup2(gpu_offset + 1, 64);
352 int this_length = min(cacheline_end - gpu_offset, length);
353 int swizzled_gpu_offset = gpu_offset ^ 64;
355 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
356 cpu_vaddr + cpu_offset,
361 cpu_offset += this_length;
362 gpu_offset += this_length;
363 length -= this_length;
369 /* Per-page copy function for the shmem pread fastpath.
370 * Flushes invalid cachelines before reading the target if
371 * needs_clflush is set. */
373 shmem_pread_fast(vm_page_t page, int shmem_page_offset, int page_length,
374 char __user *user_data,
375 bool page_do_bit17_swizzling, bool needs_clflush)
381 if (unlikely(page_do_bit17_swizzling))
385 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE);
390 vaddr = (char *)sf_buf_kva(sf);
392 drm_clflush_virt_range(vaddr + shmem_page_offset,
394 ret = __copy_to_user_inatomic(user_data,
395 vaddr + shmem_page_offset,
400 return ret ? -EFAULT : 0;
404 shmem_clflush_swizzled_range(char *addr, unsigned long length,
407 if (unlikely(swizzled)) {
408 unsigned long start = (unsigned long) addr;
409 unsigned long end = (unsigned long) addr + length;
411 /* For swizzling simply ensure that we always flush both
412 * channels. Lame, but simple and it works. Swizzled
413 * pwrite/pread is far from a hotpath - current userspace
414 * doesn't use it at all. */
415 start = round_down(start, 128);
416 end = round_up(end, 128);
418 drm_clflush_virt_range((void *)start, end - start);
420 drm_clflush_virt_range(addr, length);
425 /* Only difference to the fast-path function is that this can handle bit17
426 * and uses non-atomic copy and kmap functions. */
428 shmem_pread_slow(vm_page_t page, int shmem_page_offset, int page_length,
429 char __user *user_data,
430 bool page_do_bit17_swizzling, bool needs_clflush)
436 sf = sf_buf_alloc(page, 0);
437 vaddr = (char *)sf_buf_kva(sf);
439 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
441 page_do_bit17_swizzling);
443 if (page_do_bit17_swizzling)
444 ret = __copy_to_user_swizzled(user_data,
445 vaddr, shmem_page_offset,
448 ret = __copy_to_user(user_data,
449 vaddr + shmem_page_offset,
453 return ret ? - EFAULT : 0;
457 i915_gem_shmem_pread(struct drm_device *dev,
458 struct drm_i915_gem_object *obj,
459 struct drm_i915_gem_pread *args,
460 struct drm_file *file)
462 char __user *user_data;
465 int shmem_page_offset, page_length, ret = 0;
466 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
467 int hit_slowpath = 0;
469 int needs_clflush = 0;
471 user_data = to_user_ptr(args->data_ptr);
474 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
476 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
477 /* If we're not in the cpu read domain, set ourself into the gtt
478 * read domain and manually flush cachelines (if required). This
479 * optimizes for the case when the gpu will dirty the data
480 * anyway again before the next pread happens. */
481 if (obj->cache_level == I915_CACHE_NONE)
483 if (obj->gtt_space) {
484 ret = i915_gem_object_set_to_gtt_domain(obj, false);
490 ret = i915_gem_object_get_pages(obj);
494 i915_gem_object_pin_pages(obj);
496 offset = args->offset;
498 VM_OBJECT_WLOCK(obj->base.vm_obj);
499 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
500 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
501 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
506 /* Operation in this page
508 * shmem_page_offset = offset within page in shmem file
509 * page_length = bytes to copy for this page
511 shmem_page_offset = offset_in_page(offset);
512 page_length = remain;
513 if ((shmem_page_offset + page_length) > PAGE_SIZE)
514 page_length = PAGE_SIZE - shmem_page_offset;
516 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
517 (page_to_phys(page) & (1 << 17)) != 0;
519 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
520 user_data, page_do_bit17_swizzling,
529 ret = fault_in_multipages_writeable(user_data, remain);
530 /* Userspace is tricking us, but we've already clobbered
531 * its pages with the prefault and promised to write the
532 * data up to the first fault. Hence ignore any errors
533 * and just continue. */
538 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
539 user_data, page_do_bit17_swizzling,
545 vm_page_reference(page);
550 remain -= page_length;
551 user_data += page_length;
552 offset += page_length;
553 VM_OBJECT_WLOCK(obj->base.vm_obj);
557 i915_gem_object_unpin_pages(obj);
560 /* Fixup: Kill any reinstated backing storage pages */
561 if (obj->madv == __I915_MADV_PURGED)
562 i915_gem_object_truncate(obj);
569 * Reads data from the object referenced by handle.
571 * On error, the contents of *data are undefined.
574 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
575 struct drm_file *file)
577 struct drm_i915_gem_pread *args = data;
578 struct drm_i915_gem_object *obj;
584 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_WRITE))
587 ret = i915_mutex_lock_interruptible(dev);
591 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
592 if (&obj->base == NULL) {
597 /* Bounds check source. */
598 if (args->offset > obj->base.size ||
599 args->size > obj->base.size - args->offset) {
605 /* prime objects have no backing filp to GEM pread/pwrite
608 if (!obj->base.filp) {
612 #endif /* FREEBSD_WIP */
614 CTR3(KTR_DRM, "pread %p %jx %jx", obj, args->offset, args->size);
616 ret = i915_gem_shmem_pread(dev, obj, args, file);
619 drm_gem_object_unreference(&obj->base);
625 /* This is the fast write path which cannot handle
626 * page faults in the source data
630 fast_user_write(vm_paddr_t mapping_addr,
631 off_t page_base, int page_offset,
632 char __user *user_data,
635 void __iomem *vaddr_atomic;
637 unsigned long unwritten;
639 vaddr_atomic = pmap_mapdev_attr(mapping_addr + page_base,
640 length, PAT_WRITE_COMBINING);
641 /* We can use the cpu mem copy function because this is X86. */
642 vaddr = (char __force*)vaddr_atomic + page_offset;
643 unwritten = __copy_from_user_inatomic_nocache(vaddr,
645 pmap_unmapdev((vm_offset_t)vaddr_atomic, length);
650 * This is the fast pwrite path, where we copy the data directly from the
651 * user into the GTT, uncached.
654 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
655 struct drm_i915_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file)
659 drm_i915_private_t *dev_priv = dev->dev_private;
661 off_t offset, page_base;
662 char __user *user_data;
663 int page_offset, page_length, ret;
665 ret = i915_gem_object_pin(obj, 0, true, true);
669 ret = i915_gem_object_set_to_gtt_domain(obj, true);
673 ret = i915_gem_object_put_fence(obj);
677 user_data = to_user_ptr(args->data_ptr);
680 offset = obj->gtt_offset + args->offset;
683 /* Operation in this page
685 * page_base = page offset within aperture
686 * page_offset = offset within page
687 * page_length = bytes to copy for this page
689 page_base = offset & ~PAGE_MASK;
690 page_offset = offset_in_page(offset);
691 page_length = remain;
692 if ((page_offset + remain) > PAGE_SIZE)
693 page_length = PAGE_SIZE - page_offset;
695 /* If we get a fault while copying data, then (presumably) our
696 * source page isn't available. Return the error and we'll
697 * retry in the slow path.
699 if (fast_user_write(dev_priv->mm.gtt_base_addr, page_base,
700 page_offset, user_data, page_length)) {
705 remain -= page_length;
706 user_data += page_length;
707 offset += page_length;
711 i915_gem_object_unpin(obj);
716 /* Per-page copy function for the shmem pwrite fastpath.
717 * Flushes invalid cachelines before writing to the target if
718 * needs_clflush_before is set and flushes out any written cachelines after
719 * writing if needs_clflush is set. */
721 shmem_pwrite_fast(vm_page_t page, int shmem_page_offset, int page_length,
722 char __user *user_data,
723 bool page_do_bit17_swizzling,
724 bool needs_clflush_before,
725 bool needs_clflush_after)
731 if (unlikely(page_do_bit17_swizzling))
735 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE);
740 vaddr = (char *)sf_buf_kva(sf);
741 if (needs_clflush_before)
742 drm_clflush_virt_range(vaddr + shmem_page_offset,
744 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
747 if (needs_clflush_after)
748 drm_clflush_virt_range(vaddr + shmem_page_offset,
753 return ret ? -EFAULT : 0;
756 /* Only difference to the fast-path function is that this can handle bit17
757 * and uses non-atomic copy and kmap functions. */
759 shmem_pwrite_slow(vm_page_t page, int shmem_page_offset, int page_length,
760 char __user *user_data,
761 bool page_do_bit17_swizzling,
762 bool needs_clflush_before,
763 bool needs_clflush_after)
769 sf = sf_buf_alloc(page, 0);
770 vaddr = (char *)sf_buf_kva(sf);
771 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
772 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
774 page_do_bit17_swizzling);
775 if (page_do_bit17_swizzling)
776 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
780 ret = __copy_from_user(vaddr + shmem_page_offset,
783 if (needs_clflush_after)
784 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
786 page_do_bit17_swizzling);
789 return ret ? -EFAULT : 0;
793 i915_gem_shmem_pwrite(struct drm_device *dev,
794 struct drm_i915_gem_object *obj,
795 struct drm_i915_gem_pwrite *args,
796 struct drm_file *file)
800 char __user *user_data;
801 int shmem_page_offset, page_length, ret = 0;
802 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
803 int hit_slowpath = 0;
804 int needs_clflush_after = 0;
805 int needs_clflush_before = 0;
807 user_data = to_user_ptr(args->data_ptr);
810 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
812 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
813 /* If we're not in the cpu write domain, set ourself into the gtt
814 * write domain and manually flush cachelines (if required). This
815 * optimizes for the case when the gpu will use the data
816 * right away and we therefore have to clflush anyway. */
817 if (obj->cache_level == I915_CACHE_NONE)
818 needs_clflush_after = 1;
819 if (obj->gtt_space) {
820 ret = i915_gem_object_set_to_gtt_domain(obj, true);
825 /* Same trick applies for invalidate partially written cachelines before
827 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
828 && obj->cache_level == I915_CACHE_NONE)
829 needs_clflush_before = 1;
831 ret = i915_gem_object_get_pages(obj);
835 i915_gem_object_pin_pages(obj);
837 offset = args->offset;
840 VM_OBJECT_WLOCK(obj->base.vm_obj);
841 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
842 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
843 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
844 int partial_cacheline_write;
849 /* Operation in this page
851 * shmem_page_offset = offset within page in shmem file
852 * page_length = bytes to copy for this page
854 shmem_page_offset = offset_in_page(offset);
856 page_length = remain;
857 if ((shmem_page_offset + page_length) > PAGE_SIZE)
858 page_length = PAGE_SIZE - shmem_page_offset;
860 /* If we don't overwrite a cacheline completely we need to be
861 * careful to have up-to-date data by first clflushing. Don't
862 * overcomplicate things and flush the entire patch. */
863 partial_cacheline_write = needs_clflush_before &&
864 ((shmem_page_offset | page_length)
865 & (cpu_clflush_line_size - 1));
867 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
868 (page_to_phys(page) & (1 << 17)) != 0;
870 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
871 user_data, page_do_bit17_swizzling,
872 partial_cacheline_write,
873 needs_clflush_after);
879 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
880 user_data, page_do_bit17_swizzling,
881 partial_cacheline_write,
882 needs_clflush_after);
888 vm_page_reference(page);
893 remain -= page_length;
894 user_data += page_length;
895 offset += page_length;
896 VM_OBJECT_WLOCK(obj->base.vm_obj);
900 i915_gem_object_unpin_pages(obj);
903 /* Fixup: Kill any reinstated backing storage pages */
904 if (obj->madv == __I915_MADV_PURGED)
905 i915_gem_object_truncate(obj);
906 /* and flush dirty cachelines in case the object isn't in the cpu write
908 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
909 i915_gem_clflush_object(obj);
910 i915_gem_chipset_flush(dev);
914 if (needs_clflush_after)
915 i915_gem_chipset_flush(dev);
921 * Writes data to the object referenced by handle.
923 * On error, the contents of the buffer that were to be modified are undefined.
926 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
927 struct drm_file *file)
929 struct drm_i915_gem_pwrite *args = data;
930 struct drm_i915_gem_object *obj;
936 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_READ))
939 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
944 ret = i915_mutex_lock_interruptible(dev);
948 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
949 if (&obj->base == NULL) {
954 /* Bounds check destination. */
955 if (args->offset > obj->base.size ||
956 args->size > obj->base.size - args->offset) {
962 /* prime objects have no backing filp to GEM pread/pwrite
965 if (!obj->base.filp) {
969 #endif /* FREEBSD_WIP */
971 CTR3(KTR_DRM, "pwrite %p %jx %jx", obj, args->offset, args->size);
974 /* We can only do the GTT pwrite on untiled buffers, as otherwise
975 * it would end up going through the fenced access, and we'll get
976 * different detiling behavior between reading and writing.
977 * pread/pwrite currently are reading and writing from the CPU
978 * perspective, requiring manual detiling by the client.
981 ret = i915_gem_phys_pwrite(dev, obj, args, file);
985 if (obj->cache_level == I915_CACHE_NONE &&
986 obj->tiling_mode == I915_TILING_NONE &&
987 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
988 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
989 /* Note that the gtt paths might fail with non-page-backed user
990 * pointers (e.g. gtt mappings when moving data between
991 * textures). Fallback to the shmem path in that case. */
994 if (ret == -EFAULT || ret == -ENOSPC)
995 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
998 drm_gem_object_unreference(&obj->base);
1005 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1008 if (atomic_read(&dev_priv->mm.wedged)) {
1009 struct completion *x = &dev_priv->error_completion;
1010 bool recovery_complete;
1012 /* Give the error handler a chance to run. */
1014 recovery_complete = x->done > 0;
1015 mtx_unlock(&x->lock);
1017 /* Non-interruptible callers can't handle -EAGAIN, hence return
1018 * -EIO unconditionally for these. */
1022 /* Recovery complete, but still wedged means reset failure. */
1023 if (recovery_complete)
1033 * Compare seqno against outstanding lazy request. Emit a request if they are
1037 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1041 DRM_LOCK_ASSERT(ring->dev);
1044 if (seqno == ring->outstanding_lazy_request)
1045 ret = i915_add_request(ring, NULL, NULL);
1051 * __wait_seqno - wait until execution of seqno has finished
1052 * @ring: the ring expected to report seqno
1054 * @interruptible: do an interruptible wait (normally yes)
1055 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1057 * Returns 0 if the seqno was found within the alloted time. Else returns the
1058 * errno with remaining time filled in timeout argument.
1060 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1061 bool interruptible, struct timespec *timeout)
1063 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1064 struct timespec before, now, wait_time={1,0};
1065 sbintime_t timeout_sbt;
1067 bool wait_forever = true;
1070 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1073 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
1075 if (timeout != NULL) {
1076 wait_time = *timeout;
1077 wait_forever = false;
1080 timeout_sbt = tstosbt(wait_time);
1082 if (WARN_ON(!ring->irq_get(ring)))
1085 /* Record current time in case interrupted by signal, or wedged * */
1086 getrawmonotonic(&before);
1089 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1090 atomic_read(&dev_priv->mm.wedged))
1091 flags = interruptible ? PCATCH : 0;
1092 mtx_lock(&dev_priv->irq_lock);
1097 ret = -msleep_sbt(&ring->irq_queue, &dev_priv->irq_lock, flags,
1098 "915gwr", timeout_sbt, 0, 0);
1101 * NOTE Linux<->FreeBSD: Convert msleep_sbt() return
1102 * value to something close to wait_event*_timeout()
1103 * functions used on Linux.
1105 * >0 -> condition is true (end = time remaining)
1106 * =0 -> sleep timed out
1107 * <0 -> error (interrupted)
1109 * We fake the remaining time by returning 1. We
1110 * compute a proper value later.
1113 /* We fake a remaining time of 1 tick. */
1115 else if (ret == -EINTR || ret == -ERESTART)
1123 ret = i915_gem_check_wedge(dev_priv, interruptible);
1126 } while (end == 0 && wait_forever);
1127 mtx_unlock(&dev_priv->irq_lock);
1129 getrawmonotonic(&now);
1131 ring->irq_put(ring);
1132 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno, end);
1136 timespecsub(&now, &before);
1137 timespecsub(timeout, &now);
1142 case -EAGAIN: /* Wedged */
1143 case -ERESTARTSYS: /* Signal */
1144 case -ETIMEDOUT: /* Timeout */
1146 case 0: /* Timeout */
1148 default: /* Completed */
1149 WARN_ON(end < 0); /* We're not aware of other errors */
1155 * Waits for a sequence number to be signaled, and cleans up the
1156 * request and object lists appropriately for that event.
1159 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1161 struct drm_device *dev = ring->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 bool interruptible = dev_priv->mm.interruptible;
1166 DRM_LOCK_ASSERT(dev);
1169 ret = i915_gem_check_wedge(dev_priv, interruptible);
1173 ret = i915_gem_check_olr(ring, seqno);
1177 return __wait_seqno(ring, seqno, interruptible, NULL);
1181 * Ensures that all rendering to the object has completed and the object is
1182 * safe to unbind from the GTT or access from the CPU.
1184 static __must_check int
1185 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1188 struct intel_ring_buffer *ring = obj->ring;
1192 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1196 ret = i915_wait_seqno(ring, seqno);
1200 i915_gem_retire_requests_ring(ring);
1202 /* Manually manage the write flush as we may have not yet
1203 * retired the buffer.
1205 if (obj->last_write_seqno &&
1206 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1207 obj->last_write_seqno = 0;
1208 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1214 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1215 * as the object state may change during this call.
1217 static __must_check int
1218 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1221 struct drm_device *dev = obj->base.dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 struct intel_ring_buffer *ring = obj->ring;
1227 DRM_LOCK_ASSERT(dev);
1228 BUG_ON(!dev_priv->mm.interruptible);
1230 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1234 ret = i915_gem_check_wedge(dev_priv, true);
1238 ret = i915_gem_check_olr(ring, seqno);
1243 ret = __wait_seqno(ring, seqno, true, NULL);
1246 i915_gem_retire_requests_ring(ring);
1248 /* Manually manage the write flush as we may have not yet
1249 * retired the buffer.
1252 obj->last_write_seqno &&
1253 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1254 obj->last_write_seqno = 0;
1255 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1262 * Called when user space prepares to use an object with the CPU, either
1263 * through the mmap ioctl's mapping or a GTT mapping.
1266 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1267 struct drm_file *file)
1269 struct drm_i915_gem_set_domain *args = data;
1270 struct drm_i915_gem_object *obj;
1271 uint32_t read_domains = args->read_domains;
1272 uint32_t write_domain = args->write_domain;
1275 /* Only handle setting domains to types used by the CPU. */
1276 if (write_domain & I915_GEM_GPU_DOMAINS)
1279 if (read_domains & I915_GEM_GPU_DOMAINS)
1282 /* Having something in the write domain implies it's in the read
1283 * domain, and only that read domain. Enforce that in the request.
1285 if (write_domain != 0 && read_domains != write_domain)
1288 ret = i915_mutex_lock_interruptible(dev);
1292 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1293 if (&obj->base == NULL) {
1298 /* Try to flush the object off the GPU without holding the lock.
1299 * We will repeat the flush holding the lock in the normal manner
1300 * to catch cases where we are gazumped.
1302 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1306 if (read_domains & I915_GEM_DOMAIN_GTT) {
1307 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1309 /* Silently promote "you're not bound, there was nothing to do"
1310 * to success, since the client was just asking us to
1311 * make sure everything was done.
1316 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1320 drm_gem_object_unreference(&obj->base);
1327 * Called when user space has done writes to this buffer
1330 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1331 struct drm_file *file)
1333 struct drm_i915_gem_sw_finish *args = data;
1334 struct drm_i915_gem_object *obj;
1337 ret = i915_mutex_lock_interruptible(dev);
1341 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1342 if (&obj->base == NULL) {
1347 /* Pinned buffers may be scanout, so flush the cache */
1349 i915_gem_object_flush_cpu_write_domain(obj);
1351 drm_gem_object_unreference(&obj->base);
1358 * Maps the contents of an object, returning the address it is mapped
1361 * While the mapping holds a reference on the contents of the object, it doesn't
1362 * imply a ref on the object itself.
1365 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1366 struct drm_file *file)
1368 struct drm_i915_gem_mmap *args = data;
1369 struct drm_gem_object *obj;
1376 obj = drm_gem_object_lookup(dev, file, args->handle);
1381 /* prime objects have no backing filp to GEM mmap
1385 drm_gem_object_unreference_unlocked(obj);
1388 #endif /* FREEBSD_WIP */
1391 if (args->size == 0)
1394 map = &p->p_vmspace->vm_map;
1395 size = round_page(args->size);
1397 if (map->size + size > lim_cur_proc(p, RLIMIT_VMEM)) {
1405 vm_object_reference(obj->vm_obj);
1406 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size, 0,
1407 VMFS_OPTIMAL_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1408 VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1409 if (rv != KERN_SUCCESS) {
1410 vm_object_deallocate(obj->vm_obj);
1411 error = -vm_mmap_to_errno(rv);
1413 args->addr_ptr = (uint64_t)addr;
1416 drm_gem_object_unreference_unlocked(obj);
1421 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1422 vm_ooffset_t foff, struct ucred *cred, u_short *color)
1426 * NOTE Linux<->FreeBSD: drm_gem_mmap_single() takes care of
1427 * calling drm_gem_object_reference(). That's why we don't
1428 * do this here. i915_gem_pager_dtor(), below, will call
1429 * drm_gem_object_unreference().
1431 * On Linux, drm_gem_vm_open() references the object because
1432 * it's called the mapping is copied. drm_gem_vm_open() is not
1433 * called when the mapping is created. So the possible sequences
1435 * 1. drm_gem_mmap(): ref++
1436 * 2. drm_gem_vm_close(): ref--
1438 * 1. drm_gem_mmap(): ref++
1439 * 2. drm_gem_vm_open(): ref++ (for the copied vma)
1440 * 3. drm_gem_vm_close(): ref-- (for the copied vma)
1441 * 4. drm_gem_vm_close(): ref-- (for the initial vma)
1443 * On FreeBSD, i915_gem_pager_ctor() is called once during the
1444 * creation of the mapping. No callback is called when the
1445 * mapping is shared during a fork(). i915_gem_pager_dtor() is
1446 * called when the last reference to the mapping is dropped. So
1447 * the only sequence is:
1448 * 1. drm_gem_mmap_single(): ref++
1449 * 2. i915_gem_pager_ctor(): <noop>
1450 * 3. i915_gem_pager_dtor(): ref--
1453 *color = 0; /* XXXKIB */
1458 * i915_gem_fault - fault a page into the GTT
1459 * vma: VMA in question
1462 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1463 * from userspace. The fault handler takes care of binding the object to
1464 * the GTT (if needed), allocating and programming a fence register (again,
1465 * only if needed based on whether the old reg is still valid or the object
1466 * is tiled) and inserting a new PTE into the faulting process.
1468 * Note that the faulting process may involve evicting existing objects
1469 * from the GTT and/or fence registers to make room. So performance may
1470 * suffer if the GTT working set is large or there are few fence registers
1477 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1480 struct drm_gem_object *gem_obj = vm_obj->handle;
1481 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
1482 struct drm_device *dev = obj->base.dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1487 bool write = (prot & VM_PROT_WRITE) != 0;
1490 #endif /* FREEBSD_WIP */
1493 vm_object_pip_add(vm_obj, 1);
1496 * Remove the placeholder page inserted by vm_fault() from the
1497 * object before dropping the object lock. If
1498 * i915_gem_release_mmap() is active in parallel on this gem
1499 * object, then it owns the drm device sx and might find the
1500 * placeholder already. Then, since the page is busy,
1501 * i915_gem_release_mmap() sleeps waiting for the busy state
1502 * of the page cleared. We will be unable to acquire drm
1503 * device lock until i915_gem_release_mmap() is able to make a
1506 if (*mres != NULL) {
1507 vm_page_lock(*mres);
1508 vm_page_remove(*mres);
1509 vm_page_unlock(*mres);
1511 VM_OBJECT_WUNLOCK(vm_obj);
1518 ret = i915_mutex_lock_interruptible(dev);
1525 * Since the object lock was dropped, other thread might have
1526 * faulted on the same GTT address and instantiated the
1527 * mapping for the page. Recheck.
1529 VM_OBJECT_WLOCK(vm_obj);
1530 page = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1532 if (vm_page_busied(page)) {
1535 VM_OBJECT_WUNLOCK(vm_obj);
1536 vm_page_busy_sleep(page, "915pee");
1541 VM_OBJECT_WUNLOCK(vm_obj);
1543 /* Now bind it into the GTT if needed */
1544 ret = i915_gem_object_pin(obj, 0, true, false);
1549 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1553 ret = i915_gem_object_get_fence(obj);
1557 obj->fault_mappable = true;
1559 VM_OBJECT_WLOCK(vm_obj);
1560 page = PHYS_TO_VM_PAGE(dev_priv->mm.gtt_base_addr + obj->gtt_offset + offset);
1561 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1562 ("physical address %#jx not fictitious",
1563 (uintmax_t)(dev_priv->mm.gtt_base_addr + obj->gtt_offset + offset)));
1565 VM_OBJECT_WUNLOCK(vm_obj);
1569 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1570 ("not fictitious %p", page));
1571 KASSERT(page->wire_count == 1, ("wire_count not 1 %p", page));
1573 if (vm_page_busied(page)) {
1574 i915_gem_object_unpin(obj);
1577 VM_OBJECT_WUNLOCK(vm_obj);
1578 vm_page_busy_sleep(page, "915pbs");
1581 if (vm_page_insert(page, vm_obj, OFF_TO_IDX(offset))) {
1582 i915_gem_object_unpin(obj);
1584 VM_OBJECT_WUNLOCK(vm_obj);
1588 page->valid = VM_PAGE_BITS_ALL;
1590 vm_page_xbusy(page);
1592 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
1596 * We may have not pinned the object if the page was
1597 * found by the call to vm_page_lookup()
1599 i915_gem_object_unpin(obj);
1602 if (*mres != NULL) {
1603 KASSERT(*mres != page, ("losing %p %p", *mres, page));
1604 vm_page_lock(*mres);
1605 vm_page_free(*mres);
1606 vm_page_unlock(*mres);
1609 vm_object_pip_wakeup(vm_obj);
1610 return (VM_PAGER_OK);
1613 i915_gem_object_unpin(obj);
1617 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1618 CTR4(KTR_DRM, "fault_fail %p %jx %x err %d", gem_obj, offset, prot,
1620 if (ret == -ERESTARTSYS) {
1622 * NOTE Linux<->FreeBSD: Convert Linux' -ERESTARTSYS to
1623 * the more common -EINTR, so the page fault is retried.
1627 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1628 kern_yield(PRI_USER);
1631 VM_OBJECT_WLOCK(vm_obj);
1632 vm_object_pip_wakeup(vm_obj);
1633 return (VM_PAGER_ERROR);
1637 i915_gem_pager_dtor(void *handle)
1639 struct drm_gem_object *obj = handle;
1640 struct drm_device *dev = obj->dev;
1643 drm_gem_object_unreference(obj);
1647 struct cdev_pager_ops i915_gem_pager_ops = {
1648 .cdev_pg_fault = i915_gem_pager_fault,
1649 .cdev_pg_ctor = i915_gem_pager_ctor,
1650 .cdev_pg_dtor = i915_gem_pager_dtor
1654 * i915_gem_release_mmap - remove physical page mappings
1655 * @obj: obj in question
1657 * Preserve the reservation of the mmapping with the DRM core code, but
1658 * relinquish ownership of the pages back to the system.
1660 * It is vital that we remove the page mapping if we have mapped a tiled
1661 * object through the GTT and then lose the fence register due to
1662 * resource pressure. Similarly if the object has been moved out of the
1663 * aperture, than pages mapped into userspace must be revoked. Removing the
1664 * mapping will then trigger a page fault on the next user access, allowing
1665 * fixup by i915_gem_fault().
1668 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1674 if (!obj->fault_mappable)
1677 CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset,
1678 OFF_TO_IDX(obj->base.size));
1679 devobj = cdev_pager_lookup(obj);
1680 if (devobj != NULL) {
1681 page_count = OFF_TO_IDX(obj->base.size);
1683 VM_OBJECT_WLOCK(devobj);
1685 for (i = 0; i < page_count; i++) {
1686 page = vm_page_lookup(devobj, i);
1689 if (vm_page_sleep_if_busy(page, "915unm"))
1691 cdev_pager_free_page(devobj, page);
1693 VM_OBJECT_WUNLOCK(devobj);
1694 vm_object_deallocate(devobj);
1697 obj->fault_mappable = false;
1701 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1705 if (INTEL_INFO(dev)->gen >= 4 ||
1706 tiling_mode == I915_TILING_NONE)
1709 /* Previous chips need a power-of-two fence region when tiling */
1710 if (INTEL_INFO(dev)->gen == 3)
1711 gtt_size = 1024*1024;
1713 gtt_size = 512*1024;
1715 while (gtt_size < size)
1722 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1723 * @obj: object to check
1725 * Return the required GTT alignment for an object, taking into account
1726 * potential fence register mapping.
1729 i915_gem_get_gtt_alignment(struct drm_device *dev,
1734 * Minimum alignment is 4k (GTT page size), but might be greater
1735 * if a fence register is needed for the object.
1737 if (INTEL_INFO(dev)->gen >= 4 ||
1738 tiling_mode == I915_TILING_NONE)
1742 * Previous chips need to be aligned to the size of the smallest
1743 * fence register that can contain the object.
1745 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1749 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1752 * @size: size of the object
1753 * @tiling_mode: tiling mode of the object
1755 * Return the required GTT alignment for an object, only taking into account
1756 * unfenced tiled surface requirements.
1759 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1764 * Minimum alignment is 4k (GTT page size) for sane hw.
1766 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1767 tiling_mode == I915_TILING_NONE)
1770 /* Previous hardware however needs to be aligned to a power-of-two
1771 * tile height. The simplest method for determining this is to reuse
1772 * the power-of-tile object size.
1774 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1777 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1779 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1782 if (obj->base.on_map)
1785 dev_priv->mm.shrinker_no_lock_stealing = true;
1787 ret = drm_gem_create_mmap_offset(&obj->base);
1791 /* Badly fragmented mmap space? The only way we can recover
1792 * space is by destroying unwanted objects. We can't randomly release
1793 * mmap_offsets as userspace expects them to be persistent for the
1794 * lifetime of the objects. The closest we can is to release the
1795 * offsets on purgeable objects by truncating it and marking it purged,
1796 * which prevents userspace from ever using that object again.
1798 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1799 ret = drm_gem_create_mmap_offset(&obj->base);
1803 i915_gem_shrink_all(dev_priv);
1804 ret = drm_gem_create_mmap_offset(&obj->base);
1806 dev_priv->mm.shrinker_no_lock_stealing = false;
1811 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1813 if (!obj->base.on_map)
1816 drm_gem_free_mmap_offset(&obj->base);
1820 i915_gem_mmap_gtt(struct drm_file *file,
1821 struct drm_device *dev,
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 struct drm_i915_gem_object *obj;
1829 ret = i915_mutex_lock_interruptible(dev);
1833 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1834 if (&obj->base == NULL) {
1839 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1844 if (obj->madv != I915_MADV_WILLNEED) {
1845 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1850 ret = i915_gem_object_create_mmap_offset(obj);
1854 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1855 DRM_GEM_MAPPING_KEY;
1858 drm_gem_object_unreference(&obj->base);
1865 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1867 * @data: GTT mapping ioctl data
1868 * @file: GEM object info
1870 * Simply returns the fake offset to userspace so it can mmap it.
1871 * The mmap call will end up in drm_gem_mmap(), which will set things
1872 * up so we can get faults in the handler above.
1874 * The fault handler will take care of binding the object into the GTT
1875 * (since it may have been evicted to make room for something), allocating
1876 * a fence register, and mapping the appropriate aperture address into
1880 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1881 struct drm_file *file)
1883 struct drm_i915_gem_mmap_gtt *args = data;
1885 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1888 /* Immediately discard the backing storage */
1890 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1894 vm_obj = obj->base.vm_obj;
1895 VM_OBJECT_WLOCK(vm_obj);
1896 vm_object_page_remove(vm_obj, 0, 0, false);
1897 VM_OBJECT_WUNLOCK(vm_obj);
1898 i915_gem_object_free_mmap_offset(obj);
1900 obj->madv = __I915_MADV_PURGED;
1904 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1906 return obj->madv == I915_MADV_DONTNEED;
1910 i915_gem_object_put_pages_range_locked(struct drm_i915_gem_object *obj,
1911 vm_pindex_t si, vm_pindex_t ei)
1917 vm_obj = obj->base.vm_obj;
1918 VM_OBJECT_ASSERT_LOCKED(vm_obj);
1919 for (i = si, page = vm_page_lookup(vm_obj, i); i < ei;
1920 page = vm_page_next(page), i++) {
1921 KASSERT(page->pindex == i, ("pindex %jx %jx",
1922 (uintmax_t)page->pindex, (uintmax_t)i));
1924 vm_page_unwire(page, PQ_INACTIVE);
1925 if (page->wire_count == 0)
1926 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1927 vm_page_unlock(page);
1931 #define GEM_PARANOID_CHECK_GTT 0
1932 #if GEM_PARANOID_CHECK_GTT
1934 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
1937 struct drm_i915_private *dev_priv;
1939 unsigned long start, end;
1943 dev_priv = dev->dev_private;
1944 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
1945 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
1946 for (i = start; i < end; i++) {
1947 pa = intel_gtt_read_pte_paddr(i);
1948 for (j = 0; j < page_count; j++) {
1949 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
1950 panic("Page %p in GTT pte index %d pte %x",
1951 ma[i], i, intel_gtt_read_pte(i));
1959 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1961 int page_count = obj->base.size / PAGE_SIZE;
1964 BUG_ON(obj->madv == __I915_MADV_PURGED);
1966 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1968 /* In the event of a disaster, abandon all caches and
1969 * hope for the best.
1971 WARN_ON(ret != -EIO);
1972 i915_gem_clflush_object(obj);
1973 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1976 if (i915_gem_object_needs_bit17_swizzle(obj))
1977 i915_gem_object_save_bit_17_swizzle(obj);
1979 if (obj->madv == I915_MADV_DONTNEED)
1982 VM_OBJECT_WLOCK(obj->base.vm_obj);
1983 #if GEM_PARANOID_CHECK_GTT
1984 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1986 for (i = 0; i < page_count; i++) {
1987 vm_page_t page = obj->pages[i];
1990 vm_page_dirty(page);
1992 if (obj->madv == I915_MADV_WILLNEED)
1993 vm_page_reference(page);
1996 vm_page_unwire(obj->pages[i], PQ_ACTIVE);
1997 vm_page_unlock(page);
1998 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2000 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
2003 free(obj->pages, DRM_I915_GEM);
2008 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2010 const struct drm_i915_gem_object_ops *ops = obj->ops;
2012 if (obj->pages == NULL)
2015 BUG_ON(obj->gtt_space);
2017 if (obj->pages_pin_count)
2020 /* ->put_pages might need to allocate memory for the bit17 swizzle
2021 * array, hence protect them from being reaped by removing them from gtt
2023 list_del(&obj->gtt_list);
2025 ops->put_pages(obj);
2028 if (i915_gem_object_is_purgeable(obj))
2029 i915_gem_object_truncate(obj);
2035 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
2036 bool purgeable_only)
2038 struct drm_i915_gem_object *obj, *next;
2041 list_for_each_entry_safe(obj, next,
2042 &dev_priv->mm.unbound_list,
2044 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2045 i915_gem_object_put_pages(obj) == 0) {
2046 count += obj->base.size >> PAGE_SHIFT;
2047 if (target != -1 && count >= target)
2052 list_for_each_entry_safe(obj, next,
2053 &dev_priv->mm.inactive_list,
2055 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2056 i915_gem_object_unbind(obj) == 0 &&
2057 i915_gem_object_put_pages(obj) == 0) {
2058 count += obj->base.size >> PAGE_SHIFT;
2059 if (target != -1 && count >= target)
2068 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2070 return __i915_gem_shrink(dev_priv, target, true);
2074 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2076 struct drm_i915_gem_object *obj, *next;
2078 i915_gem_evict_everything(dev_priv->dev);
2080 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
2081 i915_gem_object_put_pages(obj);
2085 i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
2086 off_t start, off_t end)
2090 vm_pindex_t si, ei, i;
2091 bool need_swizzle, fresh;
2093 need_swizzle = i915_gem_object_needs_bit17_swizzle(obj) != 0;
2094 vm_obj = obj->base.vm_obj;
2095 si = OFF_TO_IDX(trunc_page(start));
2096 ei = OFF_TO_IDX(round_page(end));
2097 VM_OBJECT_WLOCK(vm_obj);
2098 for (i = si; i < ei; i++) {
2099 page = i915_gem_wire_page(vm_obj, i, &fresh);
2102 if (need_swizzle && fresh)
2103 i915_gem_object_do_bit_17_swizzle_page(obj, page);
2105 VM_OBJECT_WUNLOCK(vm_obj);
2108 i915_gem_object_put_pages_range_locked(obj, si, i);
2109 VM_OBJECT_WUNLOCK(vm_obj);
2114 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2118 vm_pindex_t i, page_count;
2121 /* Assert that the object is not currently in any GPU domain. As it
2122 * wasn't in the GTT, there shouldn't be any way it could have been in
2125 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2126 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2127 KASSERT(obj->pages == NULL, ("Obj already has pages"));
2129 page_count = OFF_TO_IDX(obj->base.size);
2130 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2132 res = i915_gem_object_get_pages_range(obj, 0, obj->base.size);
2134 free(obj->pages, DRM_I915_GEM);
2138 vm_obj = obj->base.vm_obj;
2139 VM_OBJECT_WLOCK(vm_obj);
2140 for (i = 0, page = vm_page_lookup(vm_obj, 0); i < page_count;
2141 i++, page = vm_page_next(page)) {
2142 KASSERT(page->pindex == i, ("pindex %jx %jx",
2143 (uintmax_t)page->pindex, (uintmax_t)i));
2144 obj->pages[i] = page;
2146 VM_OBJECT_WUNLOCK(vm_obj);
2150 /* Ensure that the associated pages are gathered from the backing storage
2151 * and pinned into our object. i915_gem_object_get_pages() may be called
2152 * multiple times before they are released by a single call to
2153 * i915_gem_object_put_pages() - once the pages are no longer referenced
2154 * either as a result of memory pressure (reaping pages under the shrinker)
2155 * or as the object is itself released.
2158 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2160 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2161 const struct drm_i915_gem_object_ops *ops = obj->ops;
2167 BUG_ON(obj->pages_pin_count);
2169 ret = ops->get_pages(obj);
2173 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2178 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2179 struct intel_ring_buffer *ring)
2181 struct drm_device *dev = obj->base.dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 u32 seqno = intel_ring_get_seqno(ring);
2185 BUG_ON(ring == NULL);
2188 /* Add a reference if we're newly entering the active list. */
2190 drm_gem_object_reference(&obj->base);
2194 /* Move from whatever list we were on to the tail of execution. */
2195 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2196 list_move_tail(&obj->ring_list, &ring->active_list);
2198 obj->last_read_seqno = seqno;
2200 if (obj->fenced_gpu_access) {
2201 obj->last_fenced_seqno = seqno;
2203 /* Bump MRU to take account of the delayed flush */
2204 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2205 struct drm_i915_fence_reg *reg;
2207 reg = &dev_priv->fence_regs[obj->fence_reg];
2208 list_move_tail(®->lru_list,
2209 &dev_priv->mm.fence_list);
2215 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2217 struct drm_device *dev = obj->base.dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2220 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2221 BUG_ON(!obj->active);
2223 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2225 list_del_init(&obj->ring_list);
2228 obj->last_read_seqno = 0;
2229 obj->last_write_seqno = 0;
2230 obj->base.write_domain = 0;
2232 obj->last_fenced_seqno = 0;
2233 obj->fenced_gpu_access = false;
2236 drm_gem_object_unreference(&obj->base);
2238 WARN_ON(i915_verify_lists(dev));
2242 i915_gem_handle_seqno_wrap(struct drm_device *dev)
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 struct intel_ring_buffer *ring;
2248 /* The hardware uses various monotonic 32-bit counters, if we
2249 * detect that they will wraparound we need to idle the GPU
2250 * and reset those counters.
2253 for_each_ring(ring, dev_priv, i) {
2254 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2255 ret |= ring->sync_seqno[j] != 0;
2260 ret = i915_gpu_idle(dev);
2264 i915_gem_retire_requests(dev);
2265 for_each_ring(ring, dev_priv, i) {
2266 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2267 ring->sync_seqno[j] = 0;
2274 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2278 /* reserve 0 for non-seqno */
2279 if (dev_priv->next_seqno == 0) {
2280 int ret = i915_gem_handle_seqno_wrap(dev);
2284 dev_priv->next_seqno = 1;
2287 *seqno = dev_priv->next_seqno++;
2292 i915_add_request(struct intel_ring_buffer *ring,
2293 struct drm_file *file,
2296 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2297 struct drm_i915_gem_request *request;
2298 u32 request_ring_position;
2303 * Emit any outstanding flushes - execbuf can fail to emit the flush
2304 * after having emitted the batchbuffer command. Hence we need to fix
2305 * things up similar to emitting the lazy request. The difference here
2306 * is that the flush _must_ happen before the next request, no matter
2309 ret = intel_ring_flush_all_caches(ring);
2313 request = malloc(sizeof(*request), DRM_I915_GEM, M_NOWAIT);
2314 if (request == NULL)
2318 /* Record the position of the start of the request so that
2319 * should we detect the updated seqno part-way through the
2320 * GPU processing the request, we never over-estimate the
2321 * position of the head.
2323 request_ring_position = intel_ring_get_tail(ring);
2325 ret = ring->add_request(ring);
2327 free(request, DRM_I915_GEM);
2331 request->seqno = intel_ring_get_seqno(ring);
2332 request->ring = ring;
2333 request->tail = request_ring_position;
2334 request->emitted_jiffies = jiffies;
2335 was_empty = list_empty(&ring->request_list);
2336 list_add_tail(&request->list, &ring->request_list);
2337 request->file_priv = NULL;
2340 struct drm_i915_file_private *file_priv = file->driver_priv;
2342 mtx_lock(&file_priv->mm.lock);
2343 request->file_priv = file_priv;
2344 list_add_tail(&request->client_list,
2345 &file_priv->mm.request_list);
2346 mtx_unlock(&file_priv->mm.lock);
2349 CTR2(KTR_DRM, "request_add %s %d", ring->name, request->seqno);
2350 ring->outstanding_lazy_request = 0;
2352 if (!dev_priv->mm.suspended) {
2353 if (i915_enable_hangcheck) {
2354 callout_schedule(&dev_priv->hangcheck_timer,
2355 DRM_I915_HANGCHECK_PERIOD);
2358 taskqueue_enqueue_timeout(dev_priv->wq,
2359 &dev_priv->mm.retire_work, hz);
2360 intel_mark_busy(dev_priv->dev);
2365 *out_seqno = request->seqno;
2370 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2372 struct drm_i915_file_private *file_priv = request->file_priv;
2377 mtx_lock(&file_priv->mm.lock);
2378 if (request->file_priv) {
2379 list_del(&request->client_list);
2380 request->file_priv = NULL;
2382 mtx_unlock(&file_priv->mm.lock);
2385 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2386 struct intel_ring_buffer *ring)
2388 if (ring->dev != NULL)
2389 DRM_LOCK_ASSERT(ring->dev);
2391 while (!list_empty(&ring->request_list)) {
2392 struct drm_i915_gem_request *request;
2394 request = list_first_entry(&ring->request_list,
2395 struct drm_i915_gem_request,
2398 list_del(&request->list);
2399 i915_gem_request_remove_from_client(request);
2400 free(request, DRM_I915_GEM);
2403 while (!list_empty(&ring->active_list)) {
2404 struct drm_i915_gem_object *obj;
2406 obj = list_first_entry(&ring->active_list,
2407 struct drm_i915_gem_object,
2410 i915_gem_object_move_to_inactive(obj);
2414 static void i915_gem_reset_fences(struct drm_device *dev)
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2419 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2420 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2422 i915_gem_write_fence(dev, i, NULL);
2425 i915_gem_object_fence_lost(reg->obj);
2429 INIT_LIST_HEAD(®->lru_list);
2432 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2435 void i915_gem_reset(struct drm_device *dev)
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct drm_i915_gem_object *obj;
2439 struct intel_ring_buffer *ring;
2442 for_each_ring(ring, dev_priv, i)
2443 i915_gem_reset_ring_lists(dev_priv, ring);
2445 /* Move everything out of the GPU domains to ensure we do any
2446 * necessary invalidation upon reuse.
2448 list_for_each_entry(obj,
2449 &dev_priv->mm.inactive_list,
2452 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2455 /* The fence registers are invalidated so clear them out */
2456 i915_gem_reset_fences(dev);
2460 * This function clears the request list as sequence numbers are passed.
2463 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2467 if (list_empty(&ring->request_list))
2470 WARN_ON(i915_verify_lists(ring->dev));
2472 seqno = ring->get_seqno(ring, true);
2473 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2475 while (!list_empty(&ring->request_list)) {
2476 struct drm_i915_gem_request *request;
2478 request = list_first_entry(&ring->request_list,
2479 struct drm_i915_gem_request,
2482 if (!i915_seqno_passed(seqno, request->seqno))
2485 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2487 /* We know the GPU must have read the request to have
2488 * sent us the seqno + interrupt, so use the position
2489 * of tail of the request to update the last known position
2492 ring->last_retired_head = request->tail;
2494 list_del(&request->list);
2495 i915_gem_request_remove_from_client(request);
2496 free(request, DRM_I915_GEM);
2499 /* Move any buffers on the active list that are no longer referenced
2500 * by the ringbuffer to the flushing/inactive lists as appropriate.
2502 while (!list_empty(&ring->active_list)) {
2503 struct drm_i915_gem_object *obj;
2505 obj = list_first_entry(&ring->active_list,
2506 struct drm_i915_gem_object,
2509 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2512 i915_gem_object_move_to_inactive(obj);
2515 if (unlikely(ring->trace_irq_seqno &&
2516 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2517 ring->irq_put(ring);
2518 ring->trace_irq_seqno = 0;
2521 WARN_ON(i915_verify_lists(ring->dev));
2525 i915_gem_retire_requests(struct drm_device *dev)
2527 drm_i915_private_t *dev_priv = dev->dev_private;
2528 struct intel_ring_buffer *ring;
2531 for_each_ring(ring, dev_priv, i)
2532 i915_gem_retire_requests_ring(ring);
2536 i915_gem_retire_work_handler(void *arg, int pending)
2538 drm_i915_private_t *dev_priv;
2539 struct drm_device *dev;
2540 struct intel_ring_buffer *ring;
2545 dev = dev_priv->dev;
2547 /* Come back later if the device is busy... */
2548 if (!sx_try_xlock(&dev->dev_struct_lock)) {
2549 taskqueue_enqueue_timeout(dev_priv->wq,
2550 &dev_priv->mm.retire_work, hz);
2554 CTR0(KTR_DRM, "retire_task");
2556 i915_gem_retire_requests(dev);
2558 /* Send a periodic flush down the ring so we don't hold onto GEM
2559 * objects indefinitely.
2562 for_each_ring(ring, dev_priv, i) {
2563 if (ring->gpu_caches_dirty)
2564 i915_add_request(ring, NULL, NULL);
2566 idle &= list_empty(&ring->request_list);
2569 if (!dev_priv->mm.suspended && !idle)
2570 taskqueue_enqueue_timeout(dev_priv->wq,
2571 &dev_priv->mm.retire_work, hz);
2573 intel_mark_idle(dev);
2579 * Ensures that an object will eventually get non-busy by flushing any required
2580 * write domains, emitting any outstanding lazy request and retiring and
2581 * completed requests.
2584 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2589 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2593 i915_gem_retire_requests_ring(obj->ring);
2600 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2601 * @DRM_IOCTL_ARGS: standard ioctl arguments
2603 * Returns 0 if successful, else an error is returned with the remaining time in
2604 * the timeout parameter.
2605 * -ETIME: object is still busy after timeout
2606 * -ERESTARTSYS: signal interrupted the wait
2607 * -ENONENT: object doesn't exist
2608 * Also possible, but rare:
2609 * -EAGAIN: GPU wedged
2611 * -ENODEV: Internal IRQ fail
2612 * -E?: The add request failed
2614 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2615 * non-zero timeout parameter the wait ioctl will wait for the given number of
2616 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2617 * without holding struct_mutex the object may become re-busied before this
2618 * function completes. A similar but shorter * race condition exists in the busy
2622 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2624 struct drm_i915_gem_wait *args = data;
2625 struct drm_i915_gem_object *obj;
2626 struct intel_ring_buffer *ring = NULL;
2627 struct timespec timeout_stack, *timeout = NULL;
2631 if (args->timeout_ns >= 0) {
2632 timeout_stack.tv_sec = args->timeout_ns / 1000000;
2633 timeout_stack.tv_nsec = args->timeout_ns % 1000000;
2634 timeout = &timeout_stack;
2637 ret = i915_mutex_lock_interruptible(dev);
2641 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2642 if (&obj->base == NULL) {
2647 /* Need to make sure the object gets inactive eventually. */
2648 ret = i915_gem_object_flush_active(obj);
2653 seqno = obj->last_read_seqno;
2660 /* Do this after OLR check to make sure we make forward progress polling
2661 * on this IOCTL with a 0 timeout (like busy ioctl)
2663 if (!args->timeout_ns) {
2668 drm_gem_object_unreference(&obj->base);
2671 ret = __wait_seqno(ring, seqno, true, timeout);
2673 args->timeout_ns = timeout->tv_sec * 1000000 + timeout->tv_nsec;
2678 drm_gem_object_unreference(&obj->base);
2684 * i915_gem_object_sync - sync an object to a ring.
2686 * @obj: object which may be in use on another ring.
2687 * @to: ring we wish to use the object on. May be NULL.
2689 * This code is meant to abstract object synchronization with the GPU.
2690 * Calling with NULL implies synchronizing the object with the CPU
2691 * rather than a particular GPU ring.
2693 * Returns 0 if successful, else propagates up the lower layer error.
2696 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2697 struct intel_ring_buffer *to)
2699 struct intel_ring_buffer *from = obj->ring;
2703 if (from == NULL || to == from)
2706 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2707 return i915_gem_object_wait_rendering(obj, false);
2709 idx = intel_ring_sync_index(from, to);
2711 seqno = obj->last_read_seqno;
2712 if (seqno <= from->sync_seqno[idx])
2715 ret = i915_gem_check_olr(obj->ring, seqno);
2719 ret = to->sync_to(to, from, seqno);
2721 /* We use last_read_seqno because sync_to()
2722 * might have just caused seqno wrap under
2725 from->sync_seqno[idx] = obj->last_read_seqno;
2730 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2732 u32 old_write_domain, old_read_domains;
2734 /* Act a barrier for all accesses through the GTT */
2737 /* Force a pagefault for domain tracking on next user access */
2738 i915_gem_release_mmap(obj);
2740 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2743 old_read_domains = obj->base.read_domains;
2744 old_write_domain = obj->base.write_domain;
2746 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2747 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2749 CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
2750 obj, old_read_domains, old_write_domain);
2754 * Unbinds an object from the GTT aperture.
2757 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2759 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2762 if (obj->gtt_space == NULL)
2768 BUG_ON(obj->pages == NULL);
2770 ret = i915_gem_object_finish_gpu(obj);
2773 /* Continue on if we fail due to EIO, the GPU is hung so we
2774 * should be safe and we need to cleanup or else we might
2775 * cause memory corruption through use-after-free.
2778 i915_gem_object_finish_gtt(obj);
2780 /* release the fence reg _after_ flushing */
2781 ret = i915_gem_object_put_fence(obj);
2785 if (obj->has_global_gtt_mapping)
2786 i915_gem_gtt_unbind_object(obj);
2787 if (obj->has_aliasing_ppgtt_mapping) {
2788 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2789 obj->has_aliasing_ppgtt_mapping = 0;
2791 i915_gem_gtt_finish_object(obj);
2793 list_del(&obj->mm_list);
2794 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2795 /* Avoid an unnecessary call to unbind on rebind. */
2796 obj->map_and_fenceable = true;
2798 drm_mm_put_block(obj->gtt_space);
2799 obj->gtt_space = NULL;
2800 obj->gtt_offset = 0;
2805 int i915_gpu_idle(struct drm_device *dev)
2807 drm_i915_private_t *dev_priv = dev->dev_private;
2808 struct intel_ring_buffer *ring;
2811 /* Flush everything onto the inactive list. */
2812 for_each_ring(ring, dev_priv, i) {
2813 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2817 ret = intel_ring_idle(ring);
2825 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2826 struct drm_i915_gem_object *obj)
2828 drm_i915_private_t *dev_priv = dev->dev_private;
2832 u32 size = obj->gtt_space->size;
2834 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2836 val |= obj->gtt_offset & 0xfffff000;
2837 val |= (uint64_t)((obj->stride / 128) - 1) <<
2838 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2840 if (obj->tiling_mode == I915_TILING_Y)
2841 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2842 val |= I965_FENCE_REG_VALID;
2846 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2847 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2850 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2851 struct drm_i915_gem_object *obj)
2853 drm_i915_private_t *dev_priv = dev->dev_private;
2857 u32 size = obj->gtt_space->size;
2859 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2861 val |= obj->gtt_offset & 0xfffff000;
2862 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2863 if (obj->tiling_mode == I915_TILING_Y)
2864 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2865 val |= I965_FENCE_REG_VALID;
2869 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2870 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2873 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2874 struct drm_i915_gem_object *obj)
2876 drm_i915_private_t *dev_priv = dev->dev_private;
2880 u32 size = obj->gtt_space->size;
2884 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2885 (size & -size) != size ||
2886 (obj->gtt_offset & (size - 1)),
2887 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2888 obj->gtt_offset, obj->map_and_fenceable, size);
2890 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2895 /* Note: pitch better be a power of two tile widths */
2896 pitch_val = obj->stride / tile_width;
2897 pitch_val = ffs(pitch_val) - 1;
2899 val = obj->gtt_offset;
2900 if (obj->tiling_mode == I915_TILING_Y)
2901 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2902 val |= I915_FENCE_SIZE_BITS(size);
2903 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2904 val |= I830_FENCE_REG_VALID;
2909 reg = FENCE_REG_830_0 + reg * 4;
2911 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2913 I915_WRITE(reg, val);
2917 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2918 struct drm_i915_gem_object *obj)
2920 drm_i915_private_t *dev_priv = dev->dev_private;
2924 u32 size = obj->gtt_space->size;
2927 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2928 (size & -size) != size ||
2929 (obj->gtt_offset & (size - 1)),
2930 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2931 obj->gtt_offset, size);
2933 pitch_val = obj->stride / 128;
2934 pitch_val = ffs(pitch_val) - 1;
2936 val = obj->gtt_offset;
2937 if (obj->tiling_mode == I915_TILING_Y)
2938 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2939 val |= I830_FENCE_SIZE_BITS(size);
2940 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2941 val |= I830_FENCE_REG_VALID;
2945 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2946 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2949 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2950 struct drm_i915_gem_object *obj)
2952 switch (INTEL_INFO(dev)->gen) {
2954 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2956 case 4: i965_write_fence_reg(dev, reg, obj); break;
2957 case 3: i915_write_fence_reg(dev, reg, obj); break;
2958 case 2: i830_write_fence_reg(dev, reg, obj); break;
2963 static inline int fence_number(struct drm_i915_private *dev_priv,
2964 struct drm_i915_fence_reg *fence)
2966 return fence - dev_priv->fence_regs;
2969 static void i915_gem_write_fence__ipi(void *data)
2974 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2975 struct drm_i915_fence_reg *fence,
2978 struct drm_device *dev = obj->base.dev;
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 int fence_reg = fence_number(dev_priv, fence);
2982 /* In order to fully serialize access to the fenced region and
2983 * the update to the fence register we need to take extreme
2984 * measures on SNB+. In theory, the write to the fence register
2985 * flushes all memory transactions before, and coupled with the
2986 * mb() placed around the register write we serialise all memory
2987 * operations with respect to the changes in the tiler. Yet, on
2988 * SNB+ we need to take a step further and emit an explicit wbinvd()
2989 * on each processor in order to manually flush all memory
2990 * transactions before updating the fence register.
2992 if (HAS_LLC(obj->base.dev))
2993 on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
2994 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2997 obj->fence_reg = fence_reg;
2999 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3001 obj->fence_reg = I915_FENCE_REG_NONE;
3003 list_del_init(&fence->lru_list);
3008 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
3010 if (obj->last_fenced_seqno) {
3011 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3015 obj->last_fenced_seqno = 0;
3018 /* Ensure that all CPU reads are completed before installing a fence
3019 * and all writes before removing the fence.
3021 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3024 obj->fenced_gpu_access = false;
3029 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3031 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3034 ret = i915_gem_object_flush_fence(obj);
3038 if (obj->fence_reg == I915_FENCE_REG_NONE)
3041 i915_gem_object_update_fence(obj,
3042 &dev_priv->fence_regs[obj->fence_reg],
3044 i915_gem_object_fence_lost(obj);
3049 static struct drm_i915_fence_reg *
3050 i915_find_fence_reg(struct drm_device *dev)
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct drm_i915_fence_reg *reg, *avail;
3056 /* First try to find a free reg */
3058 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3059 reg = &dev_priv->fence_regs[i];
3063 if (!reg->pin_count)
3070 /* None available, try to steal one or wait for a user to finish */
3071 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3082 * i915_gem_object_get_fence - set up fencing for an object
3083 * @obj: object to map through a fence reg
3085 * When mapping objects through the GTT, userspace wants to be able to write
3086 * to them without having to worry about swizzling if the object is tiled.
3087 * This function walks the fence regs looking for a free one for @obj,
3088 * stealing one if it can't find any.
3090 * It then sets up the reg based on the object's properties: address, pitch
3091 * and tiling format.
3093 * For an untiled surface, this removes any existing fence.
3096 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3098 struct drm_device *dev = obj->base.dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 bool enable = obj->tiling_mode != I915_TILING_NONE;
3101 struct drm_i915_fence_reg *reg;
3104 /* Have we updated the tiling parameters upon the object and so
3105 * will need to serialise the write to the associated fence register?
3107 if (obj->fence_dirty) {
3108 ret = i915_gem_object_flush_fence(obj);
3113 /* Just update our place in the LRU if our fence is getting reused. */
3114 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3115 reg = &dev_priv->fence_regs[obj->fence_reg];
3116 if (!obj->fence_dirty) {
3117 list_move_tail(®->lru_list,
3118 &dev_priv->mm.fence_list);
3121 } else if (enable) {
3122 reg = i915_find_fence_reg(dev);
3127 struct drm_i915_gem_object *old = reg->obj;
3129 ret = i915_gem_object_flush_fence(old);
3133 i915_gem_object_fence_lost(old);
3138 i915_gem_object_update_fence(obj, reg, enable);
3139 obj->fence_dirty = false;
3144 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3145 struct drm_mm_node *gtt_space,
3146 unsigned long cache_level)
3148 struct drm_mm_node *other;
3150 /* On non-LLC machines we have to be careful when putting differing
3151 * types of snoopable memory together to avoid the prefetcher
3152 * crossing memory domains and dying.
3157 if (gtt_space == NULL)
3160 if (list_empty(>t_space->node_list))
3163 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3164 if (other->allocated && !other->hole_follows && other->color != cache_level)
3167 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3168 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3174 static void i915_gem_verify_gtt(struct drm_device *dev)
3177 struct drm_i915_private *dev_priv = dev->dev_private;
3178 struct drm_i915_gem_object *obj;
3181 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
3182 if (obj->gtt_space == NULL) {
3183 DRM_ERROR("object found on GTT list with no space reserved\n");
3188 if (obj->cache_level != obj->gtt_space->color) {
3189 DRM_ERROR("object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3190 obj->gtt_space->start,
3191 obj->gtt_space->start + obj->gtt_space->size,
3193 obj->gtt_space->color);
3198 if (!i915_gem_valid_gtt_space(dev,
3200 obj->cache_level)) {
3201 DRM_ERROR("invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3202 obj->gtt_space->start,
3203 obj->gtt_space->start + obj->gtt_space->size,
3215 * Finds free space in the GTT aperture and binds the object there.
3218 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3220 bool map_and_fenceable,
3223 struct drm_device *dev = obj->base.dev;
3224 drm_i915_private_t *dev_priv = dev->dev_private;
3225 struct drm_mm_node *node;
3226 u32 size, fence_size, fence_alignment, unfenced_alignment;
3227 bool mappable, fenceable;
3230 if (obj->madv != I915_MADV_WILLNEED) {
3231 DRM_ERROR("Attempting to bind a purgeable object\n");
3235 fence_size = i915_gem_get_gtt_size(dev,
3238 fence_alignment = i915_gem_get_gtt_alignment(dev,
3241 unfenced_alignment =
3242 i915_gem_get_unfenced_gtt_alignment(dev,
3247 alignment = map_and_fenceable ? fence_alignment :
3249 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3250 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3254 size = map_and_fenceable ? fence_size : obj->base.size;
3256 /* If the object is bigger than the entire aperture, reject it early
3257 * before evicting everything in a vain attempt to find space.
3259 if (obj->base.size >
3260 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
3261 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
3265 ret = i915_gem_object_get_pages(obj);
3269 i915_gem_object_pin_pages(obj);
3271 node = malloc(sizeof(*node), DRM_MEM_MM, M_NOWAIT | M_ZERO);
3273 i915_gem_object_unpin_pages(obj);
3278 if (map_and_fenceable)
3279 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3280 size, alignment, obj->cache_level,
3281 0, dev_priv->mm.gtt_mappable_end);
3283 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
3284 size, alignment, obj->cache_level);
3286 ret = i915_gem_evict_something(dev, size, alignment,
3293 i915_gem_object_unpin_pages(obj);
3294 free(node, DRM_MEM_MM);
3297 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3298 i915_gem_object_unpin_pages(obj);
3299 drm_mm_put_block(node);
3303 ret = i915_gem_gtt_prepare_object(obj);
3305 i915_gem_object_unpin_pages(obj);
3306 drm_mm_put_block(node);
3310 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3311 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3313 obj->gtt_space = node;
3314 obj->gtt_offset = node->start;
3317 node->size == fence_size &&
3318 (node->start & (fence_alignment - 1)) == 0;
3321 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3323 obj->map_and_fenceable = mappable && fenceable;
3325 i915_gem_object_unpin_pages(obj);
3326 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
3327 obj->base.size, map_and_fenceable);
3328 i915_gem_verify_gtt(dev);
3333 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3335 /* If we don't have a page list set up, then we're not pinned
3336 * to GPU, and we can ignore the cache flush because it'll happen
3337 * again at bind time.
3339 if (obj->pages == NULL)
3342 /* If the GPU is snooping the contents of the CPU cache,
3343 * we do not need to manually clear the CPU cache lines. However,
3344 * the caches are only snooped when the render cache is
3345 * flushed/invalidated. As we always have to emit invalidations
3346 * and flushes when moving into and out of the RENDER domain, correct
3347 * snooping behaviour occurs naturally as the result of our domain
3350 if (obj->cache_level != I915_CACHE_NONE)
3353 CTR1(KTR_DRM, "object_clflush %p", obj);
3355 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3358 /** Flushes the GTT write domain for the object if it's dirty. */
3360 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3362 uint32_t old_write_domain;
3364 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3367 /* No actual flushing is required for the GTT write domain. Writes
3368 * to it immediately go to main memory as far as we know, so there's
3369 * no chipset flush. It also doesn't land in render cache.
3371 * However, we do have to enforce the order so that all writes through
3372 * the GTT land before any writes to the device, such as updates to
3377 old_write_domain = obj->base.write_domain;
3378 obj->base.write_domain = 0;
3380 CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj,
3381 obj->base.read_domains, old_write_domain);
3384 /** Flushes the CPU write domain for the object if it's dirty. */
3386 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3388 uint32_t old_write_domain;
3390 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3393 i915_gem_clflush_object(obj);
3394 i915_gem_chipset_flush(obj->base.dev);
3395 old_write_domain = obj->base.write_domain;
3396 obj->base.write_domain = 0;
3398 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
3399 obj->base.read_domains, old_write_domain);
3403 * Moves a single object to the GTT read, and possibly write domain.
3405 * This function returns when the move is complete, including waiting on
3409 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3411 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3412 uint32_t old_write_domain, old_read_domains;
3415 /* Not valid to be called on unbound objects. */
3416 if (obj->gtt_space == NULL)
3419 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3422 ret = i915_gem_object_wait_rendering(obj, !write);
3426 i915_gem_object_flush_cpu_write_domain(obj);
3428 old_write_domain = obj->base.write_domain;
3429 old_read_domains = obj->base.read_domains;
3431 /* It should now be out of any other write domains, and we can update
3432 * the domain values for our changes.
3434 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3435 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3437 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3438 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3442 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,
3443 old_read_domains, old_write_domain);
3445 /* And bump the LRU for this access */
3446 if (i915_gem_object_is_inactive(obj))
3447 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3452 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3453 enum i915_cache_level cache_level)
3455 struct drm_device *dev = obj->base.dev;
3456 drm_i915_private_t *dev_priv = dev->dev_private;
3459 if (obj->cache_level == cache_level)
3462 if (obj->pin_count) {
3463 DRM_DEBUG("can not change the cache level of pinned objects\n");
3467 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3468 ret = i915_gem_object_unbind(obj);
3473 if (obj->gtt_space) {
3474 ret = i915_gem_object_finish_gpu(obj);
3478 i915_gem_object_finish_gtt(obj);
3480 /* Before SandyBridge, you could not use tiling or fence
3481 * registers with snooped memory, so relinquish any fences
3482 * currently pointing to our region in the aperture.
3484 if (INTEL_INFO(dev)->gen < 6) {
3485 ret = i915_gem_object_put_fence(obj);
3490 if (obj->has_global_gtt_mapping)
3491 i915_gem_gtt_bind_object(obj, cache_level);
3492 if (obj->has_aliasing_ppgtt_mapping)
3493 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3496 obj->gtt_space->color = cache_level;
3499 if (cache_level == I915_CACHE_NONE) {
3500 u32 old_read_domains, old_write_domain;
3502 /* If we're coming from LLC cached, then we haven't
3503 * actually been tracking whether the data is in the
3504 * CPU cache or not, since we only allow one bit set
3505 * in obj->write_domain and have been skipping the clflushes.
3506 * Just set it to the CPU cache for now.
3508 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3509 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3511 old_read_domains = obj->base.read_domains;
3512 old_write_domain = obj->base.write_domain;
3514 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3515 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3517 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
3518 obj, old_read_domains, old_write_domain);
3521 obj->cache_level = cache_level;
3522 i915_gem_verify_gtt(dev);
3526 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3527 struct drm_file *file)
3529 struct drm_i915_gem_caching *args = data;
3530 struct drm_i915_gem_object *obj;
3533 ret = i915_mutex_lock_interruptible(dev);
3537 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3538 if (&obj->base == NULL) {
3543 args->caching = obj->cache_level != I915_CACHE_NONE;
3545 drm_gem_object_unreference(&obj->base);
3551 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3552 struct drm_file *file)
3554 struct drm_i915_gem_caching *args = data;
3555 struct drm_i915_gem_object *obj;
3556 enum i915_cache_level level;
3559 switch (args->caching) {
3560 case I915_CACHING_NONE:
3561 level = I915_CACHE_NONE;
3563 case I915_CACHING_CACHED:
3564 level = I915_CACHE_LLC;
3570 ret = i915_mutex_lock_interruptible(dev);
3574 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3575 if (&obj->base == NULL) {
3580 ret = i915_gem_object_set_cache_level(obj, level);
3582 drm_gem_object_unreference(&obj->base);
3588 static bool is_pin_display(struct drm_i915_gem_object *obj)
3590 /* There are 3 sources that pin objects:
3591 * 1. The display engine (scanouts, sprites, cursors);
3592 * 2. Reservations for execbuffer;
3595 * We can ignore reservations as we hold the struct_mutex and
3596 * are only called outside of the reservation path. The user
3597 * can only increment pin_count once, and so if after
3598 * subtracting the potential reference by the user, any pin_count
3599 * remains, it must be due to another use by the display engine.
3601 return obj->pin_count - !!obj->user_pin_count;
3605 * Prepare buffer for display plane (scanout, cursors, etc).
3606 * Can be called from an uninterruptible phase (modesetting) and allows
3607 * any flushes to be pipelined (for pageflips).
3610 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3612 struct intel_ring_buffer *pipelined)
3614 u32 old_read_domains, old_write_domain;
3617 if (pipelined != obj->ring) {
3618 ret = i915_gem_object_sync(obj, pipelined);
3623 /* Mark the pin_display early so that we account for the
3624 * display coherency whilst setting up the cache domains.
3626 obj->pin_display = true;
3628 /* The display engine is not coherent with the LLC cache on gen6. As
3629 * a result, we make sure that the pinning that is about to occur is
3630 * done with uncached PTEs. This is lowest common denominator for all
3633 * However for gen6+, we could do better by using the GFDT bit instead
3634 * of uncaching, which would allow us to flush all the LLC-cached data
3635 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3637 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3639 goto err_unpin_display;
3641 /* As the user may map the buffer once pinned in the display plane
3642 * (e.g. libkms for the bootup splash), we have to ensure that we
3643 * always use map_and_fenceable for all scanout buffers.
3645 ret = i915_gem_object_pin(obj, alignment, true, false);
3647 goto err_unpin_display;
3649 i915_gem_object_flush_cpu_write_domain(obj);
3651 old_write_domain = obj->base.write_domain;
3652 old_read_domains = obj->base.read_domains;
3654 /* It should now be out of any other write domains, and we can update
3655 * the domain values for our changes.
3657 obj->base.write_domain = 0;
3658 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3660 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
3661 obj, old_read_domains, old_write_domain);
3666 obj->pin_display = is_pin_display(obj);
3671 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3673 i915_gem_object_unpin(obj);
3674 obj->pin_display = is_pin_display(obj);
3678 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3682 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3685 ret = i915_gem_object_wait_rendering(obj, false);
3689 /* Ensure that we invalidate the GPU's caches and TLBs. */
3690 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3695 * Moves a single object to the CPU read, and possibly write domain.
3697 * This function returns when the move is complete, including waiting on
3701 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3703 uint32_t old_write_domain, old_read_domains;
3706 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3709 ret = i915_gem_object_wait_rendering(obj, !write);
3713 i915_gem_object_flush_gtt_write_domain(obj);
3715 old_write_domain = obj->base.write_domain;
3716 old_read_domains = obj->base.read_domains;
3718 /* Flush the CPU cache if it's still invalid. */
3719 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3720 i915_gem_clflush_object(obj);
3722 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3725 /* It should now be out of any other write domains, and we can update
3726 * the domain values for our changes.
3728 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3730 /* If we're writing through the CPU, then the GPU read domains will
3731 * need to be invalidated at next use.
3734 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3735 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3738 CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj,
3739 old_read_domains, old_write_domain);
3744 /* Throttle our rendering by waiting until the ring has completed our requests
3745 * emitted over 20 msec ago.
3747 * Note that if we were to use the current jiffies each time around the loop,
3748 * we wouldn't escape the function with any frames outstanding if the time to
3749 * render a frame was over 20ms.
3751 * This should get us reasonable parallelism between CPU and GPU but also
3752 * relatively low latency when blocking on a particular request to finish.
3755 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 struct drm_i915_file_private *file_priv = file->driver_priv;
3759 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3760 struct drm_i915_gem_request *request;
3761 struct intel_ring_buffer *ring = NULL;
3765 if (atomic_read(&dev_priv->mm.wedged))
3768 mtx_lock(&file_priv->mm.lock);
3769 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3770 if (time_after_eq(request->emitted_jiffies, recent_enough))
3773 ring = request->ring;
3774 seqno = request->seqno;
3776 mtx_unlock(&file_priv->mm.lock);
3781 ret = __wait_seqno(ring, seqno, true, NULL);
3783 taskqueue_enqueue_timeout(dev_priv->wq,
3784 &dev_priv->mm.retire_work, 0);
3790 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3792 bool map_and_fenceable,
3797 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3800 if (obj->gtt_space != NULL) {
3801 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3802 (map_and_fenceable && !obj->map_and_fenceable)) {
3803 WARN(obj->pin_count,
3804 "bo is already pinned with incorrect alignment:"
3805 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3806 " obj->map_and_fenceable=%d\n",
3807 obj->gtt_offset, alignment,
3809 obj->map_and_fenceable);
3810 ret = i915_gem_object_unbind(obj);
3816 if (obj->gtt_space == NULL) {
3817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3819 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3825 if (!dev_priv->mm.aliasing_ppgtt)
3826 i915_gem_gtt_bind_object(obj, obj->cache_level);
3829 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3830 i915_gem_gtt_bind_object(obj, obj->cache_level);
3833 obj->pin_mappable |= map_and_fenceable;
3839 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3841 BUG_ON(obj->pin_count == 0);
3842 BUG_ON(obj->gtt_space == NULL);
3844 if (--obj->pin_count == 0)
3845 obj->pin_mappable = false;
3849 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3850 struct drm_file *file)
3852 struct drm_i915_gem_pin *args = data;
3853 struct drm_i915_gem_object *obj;
3856 ret = i915_mutex_lock_interruptible(dev);
3860 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3861 if (&obj->base == NULL) {
3866 if (obj->madv != I915_MADV_WILLNEED) {
3867 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3872 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3873 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3879 if (obj->user_pin_count == 0) {
3880 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3885 obj->user_pin_count++;
3886 obj->pin_filp = file;
3888 /* XXX - flush the CPU caches for pinned objects
3889 * as the X server doesn't manage domains yet
3891 i915_gem_object_flush_cpu_write_domain(obj);
3892 args->offset = obj->gtt_offset;
3894 drm_gem_object_unreference(&obj->base);
3901 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3902 struct drm_file *file)
3904 struct drm_i915_gem_pin *args = data;
3905 struct drm_i915_gem_object *obj;
3908 ret = i915_mutex_lock_interruptible(dev);
3912 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3913 if (&obj->base == NULL) {
3918 if (obj->pin_filp != file) {
3919 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3924 obj->user_pin_count--;
3925 if (obj->user_pin_count == 0) {
3926 obj->pin_filp = NULL;
3927 i915_gem_object_unpin(obj);
3931 drm_gem_object_unreference(&obj->base);
3938 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3939 struct drm_file *file)
3941 struct drm_i915_gem_busy *args = data;
3942 struct drm_i915_gem_object *obj;
3945 ret = i915_mutex_lock_interruptible(dev);
3949 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3950 if (&obj->base == NULL) {
3955 /* Count all active objects as busy, even if they are currently not used
3956 * by the gpu. Users of this interface expect objects to eventually
3957 * become non-busy without any further actions, therefore emit any
3958 * necessary flushes here.
3960 ret = i915_gem_object_flush_active(obj);
3962 args->busy = obj->active;
3964 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3965 args->busy |= intel_ring_flag(obj->ring) << 16;
3968 drm_gem_object_unreference(&obj->base);
3975 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3976 struct drm_file *file_priv)
3978 return i915_gem_ring_throttle(dev, file_priv);
3982 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3983 struct drm_file *file_priv)
3985 struct drm_i915_gem_madvise *args = data;
3986 struct drm_i915_gem_object *obj;
3989 switch (args->madv) {
3990 case I915_MADV_DONTNEED:
3991 case I915_MADV_WILLNEED:
3997 ret = i915_mutex_lock_interruptible(dev);
4001 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4002 if (&obj->base == NULL) {
4007 if (obj->pin_count) {
4012 if (obj->madv != __I915_MADV_PURGED)
4013 obj->madv = args->madv;
4015 /* if the object is no longer attached, discard its backing storage */
4016 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4017 i915_gem_object_truncate(obj);
4019 args->retained = obj->madv != __I915_MADV_PURGED;
4022 drm_gem_object_unreference(&obj->base);
4028 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4029 const struct drm_i915_gem_object_ops *ops)
4031 INIT_LIST_HEAD(&obj->mm_list);
4032 INIT_LIST_HEAD(&obj->gtt_list);
4033 INIT_LIST_HEAD(&obj->ring_list);
4034 INIT_LIST_HEAD(&obj->exec_list);
4038 obj->fence_reg = I915_FENCE_REG_NONE;
4039 obj->madv = I915_MADV_WILLNEED;
4040 /* Avoid an unnecessary call to unbind on the first bind. */
4041 obj->map_and_fenceable = true;
4043 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4046 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4047 .get_pages = i915_gem_object_get_pages_gtt,
4048 .put_pages = i915_gem_object_put_pages_gtt,
4051 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4054 struct drm_i915_gem_object *obj;
4056 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
4060 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4061 free(obj, DRM_I915_GEM);
4066 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4067 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4068 /* 965gm cannot relocate objects above 4GiB. */
4069 mask &= ~__GFP_HIGHMEM;
4070 mask |= __GFP_DMA32;
4073 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4074 mapping_set_gfp_mask(mapping, mask);
4075 #endif /* FREEBSD_WIP */
4077 i915_gem_object_init(obj, &i915_gem_object_ops);
4079 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4080 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4083 /* On some devices, we can have the GPU use the LLC (the CPU
4084 * cache) for about a 10% performance improvement
4085 * compared to uncached. Graphics requests other than
4086 * display scanout are coherent with the CPU in
4087 * accessing this cache. This means in this mode we
4088 * don't need to clflush on the CPU side, and on the
4089 * GPU side we only need to flush internal caches to
4090 * get data visible to the CPU.
4092 * However, we maintain the display planes as UC, and so
4093 * need to rebind when first used as such.
4095 obj->cache_level = I915_CACHE_LLC;
4097 obj->cache_level = I915_CACHE_NONE;
4102 int i915_gem_init_object(struct drm_gem_object *obj)
4104 printf("i915_gem_init_object called\n");
4109 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4111 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4112 struct drm_device *dev = obj->base.dev;
4113 drm_i915_private_t *dev_priv = dev->dev_private;
4115 CTR1(KTR_DRM, "object_destroy_tail %p", obj);
4118 i915_gem_detach_phys_object(dev, obj);
4121 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
4122 bool was_interruptible;
4124 was_interruptible = dev_priv->mm.interruptible;
4125 dev_priv->mm.interruptible = false;
4127 WARN_ON(i915_gem_object_unbind(obj));
4129 dev_priv->mm.interruptible = was_interruptible;
4132 obj->pages_pin_count = 0;
4133 i915_gem_object_put_pages(obj);
4134 i915_gem_object_free_mmap_offset(obj);
4139 if (obj->base.import_attach)
4140 drm_prime_gem_destroy(&obj->base, NULL);
4141 #endif /* FREEBSD_WIP */
4143 drm_gem_object_release(&obj->base);
4144 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4146 free(obj->bit_17, DRM_I915_GEM);
4147 free(obj, DRM_I915_GEM);
4151 i915_gem_idle(struct drm_device *dev)
4153 drm_i915_private_t *dev_priv = dev->dev_private;
4158 if (dev_priv->mm.suspended) {
4163 ret = i915_gpu_idle(dev);
4168 i915_gem_retire_requests(dev);
4170 /* Under UMS, be paranoid and evict. */
4171 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4172 i915_gem_evict_everything(dev);
4174 i915_gem_reset_fences(dev);
4176 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4177 * We need to replace this with a semaphore, or something.
4178 * And not confound mm.suspended!
4180 dev_priv->mm.suspended = 1;
4181 callout_stop(&dev_priv->hangcheck_timer);
4183 i915_kernel_lost_context(dev);
4184 i915_gem_cleanup_ringbuffer(dev);
4188 /* Cancel the retire work handler, which should be idle now. */
4189 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->mm.retire_work, NULL);
4194 void i915_gem_l3_remap(struct drm_device *dev)
4196 drm_i915_private_t *dev_priv = dev->dev_private;
4200 if (!HAS_L3_GPU_CACHE(dev))
4203 if (!dev_priv->l3_parity.remap_info)
4206 misccpctl = I915_READ(GEN7_MISCCPCTL);
4207 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4208 POSTING_READ(GEN7_MISCCPCTL);
4210 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4211 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4212 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4213 DRM_DEBUG("0x%x was already programmed to %x\n",
4214 GEN7_L3LOG_BASE + i, remap);
4215 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4216 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4217 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4220 /* Make sure all the writes land before disabling dop clock gating */
4221 POSTING_READ(GEN7_L3LOG_BASE);
4223 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4226 void i915_gem_init_swizzling(struct drm_device *dev)
4228 drm_i915_private_t *dev_priv = dev->dev_private;
4230 if (INTEL_INFO(dev)->gen < 5 ||
4231 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4234 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4235 DISP_TILE_SURFACE_SWIZZLING);
4240 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4242 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4244 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4248 intel_enable_blt(struct drm_device *dev)
4253 /* The blitter was dysfunctional on early prototypes */
4254 if (IS_GEN6(dev) && pci_get_revid(dev->dev) < 8) {
4255 DRM_INFO("BLT not supported on this pre-production hardware;"
4256 " graphics performance will be degraded.\n");
4264 i915_gem_init_hw(struct drm_device *dev)
4266 drm_i915_private_t *dev_priv = dev->dev_private;
4270 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4272 #endif /* FREEBSD_WIP */
4274 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4275 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4277 i915_gem_l3_remap(dev);
4279 i915_gem_init_swizzling(dev);
4281 ret = intel_init_render_ring_buffer(dev);
4286 ret = intel_init_bsd_ring_buffer(dev);
4288 goto cleanup_render_ring;
4291 if (intel_enable_blt(dev)) {
4292 ret = intel_init_blt_ring_buffer(dev);
4294 goto cleanup_bsd_ring;
4297 dev_priv->next_seqno = 1;
4300 * XXX: There was some w/a described somewhere suggesting loading
4301 * contexts before PPGTT.
4303 i915_gem_context_init(dev);
4304 i915_gem_init_ppgtt(dev);
4309 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4310 cleanup_render_ring:
4311 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4316 intel_enable_ppgtt(struct drm_device *dev)
4318 if (i915_enable_ppgtt >= 0)
4319 return i915_enable_ppgtt;
4321 #ifdef CONFIG_INTEL_IOMMU
4322 /* Disable ppgtt on SNB if VT-d is on. */
4323 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
4330 int i915_gem_init(struct drm_device *dev)
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333 unsigned long gtt_size, mappable_size;
4336 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
4337 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4340 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4341 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4342 * aperture accordingly when using aliasing ppgtt. */
4343 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4345 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4347 ret = i915_gem_init_aliasing_ppgtt(dev);
4353 /* Let GEM Manage all of the aperture.
4355 * However, leave one page at the end still bound to the scratch
4356 * page. There are a number of places where the hardware
4357 * apparently prefetches past the end of the object, and we've
4358 * seen multiple hangs with the GPU head pointer stuck in a
4359 * batchbuffer bound at the last page of the aperture. One page
4360 * should be enough to keep any prefetching inside of the
4363 i915_gem_init_global_gtt(dev, 0, mappable_size,
4367 ret = i915_gem_init_hw(dev);
4370 i915_gem_cleanup_aliasing_ppgtt(dev);
4374 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4375 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4376 dev_priv->dri1.allow_batchbuffer = 1;
4381 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4383 drm_i915_private_t *dev_priv = dev->dev_private;
4384 struct intel_ring_buffer *ring;
4387 for_each_ring(ring, dev_priv, i)
4388 intel_cleanup_ring_buffer(ring);
4392 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4393 struct drm_file *file_priv)
4395 drm_i915_private_t *dev_priv = dev->dev_private;
4398 if (drm_core_check_feature(dev, DRIVER_MODESET))
4401 if (atomic_read(&dev_priv->mm.wedged)) {
4402 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4403 atomic_set(&dev_priv->mm.wedged, 0);
4407 dev_priv->mm.suspended = 0;
4409 ret = i915_gem_init_hw(dev);
4415 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4418 ret = drm_irq_install(dev);
4420 goto cleanup_ringbuffer;
4426 i915_gem_cleanup_ringbuffer(dev);
4427 dev_priv->mm.suspended = 1;
4434 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4435 struct drm_file *file_priv)
4437 if (drm_core_check_feature(dev, DRIVER_MODESET))
4440 drm_irq_uninstall(dev);
4441 return i915_gem_idle(dev);
4445 i915_gem_lastclose(struct drm_device *dev)
4449 if (drm_core_check_feature(dev, DRIVER_MODESET))
4452 ret = i915_gem_idle(dev);
4454 DRM_ERROR("failed to idle hardware: %d\n", ret);
4458 init_ring_lists(struct intel_ring_buffer *ring)
4460 INIT_LIST_HEAD(&ring->active_list);
4461 INIT_LIST_HEAD(&ring->request_list);
4465 i915_gem_load(struct drm_device *dev)
4468 drm_i915_private_t *dev_priv = dev->dev_private;
4470 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4471 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4472 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4473 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4474 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4475 for (i = 0; i < I915_NUM_RINGS; i++)
4476 init_ring_lists(&dev_priv->ring[i]);
4477 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4478 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4479 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->mm.retire_work, 0,
4480 i915_gem_retire_work_handler, dev_priv);
4481 init_completion(&dev_priv->error_completion);
4483 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4485 I915_WRITE(MI_ARB_STATE,
4486 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4489 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4491 /* Old X drivers will take 0-2 for front, back, depth buffers */
4492 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4493 dev_priv->fence_reg_start = 3;
4495 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4496 dev_priv->num_fence_regs = 16;
4498 dev_priv->num_fence_regs = 8;
4500 /* Initialize fence registers to zero */
4501 i915_gem_reset_fences(dev);
4503 i915_gem_detect_bit_6_swizzle(dev);
4504 DRM_INIT_WAITQUEUE(&dev_priv->pending_flip_queue);
4506 dev_priv->mm.interruptible = true;
4508 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4509 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY);
4513 * Create a physically contiguous memory object for this object
4514 * e.g. for cursor + overlay regs
4516 static int i915_gem_init_phys_object(struct drm_device *dev,
4517 int id, int size, int align)
4519 drm_i915_private_t *dev_priv = dev->dev_private;
4520 struct drm_i915_gem_phys_object *phys_obj;
4523 if (dev_priv->mm.phys_objs[id - 1] || !size)
4526 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object),
4527 DRM_I915_GEM, M_WAITOK | M_ZERO);
4533 phys_obj->handle = drm_pci_alloc(dev, size, align, BUS_SPACE_MAXADDR);
4534 if (!phys_obj->handle) {
4539 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4540 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4543 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4547 free(phys_obj, DRM_I915_GEM);
4551 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4553 drm_i915_private_t *dev_priv = dev->dev_private;
4554 struct drm_i915_gem_phys_object *phys_obj;
4556 if (!dev_priv->mm.phys_objs[id - 1])
4559 phys_obj = dev_priv->mm.phys_objs[id - 1];
4560 if (phys_obj->cur_obj) {
4561 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4566 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4568 #endif /* FREEBSD_WIP */
4570 drm_pci_free(dev, phys_obj->handle);
4571 free(phys_obj, DRM_I915_GEM);
4572 dev_priv->mm.phys_objs[id - 1] = NULL;
4575 void i915_gem_free_all_phys_object(struct drm_device *dev)
4579 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4580 i915_gem_free_phys_object(dev, i);
4583 void i915_gem_detach_phys_object(struct drm_device *dev,
4584 struct drm_i915_gem_object *obj)
4594 vaddr = obj->phys_obj->handle->vaddr;
4596 page_count = obj->base.size / PAGE_SIZE;
4597 VM_OBJECT_WLOCK(obj->base.vm_obj);
4598 for (i = 0; i < page_count; i++) {
4599 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4603 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4604 sf = sf_buf_alloc(page, 0);
4606 dst = (char *)sf_buf_kva(sf);
4607 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
4610 drm_clflush_pages(&page, 1);
4612 VM_OBJECT_WLOCK(obj->base.vm_obj);
4613 vm_page_reference(page);
4615 vm_page_dirty(page);
4616 vm_page_unwire(page, PQ_INACTIVE);
4617 vm_page_unlock(page);
4618 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4620 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4621 i915_gem_chipset_flush(dev);
4623 obj->phys_obj->cur_obj = NULL;
4624 obj->phys_obj = NULL;
4628 i915_gem_attach_phys_object(struct drm_device *dev,
4629 struct drm_i915_gem_object *obj,
4633 drm_i915_private_t *dev_priv = dev->dev_private;
4640 if (id > I915_MAX_PHYS_OBJECT)
4643 if (obj->phys_obj) {
4644 if (obj->phys_obj->id == id)
4646 i915_gem_detach_phys_object(dev, obj);
4649 /* create a new object */
4650 if (!dev_priv->mm.phys_objs[id - 1]) {
4651 ret = i915_gem_init_phys_object(dev, id,
4652 obj->base.size, align);
4654 DRM_ERROR("failed to init phys object %d size: %zu\n",
4655 id, obj->base.size);
4660 /* bind to the object */
4661 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4662 obj->phys_obj->cur_obj = obj;
4664 page_count = obj->base.size / PAGE_SIZE;
4666 VM_OBJECT_WLOCK(obj->base.vm_obj);
4667 for (i = 0; i < page_count; i++) {
4668 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4673 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4674 sf = sf_buf_alloc(page, 0);
4675 src = (char *)sf_buf_kva(sf);
4676 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
4677 memcpy(dst, src, PAGE_SIZE);
4680 VM_OBJECT_WLOCK(obj->base.vm_obj);
4682 vm_page_reference(page);
4684 vm_page_unwire(page, PQ_INACTIVE);
4685 vm_page_unlock(page);
4686 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4688 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4694 i915_gem_phys_pwrite(struct drm_device *dev,
4695 struct drm_i915_gem_object *obj,
4696 struct drm_i915_gem_pwrite *args,
4697 struct drm_file *file_priv)
4699 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4700 char __user *user_data = to_user_ptr(args->data_ptr);
4702 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4703 unsigned long unwritten;
4705 /* The physical object once assigned is fixed for the lifetime
4706 * of the obj, so we can safely drop the lock and continue
4710 unwritten = copy_from_user(vaddr, user_data, args->size);
4716 i915_gem_chipset_flush(dev);
4720 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4722 struct drm_i915_file_private *file_priv = file->driver_priv;
4724 /* Clean up our request list when the client is going away, so that
4725 * later retire_requests won't dereference our soon-to-be-gone
4728 mtx_lock(&file_priv->mm.lock);
4729 while (!list_empty(&file_priv->mm.request_list)) {
4730 struct drm_i915_gem_request *request;
4732 request = list_first_entry(&file_priv->mm.request_list,
4733 struct drm_i915_gem_request,
4735 list_del(&request->client_list);
4736 request->file_priv = NULL;
4738 mtx_unlock(&file_priv->mm.lock);
4742 i915_gem_inactive_shrink(void *arg)
4744 struct drm_device *dev = arg;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4748 if (!sx_try_xlock(&dev->dev_struct_lock)) {
4752 CTR0(KTR_DRM, "gem_lowmem");
4754 pass1 = i915_gem_purge(dev_priv, -1);
4755 pass2 = __i915_gem_shrink(dev_priv, -1, false);
4757 if (pass2 <= pass1 / 100)
4758 i915_gem_shrink_all(dev_priv);
4764 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, bool *fresh)
4769 VM_OBJECT_ASSERT_WLOCKED(object);
4770 page = vm_page_grab(object, pindex, VM_ALLOC_NORMAL);
4771 if (page->valid != VM_PAGE_BITS_ALL) {
4772 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
4773 rv = vm_pager_get_pages(object, &page, 1, NULL, NULL);
4774 if (rv != VM_PAGER_OK) {
4777 vm_page_unlock(page);
4783 pmap_zero_page(page);
4784 page->valid = VM_PAGE_BITS_ALL;
4789 } else if (fresh != NULL) {
4794 vm_page_unlock(page);
4795 vm_page_xunbusy(page);
4796 atomic_add_long(&i915_gem_wired_pages_cnt, 1);