2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 #include <sys/cdefs.h>
55 __FBSDID("$FreeBSD$");
57 #include <dev/drm2/drmP.h>
58 #include <dev/drm2/drm.h>
59 #include <dev/drm2/i915/i915_drm.h>
60 #include <dev/drm2/i915/i915_drv.h>
61 #include <dev/drm2/i915/intel_drv.h>
62 #include <dev/drm2/i915/intel_ringbuffer.h>
63 #include <sys/resourcevar.h>
64 #include <sys/sched.h>
65 #include <sys/sf_buf.h>
68 #include <vm/vm_pageout.h>
70 #include <machine/md_var.h>
72 static void i915_gem_object_flush_cpu_write_domain(
73 struct drm_i915_gem_object *obj);
74 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
76 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
77 uint32_t size, int tiling_mode);
78 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
79 unsigned alignment, bool map_and_fenceable);
80 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
82 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
83 static void i915_gem_object_put_pages_range(struct drm_i915_gem_object *obj,
84 off_t start, off_t end);
85 static int i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
86 off_t start, off_t end);
87 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
88 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
89 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
90 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
91 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
92 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex,
94 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
95 uint32_t flush_domains);
96 static void i915_gem_reset_fences(struct drm_device *dev);
97 static void i915_gem_retire_task_handler(void *arg, int pending);
98 static void i915_gem_lowmem(void *arg);
99 static void i915_gem_write_fence(struct drm_device *dev, int reg,
100 struct drm_i915_gem_object *obj);
101 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
103 static int i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno);
105 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
106 long i915_gem_wired_pages_cnt;
108 static bool cpu_cache_is_coherent(struct drm_device *dev,
109 enum i915_cache_level level)
111 return HAS_LLC(dev) || level != I915_CACHE_NONE;
114 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
116 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
119 return obj->pin_display;
122 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
124 if (obj->tiling_mode)
125 i915_gem_release_mmap(obj);
127 /* As we do not have an associated fence register, we will force
128 * a tiling change if we ever need to acquire one.
130 obj->fence_dirty = false;
131 obj->fence_reg = I915_FENCE_REG_NONE;
135 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
138 dev_priv->mm.object_count++;
139 dev_priv->mm.object_memory += size;
143 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
146 dev_priv->mm.object_count--;
147 dev_priv->mm.object_memory -= size;
151 i915_gem_wait_for_error(struct drm_device *dev)
153 struct drm_i915_private *dev_priv;
156 dev_priv = dev->dev_private;
157 if (!atomic_load_acq_int(&dev_priv->mm.wedged))
160 mtx_lock(&dev_priv->error_completion_lock);
161 while (dev_priv->error_completion == 0) {
162 ret = -msleep(&dev_priv->error_completion,
163 &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
164 if (ret == -ERESTART)
167 mtx_unlock(&dev_priv->error_completion_lock);
171 mtx_unlock(&dev_priv->error_completion_lock);
173 if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
174 mtx_lock(&dev_priv->error_completion_lock);
175 dev_priv->error_completion++;
176 mtx_unlock(&dev_priv->error_completion_lock);
182 i915_mutex_lock_interruptible(struct drm_device *dev)
184 struct drm_i915_private *dev_priv;
187 dev_priv = dev->dev_private;
188 ret = i915_gem_wait_for_error(dev);
193 * interruptible shall it be. might indeed be if dev_lock is
196 ret = sx_xlock_sig(&dev->dev_struct_lock);
205 i915_gem_free_object(struct drm_gem_object *gem_obj)
207 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
208 struct drm_device *dev;
209 drm_i915_private_t *dev_priv;
212 dev_priv = dev->dev_private;
214 CTR1(KTR_DRM, "object_destroy_tail %p", obj);
217 i915_gem_detach_phys_object(dev, obj);
220 if (i915_gem_object_unbind(obj) == -ERESTARTSYS) {
221 bool was_interruptible;
223 was_interruptible = dev_priv->mm.interruptible;
224 dev_priv->mm.interruptible = false;
226 if (i915_gem_object_unbind(obj))
227 printf("i915_gem_free_object: unbind\n");
229 dev_priv->mm.interruptible = was_interruptible;
232 drm_gem_free_mmap_offset(&obj->base);
233 drm_gem_object_release(&obj->base);
234 i915_gem_info_remove_obj(dev_priv, obj->base.size);
236 free(obj->bit_17, DRM_I915_GEM);
237 free(obj, DRM_I915_GEM);
241 init_ring_lists(struct intel_ring_buffer *ring)
244 INIT_LIST_HEAD(&ring->active_list);
245 INIT_LIST_HEAD(&ring->request_list);
246 INIT_LIST_HEAD(&ring->gpu_write_list);
250 i915_gem_load(struct drm_device *dev)
252 drm_i915_private_t *dev_priv;
255 dev_priv = dev->dev_private;
257 INIT_LIST_HEAD(&dev_priv->mm.active_list);
258 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
259 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
260 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
261 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
262 for (i = 0; i < I915_NUM_RINGS; i++)
263 init_ring_lists(&dev_priv->rings[i]);
264 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
265 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
266 TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
267 i915_gem_retire_task_handler, dev_priv);
268 dev_priv->error_completion = 0;
270 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
272 I915_WRITE(MI_ARB_STATE,
273 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
276 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
278 /* Old X drivers will take 0-2 for front, back, depth buffers */
279 if (!drm_core_check_feature(dev, DRIVER_MODESET))
280 dev_priv->fence_reg_start = 3;
282 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) ||
284 dev_priv->num_fence_regs = 16;
286 dev_priv->num_fence_regs = 8;
288 /* Initialize fence registers to zero */
289 i915_gem_reset_fences(dev);
291 i915_gem_detect_bit_6_swizzle(dev);
292 dev_priv->mm.interruptible = true;
294 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
295 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
299 i915_gem_init_ioctl(struct drm_device *dev, void *data,
300 struct drm_file *file)
302 struct drm_i915_gem_init *args;
303 drm_i915_private_t *dev_priv;
306 if (drm_core_check_feature(dev, DRIVER_MODESET))
309 dev_priv = dev->dev_private;
312 if (args->gtt_start >= args->gtt_end ||
313 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
316 if (mtx_initialized(&dev_priv->mm.gtt_space.unused_lock))
319 /* GEM with user mode setting was never supported on ilk and later. */
320 if (INTEL_INFO(dev)->gen >= 5)
324 * XXXKIB. The second-time initialization should be guarded
328 error = i915_gem_init_global_gtt(dev, args->gtt_start,
329 args->gtt_end, args->gtt_end);
335 i915_gem_idle(struct drm_device *dev)
337 drm_i915_private_t *dev_priv;
342 dev_priv = dev->dev_private;
343 if (dev_priv->mm.suspended) {
348 ret = i915_gpu_idle(dev);
353 i915_gem_retire_requests(dev);
355 /* Under UMS, be paranoid and evict. */
356 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
357 ret = i915_gem_evict_everything(dev, false);
364 i915_gem_reset_fences(dev);
366 /* Hack! Don't let anybody do execbuf while we don't control the chip.
367 * We need to replace this with a semaphore, or something.
368 * And not confound mm.suspended!
370 dev_priv->mm.suspended = 1;
371 callout_stop(&dev_priv->hangcheck_timer);
373 i915_kernel_lost_context(dev);
374 i915_gem_cleanup_ringbuffer(dev);
378 /* Cancel the retire work handler, which should be idle now. */
379 taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
384 i915_gem_init_swizzling(struct drm_device *dev)
386 drm_i915_private_t *dev_priv;
388 dev_priv = dev->dev_private;
390 if (INTEL_INFO(dev)->gen < 5 ||
391 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
394 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
395 DISP_TILE_SURFACE_SWIZZLING);
401 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
403 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
405 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
408 void i915_gem_init_ppgtt(struct drm_device *dev)
410 drm_i915_private_t *dev_priv;
411 struct i915_hw_ppgtt *ppgtt;
412 uint32_t pd_offset, pd_entry;
414 struct intel_ring_buffer *ring;
415 u_int first_pd_entry_in_global_pt, i;
417 dev_priv = dev->dev_private;
418 ppgtt = dev_priv->mm.aliasing_ppgtt;
422 first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
423 for (i = 0; i < ppgtt->num_pd_entries; i++) {
424 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
425 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
426 pd_entry |= GEN6_PDE_VALID;
427 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
429 intel_gtt_read_pte(first_pd_entry_in_global_pt);
431 pd_offset = ppgtt->pd_offset;
432 pd_offset /= 64; /* in cachelines, */
435 if (INTEL_INFO(dev)->gen == 6) {
436 uint32_t ecochk, gab_ctl, ecobits;
438 ecobits = I915_READ(GAC_ECO_BITS);
439 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
441 gab_ctl = I915_READ(GAB_CTL);
442 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
444 ecochk = I915_READ(GAM_ECOCHK);
445 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
446 ECOCHK_PPGTT_CACHE64B);
447 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
448 } else if (INTEL_INFO(dev)->gen >= 7) {
449 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
450 /* GFX_MODE is per-ring on gen7+ */
453 for_each_ring(ring, dev_priv, i) {
454 if (INTEL_INFO(dev)->gen >= 7)
455 I915_WRITE(RING_MODE_GEN7(ring),
456 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
458 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
459 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
464 i915_gem_init_hw(struct drm_device *dev)
466 drm_i915_private_t *dev_priv;
469 dev_priv = dev->dev_private;
471 i915_gem_init_swizzling(dev);
473 ret = intel_init_render_ring_buffer(dev);
478 ret = intel_init_bsd_ring_buffer(dev);
480 goto cleanup_render_ring;
484 ret = intel_init_blt_ring_buffer(dev);
486 goto cleanup_bsd_ring;
489 dev_priv->next_seqno = 1;
490 i915_gem_context_init(dev);
491 i915_gem_init_ppgtt(dev);
495 intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
497 intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
502 intel_enable_ppgtt(struct drm_device *dev)
504 if (i915_enable_ppgtt >= 0)
505 return i915_enable_ppgtt;
507 /* Disable ppgtt on SNB if VT-d is on. */
508 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
514 int i915_gem_init(struct drm_device *dev)
516 struct drm_i915_private *dev_priv = dev->dev_private;
517 unsigned long gtt_size, mappable_size;
520 gtt_size = dev_priv->mm.gtt.gtt_total_entries << PAGE_SHIFT;
521 mappable_size = dev_priv->mm.gtt.gtt_mappable_entries << PAGE_SHIFT;
524 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
525 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
526 * aperture accordingly when using aliasing ppgtt. */
527 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
529 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
531 ret = i915_gem_init_aliasing_ppgtt(dev);
537 /* Let GEM Manage all of the aperture.
539 * However, leave one page at the end still bound to the scratch
540 * page. There are a number of places where the hardware
541 * apparently prefetches past the end of the object, and we've
542 * seen multiple hangs with the GPU head pointer stuck in a
543 * batchbuffer bound at the last page of the aperture. One page
544 * should be enough to keep any prefetching inside of the
547 i915_gem_init_global_gtt(dev, 0, mappable_size,
551 ret = i915_gem_init_hw(dev);
554 i915_gem_cleanup_aliasing_ppgtt(dev);
558 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
559 if (!drm_core_check_feature(dev, DRIVER_MODESET))
560 dev_priv->dri1.allow_batchbuffer = 1;
565 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
566 struct drm_file *file)
568 struct drm_i915_private *dev_priv;
569 struct drm_i915_gem_get_aperture *args;
570 struct drm_i915_gem_object *obj;
573 dev_priv = dev->dev_private;
578 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
580 pinned += obj->gtt_space->size;
583 args->aper_size = dev_priv->mm.gtt_total;
584 args->aper_available_size = args->aper_size - pinned;
590 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
591 bool map_and_fenceable)
595 if (obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)
598 if (obj->gtt_space != NULL) {
599 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
600 (map_and_fenceable && !obj->map_and_fenceable)) {
601 DRM_DEBUG("bo is already pinned with incorrect alignment:"
602 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
603 " obj->map_and_fenceable=%d\n",
604 obj->gtt_offset, alignment,
606 obj->map_and_fenceable);
607 ret = i915_gem_object_unbind(obj);
613 if (obj->gtt_space == NULL) {
614 ret = i915_gem_object_bind_to_gtt(obj, alignment,
620 if (!obj->has_global_gtt_mapping && map_and_fenceable)
621 i915_gem_gtt_bind_object(obj, obj->cache_level);
624 obj->pin_mappable |= map_and_fenceable;
630 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
633 KASSERT(obj->pin_count != 0, ("zero pin count"));
634 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
636 if (--obj->pin_count == 0)
637 obj->pin_mappable = false;
641 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
642 struct drm_file *file)
644 struct drm_i915_gem_pin *args;
645 struct drm_i915_gem_object *obj;
646 struct drm_gem_object *gobj;
651 ret = i915_mutex_lock_interruptible(dev);
655 gobj = drm_gem_object_lookup(dev, file, args->handle);
660 obj = to_intel_bo(gobj);
662 if (obj->madv != I915_MADV_WILLNEED) {
663 DRM_ERROR("Attempting to pin a purgeable buffer\n");
668 if (obj->pin_filp != NULL && obj->pin_filp != file) {
669 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
675 obj->user_pin_count++;
676 obj->pin_filp = file;
677 if (obj->user_pin_count == 1) {
678 ret = i915_gem_object_pin(obj, args->alignment, true);
683 /* XXX - flush the CPU caches for pinned objects
684 * as the X server doesn't manage domains yet
686 i915_gem_object_flush_cpu_write_domain(obj);
687 args->offset = obj->gtt_offset;
689 drm_gem_object_unreference(&obj->base);
696 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
697 struct drm_file *file)
699 struct drm_i915_gem_pin *args;
700 struct drm_i915_gem_object *obj;
704 ret = i915_mutex_lock_interruptible(dev);
708 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
709 if (&obj->base == NULL) {
714 if (obj->pin_filp != file) {
715 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
720 obj->user_pin_count--;
721 if (obj->user_pin_count == 0) {
722 obj->pin_filp = NULL;
723 i915_gem_object_unpin(obj);
727 drm_gem_object_unreference(&obj->base);
734 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
735 struct drm_file *file)
737 struct drm_i915_gem_busy *args;
738 struct drm_i915_gem_object *obj;
743 ret = i915_mutex_lock_interruptible(dev);
747 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
748 if (&obj->base == NULL) {
753 args->busy = obj->active;
755 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
756 ret = i915_gem_flush_ring(obj->ring,
757 0, obj->base.write_domain);
759 ret = i915_gem_check_olr(obj->ring,
760 obj->last_rendering_seqno);
763 i915_gem_retire_requests_ring(obj->ring);
764 args->busy = obj->active;
767 drm_gem_object_unreference(&obj->base);
774 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
776 struct drm_i915_private *dev_priv;
777 struct drm_i915_file_private *file_priv;
778 unsigned long recent_enough;
779 struct drm_i915_gem_request *request;
780 struct intel_ring_buffer *ring;
784 dev_priv = dev->dev_private;
785 if (atomic_load_acq_int(&dev_priv->mm.wedged))
788 file_priv = file->driver_priv;
789 recent_enough = ticks - (20 * hz / 1000);
793 mtx_lock(&file_priv->mm.lck);
794 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
795 if (time_after_eq(request->emitted_jiffies, recent_enough))
797 ring = request->ring;
798 seqno = request->seqno;
800 mtx_unlock(&file_priv->mm.lck);
804 ret = __wait_seqno(ring, seqno, true);
806 taskqueue_enqueue_timeout(dev_priv->tq,
807 &dev_priv->mm.retire_task, 0);
813 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
814 struct drm_file *file_priv)
817 return (i915_gem_ring_throttle(dev, file_priv));
821 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
822 struct drm_file *file_priv)
824 struct drm_i915_gem_madvise *args;
825 struct drm_i915_gem_object *obj;
829 switch (args->madv) {
830 case I915_MADV_DONTNEED:
831 case I915_MADV_WILLNEED:
837 ret = i915_mutex_lock_interruptible(dev);
841 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
842 if (&obj->base == NULL) {
847 if (obj->pin_count != 0) {
852 if (obj->madv != I915_MADV_PURGED_INTERNAL)
853 obj->madv = args->madv;
854 if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
855 i915_gem_object_truncate(obj);
856 args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
859 drm_gem_object_unreference(&obj->base);
866 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
868 drm_i915_private_t *dev_priv;
869 struct intel_ring_buffer *ring;
872 dev_priv = dev->dev_private;
873 for_each_ring(ring, dev_priv, i)
874 intel_cleanup_ring_buffer(ring);
878 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
879 struct drm_file *file_priv)
881 drm_i915_private_t *dev_priv;
884 if (drm_core_check_feature(dev, DRIVER_MODESET))
886 dev_priv = dev->dev_private;
887 if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
888 DRM_ERROR("Reenabling wedged hardware, good luck\n");
889 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
893 dev_priv->mm.suspended = 0;
895 ret = i915_gem_init_hw(dev);
901 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
902 KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
903 KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
906 ret = drm_irq_install(dev);
908 goto cleanup_ringbuffer;
914 i915_gem_cleanup_ringbuffer(dev);
915 dev_priv->mm.suspended = 1;
922 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
923 struct drm_file *file_priv)
926 if (drm_core_check_feature(dev, DRIVER_MODESET))
929 drm_irq_uninstall(dev);
930 return (i915_gem_idle(dev));
934 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
937 struct drm_i915_gem_object *obj;
941 size = roundup(size, PAGE_SIZE);
945 obj = i915_gem_alloc_object(dev, size);
949 ret = drm_gem_handle_create(file, &obj->base, &handle);
951 drm_gem_object_release(&obj->base);
952 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
953 free(obj, DRM_I915_GEM);
957 /* drop reference from allocate - handle holds it now */
958 drm_gem_object_unreference(&obj->base);
959 CTR2(KTR_DRM, "object_create %p %x", obj, size);
965 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
966 struct drm_mode_create_dumb *args)
969 /* have to work out size/pitch and return them */
970 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
971 args->size = args->pitch * args->height;
972 return (i915_gem_create(file, dev, args->size, &args->handle));
976 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
980 return (drm_gem_handle_delete(file, handle));
984 i915_gem_create_ioctl(struct drm_device *dev, void *data,
985 struct drm_file *file)
987 struct drm_i915_gem_create *args = data;
989 return (i915_gem_create(file, dev, args->size, &args->handle));
995 #define to_user_ptr(x) ((void *)(uintptr_t)(x))
996 #define offset_in_page(x) ((x) & PAGE_MASK)
997 #define page_to_phys(x) VM_PAGE_TO_PHYS(x)
999 __copy_to_user_inatomic(void __user *to, const void *from, unsigned n)
1001 return (copyout_nofault(from, to, n) != 0 ? n : 0);
1003 static inline unsigned long
1004 __copy_from_user_inatomic_nocache(void *to, const void __user *from,
1009 * XXXKIB. Equivalent Linux function is implemented using
1010 * MOVNTI for aligned moves. For unaligned head and tail,
1011 * normal move is performed. As such, it is not incorrect, if
1012 * only somewhat slower, to use normal copyin. All uses
1013 * except shmem_pwrite_fast() have the destination mapped WC.
1015 return ((copyin_nofault(__DECONST(void *, from), to, n) != 0 ? n : 0));
1018 fault_in_multipages_readable(const char __user *uaddr, int size)
1022 const char __user *end = uaddr + size - 1;
1024 if (unlikely(size == 0))
1027 while (uaddr <= end) {
1028 ret = -copyin(uaddr, &c, 1);
1034 /* Check whether the range spilled into the next page. */
1035 if (((unsigned long)uaddr & ~PAGE_MASK) ==
1036 ((unsigned long)end & ~PAGE_MASK)) {
1037 ret = -copyin(end, &c, 1);
1044 fault_in_multipages_writeable(char __user *uaddr, int size)
1047 char __user *end = uaddr + size - 1;
1049 if (unlikely(size == 0))
1053 * Writing zeroes into userspace here is OK, because we know that if
1054 * the zero gets there, we'll be overwriting it.
1056 while (uaddr <= end) {
1057 ret = subyte(uaddr, 0);
1063 /* Check whether the range spilled into the next page. */
1064 if (((unsigned long)uaddr & ~PAGE_MASK) ==
1065 ((unsigned long)end & ~PAGE_MASK))
1066 ret = subyte(end, 0);
1072 __copy_to_user_swizzled(char __user *cpu_vaddr,
1073 const char *gpu_vaddr, int gpu_offset,
1076 int ret, cpu_offset = 0;
1078 while (length > 0) {
1079 int cacheline_end = roundup2(gpu_offset + 1, 64);
1080 int this_length = min(cacheline_end - gpu_offset, length);
1081 int swizzled_gpu_offset = gpu_offset ^ 64;
1083 ret = __copy_to_user(cpu_vaddr + cpu_offset,
1084 gpu_vaddr + swizzled_gpu_offset,
1087 return ret + length;
1089 cpu_offset += this_length;
1090 gpu_offset += this_length;
1091 length -= this_length;
1098 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
1099 const char __user *cpu_vaddr,
1102 int ret, cpu_offset = 0;
1104 while (length > 0) {
1105 int cacheline_end = roundup2(gpu_offset + 1, 64);
1106 int this_length = min(cacheline_end - gpu_offset, length);
1107 int swizzled_gpu_offset = gpu_offset ^ 64;
1109 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
1110 cpu_vaddr + cpu_offset,
1113 return ret + length;
1115 cpu_offset += this_length;
1116 gpu_offset += this_length;
1117 length -= this_length;
1124 i915_gem_phys_pwrite(struct drm_device *dev,
1125 struct drm_i915_gem_object *obj,
1126 struct drm_i915_gem_pwrite *args,
1127 struct drm_file *file_priv)
1129 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
1130 char __user *user_data = to_user_ptr(args->data_ptr);
1132 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
1133 unsigned long unwritten;
1135 /* The physical object once assigned is fixed for the lifetime
1136 * of the obj, so we can safely drop the lock and continue
1140 unwritten = copy_from_user(vaddr, user_data, args->size);
1146 i915_gem_chipset_flush(dev);
1150 /* Per-page copy function for the shmem pread fastpath.
1151 * Flushes invalid cachelines before reading the target if
1152 * needs_clflush is set. */
1154 shmem_pread_fast(vm_page_t page, int shmem_page_offset, int page_length,
1155 char __user *user_data,
1156 bool page_do_bit17_swizzling, bool needs_clflush)
1162 if (unlikely(page_do_bit17_swizzling))
1166 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE);
1171 vaddr = (char *)sf_buf_kva(sf);
1173 drm_clflush_virt_range(vaddr + shmem_page_offset,
1175 ret = __copy_to_user_inatomic(user_data,
1176 vaddr + shmem_page_offset,
1181 return ret ? -EFAULT : 0;
1185 shmem_clflush_swizzled_range(char *addr, unsigned long length,
1188 if (unlikely(swizzled)) {
1189 unsigned long start = (unsigned long) addr;
1190 unsigned long end = (unsigned long) addr + length;
1192 /* For swizzling simply ensure that we always flush both
1193 * channels. Lame, but simple and it works. Swizzled
1194 * pwrite/pread is far from a hotpath - current userspace
1195 * doesn't use it at all. */
1196 start = rounddown2(start, 128);
1197 end = roundup2(end, 128);
1199 drm_clflush_virt_range((void *)start, end - start);
1201 drm_clflush_virt_range(addr, length);
1206 /* Only difference to the fast-path function is that this can handle bit17
1207 * and uses non-atomic copy and kmap functions. */
1209 shmem_pread_slow(vm_page_t page, int shmem_page_offset, int page_length,
1210 char __user *user_data,
1211 bool page_do_bit17_swizzling, bool needs_clflush)
1217 sf = sf_buf_alloc(page, 0);
1218 vaddr = (char *)sf_buf_kva(sf);
1220 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1222 page_do_bit17_swizzling);
1224 if (page_do_bit17_swizzling)
1225 ret = __copy_to_user_swizzled(user_data,
1226 vaddr, shmem_page_offset,
1229 ret = __copy_to_user(user_data,
1230 vaddr + shmem_page_offset,
1234 return ret ? - EFAULT : 0;
1238 i915_gem_shmem_pread(struct drm_device *dev,
1239 struct drm_i915_gem_object *obj,
1240 struct drm_i915_gem_pread *args,
1241 struct drm_file *file)
1243 char __user *user_data;
1244 ssize_t remain, sremain;
1245 off_t offset, soffset;
1246 int shmem_page_offset, page_length, ret = 0;
1247 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
1249 int needs_clflush = 0;
1251 user_data = to_user_ptr(args->data_ptr);
1252 sremain = remain = args->size;
1254 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
1256 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
1257 /* If we're not in the cpu read domain, set ourself into the gtt
1258 * read domain and manually flush cachelines (if required). This
1259 * optimizes for the case when the gpu will dirty the data
1260 * anyway again before the next pread happens. */
1261 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
1262 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1267 soffset = offset = args->offset;
1268 ret = i915_gem_object_get_pages_range(obj, soffset, soffset + sremain);
1272 i915_gem_object_pin_pages(obj);
1274 VM_OBJECT_WLOCK(obj->base.vm_obj);
1275 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
1276 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
1277 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
1282 /* Operation in this page
1284 * shmem_page_offset = offset within page in shmem file
1285 * page_length = bytes to copy for this page
1287 shmem_page_offset = offset_in_page(offset);
1288 page_length = remain;
1289 if ((shmem_page_offset + page_length) > PAGE_SIZE)
1290 page_length = PAGE_SIZE - shmem_page_offset;
1292 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
1293 (page_to_phys(page) & (1 << 17)) != 0;
1295 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
1296 user_data, page_do_bit17_swizzling,
1303 if (likely(!i915_prefault_disable) && !prefaulted) {
1304 ret = fault_in_multipages_writeable(user_data, remain);
1305 /* Userspace is tricking us, but we've already clobbered
1306 * its pages with the prefault and promised to write the
1307 * data up to the first fault. Hence ignore any errors
1308 * and just continue. */
1313 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
1314 user_data, page_do_bit17_swizzling,
1320 vm_page_reference(page);
1325 remain -= page_length;
1326 user_data += page_length;
1327 offset += page_length;
1328 VM_OBJECT_WLOCK(obj->base.vm_obj);
1332 i915_gem_object_unpin_pages(obj);
1333 i915_gem_object_put_pages_range(obj, soffset, soffset + sremain);
1339 * Reads data from the object referenced by handle.
1341 * On error, the contents of *data are undefined.
1344 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1345 struct drm_file *file)
1347 struct drm_i915_gem_pread *args = data;
1348 struct drm_i915_gem_object *obj;
1351 if (args->size == 0)
1354 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_WRITE))
1357 ret = i915_mutex_lock_interruptible(dev);
1361 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1362 if (&obj->base == NULL) {
1367 /* Bounds check source. */
1368 if (args->offset > obj->base.size ||
1369 args->size > obj->base.size - args->offset) {
1377 /* prime objects have no backing filp to GEM pread/pwrite
1380 if (!obj->base.filp) {
1386 CTR3(KTR_DRM, "pread %p %jx %jx", obj, args->offset, args->size);
1388 ret = i915_gem_shmem_pread(dev, obj, args, file);
1391 drm_gem_object_unreference(&obj->base);
1397 /* This is the fast write path which cannot handle
1398 * page faults in the source data
1402 fast_user_write(struct drm_device *dev,
1403 off_t page_base, int page_offset,
1404 char __user *user_data,
1407 void __iomem *vaddr_atomic;
1409 unsigned long unwritten;
1411 vaddr_atomic = pmap_mapdev_attr(dev->agp->base + page_base,
1412 length, PAT_WRITE_COMBINING);
1413 /* We can use the cpu mem copy function because this is X86. */
1414 vaddr = (char *)vaddr_atomic + page_offset;
1415 unwritten = __copy_from_user_inatomic_nocache(vaddr,
1417 pmap_unmapdev((vm_offset_t)vaddr_atomic, length);
1422 * This is the fast pwrite path, where we copy the data directly from the
1423 * user into the GTT, uncached.
1426 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
1427 struct drm_i915_gem_object *obj,
1428 struct drm_i915_gem_pwrite *args,
1429 struct drm_file *file)
1432 off_t offset, page_base;
1433 char __user *user_data;
1434 int page_offset, page_length, ret;
1436 ret = i915_gem_object_pin(obj, 0, true);
1437 /* XXXKIB ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); */
1441 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1445 ret = i915_gem_object_put_fence(obj);
1449 user_data = to_user_ptr(args->data_ptr);
1450 remain = args->size;
1452 offset = obj->gtt_offset + args->offset;
1454 while (remain > 0) {
1455 /* Operation in this page
1457 * page_base = page offset within aperture
1458 * page_offset = offset within page
1459 * page_length = bytes to copy for this page
1461 page_base = offset & ~PAGE_MASK;
1462 page_offset = offset_in_page(offset);
1463 page_length = remain;
1464 if ((page_offset + remain) > PAGE_SIZE)
1465 page_length = PAGE_SIZE - page_offset;
1467 /* If we get a fault while copying data, then (presumably) our
1468 * source page isn't available. Return the error and we'll
1469 * retry in the slow path.
1471 if (fast_user_write(dev, page_base,
1472 page_offset, user_data, page_length)) {
1477 remain -= page_length;
1478 user_data += page_length;
1479 offset += page_length;
1483 i915_gem_object_unpin(obj);
1488 /* Per-page copy function for the shmem pwrite fastpath.
1489 * Flushes invalid cachelines before writing to the target if
1490 * needs_clflush_before is set and flushes out any written cachelines after
1491 * writing if needs_clflush is set. */
1493 shmem_pwrite_fast(vm_page_t page, int shmem_page_offset, int page_length,
1494 char __user *user_data,
1495 bool page_do_bit17_swizzling,
1496 bool needs_clflush_before,
1497 bool needs_clflush_after)
1503 if (unlikely(page_do_bit17_swizzling))
1507 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE);
1512 vaddr = (char *)sf_buf_kva(sf);
1513 if (needs_clflush_before)
1514 drm_clflush_virt_range(vaddr + shmem_page_offset,
1516 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
1519 if (needs_clflush_after)
1520 drm_clflush_virt_range(vaddr + shmem_page_offset,
1525 return ret ? -EFAULT : 0;
1528 /* Only difference to the fast-path function is that this can handle bit17
1529 * and uses non-atomic copy and kmap functions. */
1531 shmem_pwrite_slow(vm_page_t page, int shmem_page_offset, int page_length,
1532 char __user *user_data,
1533 bool page_do_bit17_swizzling,
1534 bool needs_clflush_before,
1535 bool needs_clflush_after)
1541 sf = sf_buf_alloc(page, 0);
1542 vaddr = (char *)sf_buf_kva(sf);
1543 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1544 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1546 page_do_bit17_swizzling);
1547 if (page_do_bit17_swizzling)
1548 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
1552 ret = __copy_from_user(vaddr + shmem_page_offset,
1555 if (needs_clflush_after)
1556 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1558 page_do_bit17_swizzling);
1561 return ret ? -EFAULT : 0;
1565 i915_gem_shmem_pwrite(struct drm_device *dev,
1566 struct drm_i915_gem_object *obj,
1567 struct drm_i915_gem_pwrite *args,
1568 struct drm_file *file)
1570 ssize_t remain, sremain;
1571 off_t offset, soffset;
1572 char __user *user_data;
1573 int shmem_page_offset, page_length, ret = 0;
1574 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
1575 int hit_slowpath = 0;
1576 int needs_clflush_after = 0;
1577 int needs_clflush_before = 0;
1579 user_data = to_user_ptr(args->data_ptr);
1580 sremain = remain = args->size;
1582 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
1584 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1585 /* If we're not in the cpu write domain, set ourself into the gtt
1586 * write domain and manually flush cachelines (if required). This
1587 * optimizes for the case when the gpu will use the data
1588 * right away and we therefore have to clflush anyway. */
1589 needs_clflush_after = cpu_write_needs_clflush(obj);
1590 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1594 /* Same trick applies to invalidate partially written cachelines read
1595 * before writing. */
1596 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1597 needs_clflush_before =
1598 !cpu_cache_is_coherent(dev, obj->cache_level);
1600 soffset = offset = args->offset;
1601 ret = i915_gem_object_get_pages_range(obj, soffset, soffset + sremain);
1605 i915_gem_object_pin_pages(obj);
1609 VM_OBJECT_WLOCK(obj->base.vm_obj);
1610 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
1611 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
1612 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
1613 int partial_cacheline_write;
1618 /* Operation in this page
1620 * shmem_page_offset = offset within page in shmem file
1621 * page_length = bytes to copy for this page
1623 shmem_page_offset = offset_in_page(offset);
1625 page_length = remain;
1626 if ((shmem_page_offset + page_length) > PAGE_SIZE)
1627 page_length = PAGE_SIZE - shmem_page_offset;
1629 /* If we don't overwrite a cacheline completely we need to be
1630 * careful to have up-to-date data by first clflushing. Don't
1631 * overcomplicate things and flush the entire patch. */
1632 partial_cacheline_write = needs_clflush_before &&
1633 ((shmem_page_offset | page_length)
1634 & (cpu_clflush_line_size - 1));
1636 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
1637 (page_to_phys(page) & (1 << 17)) != 0;
1639 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
1640 user_data, page_do_bit17_swizzling,
1641 partial_cacheline_write,
1642 needs_clflush_after);
1648 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1649 user_data, page_do_bit17_swizzling,
1650 partial_cacheline_write,
1651 needs_clflush_after);
1656 vm_page_dirty(page);
1657 vm_page_reference(page);
1662 remain -= page_length;
1663 user_data += page_length;
1664 offset += page_length;
1665 VM_OBJECT_WLOCK(obj->base.vm_obj);
1669 i915_gem_object_unpin_pages(obj);
1670 i915_gem_object_put_pages_range(obj, soffset, soffset + sremain);
1674 * Fixup: Flush cpu caches in case we didn't flush the dirty
1675 * cachelines in-line while writing and the object moved
1676 * out of the cpu write domain while we've dropped the lock.
1678 if (!needs_clflush_after &&
1679 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1680 i915_gem_clflush_object(obj);
1681 i915_gem_chipset_flush(dev);
1685 if (needs_clflush_after)
1686 i915_gem_chipset_flush(dev);
1692 * Writes data to the object referenced by handle.
1694 * On error, the contents of the buffer that were to be modified are undefined.
1697 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1698 struct drm_file *file)
1700 struct drm_i915_gem_pwrite *args = data;
1701 struct drm_i915_gem_object *obj;
1704 if (args->size == 0)
1707 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_READ))
1710 if (likely(!i915_prefault_disable)) {
1711 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1717 ret = i915_mutex_lock_interruptible(dev);
1721 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1722 if (&obj->base == NULL) {
1727 /* Bounds check destination. */
1728 if (args->offset > obj->base.size ||
1729 args->size > obj->base.size - args->offset) {
1737 /* prime objects have no backing filp to GEM pread/pwrite
1740 if (!obj->base.filp) {
1746 CTR3(KTR_DRM, "pwrite %p %jx %jx", obj, args->offset, args->size);
1749 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1750 * it would end up going through the fenced access, and we'll get
1751 * different detiling behavior between reading and writing.
1752 * pread/pwrite currently are reading and writing from the CPU
1753 * perspective, requiring manual detiling by the client.
1755 if (obj->phys_obj) {
1756 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1760 if (obj->tiling_mode == I915_TILING_NONE &&
1761 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1762 cpu_write_needs_clflush(obj)) {
1763 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1764 /* Note that the gtt paths might fail with non-page-backed user
1765 * pointers (e.g. gtt mappings when moving data between
1766 * textures). Fallback to the shmem path in that case. */
1769 if (ret == -EFAULT || ret == -ENOSPC)
1770 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1773 drm_gem_object_unreference(&obj->base);
1782 #undef offset_in_page
1786 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1787 struct drm_file *file)
1789 struct drm_i915_gem_set_domain *args;
1790 struct drm_i915_gem_object *obj;
1791 uint32_t read_domains;
1792 uint32_t write_domain;
1796 read_domains = args->read_domains;
1797 write_domain = args->write_domain;
1799 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1800 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1801 (write_domain != 0 && read_domains != write_domain))
1804 ret = i915_mutex_lock_interruptible(dev);
1808 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1809 if (&obj->base == NULL) {
1814 if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1815 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1819 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1821 drm_gem_object_unreference(&obj->base);
1828 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1829 struct drm_file *file)
1831 struct drm_i915_gem_sw_finish *args;
1832 struct drm_i915_gem_object *obj;
1837 ret = i915_mutex_lock_interruptible(dev);
1840 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1841 if (&obj->base == NULL) {
1845 if (obj->pin_count != 0)
1846 i915_gem_object_flush_cpu_write_domain(obj);
1847 drm_gem_object_unreference(&obj->base);
1854 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *file)
1857 struct drm_i915_gem_mmap *args;
1858 struct drm_gem_object *obj;
1867 obj = drm_gem_object_lookup(dev, file, args->handle);
1871 if (args->size == 0)
1874 map = &p->p_vmspace->vm_map;
1875 size = round_page(args->size);
1877 if (map->size + size > lim_cur_proc(p, RLIMIT_VMEM)) {
1885 vm_object_reference(obj->vm_obj);
1886 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size, 0,
1887 VMFS_OPTIMAL_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1888 VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1889 if (rv != KERN_SUCCESS) {
1890 vm_object_deallocate(obj->vm_obj);
1891 error = -vm_mmap_to_errno(rv);
1893 args->addr_ptr = (uint64_t)addr;
1896 drm_gem_object_unreference(obj);
1901 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1902 vm_ooffset_t foff, struct ucred *cred, u_short *color)
1905 *color = 0; /* XXXKIB */
1912 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1915 struct drm_gem_object *gem_obj;
1916 struct drm_i915_gem_object *obj;
1917 struct drm_device *dev;
1918 drm_i915_private_t *dev_priv;
1923 gem_obj = vm_obj->handle;
1924 obj = to_intel_bo(gem_obj);
1925 dev = obj->base.dev;
1926 dev_priv = dev->dev_private;
1928 write = (prot & VM_PROT_WRITE) != 0;
1932 vm_object_pip_add(vm_obj, 1);
1935 * Remove the placeholder page inserted by vm_fault() from the
1936 * object before dropping the object lock. If
1937 * i915_gem_release_mmap() is active in parallel on this gem
1938 * object, then it owns the drm device sx and might find the
1939 * placeholder already. Then, since the page is busy,
1940 * i915_gem_release_mmap() sleeps waiting for the busy state
1941 * of the page cleared. We will be not able to acquire drm
1942 * device lock until i915_gem_release_mmap() is able to make a
1945 if (*mres != NULL) {
1948 vm_page_remove(oldm);
1949 vm_page_unlock(oldm);
1953 VM_OBJECT_WUNLOCK(vm_obj);
1959 ret = i915_mutex_lock_interruptible(dev);
1968 * Since the object lock was dropped, other thread might have
1969 * faulted on the same GTT address and instantiated the
1970 * mapping for the page. Recheck.
1972 VM_OBJECT_WLOCK(vm_obj);
1973 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1975 if (vm_page_busied(m)) {
1978 VM_OBJECT_WUNLOCK(vm_obj);
1979 vm_page_busy_sleep(m, "915pee");
1984 VM_OBJECT_WUNLOCK(vm_obj);
1986 /* Now bind it into the GTT if needed */
1987 if (!obj->map_and_fenceable) {
1988 ret = i915_gem_object_unbind(obj);
1994 if (!obj->gtt_space) {
1995 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
2001 ret = i915_gem_object_set_to_gtt_domain(obj, write);
2008 if (!obj->has_global_gtt_mapping)
2009 i915_gem_gtt_bind_object(obj, obj->cache_level);
2011 ret = i915_gem_object_get_fence(obj);
2017 if (i915_gem_object_is_inactive(obj))
2018 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2020 obj->fault_mappable = true;
2021 VM_OBJECT_WLOCK(vm_obj);
2022 m = PHYS_TO_VM_PAGE(dev->agp->base + obj->gtt_offset + offset);
2023 KASSERT((m->flags & PG_FICTITIOUS) != 0,
2024 ("physical address %#jx not fictitious",
2025 (uintmax_t)(dev->agp->base + obj->gtt_offset + offset)));
2027 VM_OBJECT_WUNLOCK(vm_obj);
2032 KASSERT((m->flags & PG_FICTITIOUS) != 0,
2033 ("not fictitious %p", m));
2034 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
2036 if (vm_page_busied(m)) {
2039 VM_OBJECT_WUNLOCK(vm_obj);
2040 vm_page_busy_sleep(m, "915pbs");
2043 if (vm_page_insert(m, vm_obj, OFF_TO_IDX(offset))) {
2045 VM_OBJECT_WUNLOCK(vm_obj);
2049 m->valid = VM_PAGE_BITS_ALL;
2054 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
2060 vm_page_unlock(oldm);
2062 vm_object_pip_wakeup(vm_obj);
2063 return (VM_PAGER_OK);
2068 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
2069 CTR5(KTR_DRM, "fault_fail %p %jx %x err %d %d", gem_obj, offset, prot,
2071 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
2072 kern_yield(PRI_USER);
2075 VM_OBJECT_WLOCK(vm_obj);
2076 vm_object_pip_wakeup(vm_obj);
2077 return (VM_PAGER_ERROR);
2081 i915_gem_pager_dtor(void *handle)
2083 struct drm_gem_object *obj;
2084 struct drm_device *dev;
2090 drm_gem_free_mmap_offset(obj);
2091 i915_gem_release_mmap(to_intel_bo(obj));
2092 drm_gem_object_unreference(obj);
2096 struct cdev_pager_ops i915_gem_pager_ops = {
2097 .cdev_pg_fault = i915_gem_pager_fault,
2098 .cdev_pg_ctor = i915_gem_pager_ctor,
2099 .cdev_pg_dtor = i915_gem_pager_dtor
2103 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
2104 uint32_t handle, uint64_t *offset)
2106 struct drm_i915_private *dev_priv;
2107 struct drm_i915_gem_object *obj;
2110 dev_priv = dev->dev_private;
2112 ret = i915_mutex_lock_interruptible(dev);
2116 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
2117 if (&obj->base == NULL) {
2122 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
2127 if (obj->madv != I915_MADV_WILLNEED) {
2128 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
2133 ret = drm_gem_create_mmap_offset(&obj->base);
2137 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
2138 DRM_GEM_MAPPING_KEY;
2140 drm_gem_object_unreference(&obj->base);
2147 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *file)
2150 struct drm_i915_private *dev_priv;
2151 struct drm_i915_gem_mmap_gtt *args;
2153 dev_priv = dev->dev_private;
2156 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
2159 struct drm_i915_gem_object *
2160 i915_gem_alloc_object(struct drm_device *dev, size_t size)
2162 struct drm_i915_private *dev_priv;
2163 struct drm_i915_gem_object *obj;
2165 dev_priv = dev->dev_private;
2167 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
2169 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
2170 free(obj, DRM_I915_GEM);
2174 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2175 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2178 obj->cache_level = I915_CACHE_LLC;
2180 obj->cache_level = I915_CACHE_NONE;
2181 obj->base.driver_private = NULL;
2182 obj->fence_reg = I915_FENCE_REG_NONE;
2183 INIT_LIST_HEAD(&obj->mm_list);
2184 INIT_LIST_HEAD(&obj->gtt_list);
2185 INIT_LIST_HEAD(&obj->ring_list);
2186 INIT_LIST_HEAD(&obj->exec_list);
2187 INIT_LIST_HEAD(&obj->gpu_write_list);
2188 obj->madv = I915_MADV_WILLNEED;
2189 /* Avoid an unnecessary call to unbind on the first bind. */
2190 obj->map_and_fenceable = true;
2192 i915_gem_info_add_obj(dev_priv, size);
2198 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2201 /* If we don't have a page list set up, then we're not pinned
2202 * to GPU, and we can ignore the cache flush because it'll happen
2203 * again at bind time.
2205 if (obj->pages == NULL)
2208 /* If the GPU is snooping the contents of the CPU cache,
2209 * we do not need to manually clear the CPU cache lines. However,
2210 * the caches are only snooped when the render cache is
2211 * flushed/invalidated. As we always have to emit invalidations
2212 * and flushes when moving into and out of the RENDER domain, correct
2213 * snooping behaviour occurs naturally as the result of our domain
2216 if (obj->cache_level != I915_CACHE_NONE)
2219 CTR1(KTR_DRM, "object_clflush %p", obj);
2220 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2224 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2226 uint32_t old_write_domain;
2228 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2231 i915_gem_clflush_object(obj);
2232 intel_gtt_chipset_flush();
2233 old_write_domain = obj->base.write_domain;
2234 obj->base.write_domain = 0;
2236 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
2237 obj->base.read_domains, old_write_domain);
2241 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2244 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2246 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
2250 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2252 uint32_t old_write_domain;
2254 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2259 old_write_domain = obj->base.write_domain;
2260 obj->base.write_domain = 0;
2262 CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj,
2263 obj->base.read_domains, old_write_domain);
2267 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2269 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2270 uint32_t old_write_domain, old_read_domains;
2273 if (obj->gtt_space == NULL)
2276 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2279 ret = i915_gem_object_flush_gpu_write_domain(obj);
2283 if (obj->pending_gpu_write || write) {
2284 ret = i915_gem_object_wait_rendering(obj);
2289 i915_gem_object_flush_cpu_write_domain(obj);
2291 old_write_domain = obj->base.write_domain;
2292 old_read_domains = obj->base.read_domains;
2294 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
2295 ("In GTT write domain"));
2296 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2298 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2299 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2303 /* And bump the LRU for this access */
2304 if (i915_gem_object_is_inactive(obj))
2305 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2307 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,
2308 old_read_domains, old_write_domain);
2313 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2314 enum i915_cache_level cache_level)
2316 struct drm_device *dev;
2317 drm_i915_private_t *dev_priv;
2320 if (obj->cache_level == cache_level)
2323 if (obj->pin_count) {
2324 DRM_DEBUG("can not change the cache level of pinned objects\n");
2328 dev = obj->base.dev;
2329 dev_priv = dev->dev_private;
2330 if (obj->gtt_space) {
2331 ret = i915_gem_object_finish_gpu(obj);
2335 i915_gem_object_finish_gtt(obj);
2337 /* Before SandyBridge, you could not use tiling or fence
2338 * registers with snooped memory, so relinquish any fences
2339 * currently pointing to our region in the aperture.
2341 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2342 ret = i915_gem_object_put_fence(obj);
2347 if (obj->has_global_gtt_mapping)
2348 i915_gem_gtt_bind_object(obj, cache_level);
2349 if (obj->has_aliasing_ppgtt_mapping)
2350 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2354 if (cache_level == I915_CACHE_NONE) {
2355 u32 old_read_domains, old_write_domain;
2357 /* If we're coming from LLC cached, then we haven't
2358 * actually been tracking whether the data is in the
2359 * CPU cache or not, since we only allow one bit set
2360 * in obj->write_domain and have been skipping the clflushes.
2361 * Just set it to the CPU cache for now.
2363 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2364 ("obj %p in CPU write domain", obj));
2365 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
2366 ("obj %p in CPU read domain", obj));
2368 old_read_domains = obj->base.read_domains;
2369 old_write_domain = obj->base.write_domain;
2371 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2372 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2374 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
2375 obj, old_read_domains, old_write_domain);
2378 obj->cache_level = cache_level;
2382 static bool is_pin_display(struct drm_i915_gem_object *obj)
2384 /* There are 3 sources that pin objects:
2385 * 1. The display engine (scanouts, sprites, cursors);
2386 * 2. Reservations for execbuffer;
2389 * We can ignore reservations as we hold the struct_mutex and
2390 * are only called outside of the reservation path. The user
2391 * can only increment pin_count once, and so if after
2392 * subtracting the potential reference by the user, any pin_count
2393 * remains, it must be due to another use by the display engine.
2395 return obj->pin_count - !!obj->user_pin_count;
2399 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2400 u32 alignment, struct intel_ring_buffer *pipelined)
2402 u32 old_read_domains, old_write_domain;
2405 ret = i915_gem_object_flush_gpu_write_domain(obj);
2409 if (pipelined != obj->ring) {
2410 ret = i915_gem_object_sync(obj, pipelined);
2415 obj->pin_display = true;
2416 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2418 goto err_unpin_display;
2420 ret = i915_gem_object_pin(obj, alignment, true);
2422 goto err_unpin_display;
2424 i915_gem_object_flush_cpu_write_domain(obj);
2426 old_write_domain = obj->base.write_domain;
2427 old_read_domains = obj->base.read_domains;
2429 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
2430 ("obj %p in GTT write domain", obj));
2431 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2433 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
2434 obj, old_read_domains, obj->base.write_domain);
2438 obj->pin_display = is_pin_display(obj);
2443 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
2445 i915_gem_object_unpin(obj);
2446 obj->pin_display = is_pin_display(obj);
2450 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2454 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2457 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2458 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2463 ret = i915_gem_object_wait_rendering(obj);
2467 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2473 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2475 uint32_t old_write_domain, old_read_domains;
2478 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2481 ret = i915_gem_object_flush_gpu_write_domain(obj);
2485 if (write || obj->pending_gpu_write) {
2486 ret = i915_gem_object_wait_rendering(obj);
2491 i915_gem_object_flush_gtt_write_domain(obj);
2493 old_write_domain = obj->base.write_domain;
2494 old_read_domains = obj->base.read_domains;
2496 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2497 i915_gem_clflush_object(obj);
2498 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2501 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
2502 ("In cpu write domain"));
2505 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2506 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2509 CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj,
2510 old_read_domains, old_write_domain);
2515 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
2519 if (INTEL_INFO(dev)->gen >= 4 ||
2520 tiling_mode == I915_TILING_NONE)
2523 /* Previous chips need a power-of-two fence region when tiling */
2524 if (INTEL_INFO(dev)->gen == 3)
2525 gtt_size = 1024*1024;
2527 gtt_size = 512*1024;
2529 while (gtt_size < size)
2536 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2537 * @obj: object to check
2539 * Return the required GTT alignment for an object, taking into account
2540 * potential fence register mapping.
2543 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2548 * Minimum alignment is 4k (GTT page size), but might be greater
2549 * if a fence register is needed for the object.
2551 if (INTEL_INFO(dev)->gen >= 4 ||
2552 tiling_mode == I915_TILING_NONE)
2556 * Previous chips need to be aligned to the size of the smallest
2557 * fence register that can contain the object.
2559 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
2563 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
2567 if (tiling_mode == I915_TILING_NONE)
2571 * Minimum alignment is 4k (GTT page size) for sane hw.
2573 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
2577 * Previous hardware however needs to be aligned to a power-of-two
2578 * tile height. The simplest method for determining this is to reuse
2579 * the power-of-tile object size.
2581 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
2585 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2586 unsigned alignment, bool map_and_fenceable)
2588 struct drm_device *dev;
2589 struct drm_i915_private *dev_priv;
2590 struct drm_mm_node *free_space;
2591 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2592 bool mappable, fenceable;
2595 dev = obj->base.dev;
2596 dev_priv = dev->dev_private;
2598 if (obj->madv != I915_MADV_WILLNEED) {
2599 DRM_ERROR("Attempting to bind a purgeable object\n");
2603 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2605 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2607 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2608 obj->base.size, obj->tiling_mode);
2610 alignment = map_and_fenceable ? fence_alignment :
2612 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2613 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2617 size = map_and_fenceable ? fence_size : obj->base.size;
2619 /* If the object is bigger than the entire aperture, reject it early
2620 * before evicting everything in a vain attempt to find space.
2622 if (obj->base.size > (map_and_fenceable ?
2623 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2625 "Attempting to bind an object larger than the aperture\n");
2630 if (map_and_fenceable)
2631 free_space = drm_mm_search_free_in_range(
2632 &dev_priv->mm.gtt_space, size, alignment, 0,
2633 dev_priv->mm.gtt_mappable_end, 0);
2635 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2636 size, alignment, 0);
2637 if (free_space != NULL) {
2638 if (map_and_fenceable)
2639 obj->gtt_space = drm_mm_get_block_range_generic(
2640 free_space, size, alignment, 0, 0,
2641 dev_priv->mm.gtt_mappable_end, 1);
2643 obj->gtt_space = drm_mm_get_block_generic(free_space,
2644 size, alignment, 0, 1);
2646 if (obj->gtt_space == NULL) {
2647 ret = i915_gem_evict_something(dev, size, alignment,
2653 ret = i915_gem_object_get_pages_gtt(obj, 0);
2655 drm_mm_put_block(obj->gtt_space);
2656 obj->gtt_space = NULL;
2658 * i915_gem_object_get_pages_gtt() cannot return
2659 * ENOMEM, since we use vm_page_grab().
2664 ret = i915_gem_gtt_prepare_object(obj);
2666 i915_gem_object_put_pages_gtt(obj);
2667 drm_mm_put_block(obj->gtt_space);
2668 obj->gtt_space = NULL;
2669 if (i915_gem_evict_everything(dev, false))
2674 if (!dev_priv->mm.aliasing_ppgtt)
2675 i915_gem_gtt_bind_object(obj, obj->cache_level);
2677 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2678 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2680 KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2681 ("Object in gpu read domain"));
2682 KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2683 ("Object in gpu write domain"));
2685 obj->gtt_offset = obj->gtt_space->start;
2688 obj->gtt_space->size == fence_size &&
2689 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2692 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2693 obj->map_and_fenceable = mappable && fenceable;
2695 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
2696 obj->base.size, map_and_fenceable);
2701 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2702 struct intel_ring_buffer *to)
2704 struct intel_ring_buffer *from = obj->ring;
2708 if (from == NULL || to == from)
2711 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2712 return i915_gem_object_wait_rendering(obj);
2714 idx = intel_ring_sync_index(from, to);
2716 seqno = obj->last_rendering_seqno;
2717 if (seqno <= from->sync_seqno[idx])
2720 if (seqno == from->outstanding_lazy_request) {
2721 struct drm_i915_gem_request *request;
2723 request = malloc(sizeof(*request), DRM_I915_GEM,
2725 ret = i915_add_request(from, NULL, request);
2727 free(request, DRM_I915_GEM);
2730 seqno = request->seqno;
2734 ret = to->sync_to(to, from, seqno);
2736 from->sync_seqno[idx] = seqno;
2741 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2743 u32 old_write_domain, old_read_domains;
2745 /* Act a barrier for all accesses through the GTT */
2748 /* Force a pagefault for domain tracking on next user access */
2749 i915_gem_release_mmap(obj);
2751 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2754 old_read_domains = obj->base.read_domains;
2755 old_write_domain = obj->base.write_domain;
2757 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2758 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2760 CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
2761 obj, old_read_domains, old_write_domain);
2765 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2767 drm_i915_private_t *dev_priv;
2770 dev_priv = obj->base.dev->dev_private;
2772 if (obj->gtt_space == NULL)
2774 if (obj->pin_count != 0) {
2775 DRM_ERROR("Attempting to unbind pinned buffer\n");
2779 ret = i915_gem_object_finish_gpu(obj);
2780 if (ret == -ERESTARTSYS || ret == -EINTR)
2783 i915_gem_object_finish_gtt(obj);
2786 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2787 if (ret == -ERESTARTSYS || ret == -EINTR)
2790 i915_gem_clflush_object(obj);
2791 obj->base.read_domains = obj->base.write_domain =
2792 I915_GEM_DOMAIN_CPU;
2795 ret = i915_gem_object_put_fence(obj);
2799 if (obj->has_global_gtt_mapping)
2800 i915_gem_gtt_unbind_object(obj);
2801 if (obj->has_aliasing_ppgtt_mapping) {
2802 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2803 obj->has_aliasing_ppgtt_mapping = 0;
2805 i915_gem_gtt_finish_object(obj);
2807 i915_gem_object_put_pages_gtt(obj);
2809 list_del_init(&obj->gtt_list);
2810 list_del_init(&obj->mm_list);
2811 obj->map_and_fenceable = true;
2813 drm_mm_put_block(obj->gtt_space);
2814 obj->gtt_space = NULL;
2815 obj->gtt_offset = 0;
2817 if (i915_gem_object_is_purgeable(obj))
2818 i915_gem_object_truncate(obj);
2819 CTR1(KTR_DRM, "object_unbind %p", obj);
2825 i915_gem_object_put_pages_range_locked(struct drm_i915_gem_object *obj,
2826 vm_pindex_t si, vm_pindex_t ei)
2832 vm_obj = obj->base.vm_obj;
2833 VM_OBJECT_ASSERT_LOCKED(vm_obj);
2834 for (i = si, m = vm_page_lookup(vm_obj, i); i < ei;
2835 m = vm_page_next(m), i++) {
2836 KASSERT(m->pindex == i, ("pindex %jx %jx",
2837 (uintmax_t)m->pindex, (uintmax_t)i));
2839 vm_page_unwire(m, PQ_INACTIVE);
2840 if (m->wire_count == 0)
2841 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2847 i915_gem_object_put_pages_range(struct drm_i915_gem_object *obj,
2848 off_t start, off_t end)
2852 vm_obj = obj->base.vm_obj;
2853 VM_OBJECT_WLOCK(vm_obj);
2854 i915_gem_object_put_pages_range_locked(obj,
2855 OFF_TO_IDX(trunc_page(start)), OFF_TO_IDX(round_page(end)));
2856 VM_OBJECT_WUNLOCK(vm_obj);
2860 i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
2861 off_t start, off_t end)
2865 vm_pindex_t si, ei, i;
2866 bool need_swizzle, fresh;
2868 need_swizzle = i915_gem_object_needs_bit17_swizzle(obj) != 0;
2869 vm_obj = obj->base.vm_obj;
2870 si = OFF_TO_IDX(trunc_page(start));
2871 ei = OFF_TO_IDX(round_page(end));
2872 VM_OBJECT_WLOCK(vm_obj);
2873 for (i = si; i < ei; i++) {
2874 m = i915_gem_wire_page(vm_obj, i, &fresh);
2877 if (need_swizzle && fresh)
2878 i915_gem_object_do_bit_17_swizzle_page(obj, m);
2880 VM_OBJECT_WUNLOCK(vm_obj);
2883 i915_gem_object_put_pages_range_locked(obj, si, i);
2884 VM_OBJECT_WUNLOCK(vm_obj);
2889 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2892 struct drm_device *dev;
2895 vm_pindex_t i, page_count;
2898 dev = obj->base.dev;
2899 KASSERT(obj->pages == NULL, ("Obj already has pages"));
2900 page_count = OFF_TO_IDX(obj->base.size);
2901 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2903 res = i915_gem_object_get_pages_range(obj, 0, obj->base.size);
2905 free(obj->pages, DRM_I915_GEM);
2909 vm_obj = obj->base.vm_obj;
2910 VM_OBJECT_WLOCK(vm_obj);
2911 for (i = 0, m = vm_page_lookup(vm_obj, 0); i < page_count;
2912 i++, m = vm_page_next(m)) {
2913 KASSERT(m->pindex == i, ("pindex %jx %jx",
2914 (uintmax_t)m->pindex, (uintmax_t)i));
2917 VM_OBJECT_WUNLOCK(vm_obj);
2921 #define GEM_PARANOID_CHECK_GTT 0
2922 #if GEM_PARANOID_CHECK_GTT
2924 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2927 struct drm_i915_private *dev_priv;
2929 unsigned long start, end;
2933 dev_priv = dev->dev_private;
2934 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2935 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2936 for (i = start; i < end; i++) {
2937 pa = intel_gtt_read_pte_paddr(i);
2938 for (j = 0; j < page_count; j++) {
2939 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2940 panic("Page %p in GTT pte index %d pte %x",
2941 ma[i], i, intel_gtt_read_pte(i));
2949 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2954 KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
2956 if (obj->tiling_mode != I915_TILING_NONE)
2957 i915_gem_object_save_bit_17_swizzle(obj);
2958 if (obj->madv == I915_MADV_DONTNEED)
2960 page_count = obj->base.size / PAGE_SIZE;
2961 VM_OBJECT_WLOCK(obj->base.vm_obj);
2962 #if GEM_PARANOID_CHECK_GTT
2963 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2965 for (i = 0; i < page_count; i++) {
2969 if (obj->madv == I915_MADV_WILLNEED)
2970 vm_page_reference(m);
2972 vm_page_unwire(obj->pages[i], PQ_ACTIVE);
2974 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2976 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
2978 free(obj->pages, DRM_I915_GEM);
2983 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2989 if (!obj->fault_mappable)
2992 CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset,
2993 OFF_TO_IDX(obj->base.size));
2994 devobj = cdev_pager_lookup(obj);
2995 if (devobj != NULL) {
2996 page_count = OFF_TO_IDX(obj->base.size);
2998 VM_OBJECT_WLOCK(devobj);
3000 for (i = 0; i < page_count; i++) {
3001 m = vm_page_lookup(devobj, i);
3004 if (vm_page_sleep_if_busy(m, "915unm"))
3006 cdev_pager_free_page(devobj, m);
3008 VM_OBJECT_WUNLOCK(devobj);
3009 vm_object_deallocate(devobj);
3012 obj->fault_mappable = false;
3016 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
3020 KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
3021 ("In GPU write domain"));
3023 CTR5(KTR_DRM, "object_wait_rendering %p %s %x %d %d", obj,
3024 obj->ring != NULL ? obj->ring->name : "none", obj->gtt_offset,
3025 obj->active, obj->last_rendering_seqno);
3027 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
3030 i915_gem_retire_requests_ring(obj->ring);
3036 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
3037 struct intel_ring_buffer *ring, uint32_t seqno)
3039 struct drm_device *dev = obj->base.dev;
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 struct drm_i915_fence_reg *reg;
3044 KASSERT(ring != NULL, ("NULL ring"));
3046 /* Add a reference if we're newly entering the active list. */
3048 drm_gem_object_reference(&obj->base);
3052 /* Move from whatever list we were on to the tail of execution. */
3053 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
3054 list_move_tail(&obj->ring_list, &ring->active_list);
3056 obj->last_rendering_seqno = seqno;
3057 if (obj->fenced_gpu_access) {
3058 obj->last_fenced_seqno = seqno;
3060 /* Bump MRU to take account of the delayed flush */
3061 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3062 reg = &dev_priv->fence_regs[obj->fence_reg];
3063 list_move_tail(®->lru_list,
3064 &dev_priv->mm.fence_list);
3070 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
3072 list_del_init(&obj->ring_list);
3073 obj->last_rendering_seqno = 0;
3074 obj->last_fenced_seqno = 0;
3078 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
3080 struct drm_device *dev = obj->base.dev;
3081 drm_i915_private_t *dev_priv = dev->dev_private;
3083 KASSERT(obj->active, ("Object not active"));
3084 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
3086 i915_gem_object_move_off_active(obj);
3090 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
3092 struct drm_device *dev = obj->base.dev;
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3095 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3097 KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
3098 KASSERT(obj->active, ("Object not active"));
3101 i915_gem_object_move_off_active(obj);
3102 obj->fenced_gpu_access = false;
3105 obj->pending_gpu_write = false;
3106 drm_gem_object_unreference(&obj->base);
3111 WARN_ON(i915_verify_lists(dev));
3116 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
3120 vm_obj = obj->base.vm_obj;
3121 VM_OBJECT_WLOCK(vm_obj);
3122 vm_object_page_remove(vm_obj, 0, 0, false);
3123 VM_OBJECT_WUNLOCK(vm_obj);
3124 drm_gem_free_mmap_offset(&obj->base);
3125 obj->madv = I915_MADV_PURGED_INTERNAL;
3129 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
3132 return (obj->madv == I915_MADV_DONTNEED);
3136 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
3137 uint32_t flush_domains)
3139 struct drm_i915_gem_object *obj, *next;
3140 uint32_t old_write_domain;
3142 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
3144 if (obj->base.write_domain & flush_domains) {
3145 old_write_domain = obj->base.write_domain;
3146 obj->base.write_domain = 0;
3147 list_del_init(&obj->gpu_write_list);
3148 i915_gem_object_move_to_active(obj, ring,
3149 i915_gem_next_request_seqno(ring));
3151 CTR3(KTR_DRM, "object_change_domain process_flush %p %x %x",
3152 obj, obj->base.read_domains, old_write_domain);
3158 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3160 drm_i915_private_t *dev_priv;
3162 dev_priv = obj->base.dev->dev_private;
3163 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3164 obj->tiling_mode != I915_TILING_NONE);
3168 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, bool *fresh)
3173 VM_OBJECT_ASSERT_WLOCKED(object);
3174 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL);
3175 if (m->valid != VM_PAGE_BITS_ALL) {
3176 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
3177 rv = vm_pager_get_pages(object, &m, 1, 0);
3178 if (rv != VM_PAGER_OK) {
3188 m->valid = VM_PAGE_BITS_ALL;
3193 } else if (fresh != NULL) {
3200 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
3205 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
3206 uint32_t flush_domains)
3210 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
3213 CTR3(KTR_DRM, "ring_flush %s %x %x", ring->name, invalidate_domains,
3215 ret = ring->flush(ring, invalidate_domains, flush_domains);
3219 if (flush_domains & I915_GEM_GPU_DOMAINS)
3220 i915_gem_process_flushing_list(ring, flush_domains);
3225 i915_ring_idle(struct intel_ring_buffer *ring)
3229 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
3232 if (!list_empty(&ring->gpu_write_list)) {
3233 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
3234 I915_GEM_GPU_DOMAINS);
3239 return (i915_wait_request(ring, i915_gem_next_request_seqno(ring)));
3243 i915_gpu_idle(struct drm_device *dev)
3245 drm_i915_private_t *dev_priv = dev->dev_private;
3246 struct intel_ring_buffer *ring;
3249 /* Flush everything onto the inactive list. */
3250 for_each_ring(ring, dev_priv, i) {
3251 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
3255 ret = i915_ring_idle(ring);
3259 /* Is the device fubar? */
3260 if (!list_empty(&ring->gpu_write_list))
3268 i915_gem_check_wedge(struct drm_i915_private *dev_priv)
3270 DRM_LOCK_ASSERT(dev_priv->dev);
3272 if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
3273 bool recovery_complete;
3274 /* Give the error handler a chance to run. */
3275 mtx_lock(&dev_priv->error_completion_lock);
3276 recovery_complete = (&dev_priv->error_completion) > 0;
3277 mtx_unlock(&dev_priv->error_completion_lock);
3278 return (recovery_complete ? -EIO : -EAGAIN);
3285 * Compare seqno against outstanding lazy request. Emit a request if they are
3289 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
3293 DRM_LOCK_ASSERT(ring->dev);
3295 if (seqno == ring->outstanding_lazy_request) {
3296 struct drm_i915_gem_request *request;
3298 request = malloc(sizeof(*request), DRM_I915_GEM,
3301 ret = i915_add_request(ring, NULL, request);
3303 free(request, DRM_I915_GEM);
3307 MPASS(seqno == request->seqno);
3312 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
3315 drm_i915_private_t *dev_priv = ring->dev->dev_private;
3318 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
3321 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
3323 mtx_lock(&dev_priv->irq_lock);
3324 if (!ring->irq_get(ring)) {
3325 mtx_unlock(&dev_priv->irq_lock);
3329 flags = interruptible ? PCATCH : 0;
3330 while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
3331 && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
3333 ret = -msleep(ring, &dev_priv->irq_lock, flags, "915gwr", 0);
3334 if (ret == -ERESTART)
3337 ring->irq_put(ring);
3338 mtx_unlock(&dev_priv->irq_lock);
3340 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno, ret);
3346 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno)
3348 drm_i915_private_t *dev_priv;
3351 KASSERT(seqno != 0, ("Zero seqno"));
3353 dev_priv = ring->dev->dev_private;
3356 ret = i915_gem_check_wedge(dev_priv);
3360 ret = i915_gem_check_olr(ring, seqno);
3364 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible);
3365 if (atomic_load_acq_int(&dev_priv->mm.wedged))
3372 i915_gem_get_seqno(struct drm_device *dev)
3374 drm_i915_private_t *dev_priv = dev->dev_private;
3375 u32 seqno = dev_priv->next_seqno;
3377 /* reserve 0 for non-seqno */
3378 if (++dev_priv->next_seqno == 0)
3379 dev_priv->next_seqno = 1;
3385 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
3387 if (ring->outstanding_lazy_request == 0)
3388 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
3390 return ring->outstanding_lazy_request;
3394 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
3395 struct drm_i915_gem_request *request)
3397 drm_i915_private_t *dev_priv;
3398 struct drm_i915_file_private *file_priv;
3400 u32 request_ring_position;
3404 KASSERT(request != NULL, ("NULL request in add"));
3405 DRM_LOCK_ASSERT(ring->dev);
3406 dev_priv = ring->dev->dev_private;
3408 seqno = i915_gem_next_request_seqno(ring);
3409 request_ring_position = intel_ring_get_tail(ring);
3411 ret = ring->add_request(ring, &seqno);
3415 CTR2(KTR_DRM, "request_add %s %d", ring->name, seqno);
3417 request->seqno = seqno;
3418 request->ring = ring;
3419 request->tail = request_ring_position;
3420 request->emitted_jiffies = ticks;
3421 was_empty = list_empty(&ring->request_list);
3422 list_add_tail(&request->list, &ring->request_list);
3425 file_priv = file->driver_priv;
3427 mtx_lock(&file_priv->mm.lck);
3428 request->file_priv = file_priv;
3429 list_add_tail(&request->client_list,
3430 &file_priv->mm.request_list);
3431 mtx_unlock(&file_priv->mm.lck);
3434 ring->outstanding_lazy_request = 0;
3436 if (!dev_priv->mm.suspended) {
3437 if (i915_enable_hangcheck) {
3438 callout_schedule(&dev_priv->hangcheck_timer,
3439 DRM_I915_HANGCHECK_PERIOD);
3442 taskqueue_enqueue_timeout(dev_priv->tq,
3443 &dev_priv->mm.retire_task, hz);
3449 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
3451 struct drm_i915_file_private *file_priv = request->file_priv;
3456 DRM_LOCK_ASSERT(request->ring->dev);
3458 mtx_lock(&file_priv->mm.lck);
3459 if (request->file_priv != NULL) {
3460 list_del(&request->client_list);
3461 request->file_priv = NULL;
3463 mtx_unlock(&file_priv->mm.lck);
3467 i915_gem_release(struct drm_device *dev, struct drm_file *file)
3469 struct drm_i915_file_private *file_priv;
3470 struct drm_i915_gem_request *request;
3472 file_priv = file->driver_priv;
3474 /* Clean up our request list when the client is going away, so that
3475 * later retire_requests won't dereference our soon-to-be-gone
3478 mtx_lock(&file_priv->mm.lck);
3479 while (!list_empty(&file_priv->mm.request_list)) {
3480 request = list_first_entry(&file_priv->mm.request_list,
3481 struct drm_i915_gem_request,
3483 list_del(&request->client_list);
3484 request->file_priv = NULL;
3486 mtx_unlock(&file_priv->mm.lck);
3490 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
3491 struct intel_ring_buffer *ring)
3494 if (ring->dev != NULL)
3495 DRM_LOCK_ASSERT(ring->dev);
3497 while (!list_empty(&ring->request_list)) {
3498 struct drm_i915_gem_request *request;
3500 request = list_first_entry(&ring->request_list,
3501 struct drm_i915_gem_request, list);
3503 list_del(&request->list);
3504 i915_gem_request_remove_from_client(request);
3505 free(request, DRM_I915_GEM);
3508 while (!list_empty(&ring->active_list)) {
3509 struct drm_i915_gem_object *obj;
3511 obj = list_first_entry(&ring->active_list,
3512 struct drm_i915_gem_object, ring_list);
3514 obj->base.write_domain = 0;
3515 list_del_init(&obj->gpu_write_list);
3516 i915_gem_object_move_to_inactive(obj);
3521 i915_gem_reset_fences(struct drm_device *dev)
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3526 for (i = 0; i < dev_priv->num_fence_regs; i++) {
3527 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
3529 i915_gem_write_fence(dev, i, NULL);
3532 i915_gem_object_fence_lost(reg->obj);
3536 INIT_LIST_HEAD(®->lru_list);
3539 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3543 i915_gem_reset(struct drm_device *dev)
3545 struct drm_i915_private *dev_priv = dev->dev_private;
3546 struct drm_i915_gem_object *obj;
3547 struct intel_ring_buffer *ring;
3550 for_each_ring(ring, dev_priv, i)
3551 i915_gem_reset_ring_lists(dev_priv, ring);
3553 /* Remove anything from the flushing lists. The GPU cache is likely
3554 * to be lost on reset along with the data, so simply move the
3555 * lost bo to the inactive list.
3557 while (!list_empty(&dev_priv->mm.flushing_list)) {
3558 obj = list_first_entry(&dev_priv->mm.flushing_list,
3559 struct drm_i915_gem_object,
3562 obj->base.write_domain = 0;
3563 list_del_init(&obj->gpu_write_list);
3564 i915_gem_object_move_to_inactive(obj);
3567 /* Move everything out of the GPU domains to ensure we do any
3568 * necessary invalidation upon reuse.
3570 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
3571 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3574 /* The fence registers are invalidated so clear them out */
3575 i915_gem_reset_fences(dev);
3579 * This function clears the request list as sequence numbers are passed.
3582 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
3587 if (list_empty(&ring->request_list))
3590 seqno = ring->get_seqno(ring);
3591 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
3593 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
3594 if (seqno >= ring->sync_seqno[i])
3595 ring->sync_seqno[i] = 0;
3597 while (!list_empty(&ring->request_list)) {
3598 struct drm_i915_gem_request *request;
3600 request = list_first_entry(&ring->request_list,
3601 struct drm_i915_gem_request,
3604 if (!i915_seqno_passed(seqno, request->seqno))
3607 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
3609 ring->last_retired_head = request->tail;
3611 list_del(&request->list);
3612 i915_gem_request_remove_from_client(request);
3613 free(request, DRM_I915_GEM);
3616 /* Move any buffers on the active list that are no longer referenced
3617 * by the ringbuffer to the flushing/inactive lists as appropriate.
3619 while (!list_empty(&ring->active_list)) {
3620 struct drm_i915_gem_object *obj;
3622 obj = list_first_entry(&ring->active_list,
3623 struct drm_i915_gem_object,
3626 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
3629 if (obj->base.write_domain != 0)
3630 i915_gem_object_move_to_flushing(obj);
3632 i915_gem_object_move_to_inactive(obj);
3635 if (ring->trace_irq_seqno &&
3636 i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
3637 struct drm_i915_private *dev_priv = ring->dev->dev_private;
3638 mtx_lock(&dev_priv->irq_lock);
3639 ring->irq_put(ring);
3640 mtx_unlock(&dev_priv->irq_lock);
3641 ring->trace_irq_seqno = 0;
3646 i915_gem_retire_requests(struct drm_device *dev)
3648 drm_i915_private_t *dev_priv = dev->dev_private;
3649 struct intel_ring_buffer *ring;
3652 for_each_ring(ring, dev_priv, i)
3653 i915_gem_retire_requests_ring(ring);
3656 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
3657 struct drm_i915_gem_object *obj)
3659 drm_i915_private_t *dev_priv = dev->dev_private;
3663 u32 size = obj->gtt_space->size;
3665 val = (uint64_t)((obj->gtt_offset + size - 4096) &
3667 val |= obj->gtt_offset & 0xfffff000;
3668 val |= (uint64_t)((obj->stride / 128) - 1) <<
3669 SANDYBRIDGE_FENCE_PITCH_SHIFT;
3671 if (obj->tiling_mode == I915_TILING_Y)
3672 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3673 val |= I965_FENCE_REG_VALID;
3677 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
3678 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
3681 static void i965_write_fence_reg(struct drm_device *dev, int reg,
3682 struct drm_i915_gem_object *obj)
3684 drm_i915_private_t *dev_priv = dev->dev_private;
3688 u32 size = obj->gtt_space->size;
3690 val = (uint64_t)((obj->gtt_offset + size - 4096) &
3692 val |= obj->gtt_offset & 0xfffff000;
3693 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
3694 if (obj->tiling_mode == I915_TILING_Y)
3695 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3696 val |= I965_FENCE_REG_VALID;
3700 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
3701 POSTING_READ(FENCE_REG_965_0 + reg * 8);
3704 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3705 struct drm_i915_gem_object *obj)
3707 drm_i915_private_t *dev_priv = dev->dev_private;
3711 u32 size = obj->gtt_space->size;
3715 if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
3716 (size & -size) != size ||
3717 (obj->gtt_offset & (size - 1)))
3719 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3720 obj->gtt_offset, obj->map_and_fenceable, size);
3722 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3727 /* Note: pitch better be a power of two tile widths */
3728 pitch_val = obj->stride / tile_width;
3729 pitch_val = ffs(pitch_val) - 1;
3731 val = obj->gtt_offset;
3732 if (obj->tiling_mode == I915_TILING_Y)
3733 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3734 val |= I915_FENCE_SIZE_BITS(size);
3735 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3736 val |= I830_FENCE_REG_VALID;
3741 reg = FENCE_REG_830_0 + reg * 4;
3743 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3745 I915_WRITE(reg, val);
3749 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3750 struct drm_i915_gem_object *obj)
3752 drm_i915_private_t *dev_priv = dev->dev_private;
3756 u32 size = obj->gtt_space->size;
3759 if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3760 (size & -size) != size ||
3761 (obj->gtt_offset & (size - 1)))
3763 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3764 obj->gtt_offset, size);
3766 pitch_val = obj->stride / 128;
3767 pitch_val = ffs(pitch_val) - 1;
3769 val = obj->gtt_offset;
3770 if (obj->tiling_mode == I915_TILING_Y)
3771 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3772 val |= I830_FENCE_SIZE_BITS(size);
3773 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3774 val |= I830_FENCE_REG_VALID;
3778 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3779 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3782 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3783 struct drm_i915_gem_object *obj)
3785 switch (INTEL_INFO(dev)->gen) {
3787 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
3789 case 4: i965_write_fence_reg(dev, reg, obj); break;
3790 case 3: i915_write_fence_reg(dev, reg, obj); break;
3791 case 2: i830_write_fence_reg(dev, reg, obj); break;
3796 static inline int fence_number(struct drm_i915_private *dev_priv,
3797 struct drm_i915_fence_reg *fence)
3799 return fence - dev_priv->fence_regs;
3802 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3803 struct drm_i915_fence_reg *fence,
3806 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3807 int reg = fence_number(dev_priv, fence);
3809 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3812 obj->fence_reg = reg;
3814 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3816 obj->fence_reg = I915_FENCE_REG_NONE;
3818 list_del_init(&fence->lru_list);
3823 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
3827 if (obj->fenced_gpu_access) {
3828 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3829 ret = i915_gem_flush_ring(obj->ring,
3830 0, obj->base.write_domain);
3835 obj->fenced_gpu_access = false;
3838 if (obj->last_fenced_seqno) {
3839 ret = i915_wait_request(obj->ring,
3840 obj->last_fenced_seqno);
3844 obj->last_fenced_seqno = 0;
3847 /* Ensure that all CPU reads are completed before installing a fence
3848 * and all writes before removing the fence.
3850 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3857 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3859 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3862 ret = i915_gem_object_flush_fence(obj);
3866 if (obj->fence_reg == I915_FENCE_REG_NONE)
3869 i915_gem_object_update_fence(obj,
3870 &dev_priv->fence_regs[obj->fence_reg],
3872 i915_gem_object_fence_lost(obj);
3877 static struct drm_i915_fence_reg *
3878 i915_find_fence_reg(struct drm_device *dev)
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 struct drm_i915_fence_reg *reg, *avail;
3884 /* First try to find a free reg */
3886 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3887 reg = &dev_priv->fence_regs[i];
3891 if (!reg->pin_count)
3898 /* None available, try to steal one or wait for a user to finish */
3899 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3910 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3912 struct drm_device *dev = obj->base.dev;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 bool enable = obj->tiling_mode != I915_TILING_NONE;
3915 struct drm_i915_fence_reg *reg;
3918 /* Have we updated the tiling parameters upon the object and so
3919 * will need to serialise the write to the associated fence register?
3921 if (obj->fence_dirty) {
3922 ret = i915_gem_object_flush_fence(obj);
3929 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3930 reg = &dev_priv->fence_regs[obj->fence_reg];
3931 if (!obj->fence_dirty) {
3932 list_move_tail(®->lru_list,
3933 &dev_priv->mm.fence_list);
3936 } else if (enable) {
3937 reg = i915_find_fence_reg(dev);
3942 struct drm_i915_gem_object *old = reg->obj;
3944 ret = i915_gem_object_flush_fence(old);
3948 i915_gem_object_fence_lost(old);
3953 i915_gem_object_update_fence(obj, reg, enable);
3954 obj->fence_dirty = false;
3960 i915_gem_init_object(struct drm_gem_object *obj)
3963 printf("i915_gem_init_object called\n");
3968 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3971 return !obj->active;
3975 i915_gem_retire_task_handler(void *arg, int pending)
3977 drm_i915_private_t *dev_priv;
3978 struct drm_device *dev;
3979 struct intel_ring_buffer *ring;
3984 dev = dev_priv->dev;
3986 /* Come back later if the device is busy... */
3987 if (!sx_try_xlock(&dev->dev_struct_lock)) {
3988 taskqueue_enqueue_timeout(dev_priv->tq,
3989 &dev_priv->mm.retire_task, hz);
3993 CTR0(KTR_DRM, "retire_task");
3995 i915_gem_retire_requests(dev);
3997 /* Send a periodic flush down the ring so we don't hold onto GEM
3998 * objects indefinitely.
4001 for_each_ring(ring, dev_priv, i) {
4002 struct intel_ring_buffer *ring = &dev_priv->rings[i];
4004 if (!list_empty(&ring->gpu_write_list)) {
4005 struct drm_i915_gem_request *request;
4008 ret = i915_gem_flush_ring(ring,
4009 0, I915_GEM_GPU_DOMAINS);
4010 request = malloc(sizeof(*request), DRM_I915_GEM,
4012 if (ret || request == NULL ||
4013 i915_add_request(ring, NULL, request))
4014 free(request, DRM_I915_GEM);
4017 idle &= list_empty(&ring->request_list);
4020 if (!dev_priv->mm.suspended && !idle)
4021 taskqueue_enqueue_timeout(dev_priv->tq,
4022 &dev_priv->mm.retire_task, hz);
4028 i915_gem_lastclose(struct drm_device *dev)
4032 if (drm_core_check_feature(dev, DRIVER_MODESET))
4035 ret = i915_gem_idle(dev);
4037 DRM_ERROR("failed to idle hardware: %d\n", ret);
4041 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
4043 drm_i915_private_t *dev_priv;
4044 struct drm_i915_gem_phys_object *phys_obj;
4047 dev_priv = dev->dev_private;
4048 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
4051 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
4056 phys_obj->handle = drm_pci_alloc(dev, size, align, BUS_SPACE_MAXADDR);
4057 if (phys_obj->handle == NULL) {
4061 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4062 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4064 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4069 free(phys_obj, DRM_I915_GEM);
4074 i915_gem_free_phys_object(struct drm_device *dev, int id)
4076 drm_i915_private_t *dev_priv;
4077 struct drm_i915_gem_phys_object *phys_obj;
4079 dev_priv = dev->dev_private;
4080 if (dev_priv->mm.phys_objs[id - 1] == NULL)
4083 phys_obj = dev_priv->mm.phys_objs[id - 1];
4084 if (phys_obj->cur_obj != NULL)
4085 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4087 drm_pci_free(dev, phys_obj->handle);
4088 free(phys_obj, DRM_I915_GEM);
4089 dev_priv->mm.phys_objs[id - 1] = NULL;
4093 i915_gem_free_all_phys_object(struct drm_device *dev)
4097 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4098 i915_gem_free_phys_object(dev, i);
4102 i915_gem_detach_phys_object(struct drm_device *dev,
4103 struct drm_i915_gem_object *obj)
4110 if (obj->phys_obj == NULL)
4112 vaddr = obj->phys_obj->handle->vaddr;
4114 page_count = obj->base.size / PAGE_SIZE;
4115 VM_OBJECT_WLOCK(obj->base.vm_obj);
4116 for (i = 0; i < page_count; i++) {
4117 m = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4121 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4122 sf = sf_buf_alloc(m, 0);
4124 dst = (char *)sf_buf_kva(sf);
4125 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
4128 drm_clflush_pages(&m, 1);
4130 VM_OBJECT_WLOCK(obj->base.vm_obj);
4131 vm_page_reference(m);
4134 vm_page_unwire(m, PQ_INACTIVE);
4136 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4138 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4139 intel_gtt_chipset_flush();
4141 obj->phys_obj->cur_obj = NULL;
4142 obj->phys_obj = NULL;
4146 i915_gem_attach_phys_object(struct drm_device *dev,
4147 struct drm_i915_gem_object *obj, int id, int align)
4149 drm_i915_private_t *dev_priv;
4153 int i, page_count, ret;
4155 if (id > I915_MAX_PHYS_OBJECT)
4158 if (obj->phys_obj != NULL) {
4159 if (obj->phys_obj->id == id)
4161 i915_gem_detach_phys_object(dev, obj);
4164 dev_priv = dev->dev_private;
4165 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
4166 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
4168 DRM_ERROR("failed to init phys object %d size: %zu\n",
4169 id, obj->base.size);
4174 /* bind to the object */
4175 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4176 obj->phys_obj->cur_obj = obj;
4178 page_count = obj->base.size / PAGE_SIZE;
4180 VM_OBJECT_WLOCK(obj->base.vm_obj);
4182 for (i = 0; i < page_count; i++) {
4183 m = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4188 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4189 sf = sf_buf_alloc(m, 0);
4190 src = (char *)sf_buf_kva(sf);
4191 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
4192 memcpy(dst, src, PAGE_SIZE);
4195 VM_OBJECT_WLOCK(obj->base.vm_obj);
4197 vm_page_reference(m);
4199 vm_page_unwire(m, PQ_INACTIVE);
4201 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4203 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4209 i915_gpu_is_active(struct drm_device *dev)
4211 drm_i915_private_t *dev_priv;
4213 dev_priv = dev->dev_private;
4214 return (!list_empty(&dev_priv->mm.flushing_list) ||
4215 !list_empty(&dev_priv->mm.active_list));
4219 i915_gem_lowmem(void *arg)
4221 struct drm_device *dev;
4222 struct drm_i915_private *dev_priv;
4223 struct drm_i915_gem_object *obj, *next;
4224 int cnt, cnt_fail, cnt_total;
4227 dev_priv = dev->dev_private;
4229 if (!sx_try_xlock(&dev->dev_struct_lock))
4232 CTR0(KTR_DRM, "gem_lowmem");
4235 /* first scan for clean buffers */
4236 i915_gem_retire_requests(dev);
4238 cnt_total = cnt_fail = cnt = 0;
4240 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4242 if (i915_gem_object_is_purgeable(obj)) {
4243 if (i915_gem_object_unbind(obj) != 0)
4249 /* second pass, evict/count anything still on the inactive list */
4250 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
4252 if (i915_gem_object_unbind(obj) == 0)
4258 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
4260 * We are desperate for pages, so as a last resort, wait
4261 * for the GPU to finish and discard whatever we can.
4262 * This has a dramatic impact to reduce the number of
4263 * OOM-killer events whilst running the GPU aggressively.
4265 if (i915_gpu_idle(dev) == 0)
4272 i915_gem_unload(struct drm_device *dev)
4274 struct drm_i915_private *dev_priv;
4276 dev_priv = dev->dev_private;
4277 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);