2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 #include <sys/cdefs.h>
55 __FBSDID("$FreeBSD$");
57 #include <dev/drm2/drmP.h>
58 #include <dev/drm2/i915/i915_drm.h>
59 #include <dev/drm2/i915/i915_drv.h>
60 #include <dev/drm2/i915/intel_drv.h>
62 #include <sys/resourcevar.h>
63 #include <sys/sched.h>
64 #include <sys/sf_buf.h>
67 #include <vm/vm_pageout.h>
69 #include <machine/md_var.h>
71 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
72 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
73 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
75 bool map_and_fenceable,
77 static int i915_gem_phys_pwrite(struct drm_device *dev,
78 struct drm_i915_gem_object *obj,
79 struct drm_i915_gem_pwrite *args,
80 struct drm_file *file);
82 static void i915_gem_write_fence(struct drm_device *dev, int reg,
83 struct drm_i915_gem_object *obj);
84 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
85 struct drm_i915_fence_reg *fence,
88 static void i915_gem_inactive_shrink(void *);
89 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
90 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
91 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
93 static int i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
94 off_t start, off_t end);
96 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex,
99 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
100 long i915_gem_wired_pages_cnt;
102 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
104 if (obj->tiling_mode)
105 i915_gem_release_mmap(obj);
107 /* As we do not have an associated fence register, we will force
108 * a tiling change if we ever need to acquire one.
110 obj->fence_dirty = false;
111 obj->fence_reg = I915_FENCE_REG_NONE;
114 /* some bookkeeping */
115 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
118 dev_priv->mm.object_count++;
119 dev_priv->mm.object_memory += size;
122 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
125 dev_priv->mm.object_count--;
126 dev_priv->mm.object_memory -= size;
130 i915_gem_wait_for_error(struct drm_device *dev)
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct completion *x = &dev_priv->error_completion;
136 if (!atomic_read(&dev_priv->mm.wedged))
140 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
141 * userspace. If it takes that long something really bad is going on and
142 * we should simply try to bail out and fail as gracefully as possible.
144 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
146 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
148 } else if (ret < 0) {
152 if (atomic_read(&dev_priv->mm.wedged)) {
153 /* GPU is hung, bump the completion count to account for
154 * the token we just consumed so that we never hit zero and
155 * end up waiting upon a subsequent completion event that
160 mtx_unlock(&x->lock);
165 int i915_mutex_lock_interruptible(struct drm_device *dev)
169 ret = i915_gem_wait_for_error(dev);
174 * interruptible shall it be. might indeed be if dev_lock is
177 ret = sx_xlock_sig(&dev->dev_struct_lock);
181 WARN_ON(i915_verify_lists(dev));
186 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
188 return obj->gtt_space && !obj->active;
192 i915_gem_init_ioctl(struct drm_device *dev, void *data,
193 struct drm_file *file)
195 struct drm_i915_gem_init *args = data;
197 if (drm_core_check_feature(dev, DRIVER_MODESET))
200 if (args->gtt_start >= args->gtt_end ||
201 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
204 /* GEM with user mode setting was never supported on ilk and later. */
205 if (INTEL_INFO(dev)->gen >= 5)
209 * XXXKIB. The second-time initialization should be guarded
213 i915_gem_init_global_gtt(dev, args->gtt_start,
214 args->gtt_end, args->gtt_end);
221 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
222 struct drm_file *file)
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 struct drm_i915_gem_get_aperture *args = data;
226 struct drm_i915_gem_object *obj;
231 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
233 pinned += obj->gtt_space->size;
236 args->aper_size = dev_priv->mm.gtt_total;
237 args->aper_available_size = args->aper_size - pinned;
243 i915_gem_create(struct drm_file *file,
244 struct drm_device *dev,
248 struct drm_i915_gem_object *obj;
252 size = roundup(size, PAGE_SIZE);
256 /* Allocate the new object */
257 obj = i915_gem_alloc_object(dev, size);
261 ret = drm_gem_handle_create(file, &obj->base, &handle);
263 drm_gem_object_release(&obj->base);
264 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
265 free(obj, DRM_I915_GEM);
269 /* drop reference from allocate - handle holds it now */
270 drm_gem_object_unreference(&obj->base);
271 CTR2(KTR_DRM, "object_create %p %x", obj, size);
278 i915_gem_dumb_create(struct drm_file *file,
279 struct drm_device *dev,
280 struct drm_mode_create_dumb *args)
282 /* have to work out size/pitch and return them */
283 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
284 args->size = args->pitch * args->height;
285 return i915_gem_create(file, dev,
286 args->size, &args->handle);
289 int i915_gem_dumb_destroy(struct drm_file *file,
290 struct drm_device *dev,
293 return drm_gem_handle_delete(file, handle);
297 * Creates a new mm object and returns a handle to it.
300 i915_gem_create_ioctl(struct drm_device *dev, void *data,
301 struct drm_file *file)
303 struct drm_i915_gem_create *args = data;
305 return i915_gem_create(file, dev,
306 args->size, &args->handle);
309 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
311 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
314 obj->tiling_mode != I915_TILING_NONE;
318 __copy_to_user_swizzled(char __user *cpu_vaddr,
319 const char *gpu_vaddr, int gpu_offset,
322 int ret, cpu_offset = 0;
325 int cacheline_end = roundup2(gpu_offset + 1, 64);
326 int this_length = min(cacheline_end - gpu_offset, length);
327 int swizzled_gpu_offset = gpu_offset ^ 64;
329 ret = __copy_to_user(cpu_vaddr + cpu_offset,
330 gpu_vaddr + swizzled_gpu_offset,
335 cpu_offset += this_length;
336 gpu_offset += this_length;
337 length -= this_length;
344 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
345 const char __user *cpu_vaddr,
348 int ret, cpu_offset = 0;
351 int cacheline_end = roundup2(gpu_offset + 1, 64);
352 int this_length = min(cacheline_end - gpu_offset, length);
353 int swizzled_gpu_offset = gpu_offset ^ 64;
355 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
356 cpu_vaddr + cpu_offset,
361 cpu_offset += this_length;
362 gpu_offset += this_length;
363 length -= this_length;
369 /* Per-page copy function for the shmem pread fastpath.
370 * Flushes invalid cachelines before reading the target if
371 * needs_clflush is set. */
373 shmem_pread_fast(vm_page_t page, int shmem_page_offset, int page_length,
374 char __user *user_data,
375 bool page_do_bit17_swizzling, bool needs_clflush)
381 if (unlikely(page_do_bit17_swizzling))
385 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE);
390 vaddr = (char *)sf_buf_kva(sf);
392 drm_clflush_virt_range(vaddr + shmem_page_offset,
394 ret = __copy_to_user_inatomic(user_data,
395 vaddr + shmem_page_offset,
400 return ret ? -EFAULT : 0;
404 shmem_clflush_swizzled_range(char *addr, unsigned long length,
407 if (unlikely(swizzled)) {
408 unsigned long start = (unsigned long) addr;
409 unsigned long end = (unsigned long) addr + length;
411 /* For swizzling simply ensure that we always flush both
412 * channels. Lame, but simple and it works. Swizzled
413 * pwrite/pread is far from a hotpath - current userspace
414 * doesn't use it at all. */
415 start = round_down(start, 128);
416 end = round_up(end, 128);
418 drm_clflush_virt_range((void *)start, end - start);
420 drm_clflush_virt_range(addr, length);
425 /* Only difference to the fast-path function is that this can handle bit17
426 * and uses non-atomic copy and kmap functions. */
428 shmem_pread_slow(vm_page_t page, int shmem_page_offset, int page_length,
429 char __user *user_data,
430 bool page_do_bit17_swizzling, bool needs_clflush)
436 sf = sf_buf_alloc(page, 0);
437 vaddr = (char *)sf_buf_kva(sf);
439 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
441 page_do_bit17_swizzling);
443 if (page_do_bit17_swizzling)
444 ret = __copy_to_user_swizzled(user_data,
445 vaddr, shmem_page_offset,
448 ret = __copy_to_user(user_data,
449 vaddr + shmem_page_offset,
453 return ret ? - EFAULT : 0;
457 i915_gem_shmem_pread(struct drm_device *dev,
458 struct drm_i915_gem_object *obj,
459 struct drm_i915_gem_pread *args,
460 struct drm_file *file)
462 char __user *user_data;
465 int shmem_page_offset, page_length, ret = 0;
466 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
467 int hit_slowpath = 0;
469 int needs_clflush = 0;
471 user_data = to_user_ptr(args->data_ptr);
474 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
476 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
477 /* If we're not in the cpu read domain, set ourself into the gtt
478 * read domain and manually flush cachelines (if required). This
479 * optimizes for the case when the gpu will dirty the data
480 * anyway again before the next pread happens. */
481 if (obj->cache_level == I915_CACHE_NONE)
483 if (obj->gtt_space) {
484 ret = i915_gem_object_set_to_gtt_domain(obj, false);
490 ret = i915_gem_object_get_pages(obj);
494 i915_gem_object_pin_pages(obj);
496 offset = args->offset;
498 VM_OBJECT_WLOCK(obj->base.vm_obj);
499 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
500 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
501 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
506 /* Operation in this page
508 * shmem_page_offset = offset within page in shmem file
509 * page_length = bytes to copy for this page
511 shmem_page_offset = offset_in_page(offset);
512 page_length = remain;
513 if ((shmem_page_offset + page_length) > PAGE_SIZE)
514 page_length = PAGE_SIZE - shmem_page_offset;
516 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
517 (page_to_phys(page) & (1 << 17)) != 0;
519 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
520 user_data, page_do_bit17_swizzling,
529 ret = fault_in_multipages_writeable(user_data, remain);
530 /* Userspace is tricking us, but we've already clobbered
531 * its pages with the prefault and promised to write the
532 * data up to the first fault. Hence ignore any errors
533 * and just continue. */
538 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
539 user_data, page_do_bit17_swizzling,
545 vm_page_reference(page);
550 remain -= page_length;
551 user_data += page_length;
552 offset += page_length;
553 VM_OBJECT_WLOCK(obj->base.vm_obj);
557 i915_gem_object_unpin_pages(obj);
560 /* Fixup: Kill any reinstated backing storage pages */
561 if (obj->madv == __I915_MADV_PURGED)
562 i915_gem_object_truncate(obj);
569 * Reads data from the object referenced by handle.
571 * On error, the contents of *data are undefined.
574 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
575 struct drm_file *file)
577 struct drm_i915_gem_pread *args = data;
578 struct drm_i915_gem_object *obj;
584 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_WRITE))
587 ret = i915_mutex_lock_interruptible(dev);
591 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
592 if (&obj->base == NULL) {
597 /* Bounds check source. */
598 if (args->offset > obj->base.size ||
599 args->size > obj->base.size - args->offset) {
605 /* prime objects have no backing filp to GEM pread/pwrite
608 if (!obj->base.filp) {
612 #endif /* FREEBSD_WIP */
614 CTR3(KTR_DRM, "pread %p %jx %jx", obj, args->offset, args->size);
616 ret = i915_gem_shmem_pread(dev, obj, args, file);
619 drm_gem_object_unreference(&obj->base);
625 /* This is the fast write path which cannot handle
626 * page faults in the source data
630 fast_user_write(vm_paddr_t mapping_addr,
631 off_t page_base, int page_offset,
632 char __user *user_data,
635 void __iomem *vaddr_atomic;
637 unsigned long unwritten;
639 vaddr_atomic = pmap_mapdev_attr(mapping_addr + page_base,
640 length, PAT_WRITE_COMBINING);
641 /* We can use the cpu mem copy function because this is X86. */
642 vaddr = (char __force*)vaddr_atomic + page_offset;
643 unwritten = __copy_from_user_inatomic_nocache(vaddr,
645 pmap_unmapdev((vm_offset_t)vaddr_atomic, length);
650 * This is the fast pwrite path, where we copy the data directly from the
651 * user into the GTT, uncached.
654 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
655 struct drm_i915_gem_object *obj,
656 struct drm_i915_gem_pwrite *args,
657 struct drm_file *file)
659 drm_i915_private_t *dev_priv = dev->dev_private;
661 off_t offset, page_base;
662 char __user *user_data;
663 int page_offset, page_length, ret;
665 ret = i915_gem_object_pin(obj, 0, true, true);
669 ret = i915_gem_object_set_to_gtt_domain(obj, true);
673 ret = i915_gem_object_put_fence(obj);
677 user_data = to_user_ptr(args->data_ptr);
680 offset = obj->gtt_offset + args->offset;
683 /* Operation in this page
685 * page_base = page offset within aperture
686 * page_offset = offset within page
687 * page_length = bytes to copy for this page
689 page_base = offset & ~PAGE_MASK;
690 page_offset = offset_in_page(offset);
691 page_length = remain;
692 if ((page_offset + remain) > PAGE_SIZE)
693 page_length = PAGE_SIZE - page_offset;
695 /* If we get a fault while copying data, then (presumably) our
696 * source page isn't available. Return the error and we'll
697 * retry in the slow path.
699 if (fast_user_write(dev_priv->mm.gtt_base_addr, page_base,
700 page_offset, user_data, page_length)) {
705 remain -= page_length;
706 user_data += page_length;
707 offset += page_length;
711 i915_gem_object_unpin(obj);
716 /* Per-page copy function for the shmem pwrite fastpath.
717 * Flushes invalid cachelines before writing to the target if
718 * needs_clflush_before is set and flushes out any written cachelines after
719 * writing if needs_clflush is set. */
721 shmem_pwrite_fast(vm_page_t page, int shmem_page_offset, int page_length,
722 char __user *user_data,
723 bool page_do_bit17_swizzling,
724 bool needs_clflush_before,
725 bool needs_clflush_after)
731 if (unlikely(page_do_bit17_swizzling))
735 sf = sf_buf_alloc(page, SFB_NOWAIT | SFB_CPUPRIVATE);
740 vaddr = (char *)sf_buf_kva(sf);
741 if (needs_clflush_before)
742 drm_clflush_virt_range(vaddr + shmem_page_offset,
744 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
747 if (needs_clflush_after)
748 drm_clflush_virt_range(vaddr + shmem_page_offset,
753 return ret ? -EFAULT : 0;
756 /* Only difference to the fast-path function is that this can handle bit17
757 * and uses non-atomic copy and kmap functions. */
759 shmem_pwrite_slow(vm_page_t page, int shmem_page_offset, int page_length,
760 char __user *user_data,
761 bool page_do_bit17_swizzling,
762 bool needs_clflush_before,
763 bool needs_clflush_after)
769 sf = sf_buf_alloc(page, 0);
770 vaddr = (char *)sf_buf_kva(sf);
771 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
772 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
774 page_do_bit17_swizzling);
775 if (page_do_bit17_swizzling)
776 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
780 ret = __copy_from_user(vaddr + shmem_page_offset,
783 if (needs_clflush_after)
784 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
786 page_do_bit17_swizzling);
789 return ret ? -EFAULT : 0;
793 i915_gem_shmem_pwrite(struct drm_device *dev,
794 struct drm_i915_gem_object *obj,
795 struct drm_i915_gem_pwrite *args,
796 struct drm_file *file)
800 char __user *user_data;
801 int shmem_page_offset, page_length, ret = 0;
802 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
803 int hit_slowpath = 0;
804 int needs_clflush_after = 0;
805 int needs_clflush_before = 0;
807 user_data = to_user_ptr(args->data_ptr);
810 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
812 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
813 /* If we're not in the cpu write domain, set ourself into the gtt
814 * write domain and manually flush cachelines (if required). This
815 * optimizes for the case when the gpu will use the data
816 * right away and we therefore have to clflush anyway. */
817 if (obj->cache_level == I915_CACHE_NONE)
818 needs_clflush_after = 1;
819 if (obj->gtt_space) {
820 ret = i915_gem_object_set_to_gtt_domain(obj, true);
825 /* Same trick applies for invalidate partially written cachelines before
827 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
828 && obj->cache_level == I915_CACHE_NONE)
829 needs_clflush_before = 1;
831 ret = i915_gem_object_get_pages(obj);
835 i915_gem_object_pin_pages(obj);
837 offset = args->offset;
840 VM_OBJECT_WLOCK(obj->base.vm_obj);
841 for (vm_page_t page = vm_page_find_least(obj->base.vm_obj,
842 OFF_TO_IDX(offset));; page = vm_page_next(page)) {
843 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
844 int partial_cacheline_write;
849 /* Operation in this page
851 * shmem_page_offset = offset within page in shmem file
852 * page_length = bytes to copy for this page
854 shmem_page_offset = offset_in_page(offset);
856 page_length = remain;
857 if ((shmem_page_offset + page_length) > PAGE_SIZE)
858 page_length = PAGE_SIZE - shmem_page_offset;
860 /* If we don't overwrite a cacheline completely we need to be
861 * careful to have up-to-date data by first clflushing. Don't
862 * overcomplicate things and flush the entire patch. */
863 partial_cacheline_write = needs_clflush_before &&
864 ((shmem_page_offset | page_length)
865 & (cpu_clflush_line_size - 1));
867 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
868 (page_to_phys(page) & (1 << 17)) != 0;
870 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
871 user_data, page_do_bit17_swizzling,
872 partial_cacheline_write,
873 needs_clflush_after);
879 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
880 user_data, page_do_bit17_swizzling,
881 partial_cacheline_write,
882 needs_clflush_after);
888 vm_page_reference(page);
893 remain -= page_length;
894 user_data += page_length;
895 offset += page_length;
896 VM_OBJECT_WLOCK(obj->base.vm_obj);
900 i915_gem_object_unpin_pages(obj);
903 /* Fixup: Kill any reinstated backing storage pages */
904 if (obj->madv == __I915_MADV_PURGED)
905 i915_gem_object_truncate(obj);
906 /* and flush dirty cachelines in case the object isn't in the cpu write
908 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
909 i915_gem_clflush_object(obj);
910 i915_gem_chipset_flush(dev);
914 if (needs_clflush_after)
915 i915_gem_chipset_flush(dev);
921 * Writes data to the object referenced by handle.
923 * On error, the contents of the buffer that were to be modified are undefined.
926 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
927 struct drm_file *file)
929 struct drm_i915_gem_pwrite *args = data;
930 struct drm_i915_gem_object *obj;
936 if (!useracc(to_user_ptr(args->data_ptr), args->size, VM_PROT_READ))
939 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
944 ret = i915_mutex_lock_interruptible(dev);
948 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
949 if (&obj->base == NULL) {
954 /* Bounds check destination. */
955 if (args->offset > obj->base.size ||
956 args->size > obj->base.size - args->offset) {
962 /* prime objects have no backing filp to GEM pread/pwrite
965 if (!obj->base.filp) {
969 #endif /* FREEBSD_WIP */
971 CTR3(KTR_DRM, "pwrite %p %jx %jx", obj, args->offset, args->size);
974 /* We can only do the GTT pwrite on untiled buffers, as otherwise
975 * it would end up going through the fenced access, and we'll get
976 * different detiling behavior between reading and writing.
977 * pread/pwrite currently are reading and writing from the CPU
978 * perspective, requiring manual detiling by the client.
981 ret = i915_gem_phys_pwrite(dev, obj, args, file);
985 if (obj->cache_level == I915_CACHE_NONE &&
986 obj->tiling_mode == I915_TILING_NONE &&
987 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
988 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
989 /* Note that the gtt paths might fail with non-page-backed user
990 * pointers (e.g. gtt mappings when moving data between
991 * textures). Fallback to the shmem path in that case. */
994 if (ret == -EFAULT || ret == -ENOSPC)
995 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
998 drm_gem_object_unreference(&obj->base);
1005 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1008 if (atomic_read(&dev_priv->mm.wedged)) {
1009 struct completion *x = &dev_priv->error_completion;
1010 bool recovery_complete;
1012 /* Give the error handler a chance to run. */
1014 recovery_complete = x->done > 0;
1015 mtx_unlock(&x->lock);
1017 /* Non-interruptible callers can't handle -EAGAIN, hence return
1018 * -EIO unconditionally for these. */
1022 /* Recovery complete, but still wedged means reset failure. */
1023 if (recovery_complete)
1033 * Compare seqno against outstanding lazy request. Emit a request if they are
1037 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1041 DRM_LOCK_ASSERT(ring->dev);
1044 if (seqno == ring->outstanding_lazy_request)
1045 ret = i915_add_request(ring, NULL, NULL);
1051 * __wait_seqno - wait until execution of seqno has finished
1052 * @ring: the ring expected to report seqno
1054 * @interruptible: do an interruptible wait (normally yes)
1055 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1057 * Returns 0 if the seqno was found within the alloted time. Else returns the
1058 * errno with remaining time filled in timeout argument.
1060 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1061 bool interruptible, struct timespec *timeout)
1063 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1064 struct timespec before, now, wait_time={1,0};
1065 sbintime_t timeout_sbt;
1067 bool wait_forever = true;
1070 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1073 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
1075 if (timeout != NULL) {
1076 wait_time = *timeout;
1077 wait_forever = false;
1080 timeout_sbt = tstosbt(wait_time);
1082 if (WARN_ON(!ring->irq_get(ring)))
1085 /* Record current time in case interrupted by signal, or wedged * */
1086 getrawmonotonic(&before);
1089 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1090 atomic_read(&dev_priv->mm.wedged))
1091 flags = interruptible ? PCATCH : 0;
1092 mtx_lock(&dev_priv->irq_lock);
1097 ret = -msleep_sbt(&ring->irq_queue, &dev_priv->irq_lock, flags,
1098 "915gwr", timeout_sbt, 0, 0);
1101 * NOTE Linux<->FreeBSD: Convert msleep_sbt() return
1102 * value to something close to wait_event*_timeout()
1103 * functions used on Linux.
1105 * >0 -> condition is true (end = time remaining)
1106 * =0 -> sleep timed out
1107 * <0 -> error (interrupted)
1109 * We fake the remaining time by returning 1. We
1110 * compute a proper value later.
1113 /* We fake a remaining time of 1 tick. */
1115 else if (ret == -EINTR || ret == -ERESTART)
1123 ret = i915_gem_check_wedge(dev_priv, interruptible);
1126 } while (end == 0 && wait_forever);
1127 mtx_unlock(&dev_priv->irq_lock);
1129 getrawmonotonic(&now);
1131 ring->irq_put(ring);
1132 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno, end);
1136 timespecsub(&now, &before);
1137 timespecsub(timeout, &now);
1142 case -EAGAIN: /* Wedged */
1143 case -ERESTARTSYS: /* Signal */
1144 case -ETIMEDOUT: /* Timeout */
1146 case 0: /* Timeout */
1148 default: /* Completed */
1149 WARN_ON(end < 0); /* We're not aware of other errors */
1155 * Waits for a sequence number to be signaled, and cleans up the
1156 * request and object lists appropriately for that event.
1159 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1161 struct drm_device *dev = ring->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 bool interruptible = dev_priv->mm.interruptible;
1166 DRM_LOCK_ASSERT(dev);
1169 ret = i915_gem_check_wedge(dev_priv, interruptible);
1173 ret = i915_gem_check_olr(ring, seqno);
1177 return __wait_seqno(ring, seqno, interruptible, NULL);
1181 * Ensures that all rendering to the object has completed and the object is
1182 * safe to unbind from the GTT or access from the CPU.
1184 static __must_check int
1185 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1188 struct intel_ring_buffer *ring = obj->ring;
1192 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1196 ret = i915_wait_seqno(ring, seqno);
1200 i915_gem_retire_requests_ring(ring);
1202 /* Manually manage the write flush as we may have not yet
1203 * retired the buffer.
1205 if (obj->last_write_seqno &&
1206 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1207 obj->last_write_seqno = 0;
1208 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1214 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1215 * as the object state may change during this call.
1217 static __must_check int
1218 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1221 struct drm_device *dev = obj->base.dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 struct intel_ring_buffer *ring = obj->ring;
1227 DRM_LOCK_ASSERT(dev);
1228 BUG_ON(!dev_priv->mm.interruptible);
1230 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1234 ret = i915_gem_check_wedge(dev_priv, true);
1238 ret = i915_gem_check_olr(ring, seqno);
1243 ret = __wait_seqno(ring, seqno, true, NULL);
1246 i915_gem_retire_requests_ring(ring);
1248 /* Manually manage the write flush as we may have not yet
1249 * retired the buffer.
1252 obj->last_write_seqno &&
1253 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1254 obj->last_write_seqno = 0;
1255 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1262 * Called when user space prepares to use an object with the CPU, either
1263 * through the mmap ioctl's mapping or a GTT mapping.
1266 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1267 struct drm_file *file)
1269 struct drm_i915_gem_set_domain *args = data;
1270 struct drm_i915_gem_object *obj;
1271 uint32_t read_domains = args->read_domains;
1272 uint32_t write_domain = args->write_domain;
1275 /* Only handle setting domains to types used by the CPU. */
1276 if (write_domain & I915_GEM_GPU_DOMAINS)
1279 if (read_domains & I915_GEM_GPU_DOMAINS)
1282 /* Having something in the write domain implies it's in the read
1283 * domain, and only that read domain. Enforce that in the request.
1285 if (write_domain != 0 && read_domains != write_domain)
1288 ret = i915_mutex_lock_interruptible(dev);
1292 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1293 if (&obj->base == NULL) {
1298 /* Try to flush the object off the GPU without holding the lock.
1299 * We will repeat the flush holding the lock in the normal manner
1300 * to catch cases where we are gazumped.
1302 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1306 if (read_domains & I915_GEM_DOMAIN_GTT) {
1307 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1309 /* Silently promote "you're not bound, there was nothing to do"
1310 * to success, since the client was just asking us to
1311 * make sure everything was done.
1316 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1320 drm_gem_object_unreference(&obj->base);
1327 * Called when user space has done writes to this buffer
1330 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1331 struct drm_file *file)
1333 struct drm_i915_gem_sw_finish *args = data;
1334 struct drm_i915_gem_object *obj;
1337 ret = i915_mutex_lock_interruptible(dev);
1341 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1342 if (&obj->base == NULL) {
1347 /* Pinned buffers may be scanout, so flush the cache */
1349 i915_gem_object_flush_cpu_write_domain(obj);
1351 drm_gem_object_unreference(&obj->base);
1358 * Maps the contents of an object, returning the address it is mapped
1361 * While the mapping holds a reference on the contents of the object, it doesn't
1362 * imply a ref on the object itself.
1365 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1366 struct drm_file *file)
1368 struct drm_i915_gem_mmap *args = data;
1369 struct drm_gem_object *obj;
1376 obj = drm_gem_object_lookup(dev, file, args->handle);
1381 /* prime objects have no backing filp to GEM mmap
1385 drm_gem_object_unreference_unlocked(obj);
1388 #endif /* FREEBSD_WIP */
1391 if (args->size == 0)
1394 map = &p->p_vmspace->vm_map;
1395 size = round_page(args->size);
1397 if (map->size + size > lim_cur_proc(p, RLIMIT_VMEM)) {
1405 vm_object_reference(obj->vm_obj);
1406 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size, 0,
1407 VMFS_OPTIMAL_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1408 VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1409 if (rv != KERN_SUCCESS) {
1410 vm_object_deallocate(obj->vm_obj);
1411 error = -vm_mmap_to_errno(rv);
1413 args->addr_ptr = (uint64_t)addr;
1416 drm_gem_object_unreference_unlocked(obj);
1421 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1422 vm_ooffset_t foff, struct ucred *cred, u_short *color)
1426 * NOTE Linux<->FreeBSD: drm_gem_mmap_single() takes care of
1427 * calling drm_gem_object_reference(). That's why we don't
1428 * do this here. i915_gem_pager_dtor(), below, will call
1429 * drm_gem_object_unreference().
1431 * On Linux, drm_gem_vm_open() references the object because
1432 * it's called the mapping is copied. drm_gem_vm_open() is not
1433 * called when the mapping is created. So the possible sequences
1435 * 1. drm_gem_mmap(): ref++
1436 * 2. drm_gem_vm_close(): ref--
1438 * 1. drm_gem_mmap(): ref++
1439 * 2. drm_gem_vm_open(): ref++ (for the copied vma)
1440 * 3. drm_gem_vm_close(): ref-- (for the copied vma)
1441 * 4. drm_gem_vm_close(): ref-- (for the initial vma)
1443 * On FreeBSD, i915_gem_pager_ctor() is called once during the
1444 * creation of the mapping. No callback is called when the
1445 * mapping is shared during a fork(). i915_gem_pager_dtor() is
1446 * called when the last reference to the mapping is dropped. So
1447 * the only sequence is:
1448 * 1. drm_gem_mmap_single(): ref++
1449 * 2. i915_gem_pager_ctor(): <noop>
1450 * 3. i915_gem_pager_dtor(): ref--
1453 *color = 0; /* XXXKIB */
1458 * i915_gem_fault - fault a page into the GTT
1459 * vma: VMA in question
1462 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1463 * from userspace. The fault handler takes care of binding the object to
1464 * the GTT (if needed), allocating and programming a fence register (again,
1465 * only if needed based on whether the old reg is still valid or the object
1466 * is tiled) and inserting a new PTE into the faulting process.
1468 * Note that the faulting process may involve evicting existing objects
1469 * from the GTT and/or fence registers to make room. So performance may
1470 * suffer if the GTT working set is large or there are few fence registers
1477 i915_gem_pager_populate(vm_object_t vm_obj, vm_pindex_t pidx, int fault_type,
1478 vm_prot_t max_prot, vm_pindex_t *first, vm_pindex_t *last)
1480 struct drm_gem_object *gem_obj = vm_obj->handle;
1481 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
1482 struct drm_device *dev = obj->base.dev;
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1486 bool write = (max_prot & VM_PROT_WRITE) != 0;
1489 VM_OBJECT_WUNLOCK(vm_obj);
1496 ret = i915_mutex_lock_interruptible(dev);
1503 * Since the object lock was dropped, other thread might have
1504 * faulted on the same GTT address and instantiated the
1505 * mapping for the page. Recheck.
1507 VM_OBJECT_WLOCK(vm_obj);
1508 page = vm_page_lookup(vm_obj, pidx);
1510 if (vm_page_busied(page)) {
1513 VM_OBJECT_WUNLOCK(vm_obj);
1514 vm_page_busy_sleep(page, "915pee", false);
1519 VM_OBJECT_WUNLOCK(vm_obj);
1521 /* Now bind it into the GTT if needed */
1522 ret = i915_gem_object_pin(obj, 0, true, false);
1527 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1531 ret = i915_gem_object_get_fence(obj);
1535 obj->fault_mappable = true;
1537 page = PHYS_TO_VM_PAGE(dev_priv->mm.gtt_base_addr + obj->gtt_offset +
1543 KASSERT((page->flags & PG_FICTITIOUS) != 0,
1544 ("physical address %#jx not fictitious, page %p",
1545 (uintmax_t)(dev_priv->mm.gtt_base_addr + obj->gtt_offset +
1546 IDX_TO_OFF(pidx)), page));
1547 KASSERT(page->wire_count == 1, ("wire_count not 1 %p", page));
1549 VM_OBJECT_WLOCK(vm_obj);
1550 if (vm_page_busied(page)) {
1551 i915_gem_object_unpin(obj);
1554 VM_OBJECT_WUNLOCK(vm_obj);
1555 vm_page_busy_sleep(page, "915pbs", false);
1558 if (vm_page_insert(page, vm_obj, pidx)) {
1559 i915_gem_object_unpin(obj);
1561 VM_OBJECT_WUNLOCK(vm_obj);
1565 page->valid = VM_PAGE_BITS_ALL;
1567 vm_page_xbusy(page);
1569 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, pidx, fault_type,
1573 * We may have not pinned the object if the page was
1574 * found by the call to vm_page_lookup().
1576 i915_gem_object_unpin(obj);
1579 *first = *last = pidx;
1580 return (VM_PAGER_OK);
1583 i915_gem_object_unpin(obj);
1587 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1588 CTR4(KTR_DRM, "fault_fail %p %jx %x err %d", gem_obj, pidx, fault_type,
1590 if (ret == -ERESTARTSYS) {
1592 * NOTE Linux<->FreeBSD: Convert Linux' -ERESTARTSYS to
1593 * the more common -EINTR, so the page fault is retried.
1597 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1598 kern_yield(PRI_USER);
1601 VM_OBJECT_WLOCK(vm_obj);
1602 return (VM_PAGER_ERROR);
1606 i915_gem_pager_dtor(void *handle)
1608 struct drm_gem_object *obj = handle;
1609 struct drm_device *dev = obj->dev;
1612 drm_gem_object_unreference(obj);
1616 struct cdev_pager_ops i915_gem_pager_ops = {
1617 .cdev_pg_populate = i915_gem_pager_populate,
1618 .cdev_pg_ctor = i915_gem_pager_ctor,
1619 .cdev_pg_dtor = i915_gem_pager_dtor,
1623 * i915_gem_release_mmap - remove physical page mappings
1624 * @obj: obj in question
1626 * Preserve the reservation of the mmapping with the DRM core code, but
1627 * relinquish ownership of the pages back to the system.
1629 * It is vital that we remove the page mapping if we have mapped a tiled
1630 * object through the GTT and then lose the fence register due to
1631 * resource pressure. Similarly if the object has been moved out of the
1632 * aperture, than pages mapped into userspace must be revoked. Removing the
1633 * mapping will then trigger a page fault on the next user access, allowing
1634 * fixup by i915_gem_fault().
1637 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1643 if (!obj->fault_mappable)
1646 CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset,
1647 OFF_TO_IDX(obj->base.size));
1648 devobj = cdev_pager_lookup(obj);
1649 if (devobj != NULL) {
1650 page_count = OFF_TO_IDX(obj->base.size);
1652 VM_OBJECT_WLOCK(devobj);
1654 for (i = 0; i < page_count; i++) {
1655 page = vm_page_lookup(devobj, i);
1658 if (vm_page_sleep_if_busy(page, "915unm"))
1660 cdev_pager_free_page(devobj, page);
1662 VM_OBJECT_WUNLOCK(devobj);
1663 vm_object_deallocate(devobj);
1666 obj->fault_mappable = false;
1670 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1674 if (INTEL_INFO(dev)->gen >= 4 ||
1675 tiling_mode == I915_TILING_NONE)
1678 /* Previous chips need a power-of-two fence region when tiling */
1679 if (INTEL_INFO(dev)->gen == 3)
1680 gtt_size = 1024*1024;
1682 gtt_size = 512*1024;
1684 while (gtt_size < size)
1691 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1692 * @obj: object to check
1694 * Return the required GTT alignment for an object, taking into account
1695 * potential fence register mapping.
1698 i915_gem_get_gtt_alignment(struct drm_device *dev,
1703 * Minimum alignment is 4k (GTT page size), but might be greater
1704 * if a fence register is needed for the object.
1706 if (INTEL_INFO(dev)->gen >= 4 ||
1707 tiling_mode == I915_TILING_NONE)
1711 * Previous chips need to be aligned to the size of the smallest
1712 * fence register that can contain the object.
1714 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1718 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1721 * @size: size of the object
1722 * @tiling_mode: tiling mode of the object
1724 * Return the required GTT alignment for an object, only taking into account
1725 * unfenced tiled surface requirements.
1728 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1733 * Minimum alignment is 4k (GTT page size) for sane hw.
1735 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1736 tiling_mode == I915_TILING_NONE)
1739 /* Previous hardware however needs to be aligned to a power-of-two
1740 * tile height. The simplest method for determining this is to reuse
1741 * the power-of-tile object size.
1743 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1746 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1748 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1751 if (obj->base.on_map)
1754 dev_priv->mm.shrinker_no_lock_stealing = true;
1756 ret = drm_gem_create_mmap_offset(&obj->base);
1760 /* Badly fragmented mmap space? The only way we can recover
1761 * space is by destroying unwanted objects. We can't randomly release
1762 * mmap_offsets as userspace expects them to be persistent for the
1763 * lifetime of the objects. The closest we can is to release the
1764 * offsets on purgeable objects by truncating it and marking it purged,
1765 * which prevents userspace from ever using that object again.
1767 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1768 ret = drm_gem_create_mmap_offset(&obj->base);
1772 i915_gem_shrink_all(dev_priv);
1773 ret = drm_gem_create_mmap_offset(&obj->base);
1775 dev_priv->mm.shrinker_no_lock_stealing = false;
1780 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1782 if (!obj->base.on_map)
1785 drm_gem_free_mmap_offset(&obj->base);
1789 i915_gem_mmap_gtt(struct drm_file *file,
1790 struct drm_device *dev,
1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 struct drm_i915_gem_object *obj;
1798 ret = i915_mutex_lock_interruptible(dev);
1802 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1803 if (&obj->base == NULL) {
1808 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1813 if (obj->madv != I915_MADV_WILLNEED) {
1814 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1819 ret = i915_gem_object_create_mmap_offset(obj);
1823 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1824 DRM_GEM_MAPPING_KEY;
1827 drm_gem_object_unreference(&obj->base);
1834 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1836 * @data: GTT mapping ioctl data
1837 * @file: GEM object info
1839 * Simply returns the fake offset to userspace so it can mmap it.
1840 * The mmap call will end up in drm_gem_mmap(), which will set things
1841 * up so we can get faults in the handler above.
1843 * The fault handler will take care of binding the object into the GTT
1844 * (since it may have been evicted to make room for something), allocating
1845 * a fence register, and mapping the appropriate aperture address into
1849 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *file)
1852 struct drm_i915_gem_mmap_gtt *args = data;
1854 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1857 /* Immediately discard the backing storage */
1859 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1863 vm_obj = obj->base.vm_obj;
1864 VM_OBJECT_WLOCK(vm_obj);
1865 vm_object_page_remove(vm_obj, 0, 0, false);
1866 VM_OBJECT_WUNLOCK(vm_obj);
1867 i915_gem_object_free_mmap_offset(obj);
1869 obj->madv = __I915_MADV_PURGED;
1873 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1875 return obj->madv == I915_MADV_DONTNEED;
1879 i915_gem_object_put_pages_range_locked(struct drm_i915_gem_object *obj,
1880 vm_pindex_t si, vm_pindex_t ei)
1886 vm_obj = obj->base.vm_obj;
1887 VM_OBJECT_ASSERT_LOCKED(vm_obj);
1888 for (i = si, page = vm_page_lookup(vm_obj, i); i < ei;
1889 page = vm_page_next(page), i++) {
1890 KASSERT(page->pindex == i, ("pindex %jx %jx",
1891 (uintmax_t)page->pindex, (uintmax_t)i));
1893 if (vm_page_unwire(page, PQ_INACTIVE))
1894 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1895 vm_page_unlock(page);
1899 #define GEM_PARANOID_CHECK_GTT 0
1900 #if GEM_PARANOID_CHECK_GTT
1902 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
1905 struct drm_i915_private *dev_priv;
1907 unsigned long start, end;
1911 dev_priv = dev->dev_private;
1912 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
1913 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
1914 for (i = start; i < end; i++) {
1915 pa = intel_gtt_read_pte_paddr(i);
1916 for (j = 0; j < page_count; j++) {
1917 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
1918 panic("Page %p in GTT pte index %d pte %x",
1919 ma[i], i, intel_gtt_read_pte(i));
1927 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1929 int page_count = obj->base.size / PAGE_SIZE;
1932 BUG_ON(obj->madv == __I915_MADV_PURGED);
1934 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1936 /* In the event of a disaster, abandon all caches and
1937 * hope for the best.
1939 WARN_ON(ret != -EIO);
1940 i915_gem_clflush_object(obj);
1941 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1944 if (i915_gem_object_needs_bit17_swizzle(obj))
1945 i915_gem_object_save_bit_17_swizzle(obj);
1947 if (obj->madv == I915_MADV_DONTNEED)
1950 VM_OBJECT_WLOCK(obj->base.vm_obj);
1951 #if GEM_PARANOID_CHECK_GTT
1952 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
1954 for (i = 0; i < page_count; i++) {
1955 vm_page_t page = obj->pages[i];
1958 vm_page_dirty(page);
1960 if (obj->madv == I915_MADV_WILLNEED)
1961 vm_page_reference(page);
1964 vm_page_unwire(obj->pages[i], PQ_ACTIVE);
1965 vm_page_unlock(page);
1966 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1968 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
1971 free(obj->pages, DRM_I915_GEM);
1976 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1978 const struct drm_i915_gem_object_ops *ops = obj->ops;
1980 if (obj->pages == NULL)
1983 BUG_ON(obj->gtt_space);
1985 if (obj->pages_pin_count)
1988 /* ->put_pages might need to allocate memory for the bit17 swizzle
1989 * array, hence protect them from being reaped by removing them from gtt
1991 list_del(&obj->gtt_list);
1993 ops->put_pages(obj);
1996 if (i915_gem_object_is_purgeable(obj))
1997 i915_gem_object_truncate(obj);
2003 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
2004 bool purgeable_only)
2006 struct drm_i915_gem_object *obj, *next;
2009 list_for_each_entry_safe(obj, next,
2010 &dev_priv->mm.unbound_list,
2012 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2013 i915_gem_object_put_pages(obj) == 0) {
2014 count += obj->base.size >> PAGE_SHIFT;
2015 if (target != -1 && count >= target)
2020 list_for_each_entry_safe(obj, next,
2021 &dev_priv->mm.inactive_list,
2023 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
2024 i915_gem_object_unbind(obj) == 0 &&
2025 i915_gem_object_put_pages(obj) == 0) {
2026 count += obj->base.size >> PAGE_SHIFT;
2027 if (target != -1 && count >= target)
2036 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2038 return __i915_gem_shrink(dev_priv, target, true);
2042 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2044 struct drm_i915_gem_object *obj, *next;
2046 i915_gem_evict_everything(dev_priv->dev);
2048 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
2049 i915_gem_object_put_pages(obj);
2053 i915_gem_object_get_pages_range(struct drm_i915_gem_object *obj,
2054 off_t start, off_t end)
2058 vm_pindex_t si, ei, i;
2059 bool need_swizzle, fresh;
2061 need_swizzle = i915_gem_object_needs_bit17_swizzle(obj) != 0;
2062 vm_obj = obj->base.vm_obj;
2063 si = OFF_TO_IDX(trunc_page(start));
2064 ei = OFF_TO_IDX(round_page(end));
2065 VM_OBJECT_WLOCK(vm_obj);
2066 for (i = si; i < ei; i++) {
2067 page = i915_gem_wire_page(vm_obj, i, &fresh);
2070 if (need_swizzle && fresh)
2071 i915_gem_object_do_bit_17_swizzle_page(obj, page);
2073 VM_OBJECT_WUNLOCK(vm_obj);
2076 i915_gem_object_put_pages_range_locked(obj, si, i);
2077 VM_OBJECT_WUNLOCK(vm_obj);
2082 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2086 vm_pindex_t i, page_count;
2089 /* Assert that the object is not currently in any GPU domain. As it
2090 * wasn't in the GTT, there shouldn't be any way it could have been in
2093 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2094 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2095 KASSERT(obj->pages == NULL, ("Obj already has pages"));
2097 page_count = OFF_TO_IDX(obj->base.size);
2098 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2100 res = i915_gem_object_get_pages_range(obj, 0, obj->base.size);
2102 free(obj->pages, DRM_I915_GEM);
2106 vm_obj = obj->base.vm_obj;
2107 VM_OBJECT_WLOCK(vm_obj);
2108 for (i = 0, page = vm_page_lookup(vm_obj, 0); i < page_count;
2109 i++, page = vm_page_next(page)) {
2110 KASSERT(page->pindex == i, ("pindex %jx %jx",
2111 (uintmax_t)page->pindex, (uintmax_t)i));
2112 obj->pages[i] = page;
2114 VM_OBJECT_WUNLOCK(vm_obj);
2118 /* Ensure that the associated pages are gathered from the backing storage
2119 * and pinned into our object. i915_gem_object_get_pages() may be called
2120 * multiple times before they are released by a single call to
2121 * i915_gem_object_put_pages() - once the pages are no longer referenced
2122 * either as a result of memory pressure (reaping pages under the shrinker)
2123 * or as the object is itself released.
2126 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2128 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129 const struct drm_i915_gem_object_ops *ops = obj->ops;
2135 BUG_ON(obj->pages_pin_count);
2137 ret = ops->get_pages(obj);
2141 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2146 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2147 struct intel_ring_buffer *ring)
2149 struct drm_device *dev = obj->base.dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 u32 seqno = intel_ring_get_seqno(ring);
2153 BUG_ON(ring == NULL);
2156 /* Add a reference if we're newly entering the active list. */
2158 drm_gem_object_reference(&obj->base);
2162 /* Move from whatever list we were on to the tail of execution. */
2163 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2164 list_move_tail(&obj->ring_list, &ring->active_list);
2166 obj->last_read_seqno = seqno;
2168 if (obj->fenced_gpu_access) {
2169 obj->last_fenced_seqno = seqno;
2171 /* Bump MRU to take account of the delayed flush */
2172 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2173 struct drm_i915_fence_reg *reg;
2175 reg = &dev_priv->fence_regs[obj->fence_reg];
2176 list_move_tail(®->lru_list,
2177 &dev_priv->mm.fence_list);
2183 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2185 struct drm_device *dev = obj->base.dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2188 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2189 BUG_ON(!obj->active);
2191 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2193 list_del_init(&obj->ring_list);
2196 obj->last_read_seqno = 0;
2197 obj->last_write_seqno = 0;
2198 obj->base.write_domain = 0;
2200 obj->last_fenced_seqno = 0;
2201 obj->fenced_gpu_access = false;
2204 drm_gem_object_unreference(&obj->base);
2206 WARN_ON(i915_verify_lists(dev));
2210 i915_gem_handle_seqno_wrap(struct drm_device *dev)
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_ring_buffer *ring;
2216 /* The hardware uses various monotonic 32-bit counters, if we
2217 * detect that they will wraparound we need to idle the GPU
2218 * and reset those counters.
2221 for_each_ring(ring, dev_priv, i) {
2222 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2223 ret |= ring->sync_seqno[j] != 0;
2228 ret = i915_gpu_idle(dev);
2232 i915_gem_retire_requests(dev);
2233 for_each_ring(ring, dev_priv, i) {
2234 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2235 ring->sync_seqno[j] = 0;
2242 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2246 /* reserve 0 for non-seqno */
2247 if (dev_priv->next_seqno == 0) {
2248 int ret = i915_gem_handle_seqno_wrap(dev);
2252 dev_priv->next_seqno = 1;
2255 *seqno = dev_priv->next_seqno++;
2260 i915_add_request(struct intel_ring_buffer *ring,
2261 struct drm_file *file,
2264 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2265 struct drm_i915_gem_request *request;
2266 u32 request_ring_position;
2271 * Emit any outstanding flushes - execbuf can fail to emit the flush
2272 * after having emitted the batchbuffer command. Hence we need to fix
2273 * things up similar to emitting the lazy request. The difference here
2274 * is that the flush _must_ happen before the next request, no matter
2277 ret = intel_ring_flush_all_caches(ring);
2281 request = malloc(sizeof(*request), DRM_I915_GEM, M_NOWAIT);
2282 if (request == NULL)
2286 /* Record the position of the start of the request so that
2287 * should we detect the updated seqno part-way through the
2288 * GPU processing the request, we never over-estimate the
2289 * position of the head.
2291 request_ring_position = intel_ring_get_tail(ring);
2293 ret = ring->add_request(ring);
2295 free(request, DRM_I915_GEM);
2299 request->seqno = intel_ring_get_seqno(ring);
2300 request->ring = ring;
2301 request->tail = request_ring_position;
2302 request->emitted_jiffies = jiffies;
2303 was_empty = list_empty(&ring->request_list);
2304 list_add_tail(&request->list, &ring->request_list);
2305 request->file_priv = NULL;
2308 struct drm_i915_file_private *file_priv = file->driver_priv;
2310 mtx_lock(&file_priv->mm.lock);
2311 request->file_priv = file_priv;
2312 list_add_tail(&request->client_list,
2313 &file_priv->mm.request_list);
2314 mtx_unlock(&file_priv->mm.lock);
2317 CTR2(KTR_DRM, "request_add %s %d", ring->name, request->seqno);
2318 ring->outstanding_lazy_request = 0;
2320 if (!dev_priv->mm.suspended) {
2321 if (i915_enable_hangcheck) {
2322 callout_schedule(&dev_priv->hangcheck_timer,
2323 DRM_I915_HANGCHECK_PERIOD);
2326 taskqueue_enqueue_timeout(dev_priv->wq,
2327 &dev_priv->mm.retire_work, hz);
2328 intel_mark_busy(dev_priv->dev);
2333 *out_seqno = request->seqno;
2338 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2340 struct drm_i915_file_private *file_priv = request->file_priv;
2345 mtx_lock(&file_priv->mm.lock);
2346 if (request->file_priv) {
2347 list_del(&request->client_list);
2348 request->file_priv = NULL;
2350 mtx_unlock(&file_priv->mm.lock);
2353 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2354 struct intel_ring_buffer *ring)
2356 if (ring->dev != NULL)
2357 DRM_LOCK_ASSERT(ring->dev);
2359 while (!list_empty(&ring->request_list)) {
2360 struct drm_i915_gem_request *request;
2362 request = list_first_entry(&ring->request_list,
2363 struct drm_i915_gem_request,
2366 list_del(&request->list);
2367 i915_gem_request_remove_from_client(request);
2368 free(request, DRM_I915_GEM);
2371 while (!list_empty(&ring->active_list)) {
2372 struct drm_i915_gem_object *obj;
2374 obj = list_first_entry(&ring->active_list,
2375 struct drm_i915_gem_object,
2378 i915_gem_object_move_to_inactive(obj);
2382 static void i915_gem_reset_fences(struct drm_device *dev)
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2387 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2388 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2390 i915_gem_write_fence(dev, i, NULL);
2393 i915_gem_object_fence_lost(reg->obj);
2397 INIT_LIST_HEAD(®->lru_list);
2400 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2403 void i915_gem_reset(struct drm_device *dev)
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct drm_i915_gem_object *obj;
2407 struct intel_ring_buffer *ring;
2410 for_each_ring(ring, dev_priv, i)
2411 i915_gem_reset_ring_lists(dev_priv, ring);
2413 /* Move everything out of the GPU domains to ensure we do any
2414 * necessary invalidation upon reuse.
2416 list_for_each_entry(obj,
2417 &dev_priv->mm.inactive_list,
2420 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2423 /* The fence registers are invalidated so clear them out */
2424 i915_gem_reset_fences(dev);
2428 * This function clears the request list as sequence numbers are passed.
2431 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2435 if (list_empty(&ring->request_list))
2438 WARN_ON(i915_verify_lists(ring->dev));
2440 seqno = ring->get_seqno(ring, true);
2441 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2443 while (!list_empty(&ring->request_list)) {
2444 struct drm_i915_gem_request *request;
2446 request = list_first_entry(&ring->request_list,
2447 struct drm_i915_gem_request,
2450 if (!i915_seqno_passed(seqno, request->seqno))
2453 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2455 /* We know the GPU must have read the request to have
2456 * sent us the seqno + interrupt, so use the position
2457 * of tail of the request to update the last known position
2460 ring->last_retired_head = request->tail;
2462 list_del(&request->list);
2463 i915_gem_request_remove_from_client(request);
2464 free(request, DRM_I915_GEM);
2467 /* Move any buffers on the active list that are no longer referenced
2468 * by the ringbuffer to the flushing/inactive lists as appropriate.
2470 while (!list_empty(&ring->active_list)) {
2471 struct drm_i915_gem_object *obj;
2473 obj = list_first_entry(&ring->active_list,
2474 struct drm_i915_gem_object,
2477 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2480 i915_gem_object_move_to_inactive(obj);
2483 if (unlikely(ring->trace_irq_seqno &&
2484 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2485 ring->irq_put(ring);
2486 ring->trace_irq_seqno = 0;
2489 WARN_ON(i915_verify_lists(ring->dev));
2493 i915_gem_retire_requests(struct drm_device *dev)
2495 drm_i915_private_t *dev_priv = dev->dev_private;
2496 struct intel_ring_buffer *ring;
2499 for_each_ring(ring, dev_priv, i)
2500 i915_gem_retire_requests_ring(ring);
2504 i915_gem_retire_work_handler(void *arg, int pending)
2506 drm_i915_private_t *dev_priv;
2507 struct drm_device *dev;
2508 struct intel_ring_buffer *ring;
2513 dev = dev_priv->dev;
2515 /* Come back later if the device is busy... */
2516 if (!sx_try_xlock(&dev->dev_struct_lock)) {
2517 taskqueue_enqueue_timeout(dev_priv->wq,
2518 &dev_priv->mm.retire_work, hz);
2522 CTR0(KTR_DRM, "retire_task");
2524 i915_gem_retire_requests(dev);
2526 /* Send a periodic flush down the ring so we don't hold onto GEM
2527 * objects indefinitely.
2530 for_each_ring(ring, dev_priv, i) {
2531 if (ring->gpu_caches_dirty)
2532 i915_add_request(ring, NULL, NULL);
2534 idle &= list_empty(&ring->request_list);
2537 if (!dev_priv->mm.suspended && !idle)
2538 taskqueue_enqueue_timeout(dev_priv->wq,
2539 &dev_priv->mm.retire_work, hz);
2541 intel_mark_idle(dev);
2547 * Ensures that an object will eventually get non-busy by flushing any required
2548 * write domains, emitting any outstanding lazy request and retiring and
2549 * completed requests.
2552 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2557 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2561 i915_gem_retire_requests_ring(obj->ring);
2568 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2569 * @DRM_IOCTL_ARGS: standard ioctl arguments
2571 * Returns 0 if successful, else an error is returned with the remaining time in
2572 * the timeout parameter.
2573 * -ETIME: object is still busy after timeout
2574 * -ERESTARTSYS: signal interrupted the wait
2575 * -ENONENT: object doesn't exist
2576 * Also possible, but rare:
2577 * -EAGAIN: GPU wedged
2579 * -ENODEV: Internal IRQ fail
2580 * -E?: The add request failed
2582 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2583 * non-zero timeout parameter the wait ioctl will wait for the given number of
2584 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2585 * without holding struct_mutex the object may become re-busied before this
2586 * function completes. A similar but shorter * race condition exists in the busy
2590 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2592 struct drm_i915_gem_wait *args = data;
2593 struct drm_i915_gem_object *obj;
2594 struct intel_ring_buffer *ring = NULL;
2595 struct timespec timeout_stack, *timeout = NULL;
2599 if (args->timeout_ns >= 0) {
2600 timeout_stack.tv_sec = args->timeout_ns / 1000000;
2601 timeout_stack.tv_nsec = args->timeout_ns % 1000000;
2602 timeout = &timeout_stack;
2605 ret = i915_mutex_lock_interruptible(dev);
2609 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2610 if (&obj->base == NULL) {
2615 /* Need to make sure the object gets inactive eventually. */
2616 ret = i915_gem_object_flush_active(obj);
2621 seqno = obj->last_read_seqno;
2628 /* Do this after OLR check to make sure we make forward progress polling
2629 * on this IOCTL with a 0 timeout (like busy ioctl)
2631 if (!args->timeout_ns) {
2636 drm_gem_object_unreference(&obj->base);
2639 ret = __wait_seqno(ring, seqno, true, timeout);
2641 args->timeout_ns = timeout->tv_sec * 1000000 + timeout->tv_nsec;
2646 drm_gem_object_unreference(&obj->base);
2652 * i915_gem_object_sync - sync an object to a ring.
2654 * @obj: object which may be in use on another ring.
2655 * @to: ring we wish to use the object on. May be NULL.
2657 * This code is meant to abstract object synchronization with the GPU.
2658 * Calling with NULL implies synchronizing the object with the CPU
2659 * rather than a particular GPU ring.
2661 * Returns 0 if successful, else propagates up the lower layer error.
2664 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2665 struct intel_ring_buffer *to)
2667 struct intel_ring_buffer *from = obj->ring;
2671 if (from == NULL || to == from)
2674 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2675 return i915_gem_object_wait_rendering(obj, false);
2677 idx = intel_ring_sync_index(from, to);
2679 seqno = obj->last_read_seqno;
2680 if (seqno <= from->sync_seqno[idx])
2683 ret = i915_gem_check_olr(obj->ring, seqno);
2687 ret = to->sync_to(to, from, seqno);
2689 /* We use last_read_seqno because sync_to()
2690 * might have just caused seqno wrap under
2693 from->sync_seqno[idx] = obj->last_read_seqno;
2698 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2700 u32 old_write_domain, old_read_domains;
2702 /* Act a barrier for all accesses through the GTT */
2705 /* Force a pagefault for domain tracking on next user access */
2706 i915_gem_release_mmap(obj);
2708 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2711 old_read_domains = obj->base.read_domains;
2712 old_write_domain = obj->base.write_domain;
2714 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2715 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2717 CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
2718 obj, old_read_domains, old_write_domain);
2722 * Unbinds an object from the GTT aperture.
2725 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2727 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2730 if (obj->gtt_space == NULL)
2736 BUG_ON(obj->pages == NULL);
2738 ret = i915_gem_object_finish_gpu(obj);
2741 /* Continue on if we fail due to EIO, the GPU is hung so we
2742 * should be safe and we need to cleanup or else we might
2743 * cause memory corruption through use-after-free.
2746 i915_gem_object_finish_gtt(obj);
2748 /* release the fence reg _after_ flushing */
2749 ret = i915_gem_object_put_fence(obj);
2753 if (obj->has_global_gtt_mapping)
2754 i915_gem_gtt_unbind_object(obj);
2755 if (obj->has_aliasing_ppgtt_mapping) {
2756 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2757 obj->has_aliasing_ppgtt_mapping = 0;
2759 i915_gem_gtt_finish_object(obj);
2761 list_del(&obj->mm_list);
2762 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2763 /* Avoid an unnecessary call to unbind on rebind. */
2764 obj->map_and_fenceable = true;
2766 drm_mm_put_block(obj->gtt_space);
2767 obj->gtt_space = NULL;
2768 obj->gtt_offset = 0;
2773 int i915_gpu_idle(struct drm_device *dev)
2775 drm_i915_private_t *dev_priv = dev->dev_private;
2776 struct intel_ring_buffer *ring;
2779 /* Flush everything onto the inactive list. */
2780 for_each_ring(ring, dev_priv, i) {
2781 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2785 ret = intel_ring_idle(ring);
2793 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2794 struct drm_i915_gem_object *obj)
2796 drm_i915_private_t *dev_priv = dev->dev_private;
2800 u32 size = obj->gtt_space->size;
2802 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2804 val |= obj->gtt_offset & 0xfffff000;
2805 val |= (uint64_t)((obj->stride / 128) - 1) <<
2806 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2808 if (obj->tiling_mode == I915_TILING_Y)
2809 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2810 val |= I965_FENCE_REG_VALID;
2814 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2815 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2818 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2819 struct drm_i915_gem_object *obj)
2821 drm_i915_private_t *dev_priv = dev->dev_private;
2825 u32 size = obj->gtt_space->size;
2827 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2829 val |= obj->gtt_offset & 0xfffff000;
2830 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2831 if (obj->tiling_mode == I915_TILING_Y)
2832 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2833 val |= I965_FENCE_REG_VALID;
2837 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2838 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2841 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2842 struct drm_i915_gem_object *obj)
2844 drm_i915_private_t *dev_priv = dev->dev_private;
2848 u32 size = obj->gtt_space->size;
2852 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2853 (size & -size) != size ||
2854 (obj->gtt_offset & (size - 1)),
2855 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2856 obj->gtt_offset, obj->map_and_fenceable, size);
2858 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2863 /* Note: pitch better be a power of two tile widths */
2864 pitch_val = obj->stride / tile_width;
2865 pitch_val = ffs(pitch_val) - 1;
2867 val = obj->gtt_offset;
2868 if (obj->tiling_mode == I915_TILING_Y)
2869 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2870 val |= I915_FENCE_SIZE_BITS(size);
2871 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2872 val |= I830_FENCE_REG_VALID;
2877 reg = FENCE_REG_830_0 + reg * 4;
2879 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2881 I915_WRITE(reg, val);
2885 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2886 struct drm_i915_gem_object *obj)
2888 drm_i915_private_t *dev_priv = dev->dev_private;
2892 u32 size = obj->gtt_space->size;
2895 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2896 (size & -size) != size ||
2897 (obj->gtt_offset & (size - 1)),
2898 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2899 obj->gtt_offset, size);
2901 pitch_val = obj->stride / 128;
2902 pitch_val = ffs(pitch_val) - 1;
2904 val = obj->gtt_offset;
2905 if (obj->tiling_mode == I915_TILING_Y)
2906 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2907 val |= I830_FENCE_SIZE_BITS(size);
2908 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2909 val |= I830_FENCE_REG_VALID;
2913 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2914 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2917 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2918 struct drm_i915_gem_object *obj)
2920 switch (INTEL_INFO(dev)->gen) {
2922 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2924 case 4: i965_write_fence_reg(dev, reg, obj); break;
2925 case 3: i915_write_fence_reg(dev, reg, obj); break;
2926 case 2: i830_write_fence_reg(dev, reg, obj); break;
2931 static inline int fence_number(struct drm_i915_private *dev_priv,
2932 struct drm_i915_fence_reg *fence)
2934 return fence - dev_priv->fence_regs;
2937 static void i915_gem_write_fence__ipi(void *data)
2942 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2943 struct drm_i915_fence_reg *fence,
2946 struct drm_device *dev = obj->base.dev;
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948 int fence_reg = fence_number(dev_priv, fence);
2950 /* In order to fully serialize access to the fenced region and
2951 * the update to the fence register we need to take extreme
2952 * measures on SNB+. In theory, the write to the fence register
2953 * flushes all memory transactions before, and coupled with the
2954 * mb() placed around the register write we serialise all memory
2955 * operations with respect to the changes in the tiler. Yet, on
2956 * SNB+ we need to take a step further and emit an explicit wbinvd()
2957 * on each processor in order to manually flush all memory
2958 * transactions before updating the fence register.
2960 if (HAS_LLC(obj->base.dev))
2961 on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
2962 i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
2965 obj->fence_reg = fence_reg;
2967 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2969 obj->fence_reg = I915_FENCE_REG_NONE;
2971 list_del_init(&fence->lru_list);
2976 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2978 if (obj->last_fenced_seqno) {
2979 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2983 obj->last_fenced_seqno = 0;
2986 /* Ensure that all CPU reads are completed before installing a fence
2987 * and all writes before removing the fence.
2989 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2992 obj->fenced_gpu_access = false;
2997 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2999 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3002 ret = i915_gem_object_flush_fence(obj);
3006 if (obj->fence_reg == I915_FENCE_REG_NONE)
3009 i915_gem_object_update_fence(obj,
3010 &dev_priv->fence_regs[obj->fence_reg],
3012 i915_gem_object_fence_lost(obj);
3017 static struct drm_i915_fence_reg *
3018 i915_find_fence_reg(struct drm_device *dev)
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 struct drm_i915_fence_reg *reg, *avail;
3024 /* First try to find a free reg */
3026 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3027 reg = &dev_priv->fence_regs[i];
3031 if (!reg->pin_count)
3038 /* None available, try to steal one or wait for a user to finish */
3039 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3050 * i915_gem_object_get_fence - set up fencing for an object
3051 * @obj: object to map through a fence reg
3053 * When mapping objects through the GTT, userspace wants to be able to write
3054 * to them without having to worry about swizzling if the object is tiled.
3055 * This function walks the fence regs looking for a free one for @obj,
3056 * stealing one if it can't find any.
3058 * It then sets up the reg based on the object's properties: address, pitch
3059 * and tiling format.
3061 * For an untiled surface, this removes any existing fence.
3064 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3066 struct drm_device *dev = obj->base.dev;
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 bool enable = obj->tiling_mode != I915_TILING_NONE;
3069 struct drm_i915_fence_reg *reg;
3072 /* Have we updated the tiling parameters upon the object and so
3073 * will need to serialise the write to the associated fence register?
3075 if (obj->fence_dirty) {
3076 ret = i915_gem_object_flush_fence(obj);
3081 /* Just update our place in the LRU if our fence is getting reused. */
3082 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3083 reg = &dev_priv->fence_regs[obj->fence_reg];
3084 if (!obj->fence_dirty) {
3085 list_move_tail(®->lru_list,
3086 &dev_priv->mm.fence_list);
3089 } else if (enable) {
3090 reg = i915_find_fence_reg(dev);
3095 struct drm_i915_gem_object *old = reg->obj;
3097 ret = i915_gem_object_flush_fence(old);
3101 i915_gem_object_fence_lost(old);
3106 i915_gem_object_update_fence(obj, reg, enable);
3107 obj->fence_dirty = false;
3112 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3113 struct drm_mm_node *gtt_space,
3114 unsigned long cache_level)
3116 struct drm_mm_node *other;
3118 /* On non-LLC machines we have to be careful when putting differing
3119 * types of snoopable memory together to avoid the prefetcher
3120 * crossing memory domains and dying.
3125 if (gtt_space == NULL)
3128 if (list_empty(>t_space->node_list))
3131 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3132 if (other->allocated && !other->hole_follows && other->color != cache_level)
3135 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3136 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3142 static void i915_gem_verify_gtt(struct drm_device *dev)
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 struct drm_i915_gem_object *obj;
3149 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
3150 if (obj->gtt_space == NULL) {
3151 DRM_ERROR("object found on GTT list with no space reserved\n");
3156 if (obj->cache_level != obj->gtt_space->color) {
3157 DRM_ERROR("object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3158 obj->gtt_space->start,
3159 obj->gtt_space->start + obj->gtt_space->size,
3161 obj->gtt_space->color);
3166 if (!i915_gem_valid_gtt_space(dev,
3168 obj->cache_level)) {
3169 DRM_ERROR("invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3170 obj->gtt_space->start,
3171 obj->gtt_space->start + obj->gtt_space->size,
3183 * Finds free space in the GTT aperture and binds the object there.
3186 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3188 bool map_and_fenceable,
3191 struct drm_device *dev = obj->base.dev;
3192 drm_i915_private_t *dev_priv = dev->dev_private;
3193 struct drm_mm_node *node;
3194 u32 size, fence_size, fence_alignment, unfenced_alignment;
3195 bool mappable, fenceable;
3198 if (obj->madv != I915_MADV_WILLNEED) {
3199 DRM_ERROR("Attempting to bind a purgeable object\n");
3203 fence_size = i915_gem_get_gtt_size(dev,
3206 fence_alignment = i915_gem_get_gtt_alignment(dev,
3209 unfenced_alignment =
3210 i915_gem_get_unfenced_gtt_alignment(dev,
3215 alignment = map_and_fenceable ? fence_alignment :
3217 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3218 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3222 size = map_and_fenceable ? fence_size : obj->base.size;
3224 /* If the object is bigger than the entire aperture, reject it early
3225 * before evicting everything in a vain attempt to find space.
3227 if (obj->base.size >
3228 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
3229 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
3233 ret = i915_gem_object_get_pages(obj);
3237 i915_gem_object_pin_pages(obj);
3239 node = malloc(sizeof(*node), DRM_MEM_MM, M_NOWAIT | M_ZERO);
3241 i915_gem_object_unpin_pages(obj);
3246 if (map_and_fenceable)
3247 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3248 size, alignment, obj->cache_level,
3249 0, dev_priv->mm.gtt_mappable_end);
3251 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
3252 size, alignment, obj->cache_level);
3254 ret = i915_gem_evict_something(dev, size, alignment,
3261 i915_gem_object_unpin_pages(obj);
3262 free(node, DRM_MEM_MM);
3265 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3266 i915_gem_object_unpin_pages(obj);
3267 drm_mm_put_block(node);
3271 ret = i915_gem_gtt_prepare_object(obj);
3273 i915_gem_object_unpin_pages(obj);
3274 drm_mm_put_block(node);
3278 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
3279 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3281 obj->gtt_space = node;
3282 obj->gtt_offset = node->start;
3285 node->size == fence_size &&
3286 (node->start & (fence_alignment - 1)) == 0;
3289 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3291 obj->map_and_fenceable = mappable && fenceable;
3293 i915_gem_object_unpin_pages(obj);
3294 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
3295 obj->base.size, map_and_fenceable);
3296 i915_gem_verify_gtt(dev);
3301 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3303 /* If we don't have a page list set up, then we're not pinned
3304 * to GPU, and we can ignore the cache flush because it'll happen
3305 * again at bind time.
3307 if (obj->pages == NULL)
3310 /* If the GPU is snooping the contents of the CPU cache,
3311 * we do not need to manually clear the CPU cache lines. However,
3312 * the caches are only snooped when the render cache is
3313 * flushed/invalidated. As we always have to emit invalidations
3314 * and flushes when moving into and out of the RENDER domain, correct
3315 * snooping behaviour occurs naturally as the result of our domain
3318 if (obj->cache_level != I915_CACHE_NONE)
3321 CTR1(KTR_DRM, "object_clflush %p", obj);
3323 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3326 /** Flushes the GTT write domain for the object if it's dirty. */
3328 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3330 uint32_t old_write_domain;
3332 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3335 /* No actual flushing is required for the GTT write domain. Writes
3336 * to it immediately go to main memory as far as we know, so there's
3337 * no chipset flush. It also doesn't land in render cache.
3339 * However, we do have to enforce the order so that all writes through
3340 * the GTT land before any writes to the device, such as updates to
3345 old_write_domain = obj->base.write_domain;
3346 obj->base.write_domain = 0;
3348 CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj,
3349 obj->base.read_domains, old_write_domain);
3352 /** Flushes the CPU write domain for the object if it's dirty. */
3354 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3356 uint32_t old_write_domain;
3358 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3361 i915_gem_clflush_object(obj);
3362 i915_gem_chipset_flush(obj->base.dev);
3363 old_write_domain = obj->base.write_domain;
3364 obj->base.write_domain = 0;
3366 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
3367 obj->base.read_domains, old_write_domain);
3371 * Moves a single object to the GTT read, and possibly write domain.
3373 * This function returns when the move is complete, including waiting on
3377 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3379 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3380 uint32_t old_write_domain, old_read_domains;
3383 /* Not valid to be called on unbound objects. */
3384 if (obj->gtt_space == NULL)
3387 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3390 ret = i915_gem_object_wait_rendering(obj, !write);
3394 i915_gem_object_flush_cpu_write_domain(obj);
3396 old_write_domain = obj->base.write_domain;
3397 old_read_domains = obj->base.read_domains;
3399 /* It should now be out of any other write domains, and we can update
3400 * the domain values for our changes.
3402 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3403 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3405 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3406 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3410 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,
3411 old_read_domains, old_write_domain);
3413 /* And bump the LRU for this access */
3414 if (i915_gem_object_is_inactive(obj))
3415 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3420 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3421 enum i915_cache_level cache_level)
3423 struct drm_device *dev = obj->base.dev;
3424 drm_i915_private_t *dev_priv = dev->dev_private;
3427 if (obj->cache_level == cache_level)
3430 if (obj->pin_count) {
3431 DRM_DEBUG("can not change the cache level of pinned objects\n");
3435 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3436 ret = i915_gem_object_unbind(obj);
3441 if (obj->gtt_space) {
3442 ret = i915_gem_object_finish_gpu(obj);
3446 i915_gem_object_finish_gtt(obj);
3448 /* Before SandyBridge, you could not use tiling or fence
3449 * registers with snooped memory, so relinquish any fences
3450 * currently pointing to our region in the aperture.
3452 if (INTEL_INFO(dev)->gen < 6) {
3453 ret = i915_gem_object_put_fence(obj);
3458 if (obj->has_global_gtt_mapping)
3459 i915_gem_gtt_bind_object(obj, cache_level);
3460 if (obj->has_aliasing_ppgtt_mapping)
3461 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3464 obj->gtt_space->color = cache_level;
3467 if (cache_level == I915_CACHE_NONE) {
3468 u32 old_read_domains, old_write_domain;
3470 /* If we're coming from LLC cached, then we haven't
3471 * actually been tracking whether the data is in the
3472 * CPU cache or not, since we only allow one bit set
3473 * in obj->write_domain and have been skipping the clflushes.
3474 * Just set it to the CPU cache for now.
3476 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3477 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3479 old_read_domains = obj->base.read_domains;
3480 old_write_domain = obj->base.write_domain;
3482 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3483 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3485 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
3486 obj, old_read_domains, old_write_domain);
3489 obj->cache_level = cache_level;
3490 i915_gem_verify_gtt(dev);
3494 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3495 struct drm_file *file)
3497 struct drm_i915_gem_caching *args = data;
3498 struct drm_i915_gem_object *obj;
3501 ret = i915_mutex_lock_interruptible(dev);
3505 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3506 if (&obj->base == NULL) {
3511 args->caching = obj->cache_level != I915_CACHE_NONE;
3513 drm_gem_object_unreference(&obj->base);
3519 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3520 struct drm_file *file)
3522 struct drm_i915_gem_caching *args = data;
3523 struct drm_i915_gem_object *obj;
3524 enum i915_cache_level level;
3527 switch (args->caching) {
3528 case I915_CACHING_NONE:
3529 level = I915_CACHE_NONE;
3531 case I915_CACHING_CACHED:
3532 level = I915_CACHE_LLC;
3538 ret = i915_mutex_lock_interruptible(dev);
3542 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3543 if (&obj->base == NULL) {
3548 ret = i915_gem_object_set_cache_level(obj, level);
3550 drm_gem_object_unreference(&obj->base);
3556 static bool is_pin_display(struct drm_i915_gem_object *obj)
3558 /* There are 3 sources that pin objects:
3559 * 1. The display engine (scanouts, sprites, cursors);
3560 * 2. Reservations for execbuffer;
3563 * We can ignore reservations as we hold the struct_mutex and
3564 * are only called outside of the reservation path. The user
3565 * can only increment pin_count once, and so if after
3566 * subtracting the potential reference by the user, any pin_count
3567 * remains, it must be due to another use by the display engine.
3569 return obj->pin_count - !!obj->user_pin_count;
3573 * Prepare buffer for display plane (scanout, cursors, etc).
3574 * Can be called from an uninterruptible phase (modesetting) and allows
3575 * any flushes to be pipelined (for pageflips).
3578 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3580 struct intel_ring_buffer *pipelined)
3582 u32 old_read_domains, old_write_domain;
3585 if (pipelined != obj->ring) {
3586 ret = i915_gem_object_sync(obj, pipelined);
3591 /* Mark the pin_display early so that we account for the
3592 * display coherency whilst setting up the cache domains.
3594 obj->pin_display = true;
3596 /* The display engine is not coherent with the LLC cache on gen6. As
3597 * a result, we make sure that the pinning that is about to occur is
3598 * done with uncached PTEs. This is lowest common denominator for all
3601 * However for gen6+, we could do better by using the GFDT bit instead
3602 * of uncaching, which would allow us to flush all the LLC-cached data
3603 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3605 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3607 goto err_unpin_display;
3609 /* As the user may map the buffer once pinned in the display plane
3610 * (e.g. libkms for the bootup splash), we have to ensure that we
3611 * always use map_and_fenceable for all scanout buffers.
3613 ret = i915_gem_object_pin(obj, alignment, true, false);
3615 goto err_unpin_display;
3617 i915_gem_object_flush_cpu_write_domain(obj);
3619 old_write_domain = obj->base.write_domain;
3620 old_read_domains = obj->base.read_domains;
3622 /* It should now be out of any other write domains, and we can update
3623 * the domain values for our changes.
3625 obj->base.write_domain = 0;
3626 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3628 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
3629 obj, old_read_domains, old_write_domain);
3634 obj->pin_display = is_pin_display(obj);
3639 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3641 i915_gem_object_unpin(obj);
3642 obj->pin_display = is_pin_display(obj);
3646 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3650 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3653 ret = i915_gem_object_wait_rendering(obj, false);
3657 /* Ensure that we invalidate the GPU's caches and TLBs. */
3658 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3663 * Moves a single object to the CPU read, and possibly write domain.
3665 * This function returns when the move is complete, including waiting on
3669 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3671 uint32_t old_write_domain, old_read_domains;
3674 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3677 ret = i915_gem_object_wait_rendering(obj, !write);
3681 i915_gem_object_flush_gtt_write_domain(obj);
3683 old_write_domain = obj->base.write_domain;
3684 old_read_domains = obj->base.read_domains;
3686 /* Flush the CPU cache if it's still invalid. */
3687 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3688 i915_gem_clflush_object(obj);
3690 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3693 /* It should now be out of any other write domains, and we can update
3694 * the domain values for our changes.
3696 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3698 /* If we're writing through the CPU, then the GPU read domains will
3699 * need to be invalidated at next use.
3702 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3703 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3706 CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj,
3707 old_read_domains, old_write_domain);
3712 /* Throttle our rendering by waiting until the ring has completed our requests
3713 * emitted over 20 msec ago.
3715 * Note that if we were to use the current jiffies each time around the loop,
3716 * we wouldn't escape the function with any frames outstanding if the time to
3717 * render a frame was over 20ms.
3719 * This should get us reasonable parallelism between CPU and GPU but also
3720 * relatively low latency when blocking on a particular request to finish.
3723 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 struct drm_i915_file_private *file_priv = file->driver_priv;
3727 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3728 struct drm_i915_gem_request *request;
3729 struct intel_ring_buffer *ring = NULL;
3733 if (atomic_read(&dev_priv->mm.wedged))
3736 mtx_lock(&file_priv->mm.lock);
3737 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3738 if (time_after_eq(request->emitted_jiffies, recent_enough))
3741 ring = request->ring;
3742 seqno = request->seqno;
3744 mtx_unlock(&file_priv->mm.lock);
3749 ret = __wait_seqno(ring, seqno, true, NULL);
3751 taskqueue_enqueue_timeout(dev_priv->wq,
3752 &dev_priv->mm.retire_work, 0);
3758 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3760 bool map_and_fenceable,
3765 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3768 if (obj->gtt_space != NULL) {
3769 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3770 (map_and_fenceable && !obj->map_and_fenceable)) {
3771 WARN(obj->pin_count,
3772 "bo is already pinned with incorrect alignment:"
3773 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3774 " obj->map_and_fenceable=%d\n",
3775 obj->gtt_offset, alignment,
3777 obj->map_and_fenceable);
3778 ret = i915_gem_object_unbind(obj);
3784 if (obj->gtt_space == NULL) {
3785 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3787 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3793 if (!dev_priv->mm.aliasing_ppgtt)
3794 i915_gem_gtt_bind_object(obj, obj->cache_level);
3797 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3798 i915_gem_gtt_bind_object(obj, obj->cache_level);
3801 obj->pin_mappable |= map_and_fenceable;
3807 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3809 BUG_ON(obj->pin_count == 0);
3810 BUG_ON(obj->gtt_space == NULL);
3812 if (--obj->pin_count == 0)
3813 obj->pin_mappable = false;
3817 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3818 struct drm_file *file)
3820 struct drm_i915_gem_pin *args = data;
3821 struct drm_i915_gem_object *obj;
3824 ret = i915_mutex_lock_interruptible(dev);
3828 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3829 if (&obj->base == NULL) {
3834 if (obj->madv != I915_MADV_WILLNEED) {
3835 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3840 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3841 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3847 if (obj->user_pin_count == 0) {
3848 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3853 obj->user_pin_count++;
3854 obj->pin_filp = file;
3856 /* XXX - flush the CPU caches for pinned objects
3857 * as the X server doesn't manage domains yet
3859 i915_gem_object_flush_cpu_write_domain(obj);
3860 args->offset = obj->gtt_offset;
3862 drm_gem_object_unreference(&obj->base);
3869 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3870 struct drm_file *file)
3872 struct drm_i915_gem_pin *args = data;
3873 struct drm_i915_gem_object *obj;
3876 ret = i915_mutex_lock_interruptible(dev);
3880 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3881 if (&obj->base == NULL) {
3886 if (obj->pin_filp != file) {
3887 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3892 obj->user_pin_count--;
3893 if (obj->user_pin_count == 0) {
3894 obj->pin_filp = NULL;
3895 i915_gem_object_unpin(obj);
3899 drm_gem_object_unreference(&obj->base);
3906 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3907 struct drm_file *file)
3909 struct drm_i915_gem_busy *args = data;
3910 struct drm_i915_gem_object *obj;
3913 ret = i915_mutex_lock_interruptible(dev);
3917 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3918 if (&obj->base == NULL) {
3923 /* Count all active objects as busy, even if they are currently not used
3924 * by the gpu. Users of this interface expect objects to eventually
3925 * become non-busy without any further actions, therefore emit any
3926 * necessary flushes here.
3928 ret = i915_gem_object_flush_active(obj);
3930 args->busy = obj->active;
3932 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3933 args->busy |= intel_ring_flag(obj->ring) << 16;
3936 drm_gem_object_unreference(&obj->base);
3943 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3944 struct drm_file *file_priv)
3946 return i915_gem_ring_throttle(dev, file_priv);
3950 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3951 struct drm_file *file_priv)
3953 struct drm_i915_gem_madvise *args = data;
3954 struct drm_i915_gem_object *obj;
3957 switch (args->madv) {
3958 case I915_MADV_DONTNEED:
3959 case I915_MADV_WILLNEED:
3965 ret = i915_mutex_lock_interruptible(dev);
3969 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3970 if (&obj->base == NULL) {
3975 if (obj->pin_count) {
3980 if (obj->madv != __I915_MADV_PURGED)
3981 obj->madv = args->madv;
3983 /* if the object is no longer attached, discard its backing storage */
3984 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3985 i915_gem_object_truncate(obj);
3987 args->retained = obj->madv != __I915_MADV_PURGED;
3990 drm_gem_object_unreference(&obj->base);
3996 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3997 const struct drm_i915_gem_object_ops *ops)
3999 INIT_LIST_HEAD(&obj->mm_list);
4000 INIT_LIST_HEAD(&obj->gtt_list);
4001 INIT_LIST_HEAD(&obj->ring_list);
4002 INIT_LIST_HEAD(&obj->exec_list);
4006 obj->fence_reg = I915_FENCE_REG_NONE;
4007 obj->madv = I915_MADV_WILLNEED;
4008 /* Avoid an unnecessary call to unbind on the first bind. */
4009 obj->map_and_fenceable = true;
4011 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4014 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4015 .get_pages = i915_gem_object_get_pages_gtt,
4016 .put_pages = i915_gem_object_put_pages_gtt,
4019 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4022 struct drm_i915_gem_object *obj;
4024 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
4028 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4029 free(obj, DRM_I915_GEM);
4034 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4035 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4036 /* 965gm cannot relocate objects above 4GiB. */
4037 mask &= ~__GFP_HIGHMEM;
4038 mask |= __GFP_DMA32;
4041 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4042 mapping_set_gfp_mask(mapping, mask);
4043 #endif /* FREEBSD_WIP */
4045 i915_gem_object_init(obj, &i915_gem_object_ops);
4047 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4048 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4051 /* On some devices, we can have the GPU use the LLC (the CPU
4052 * cache) for about a 10% performance improvement
4053 * compared to uncached. Graphics requests other than
4054 * display scanout are coherent with the CPU in
4055 * accessing this cache. This means in this mode we
4056 * don't need to clflush on the CPU side, and on the
4057 * GPU side we only need to flush internal caches to
4058 * get data visible to the CPU.
4060 * However, we maintain the display planes as UC, and so
4061 * need to rebind when first used as such.
4063 obj->cache_level = I915_CACHE_LLC;
4065 obj->cache_level = I915_CACHE_NONE;
4070 int i915_gem_init_object(struct drm_gem_object *obj)
4072 printf("i915_gem_init_object called\n");
4077 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4079 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4080 struct drm_device *dev = obj->base.dev;
4081 drm_i915_private_t *dev_priv = dev->dev_private;
4083 CTR1(KTR_DRM, "object_destroy_tail %p", obj);
4086 i915_gem_detach_phys_object(dev, obj);
4089 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
4090 bool was_interruptible;
4092 was_interruptible = dev_priv->mm.interruptible;
4093 dev_priv->mm.interruptible = false;
4095 WARN_ON(i915_gem_object_unbind(obj));
4097 dev_priv->mm.interruptible = was_interruptible;
4100 obj->pages_pin_count = 0;
4101 i915_gem_object_put_pages(obj);
4102 i915_gem_object_free_mmap_offset(obj);
4107 if (obj->base.import_attach)
4108 drm_prime_gem_destroy(&obj->base, NULL);
4109 #endif /* FREEBSD_WIP */
4111 drm_gem_object_release(&obj->base);
4112 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4114 free(obj->bit_17, DRM_I915_GEM);
4115 free(obj, DRM_I915_GEM);
4119 i915_gem_idle(struct drm_device *dev)
4121 drm_i915_private_t *dev_priv = dev->dev_private;
4126 if (dev_priv->mm.suspended) {
4131 ret = i915_gpu_idle(dev);
4136 i915_gem_retire_requests(dev);
4138 /* Under UMS, be paranoid and evict. */
4139 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4140 i915_gem_evict_everything(dev);
4142 i915_gem_reset_fences(dev);
4144 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4145 * We need to replace this with a semaphore, or something.
4146 * And not confound mm.suspended!
4148 dev_priv->mm.suspended = 1;
4149 callout_stop(&dev_priv->hangcheck_timer);
4151 i915_kernel_lost_context(dev);
4152 i915_gem_cleanup_ringbuffer(dev);
4156 /* Cancel the retire work handler, which should be idle now. */
4157 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->mm.retire_work, NULL);
4162 void i915_gem_l3_remap(struct drm_device *dev)
4164 drm_i915_private_t *dev_priv = dev->dev_private;
4168 if (!HAS_L3_GPU_CACHE(dev))
4171 if (!dev_priv->l3_parity.remap_info)
4174 misccpctl = I915_READ(GEN7_MISCCPCTL);
4175 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4176 POSTING_READ(GEN7_MISCCPCTL);
4178 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4179 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4180 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4181 DRM_DEBUG("0x%x was already programmed to %x\n",
4182 GEN7_L3LOG_BASE + i, remap);
4183 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4184 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4185 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4188 /* Make sure all the writes land before disabling dop clock gating */
4189 POSTING_READ(GEN7_L3LOG_BASE);
4191 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4194 void i915_gem_init_swizzling(struct drm_device *dev)
4196 drm_i915_private_t *dev_priv = dev->dev_private;
4198 if (INTEL_INFO(dev)->gen < 5 ||
4199 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4202 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4203 DISP_TILE_SURFACE_SWIZZLING);
4208 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4210 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4212 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4216 intel_enable_blt(struct drm_device *dev)
4221 /* The blitter was dysfunctional on early prototypes */
4222 if (IS_GEN6(dev) && pci_get_revid(dev->dev) < 8) {
4223 DRM_INFO("BLT not supported on this pre-production hardware;"
4224 " graphics performance will be degraded.\n");
4232 i915_gem_init_hw(struct drm_device *dev)
4234 drm_i915_private_t *dev_priv = dev->dev_private;
4238 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4240 #endif /* FREEBSD_WIP */
4242 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4243 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4245 i915_gem_l3_remap(dev);
4247 i915_gem_init_swizzling(dev);
4249 ret = intel_init_render_ring_buffer(dev);
4254 ret = intel_init_bsd_ring_buffer(dev);
4256 goto cleanup_render_ring;
4259 if (intel_enable_blt(dev)) {
4260 ret = intel_init_blt_ring_buffer(dev);
4262 goto cleanup_bsd_ring;
4265 dev_priv->next_seqno = 1;
4268 * XXX: There was some w/a described somewhere suggesting loading
4269 * contexts before PPGTT.
4271 i915_gem_context_init(dev);
4272 i915_gem_init_ppgtt(dev);
4277 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4278 cleanup_render_ring:
4279 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4284 intel_enable_ppgtt(struct drm_device *dev)
4286 if (i915_enable_ppgtt >= 0)
4287 return i915_enable_ppgtt;
4289 #ifdef CONFIG_INTEL_IOMMU
4290 /* Disable ppgtt on SNB if VT-d is on. */
4291 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
4298 int i915_gem_init(struct drm_device *dev)
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 unsigned long gtt_size, mappable_size;
4304 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
4305 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
4308 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
4309 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4310 * aperture accordingly when using aliasing ppgtt. */
4311 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4313 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4315 ret = i915_gem_init_aliasing_ppgtt(dev);
4321 /* Let GEM Manage all of the aperture.
4323 * However, leave one page at the end still bound to the scratch
4324 * page. There are a number of places where the hardware
4325 * apparently prefetches past the end of the object, and we've
4326 * seen multiple hangs with the GPU head pointer stuck in a
4327 * batchbuffer bound at the last page of the aperture. One page
4328 * should be enough to keep any prefetching inside of the
4331 i915_gem_init_global_gtt(dev, 0, mappable_size,
4335 ret = i915_gem_init_hw(dev);
4338 i915_gem_cleanup_aliasing_ppgtt(dev);
4342 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4343 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4344 dev_priv->dri1.allow_batchbuffer = 1;
4349 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4351 drm_i915_private_t *dev_priv = dev->dev_private;
4352 struct intel_ring_buffer *ring;
4355 for_each_ring(ring, dev_priv, i)
4356 intel_cleanup_ring_buffer(ring);
4360 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4361 struct drm_file *file_priv)
4363 drm_i915_private_t *dev_priv = dev->dev_private;
4366 if (drm_core_check_feature(dev, DRIVER_MODESET))
4369 if (atomic_read(&dev_priv->mm.wedged)) {
4370 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4371 atomic_set(&dev_priv->mm.wedged, 0);
4375 dev_priv->mm.suspended = 0;
4377 ret = i915_gem_init_hw(dev);
4383 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4386 ret = drm_irq_install(dev);
4388 goto cleanup_ringbuffer;
4394 i915_gem_cleanup_ringbuffer(dev);
4395 dev_priv->mm.suspended = 1;
4402 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4403 struct drm_file *file_priv)
4405 if (drm_core_check_feature(dev, DRIVER_MODESET))
4408 drm_irq_uninstall(dev);
4409 return i915_gem_idle(dev);
4413 i915_gem_lastclose(struct drm_device *dev)
4417 if (drm_core_check_feature(dev, DRIVER_MODESET))
4420 ret = i915_gem_idle(dev);
4422 DRM_ERROR("failed to idle hardware: %d\n", ret);
4426 init_ring_lists(struct intel_ring_buffer *ring)
4428 INIT_LIST_HEAD(&ring->active_list);
4429 INIT_LIST_HEAD(&ring->request_list);
4433 i915_gem_load(struct drm_device *dev)
4436 drm_i915_private_t *dev_priv = dev->dev_private;
4438 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4439 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4440 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4441 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4442 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4443 for (i = 0; i < I915_NUM_RINGS; i++)
4444 init_ring_lists(&dev_priv->ring[i]);
4445 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4446 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4447 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->mm.retire_work, 0,
4448 i915_gem_retire_work_handler, dev_priv);
4449 init_completion(&dev_priv->error_completion);
4451 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4453 I915_WRITE(MI_ARB_STATE,
4454 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4457 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4459 /* Old X drivers will take 0-2 for front, back, depth buffers */
4460 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4461 dev_priv->fence_reg_start = 3;
4463 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4464 dev_priv->num_fence_regs = 16;
4466 dev_priv->num_fence_regs = 8;
4468 /* Initialize fence registers to zero */
4469 i915_gem_reset_fences(dev);
4471 i915_gem_detect_bit_6_swizzle(dev);
4472 DRM_INIT_WAITQUEUE(&dev_priv->pending_flip_queue);
4474 dev_priv->mm.interruptible = true;
4476 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4477 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY);
4481 * Create a physically contiguous memory object for this object
4482 * e.g. for cursor + overlay regs
4484 static int i915_gem_init_phys_object(struct drm_device *dev,
4485 int id, int size, int align)
4487 drm_i915_private_t *dev_priv = dev->dev_private;
4488 struct drm_i915_gem_phys_object *phys_obj;
4491 if (dev_priv->mm.phys_objs[id - 1] || !size)
4494 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object),
4495 DRM_I915_GEM, M_WAITOK | M_ZERO);
4501 phys_obj->handle = drm_pci_alloc(dev, size, align, BUS_SPACE_MAXADDR);
4502 if (!phys_obj->handle) {
4507 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4508 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4511 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4515 free(phys_obj, DRM_I915_GEM);
4519 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4521 drm_i915_private_t *dev_priv = dev->dev_private;
4522 struct drm_i915_gem_phys_object *phys_obj;
4524 if (!dev_priv->mm.phys_objs[id - 1])
4527 phys_obj = dev_priv->mm.phys_objs[id - 1];
4528 if (phys_obj->cur_obj) {
4529 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4534 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4536 #endif /* FREEBSD_WIP */
4538 drm_pci_free(dev, phys_obj->handle);
4539 free(phys_obj, DRM_I915_GEM);
4540 dev_priv->mm.phys_objs[id - 1] = NULL;
4543 void i915_gem_free_all_phys_object(struct drm_device *dev)
4547 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4548 i915_gem_free_phys_object(dev, i);
4551 void i915_gem_detach_phys_object(struct drm_device *dev,
4552 struct drm_i915_gem_object *obj)
4562 vaddr = obj->phys_obj->handle->vaddr;
4564 page_count = obj->base.size / PAGE_SIZE;
4565 VM_OBJECT_WLOCK(obj->base.vm_obj);
4566 for (i = 0; i < page_count; i++) {
4567 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4571 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4572 sf = sf_buf_alloc(page, 0);
4574 dst = (char *)sf_buf_kva(sf);
4575 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
4578 drm_clflush_pages(&page, 1);
4580 VM_OBJECT_WLOCK(obj->base.vm_obj);
4581 vm_page_reference(page);
4583 vm_page_dirty(page);
4584 vm_page_unwire(page, PQ_INACTIVE);
4585 vm_page_unlock(page);
4586 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4588 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4589 i915_gem_chipset_flush(dev);
4591 obj->phys_obj->cur_obj = NULL;
4592 obj->phys_obj = NULL;
4596 i915_gem_attach_phys_object(struct drm_device *dev,
4597 struct drm_i915_gem_object *obj,
4601 drm_i915_private_t *dev_priv = dev->dev_private;
4608 if (id > I915_MAX_PHYS_OBJECT)
4611 if (obj->phys_obj) {
4612 if (obj->phys_obj->id == id)
4614 i915_gem_detach_phys_object(dev, obj);
4617 /* create a new object */
4618 if (!dev_priv->mm.phys_objs[id - 1]) {
4619 ret = i915_gem_init_phys_object(dev, id,
4620 obj->base.size, align);
4622 DRM_ERROR("failed to init phys object %d size: %zu\n",
4623 id, obj->base.size);
4628 /* bind to the object */
4629 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4630 obj->phys_obj->cur_obj = obj;
4632 page_count = obj->base.size / PAGE_SIZE;
4634 VM_OBJECT_WLOCK(obj->base.vm_obj);
4635 for (i = 0; i < page_count; i++) {
4636 vm_page_t page = i915_gem_wire_page(obj->base.vm_obj, i, NULL);
4641 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4642 sf = sf_buf_alloc(page, 0);
4643 src = (char *)sf_buf_kva(sf);
4644 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
4645 memcpy(dst, src, PAGE_SIZE);
4648 VM_OBJECT_WLOCK(obj->base.vm_obj);
4650 vm_page_reference(page);
4652 vm_page_unwire(page, PQ_INACTIVE);
4653 vm_page_unlock(page);
4654 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
4656 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
4662 i915_gem_phys_pwrite(struct drm_device *dev,
4663 struct drm_i915_gem_object *obj,
4664 struct drm_i915_gem_pwrite *args,
4665 struct drm_file *file_priv)
4667 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4668 char __user *user_data = to_user_ptr(args->data_ptr);
4670 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4671 unsigned long unwritten;
4673 /* The physical object once assigned is fixed for the lifetime
4674 * of the obj, so we can safely drop the lock and continue
4678 unwritten = copy_from_user(vaddr, user_data, args->size);
4684 i915_gem_chipset_flush(dev);
4688 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4690 struct drm_i915_file_private *file_priv = file->driver_priv;
4692 /* Clean up our request list when the client is going away, so that
4693 * later retire_requests won't dereference our soon-to-be-gone
4696 mtx_lock(&file_priv->mm.lock);
4697 while (!list_empty(&file_priv->mm.request_list)) {
4698 struct drm_i915_gem_request *request;
4700 request = list_first_entry(&file_priv->mm.request_list,
4701 struct drm_i915_gem_request,
4703 list_del(&request->client_list);
4704 request->file_priv = NULL;
4706 mtx_unlock(&file_priv->mm.lock);
4710 i915_gem_inactive_shrink(void *arg)
4712 struct drm_device *dev = arg;
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4716 if (!sx_try_xlock(&dev->dev_struct_lock)) {
4720 CTR0(KTR_DRM, "gem_lowmem");
4722 pass1 = i915_gem_purge(dev_priv, -1);
4723 pass2 = __i915_gem_shrink(dev_priv, -1, false);
4725 if (pass2 <= pass1 / 100)
4726 i915_gem_shrink_all(dev_priv);
4732 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex, bool *fresh)
4737 VM_OBJECT_ASSERT_WLOCKED(object);
4738 page = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY |
4740 if (page->valid != VM_PAGE_BITS_ALL) {
4741 vm_page_xbusy(page);
4742 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
4743 rv = vm_pager_get_pages(object, &page, 1, NULL, NULL);
4744 if (rv != VM_PAGER_OK) {
4746 vm_page_unwire(page, PQ_NONE);
4748 vm_page_unlock(page);
4754 pmap_zero_page(page);
4755 page->valid = VM_PAGE_BITS_ALL;
4760 vm_page_xunbusy(page);
4761 } else if (fresh != NULL)
4763 atomic_add_long(&i915_gem_wired_pages_cnt, 1);