sys/dev/drm2/i915/i915_gem.c

   1 /*-
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Copyright (c) 2011 The FreeBSD Foundation
  27  * All rights reserved.
  28  *
  29  * This software was developed by Konstantin Belousov under sponsorship from
  30  * the FreeBSD Foundation.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  */
  53
  54 #include <sys/cdefs.h>
  55 __FBSDID("$FreeBSD$");
  56
  57 #include <dev/drm2/drmP.h>
  58 #include <dev/drm2/drm.h>
  59 #include <dev/drm2/i915/i915_drm.h>
  60 #include <dev/drm2/i915/i915_drv.h>
  61 #include <dev/drm2/i915/intel_drv.h>
  62 #include <dev/drm2/i915/intel_ringbuffer.h>
  63 #include <sys/resourcevar.h>
  64 #include <sys/sched.h>
  65 #include <sys/sf_buf.h>
  66
  67 #include <vm/vm.h>
  68 #include <vm/vm_pageout.h>
  69
  70 static void i915_gem_object_flush_cpu_write_domain(
  71     struct drm_i915_gem_object *obj);
  72 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
  73     int tiling_mode);
  74 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
  75     uint32_t size, int tiling_mode);
  76 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  77     unsigned alignment, bool map_and_fenceable);
  78 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
  79     int flags);
  80 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
  81 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  82     bool write);
  83 static void i915_gem_object_set_to_full_cpu_read_domain(
  84     struct drm_i915_gem_object *obj);
  85 static int i915_gem_object_set_cpu_read_domain_range(
  86     struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
  87 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
  88 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  89 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
  90 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
  91 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
  92 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
  93 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
  94     uint32_t flush_domains);
  95 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  96     struct drm_i915_fence_reg *reg);
  97 static void i915_gem_reset_fences(struct drm_device *dev);
  98 static void i915_gem_retire_task_handler(void *arg, int pending);
  99 static int i915_gem_phys_pwrite(struct drm_device *dev,
 100     struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
 101     uint64_t size, struct drm_file *file_priv);
 102 static void i915_gem_lowmem(void *arg);
 103
 104 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
 105 long i915_gem_wired_pages_cnt;
 106
 107 static void
 108 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
 109 {
 110
 111         dev_priv->mm.object_count++;
 112         dev_priv->mm.object_memory += size;
 113 }
 114
 115 static void
 116 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
 117 {
 118
 119         dev_priv->mm.object_count--;
 120         dev_priv->mm.object_memory -= size;
 121 }
 122
 123 static int
 124 i915_gem_wait_for_error(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv;
 127         int ret;
 128
 129         dev_priv = dev->dev_private;
 130         if (!atomic_load_acq_int(&dev_priv->mm.wedged))
 131                 return (0);
 132
 133         mtx_lock(&dev_priv->error_completion_lock);
 134         while (dev_priv->error_completion == 0) {
 135                 ret = -msleep(&dev_priv->error_completion,
 136                     &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
 137                 if (ret != 0) {
 138                         mtx_unlock(&dev_priv->error_completion_lock);
 139                         return (ret);
 140                 }
 141         }
 142         mtx_unlock(&dev_priv->error_completion_lock);
 143
 144         if (atomic_load_acq_int(&dev_priv->mm.wedged)) {
 145                 mtx_lock(&dev_priv->error_completion_lock);
 146                 dev_priv->error_completion++;
 147                 mtx_unlock(&dev_priv->error_completion_lock);
 148         }
 149         return (0);
 150 }
 151
 152 int
 153 i915_mutex_lock_interruptible(struct drm_device *dev)
 154 {
 155         struct drm_i915_private *dev_priv;
 156         int ret;
 157
 158         dev_priv = dev->dev_private;
 159         ret = i915_gem_wait_for_error(dev);
 160         if (ret != 0)
 161                 return (ret);
 162
 163         /*
 164          * interruptible shall it be. might indeed be if dev_lock is
 165          * changed to sx
 166          */
 167         ret = sx_xlock_sig(&dev->dev_struct_lock);
 168         if (ret != 0)
 169                 return (-ret);
 170
 171         return (0);
 172 }
 173
 174
 175 static void
 176 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 177 {
 178         struct drm_device *dev;
 179         drm_i915_private_t *dev_priv;
 180         int ret;
 181
 182         dev = obj->base.dev;
 183         dev_priv = dev->dev_private;
 184
 185         ret = i915_gem_object_unbind(obj);
 186         if (ret == -ERESTART) {
 187                 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
 188                 return;
 189         }
 190
 191         CTR1(KTR_DRM, "object_destroy_tail %p", obj);
 192         drm_gem_free_mmap_offset(&obj->base);
 193         drm_gem_object_release(&obj->base);
 194         i915_gem_info_remove_obj(dev_priv, obj->base.size);
 195
 196         free(obj->page_cpu_valid, DRM_I915_GEM);
 197         free(obj->bit_17, DRM_I915_GEM);
 198         free(obj, DRM_I915_GEM);
 199 }
 200
 201 void
 202 i915_gem_free_object(struct drm_gem_object *gem_obj)
 203 {
 204         struct drm_i915_gem_object *obj;
 205         struct drm_device *dev;
 206
 207         obj = to_intel_bo(gem_obj);
 208         dev = obj->base.dev;
 209
 210         while (obj->pin_count > 0)
 211                 i915_gem_object_unpin(obj);
 212
 213         if (obj->phys_obj != NULL)
 214                 i915_gem_detach_phys_object(dev, obj);
 215
 216         i915_gem_free_object_tail(obj);
 217 }
 218
 219 static void
 220 init_ring_lists(struct intel_ring_buffer *ring)
 221 {
 222
 223         INIT_LIST_HEAD(&ring->active_list);
 224         INIT_LIST_HEAD(&ring->request_list);
 225         INIT_LIST_HEAD(&ring->gpu_write_list);
 226 }
 227
 228 void
 229 i915_gem_load(struct drm_device *dev)
 230 {
 231         drm_i915_private_t *dev_priv;
 232         int i;
 233
 234         dev_priv = dev->dev_private;
 235
 236         INIT_LIST_HEAD(&dev_priv->mm.active_list);
 237         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
 238         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
 239         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
 240         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
 241         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
 242         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
 243         for (i = 0; i < I915_NUM_RINGS; i++)
 244                 init_ring_lists(&dev_priv->rings[i]);
 245         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
 246                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
 247         TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
 248             i915_gem_retire_task_handler, dev_priv);
 249         dev_priv->error_completion = 0;
 250
 251         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
 252         if (IS_GEN3(dev)) {
 253                 u32 tmp = I915_READ(MI_ARB_STATE);
 254                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
 255                         /*
 256                          * arb state is a masked write, so set bit +
 257                          * bit in mask.
 258                          */
 259                         tmp = MI_ARB_C3_LP_WRITE_ENABLE |
 260                             (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
 261                         I915_WRITE(MI_ARB_STATE, tmp);
 262                 }
 263         }
 264
 265         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 266
 267         /* Old X drivers will take 0-2 for front, back, depth buffers */
 268         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 269                 dev_priv->fence_reg_start = 3;
 270
 271         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) ||
 272             IS_G33(dev))
 273                 dev_priv->num_fence_regs = 16;
 274         else
 275                 dev_priv->num_fence_regs = 8;
 276
 277         /* Initialize fence registers to zero */
 278         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 279                 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
 280         }
 281         i915_gem_detect_bit_6_swizzle(dev);
 282         dev_priv->mm.interruptible = true;
 283
 284         dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
 285             i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
 286 }
 287
 288 int
 289 i915_gem_do_init(struct drm_device *dev, unsigned long start,
 290     unsigned long mappable_end, unsigned long end)
 291 {
 292         drm_i915_private_t *dev_priv;
 293         unsigned long mappable;
 294         int error;
 295
 296         dev_priv = dev->dev_private;
 297         mappable = min(end, mappable_end) - start;
 298
 299         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 300
 301         dev_priv->mm.gtt_start = start;
 302         dev_priv->mm.gtt_mappable_end = mappable_end;
 303         dev_priv->mm.gtt_end = end;
 304         dev_priv->mm.gtt_total = end - start;
 305         dev_priv->mm.mappable_gtt_total = mappable;
 306
 307         /* Take over this portion of the GTT */
 308         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 309         device_printf(dev->device,
 310             "taking over the fictitious range 0x%lx-0x%lx\n",
 311             dev->agp->base + start, dev->agp->base + start + mappable);
 312         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 313             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 314         return (error);
 315 }
 316
 317 int
 318 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 319     struct drm_file *file)
 320 {
 321         struct drm_i915_gem_init *args;
 322         drm_i915_private_t *dev_priv;
 323
 324         dev_priv = dev->dev_private;
 325         args = data;
 326
 327         if (args->gtt_start >= args->gtt_end ||
 328             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 329                 return (-EINVAL);
 330
 331         if (mtx_initialized(&dev_priv->mm.gtt_space.unused_lock))
 332                 return (-EBUSY);
 333         /*
 334          * XXXKIB. The second-time initialization should be guarded
 335          * against.
 336          */
 337         return (i915_gem_do_init(dev, args->gtt_start, args->gtt_end,
 338             args->gtt_end));
 339 }
 340
 341 int
 342 i915_gem_idle(struct drm_device *dev)
 343 {
 344         drm_i915_private_t *dev_priv;
 345         int ret;
 346
 347         dev_priv = dev->dev_private;
 348         if (dev_priv->mm.suspended)
 349                 return (0);
 350
 351         ret = i915_gpu_idle(dev, true);
 352         if (ret != 0)
 353                 return (ret);
 354
 355         /* Under UMS, be paranoid and evict. */
 356         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 357                 ret = i915_gem_evict_inactive(dev, false);
 358                 if (ret != 0)
 359                         return ret;
 360         }
 361
 362         i915_gem_reset_fences(dev);
 363
 364         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
 365          * We need to replace this with a semaphore, or something.
 366          * And not confound mm.suspended!
 367          */
 368         dev_priv->mm.suspended = 1;
 369         callout_stop(&dev_priv->hangcheck_timer);
 370
 371         i915_kernel_lost_context(dev);
 372         i915_gem_cleanup_ringbuffer(dev);
 373
 374         /* Cancel the retire work handler, which should be idle now. */
 375         taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
 376         return (ret);
 377 }
 378
 379 void
 380 i915_gem_init_swizzling(struct drm_device *dev)
 381 {
 382         drm_i915_private_t *dev_priv;
 383
 384         dev_priv = dev->dev_private;
 385
 386         if (INTEL_INFO(dev)->gen < 5 ||
 387             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 388                 return;
 389
 390         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 391                                  DISP_TILE_SURFACE_SWIZZLING);
 392
 393         if (IS_GEN5(dev))
 394                 return;
 395
 396         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
 397         if (IS_GEN6(dev))
 398                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));
 399         else
 400                 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
 401 }
 402
 403 void
 404 i915_gem_init_ppgtt(struct drm_device *dev)
 405 {
 406         drm_i915_private_t *dev_priv;
 407         struct i915_hw_ppgtt *ppgtt;
 408         uint32_t pd_offset, pd_entry;
 409         vm_paddr_t pt_addr;
 410         struct intel_ring_buffer *ring;
 411         u_int first_pd_entry_in_global_pt, i;
 412
 413         dev_priv = dev->dev_private;
 414         ppgtt = dev_priv->mm.aliasing_ppgtt;
 415         if (ppgtt == NULL)
 416                 return;
 417
 418         first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
 419         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 420                 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
 421                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 422                 pd_entry |= GEN6_PDE_VALID;
 423                 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
 424         }
 425         intel_gtt_read_pte(first_pd_entry_in_global_pt);
 426
 427         pd_offset = ppgtt->pd_offset;
 428         pd_offset /= 64; /* in cachelines, */
 429         pd_offset <<= 16;
 430
 431         if (INTEL_INFO(dev)->gen == 6) {
 432                 uint32_t ecochk = I915_READ(GAM_ECOCHK);
 433                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 434                                        ECOCHK_PPGTT_CACHE64B);
 435                 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 436         } else if (INTEL_INFO(dev)->gen >= 7) {
 437                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 438                 /* GFX_MODE is per-ring on gen7+ */
 439         }
 440
 441         for (i = 0; i < I915_NUM_RINGS; i++) {
 442                 ring = &dev_priv->rings[i];
 443
 444                 if (INTEL_INFO(dev)->gen >= 7)
 445                         I915_WRITE(RING_MODE_GEN7(ring),
 446                                    GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
 447
 448                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 449                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 450         }
 451 }
 452
 453 int
 454 i915_gem_init_hw(struct drm_device *dev)
 455 {
 456         drm_i915_private_t *dev_priv;
 457         int ret;
 458
 459         dev_priv = dev->dev_private;
 460
 461         i915_gem_init_swizzling(dev);
 462
 463         ret = intel_init_render_ring_buffer(dev);
 464         if (ret != 0)
 465                 return (ret);
 466
 467         if (HAS_BSD(dev)) {
 468                 ret = intel_init_bsd_ring_buffer(dev);
 469                 if (ret != 0)
 470                         goto cleanup_render_ring;
 471         }
 472
 473         if (HAS_BLT(dev)) {
 474                 ret = intel_init_blt_ring_buffer(dev);
 475                 if (ret != 0)
 476                         goto cleanup_bsd_ring;
 477         }
 478
 479         dev_priv->next_seqno = 1;
 480         i915_gem_init_ppgtt(dev);
 481         return (0);
 482
 483 cleanup_bsd_ring:
 484         intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
 485 cleanup_render_ring:
 486         intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
 487         return (ret);
 488 }
 489
 490 int
 491 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 492     struct drm_file *file)
 493 {
 494         struct drm_i915_private *dev_priv;
 495         struct drm_i915_gem_get_aperture *args;
 496         struct drm_i915_gem_object *obj;
 497         size_t pinned;
 498
 499         dev_priv = dev->dev_private;
 500         args = data;
 501
 502         if (!(dev->driver->driver_features & DRIVER_GEM))
 503                 return (-ENODEV);
 504
 505         pinned = 0;
 506         DRM_LOCK(dev);
 507         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 508                 pinned += obj->gtt_space->size;
 509         DRM_UNLOCK(dev);
 510
 511         args->aper_size = dev_priv->mm.gtt_total;
 512         args->aper_available_size = args->aper_size - pinned;
 513
 514         return (0);
 515 }
 516
 517 int
 518 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 519      bool map_and_fenceable)
 520 {
 521         struct drm_device *dev;
 522         struct drm_i915_private *dev_priv;
 523         int ret;
 524
 525         dev = obj->base.dev;
 526         dev_priv = dev->dev_private;
 527
 528         KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
 529             ("Max pin count"));
 530
 531         if (obj->gtt_space != NULL) {
 532                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
 533                     (map_and_fenceable && !obj->map_and_fenceable)) {
 534                         DRM_DEBUG("bo is already pinned with incorrect alignment:"
 535                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
 536                              " obj->map_and_fenceable=%d\n",
 537                              obj->gtt_offset, alignment,
 538                              map_and_fenceable,
 539                              obj->map_and_fenceable);
 540                         ret = i915_gem_object_unbind(obj);
 541                         if (ret != 0)
 542                                 return (ret);
 543                 }
 544         }
 545
 546         if (obj->gtt_space == NULL) {
 547                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
 548                     map_and_fenceable);
 549                 if (ret)
 550                         return (ret);
 551         }
 552
 553         if (obj->pin_count++ == 0 && !obj->active)
 554                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
 555         obj->pin_mappable |= map_and_fenceable;
 556
 557 #if 1
 558         KIB_NOTYET();
 559 #else
 560         WARN_ON(i915_verify_lists(dev));
 561 #endif
 562         return (0);
 563 }
 564
 565 void
 566 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
 567 {
 568         struct drm_device *dev;
 569         drm_i915_private_t *dev_priv;
 570
 571         dev = obj->base.dev;
 572         dev_priv = dev->dev_private;
 573
 574 #if 1
 575         KIB_NOTYET();
 576 #else
 577         WARN_ON(i915_verify_lists(dev));
 578 #endif
 579
 580         KASSERT(obj->pin_count != 0, ("zero pin count"));
 581         KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
 582
 583         if (--obj->pin_count == 0) {
 584                 if (!obj->active)
 585                         list_move_tail(&obj->mm_list,
 586                             &dev_priv->mm.inactive_list);
 587                 obj->pin_mappable = false;
 588         }
 589 #if 1
 590         KIB_NOTYET();
 591 #else
 592         WARN_ON(i915_verify_lists(dev));
 593 #endif
 594 }
 595
 596 int
 597 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 598     struct drm_file *file)
 599 {
 600         struct drm_i915_gem_pin *args;
 601         struct drm_i915_gem_object *obj;
 602         struct drm_gem_object *gobj;
 603         int ret;
 604
 605         args = data;
 606
 607         ret = i915_mutex_lock_interruptible(dev);
 608         if (ret != 0)
 609                 return ret;
 610
 611         gobj = drm_gem_object_lookup(dev, file, args->handle);
 612         if (gobj == NULL) {
 613                 ret = -ENOENT;
 614                 goto unlock;
 615         }
 616         obj = to_intel_bo(gobj);
 617
 618         if (obj->madv != I915_MADV_WILLNEED) {
 619                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
 620                 ret = -EINVAL;
 621                 goto out;
 622         }
 623
 624         if (obj->pin_filp != NULL && obj->pin_filp != file) {
 625                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
 626                     args->handle);
 627                 ret = -EINVAL;
 628                 goto out;
 629         }
 630
 631         obj->user_pin_count++;
 632         obj->pin_filp = file;
 633         if (obj->user_pin_count == 1) {
 634                 ret = i915_gem_object_pin(obj, args->alignment, true);
 635                 if (ret != 0)
 636                         goto out;
 637         }
 638
 639         /* XXX - flush the CPU caches for pinned objects
 640          * as the X server doesn't manage domains yet
 641          */
 642         i915_gem_object_flush_cpu_write_domain(obj);
 643         args->offset = obj->gtt_offset;
 644 out:
 645         drm_gem_object_unreference(&obj->base);
 646 unlock:
 647         DRM_UNLOCK(dev);
 648         return (ret);
 649 }
 650
 651 int
 652 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 653     struct drm_file *file)
 654 {
 655         struct drm_i915_gem_pin *args;
 656         struct drm_i915_gem_object *obj;
 657         int ret;
 658
 659         args = data;
 660         ret = i915_mutex_lock_interruptible(dev);
 661         if (ret != 0)
 662                 return (ret);
 663
 664         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 665         if (&obj->base == NULL) {
 666                 ret = -ENOENT;
 667                 goto unlock;
 668         }
 669
 670         if (obj->pin_filp != file) {
 671                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
 672                     args->handle);
 673                 ret = -EINVAL;
 674                 goto out;
 675         }
 676         obj->user_pin_count--;
 677         if (obj->user_pin_count == 0) {
 678                 obj->pin_filp = NULL;
 679                 i915_gem_object_unpin(obj);
 680         }
 681
 682 out:
 683         drm_gem_object_unreference(&obj->base);
 684 unlock:
 685         DRM_UNLOCK(dev);
 686         return (ret);
 687 }
 688
 689 int
 690 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 691     struct drm_file *file)
 692 {
 693         struct drm_i915_gem_busy *args;
 694         struct drm_i915_gem_object *obj;
 695         struct drm_i915_gem_request *request;
 696         int ret;
 697
 698         args = data;
 699
 700         ret = i915_mutex_lock_interruptible(dev);
 701         if (ret != 0)
 702                 return ret;
 703
 704         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 705         if (&obj->base == NULL) {
 706                 ret = -ENOENT;
 707                 goto unlock;
 708         }
 709
 710         args->busy = obj->active;
 711         if (args->busy) {
 712                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
 713                         ret = i915_gem_flush_ring(obj->ring,
 714                             0, obj->base.write_domain);
 715                 } else if (obj->ring->outstanding_lazy_request ==
 716                     obj->last_rendering_seqno) {
 717                         request = malloc(sizeof(*request), DRM_I915_GEM,
 718                             M_WAITOK | M_ZERO);
 719                         ret = i915_add_request(obj->ring, NULL, request);
 720                         if (ret != 0)
 721                                 free(request, DRM_I915_GEM);
 722                 }
 723
 724                 i915_gem_retire_requests_ring(obj->ring);
 725                 args->busy = obj->active;
 726         }
 727
 728         drm_gem_object_unreference(&obj->base);
 729 unlock:
 730         DRM_UNLOCK(dev);
 731         return (ret);
 732 }
 733
 734 static int
 735 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
 736 {
 737         struct drm_i915_private *dev_priv;
 738         struct drm_i915_file_private *file_priv;
 739         unsigned long recent_enough;
 740         struct drm_i915_gem_request *request;
 741         struct intel_ring_buffer *ring;
 742         u32 seqno;
 743         int ret;
 744
 745         dev_priv = dev->dev_private;
 746         if (atomic_load_acq_int(&dev_priv->mm.wedged))
 747                 return (-EIO);
 748
 749         file_priv = file->driver_priv;
 750         recent_enough = ticks - (20 * hz / 1000);
 751         ring = NULL;
 752         seqno = 0;
 753
 754         mtx_lock(&file_priv->mm.lck);
 755         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 756                 if (time_after_eq(request->emitted_jiffies, recent_enough))
 757                         break;
 758                 ring = request->ring;
 759                 seqno = request->seqno;
 760         }
 761         mtx_unlock(&file_priv->mm.lck);
 762         if (seqno == 0)
 763                 return (0);
 764
 765         ret = 0;
 766         mtx_lock(&ring->irq_lock);
 767         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 768                 if (ring->irq_get(ring)) {
 769                         while (ret == 0 &&
 770                             !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 771                             atomic_load_acq_int(&dev_priv->mm.wedged)))
 772                                 ret = -msleep(ring, &ring->irq_lock, PCATCH,
 773                                     "915thr", 0);
 774                         ring->irq_put(ring);
 775                         if (ret == 0 && atomic_load_acq_int(&dev_priv->mm.wedged))
 776                                 ret = -EIO;
 777                 } else if (_intel_wait_for(dev,
 778                     i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 779                     atomic_load_acq_int(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
 780                         ret = -EBUSY;
 781                 }
 782         }
 783         mtx_unlock(&ring->irq_lock);
 784
 785         if (ret == 0)
 786                 taskqueue_enqueue_timeout(dev_priv->tq,
 787                     &dev_priv->mm.retire_task, 0);
 788
 789         return (ret);
 790 }
 791
 792 int
 793 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 794     struct drm_file *file_priv)
 795 {
 796
 797         return (i915_gem_ring_throttle(dev, file_priv));
 798 }
 799
 800 int
 801 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 802     struct drm_file *file_priv)
 803 {
 804         struct drm_i915_gem_madvise *args;
 805         struct drm_i915_gem_object *obj;
 806         int ret;
 807
 808         args = data;
 809         switch (args->madv) {
 810         case I915_MADV_DONTNEED:
 811         case I915_MADV_WILLNEED:
 812                 break;
 813         default:
 814                 return (-EINVAL);
 815         }
 816
 817         ret = i915_mutex_lock_interruptible(dev);
 818         if (ret != 0)
 819                 return (ret);
 820
 821         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
 822         if (&obj->base == NULL) {
 823                 ret = -ENOENT;
 824                 goto unlock;
 825         }
 826
 827         if (obj->pin_count != 0) {
 828                 ret = -EINVAL;
 829                 goto out;
 830         }
 831
 832         if (obj->madv != I915_MADV_PURGED_INTERNAL)
 833                 obj->madv = args->madv;
 834         if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
 835                 i915_gem_object_truncate(obj);
 836         args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
 837
 838 out:
 839         drm_gem_object_unreference(&obj->base);
 840 unlock:
 841         DRM_UNLOCK(dev);
 842         return (ret);
 843 }
 844
 845 void
 846 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
 847 {
 848         drm_i915_private_t *dev_priv;
 849         int i;
 850
 851         dev_priv = dev->dev_private;
 852         for (i = 0; i < I915_NUM_RINGS; i++)
 853                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 854 }
 855
 856 int
 857 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 858     struct drm_file *file_priv)
 859 {
 860         drm_i915_private_t *dev_priv;
 861         int ret, i;
 862
 863         if (drm_core_check_feature(dev, DRIVER_MODESET))
 864                 return (0);
 865         dev_priv = dev->dev_private;
 866         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
 867                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
 868                 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
 869         }
 870
 871         dev_priv->mm.suspended = 0;
 872
 873         ret = i915_gem_init_hw(dev);
 874         if (ret != 0) {
 875                 return (ret);
 876         }
 877
 878         KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
 879         KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
 880         KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
 881         for (i = 0; i < I915_NUM_RINGS; i++) {
 882                 KASSERT(list_empty(&dev_priv->rings[i].active_list),
 883                     ("ring %d active list", i));
 884                 KASSERT(list_empty(&dev_priv->rings[i].request_list),
 885                     ("ring %d request list", i));
 886         }
 887
 888         DRM_UNLOCK(dev);
 889         ret = drm_irq_install(dev);
 890         DRM_LOCK(dev);
 891         if (ret)
 892                 goto cleanup_ringbuffer;
 893
 894         return (0);
 895
 896 cleanup_ringbuffer:
 897         i915_gem_cleanup_ringbuffer(dev);
 898         dev_priv->mm.suspended = 1;
 899
 900         return (ret);
 901 }
 902
 903 int
 904 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 905     struct drm_file *file_priv)
 906 {
 907
 908         if (drm_core_check_feature(dev, DRIVER_MODESET))
 909                 return 0;
 910
 911         drm_irq_uninstall(dev);
 912         return (i915_gem_idle(dev));
 913 }
 914
 915 int
 916 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
 917     uint32_t *handle_p)
 918 {
 919         struct drm_i915_gem_object *obj;
 920         uint32_t handle;
 921         int ret;
 922
 923         size = roundup(size, PAGE_SIZE);
 924         if (size == 0)
 925                 return (-EINVAL);
 926
 927         obj = i915_gem_alloc_object(dev, size);
 928         if (obj == NULL)
 929                 return (-ENOMEM);
 930
 931         handle = 0;
 932         ret = drm_gem_handle_create(file, &obj->base, &handle);
 933         if (ret != 0) {
 934                 drm_gem_object_release(&obj->base);
 935                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 936                 free(obj, DRM_I915_GEM);
 937                 return (-ret);
 938         }
 939
 940         /* drop reference from allocate - handle holds it now */
 941         drm_gem_object_unreference(&obj->base);
 942         CTR2(KTR_DRM, "object_create %p %x", obj, size);
 943         *handle_p = handle;
 944         return (0);
 945 }
 946
 947 int
 948 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 949     struct drm_mode_create_dumb *args)
 950 {
 951
 952         /* have to work out size/pitch and return them */
 953         args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
 954         args->size = args->pitch * args->height;
 955         return (i915_gem_create(file, dev, args->size, &args->handle));
 956 }
 957
 958 int
 959 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 960     uint32_t handle)
 961 {
 962
 963         return (drm_gem_handle_delete(file, handle));
 964 }
 965
 966 int
 967 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 968     struct drm_file *file)
 969 {
 970         struct drm_i915_gem_create *args = data;
 971
 972         return (i915_gem_create(file, dev, args->size, &args->handle));
 973 }
 974
 975 static int
 976 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
 977     uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
 978     struct drm_file *file)
 979 {
 980         vm_object_t vm_obj;
 981         vm_page_t m;
 982         struct sf_buf *sf;
 983         vm_offset_t mkva;
 984         vm_pindex_t obj_pi;
 985         int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
 986
 987         if (obj->gtt_offset != 0 && rw == UIO_READ)
 988                 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 989         else
 990                 do_bit17_swizzling = 0;
 991
 992         obj->dirty = 1;
 993         vm_obj = obj->base.vm_obj;
 994         ret = 0;
 995
 996         VM_OBJECT_WLOCK(vm_obj);
 997         vm_object_pip_add(vm_obj, 1);
 998         while (size > 0) {
 999                 obj_pi = OFF_TO_IDX(offset);
1000                 obj_po = offset & PAGE_MASK;
1001
1002                 m = i915_gem_wire_page(vm_obj, obj_pi);
1003                 VM_OBJECT_WUNLOCK(vm_obj);
1004
1005                 sched_pin();
1006                 sf = sf_buf_alloc(m, SFB_CPUPRIVATE);
1007                 mkva = sf_buf_kva(sf);
1008                 length = min(size, PAGE_SIZE - obj_po);
1009                 while (length > 0) {
1010                         if (do_bit17_swizzling &&
1011                             (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
1012                                 cnt = roundup2(obj_po + 1, 64);
1013                                 cnt = min(cnt - obj_po, length);
1014                                 swizzled_po = obj_po ^ 64;
1015                         } else {
1016                                 cnt = length;
1017                                 swizzled_po = obj_po;
1018                         }
1019                         if (rw == UIO_READ)
1020                                 ret = -copyout_nofault(
1021                                     (char *)mkva + swizzled_po,
1022                                     (void *)(uintptr_t)data_ptr, cnt);
1023                         else
1024                                 ret = -copyin_nofault(
1025                                     (void *)(uintptr_t)data_ptr,
1026                                     (char *)mkva + swizzled_po, cnt);
1027                         if (ret != 0)
1028                                 break;
1029                         data_ptr += cnt;
1030                         size -= cnt;
1031                         length -= cnt;
1032                         offset += cnt;
1033                         obj_po += cnt;
1034                 }
1035                 sf_buf_free(sf);
1036                 sched_unpin();
1037                 VM_OBJECT_WLOCK(vm_obj);
1038                 if (rw == UIO_WRITE)
1039                         vm_page_dirty(m);
1040                 vm_page_reference(m);
1041                 vm_page_lock(m);
1042                 vm_page_unwire(m, PQ_ACTIVE);
1043                 vm_page_unlock(m);
1044                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1045
1046                 if (ret != 0)
1047                         break;
1048         }
1049         vm_object_pip_wakeup(vm_obj);
1050         VM_OBJECT_WUNLOCK(vm_obj);
1051
1052         return (ret);
1053 }
1054
1055 static int
1056 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1057     uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1058 {
1059         vm_offset_t mkva;
1060         vm_pindex_t obj_pi;
1061         int obj_po, ret;
1062
1063         obj_pi = OFF_TO_IDX(offset);
1064         obj_po = offset & PAGE_MASK;
1065
1066         mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1067             IDX_TO_OFF(obj_pi), size, PAT_WRITE_COMBINING);
1068         ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva +
1069             obj_po, size);
1070         pmap_unmapdev(mkva, size);
1071         return (ret);
1072 }
1073
1074 static int
1075 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1076     uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1077 {
1078         struct drm_i915_gem_object *obj;
1079         vm_page_t *ma;
1080         vm_offset_t start, end;
1081         int npages, ret;
1082
1083         if (size == 0)
1084                 return (0);
1085         start = trunc_page(data_ptr);
1086         end = round_page(data_ptr + size);
1087         npages = howmany(end - start, PAGE_SIZE);
1088         ma = malloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1089             M_ZERO);
1090         npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1091             (vm_offset_t)data_ptr, size,
1092             (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1093         if (npages == -1) {
1094                 ret = -EFAULT;
1095                 goto free_ma;
1096         }
1097
1098         ret = i915_mutex_lock_interruptible(dev);
1099         if (ret != 0)
1100                 goto unlocked;
1101
1102         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1103         if (&obj->base == NULL) {
1104                 ret = -ENOENT;
1105                 goto unlock;
1106         }
1107         if (offset > obj->base.size || size > obj->base.size - offset) {
1108                 ret = -EINVAL;
1109                 goto out;
1110         }
1111
1112         if (rw == UIO_READ) {
1113                 CTR3(KTR_DRM, "object_pread %p %jx %jx", obj, offset, size);
1114                 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1115                     offset, size);
1116                 if (ret != 0)
1117                         goto out;
1118                 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1119                     UIO_READ, file);
1120         } else {
1121                 if (obj->phys_obj) {
1122                         CTR3(KTR_DRM, "object_phys_write %p %jx %jx", obj,
1123                             offset, size);
1124                         ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1125                             size, file);
1126                 } else if (obj->gtt_space &&
1127                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1128                         CTR3(KTR_DRM, "object_gtt_write %p %jx %jx", obj,
1129                             offset, size);
1130                         ret = i915_gem_object_pin(obj, 0, true);
1131                         if (ret != 0)
1132                                 goto out;
1133                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1134                         if (ret != 0)
1135                                 goto out_unpin;
1136                         ret = i915_gem_object_put_fence(obj);
1137                         if (ret != 0)
1138                                 goto out_unpin;
1139                         ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1140                             offset, file);
1141 out_unpin:
1142                         i915_gem_object_unpin(obj);
1143                 } else {
1144                         CTR3(KTR_DRM, "object_pwrite %p %jx %jx", obj,
1145                             offset, size);
1146                         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1147                         if (ret != 0)
1148                                 goto out;
1149                         ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1150                             UIO_WRITE, file);
1151                 }
1152         }
1153 out:
1154         drm_gem_object_unreference(&obj->base);
1155 unlock:
1156         DRM_UNLOCK(dev);
1157 unlocked:
1158         vm_page_unhold_pages(ma, npages);
1159 free_ma:
1160         free(ma, DRM_I915_GEM);
1161         return (ret);
1162 }
1163
1164 int
1165 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1166 {
1167         struct drm_i915_gem_pread *args;
1168
1169         args = data;
1170         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1171             args->offset, UIO_READ, file));
1172 }
1173
1174 int
1175 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1176 {
1177         struct drm_i915_gem_pwrite *args;
1178
1179         args = data;
1180         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1181             args->offset, UIO_WRITE, file));
1182 }
1183
1184 int
1185 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1186     struct drm_file *file)
1187 {
1188         struct drm_i915_gem_set_domain *args;
1189         struct drm_i915_gem_object *obj;
1190         uint32_t read_domains;
1191         uint32_t write_domain;
1192         int ret;
1193
1194         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1195                 return (-ENODEV);
1196
1197         args = data;
1198         read_domains = args->read_domains;
1199         write_domain = args->write_domain;
1200
1201         if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1202             (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1203             (write_domain != 0 && read_domains != write_domain))
1204                 return (-EINVAL);
1205
1206         ret = i915_mutex_lock_interruptible(dev);
1207         if (ret != 0)
1208                 return (ret);
1209
1210         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1211         if (&obj->base == NULL) {
1212                 ret = -ENOENT;
1213                 goto unlock;
1214         }
1215
1216         if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1217                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1218                 if (ret == -EINVAL)
1219                         ret = 0;
1220         } else
1221                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1222
1223         drm_gem_object_unreference(&obj->base);
1224 unlock:
1225         DRM_UNLOCK(dev);
1226         return (ret);
1227 }
1228
1229 int
1230 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1231     struct drm_file *file)
1232 {
1233         struct drm_i915_gem_sw_finish *args;
1234         struct drm_i915_gem_object *obj;
1235         int ret;
1236
1237         args = data;
1238         ret = 0;
1239         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1240                 return (ENODEV);
1241         ret = i915_mutex_lock_interruptible(dev);
1242         if (ret != 0)
1243                 return (ret);
1244         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1245         if (&obj->base == NULL) {
1246                 ret = -ENOENT;
1247                 goto unlock;
1248         }
1249         if (obj->pin_count != 0)
1250                 i915_gem_object_flush_cpu_write_domain(obj);
1251         drm_gem_object_unreference(&obj->base);
1252 unlock:
1253         DRM_UNLOCK(dev);
1254         return (ret);
1255 }
1256
1257 int
1258 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1259     struct drm_file *file)
1260 {
1261         struct drm_i915_gem_mmap *args;
1262         struct drm_gem_object *obj;
1263         struct proc *p;
1264         vm_map_t map;
1265         vm_offset_t addr;
1266         vm_size_t size;
1267         int error, rv;
1268
1269         args = data;
1270
1271         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1272                 return (-ENODEV);
1273
1274         obj = drm_gem_object_lookup(dev, file, args->handle);
1275         if (obj == NULL)
1276                 return (-ENOENT);
1277         error = 0;
1278         if (args->size == 0)
1279                 goto out;
1280         p = curproc;
1281         map = &p->p_vmspace->vm_map;
1282         size = round_page(args->size);
1283         PROC_LOCK(p);
1284         if (map->size + size > lim_cur(p, RLIMIT_VMEM)) {
1285                 PROC_UNLOCK(p);
1286                 error = ENOMEM;
1287                 goto out;
1288         }
1289         PROC_UNLOCK(p);
1290
1291         addr = 0;
1292         vm_object_reference(obj->vm_obj);
1293         DRM_UNLOCK(dev);
1294         rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size, 0,
1295             VMFS_OPTIMAL_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1296             VM_PROT_READ | VM_PROT_WRITE, MAP_INHERIT_SHARE);
1297         if (rv != KERN_SUCCESS) {
1298                 vm_object_deallocate(obj->vm_obj);
1299                 error = -vm_mmap_to_errno(rv);
1300         } else {
1301                 args->addr_ptr = (uint64_t)addr;
1302         }
1303         DRM_LOCK(dev);
1304 out:
1305         drm_gem_object_unreference(obj);
1306         return (error);
1307 }
1308
1309 static int
1310 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1311     vm_ooffset_t foff, struct ucred *cred, u_short *color)
1312 {
1313
1314         *color = 0; /* XXXKIB */
1315         return (0);
1316 }
1317
1318 int i915_intr_pf;
1319
1320 static int
1321 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1322     vm_page_t *mres)
1323 {
1324         struct drm_gem_object *gem_obj;
1325         struct drm_i915_gem_object *obj;
1326         struct drm_device *dev;
1327         drm_i915_private_t *dev_priv;
1328         vm_page_t m, oldm;
1329         int cause, ret;
1330         bool write;
1331
1332         gem_obj = vm_obj->handle;
1333         obj = to_intel_bo(gem_obj);
1334         dev = obj->base.dev;
1335         dev_priv = dev->dev_private;
1336 #if 0
1337         write = (prot & VM_PROT_WRITE) != 0;
1338 #else
1339         write = true;
1340 #endif
1341         vm_object_pip_add(vm_obj, 1);
1342
1343         /*
1344          * Remove the placeholder page inserted by vm_fault() from the
1345          * object before dropping the object lock. If
1346          * i915_gem_release_mmap() is active in parallel on this gem
1347          * object, then it owns the drm device sx and might find the
1348          * placeholder already. Then, since the page is busy,
1349          * i915_gem_release_mmap() sleeps waiting for the busy state
1350          * of the page cleared. We will be not able to acquire drm
1351          * device lock until i915_gem_release_mmap() is able to make a
1352          * progress.
1353          */
1354         if (*mres != NULL) {
1355                 oldm = *mres;
1356                 vm_page_lock(oldm);
1357                 vm_page_remove(oldm);
1358                 vm_page_unlock(oldm);
1359                 *mres = NULL;
1360         } else
1361                 oldm = NULL;
1362         VM_OBJECT_WUNLOCK(vm_obj);
1363 retry:
1364         cause = ret = 0;
1365         m = NULL;
1366
1367         if (i915_intr_pf) {
1368                 ret = i915_mutex_lock_interruptible(dev);
1369                 if (ret != 0) {
1370                         cause = 10;
1371                         goto out;
1372                 }
1373         } else
1374                 DRM_LOCK(dev);
1375
1376         /*
1377          * Since the object lock was dropped, other thread might have
1378          * faulted on the same GTT address and instantiated the
1379          * mapping for the page.  Recheck.
1380          */
1381         VM_OBJECT_WLOCK(vm_obj);
1382         m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1383         if (m != NULL) {
1384                 if (vm_page_busied(m)) {
1385                         DRM_UNLOCK(dev);
1386                         vm_page_lock(m);
1387                         VM_OBJECT_WUNLOCK(vm_obj);
1388                         vm_page_busy_sleep(m, "915pee");
1389                         goto retry;
1390                 }
1391                 goto have_page;
1392         } else
1393                 VM_OBJECT_WUNLOCK(vm_obj);
1394
1395         /* Now bind it into the GTT if needed */
1396         if (!obj->map_and_fenceable) {
1397                 ret = i915_gem_object_unbind(obj);
1398                 if (ret != 0) {
1399                         cause = 20;
1400                         goto unlock;
1401                 }
1402         }
1403         if (!obj->gtt_space) {
1404                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1405                 if (ret != 0) {
1406                         cause = 30;
1407                         goto unlock;
1408                 }
1409
1410                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1411                 if (ret != 0) {
1412                         cause = 40;
1413                         goto unlock;
1414                 }
1415         }
1416
1417         if (obj->tiling_mode == I915_TILING_NONE)
1418                 ret = i915_gem_object_put_fence(obj);
1419         else
1420                 ret = i915_gem_object_get_fence(obj, NULL);
1421         if (ret != 0) {
1422                 cause = 50;
1423                 goto unlock;
1424         }
1425
1426         if (i915_gem_object_is_inactive(obj))
1427                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1428
1429         obj->fault_mappable = true;
1430         VM_OBJECT_WLOCK(vm_obj);
1431         m = PHYS_TO_VM_PAGE(dev->agp->base + obj->gtt_offset + offset);
1432         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1433             ("physical address %#jx not fictitious",
1434             (uintmax_t)(dev->agp->base + obj->gtt_offset + offset)));
1435         if (m == NULL) {
1436                 VM_OBJECT_WUNLOCK(vm_obj);
1437                 cause = 60;
1438                 ret = -EFAULT;
1439                 goto unlock;
1440         }
1441         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1442             ("not fictitious %p", m));
1443         KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1444
1445         if (vm_page_busied(m)) {
1446                 DRM_UNLOCK(dev);
1447                 vm_page_lock(m);
1448                 VM_OBJECT_WUNLOCK(vm_obj);
1449                 vm_page_busy_sleep(m, "915pbs");
1450                 goto retry;
1451         }
1452         if (vm_page_insert(m, vm_obj, OFF_TO_IDX(offset))) {
1453                 DRM_UNLOCK(dev);
1454                 VM_OBJECT_WUNLOCK(vm_obj);
1455                 VM_WAIT;
1456                 goto retry;
1457         }
1458         m->valid = VM_PAGE_BITS_ALL;
1459 have_page:
1460         *mres = m;
1461         vm_page_xbusy(m);
1462
1463         CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
1464             m->phys_addr);
1465         DRM_UNLOCK(dev);
1466         if (oldm != NULL) {
1467                 vm_page_lock(oldm);
1468                 vm_page_free(oldm);
1469                 vm_page_unlock(oldm);
1470         }
1471         vm_object_pip_wakeup(vm_obj);
1472         return (VM_PAGER_OK);
1473
1474 unlock:
1475         DRM_UNLOCK(dev);
1476 out:
1477         KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1478         CTR5(KTR_DRM, "fault_fail %p %jx %x err %d %d", gem_obj, offset, prot,
1479             -ret, cause);
1480         if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1481                 kern_yield(PRI_USER);
1482                 goto retry;
1483         }
1484         VM_OBJECT_WLOCK(vm_obj);
1485         vm_object_pip_wakeup(vm_obj);
1486         return (VM_PAGER_ERROR);
1487 }
1488
1489 static void
1490 i915_gem_pager_dtor(void *handle)
1491 {
1492         struct drm_gem_object *obj;
1493         struct drm_device *dev;
1494
1495         obj = handle;
1496         dev = obj->dev;
1497
1498         DRM_LOCK(dev);
1499         drm_gem_free_mmap_offset(obj);
1500         i915_gem_release_mmap(to_intel_bo(obj));
1501         drm_gem_object_unreference(obj);
1502         DRM_UNLOCK(dev);
1503 }
1504
1505 struct cdev_pager_ops i915_gem_pager_ops = {
1506         .cdev_pg_fault  = i915_gem_pager_fault,
1507         .cdev_pg_ctor   = i915_gem_pager_ctor,
1508         .cdev_pg_dtor   = i915_gem_pager_dtor
1509 };
1510
1511 int
1512 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1513     uint32_t handle, uint64_t *offset)
1514 {
1515         struct drm_i915_private *dev_priv;
1516         struct drm_i915_gem_object *obj;
1517         int ret;
1518
1519         if (!(dev->driver->driver_features & DRIVER_GEM))
1520                 return (-ENODEV);
1521
1522         dev_priv = dev->dev_private;
1523
1524         ret = i915_mutex_lock_interruptible(dev);
1525         if (ret != 0)
1526                 return (ret);
1527
1528         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1529         if (&obj->base == NULL) {
1530                 ret = -ENOENT;
1531                 goto unlock;
1532         }
1533
1534         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1535                 ret = -E2BIG;
1536                 goto out;
1537         }
1538
1539         if (obj->madv != I915_MADV_WILLNEED) {
1540                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1541                 ret = -EINVAL;
1542                 goto out;
1543         }
1544
1545         ret = drm_gem_create_mmap_offset(&obj->base);
1546         if (ret != 0)
1547                 goto out;
1548
1549         *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1550             DRM_GEM_MAPPING_KEY;
1551 out:
1552         drm_gem_object_unreference(&obj->base);
1553 unlock:
1554         DRM_UNLOCK(dev);
1555         return (ret);
1556 }
1557
1558 int
1559 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1560     struct drm_file *file)
1561 {
1562         struct drm_i915_private *dev_priv;
1563         struct drm_i915_gem_mmap_gtt *args;
1564
1565         dev_priv = dev->dev_private;
1566         args = data;
1567
1568         return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1569 }
1570
1571 struct drm_i915_gem_object *
1572 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1573 {
1574         struct drm_i915_private *dev_priv;
1575         struct drm_i915_gem_object *obj;
1576
1577         dev_priv = dev->dev_private;
1578
1579         obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1580
1581         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1582                 free(obj, DRM_I915_GEM);
1583                 return (NULL);
1584         }
1585
1586         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1587         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1588
1589         if (HAS_LLC(dev))
1590                 obj->cache_level = I915_CACHE_LLC;
1591         else
1592                 obj->cache_level = I915_CACHE_NONE;
1593         obj->base.driver_private = NULL;
1594         obj->fence_reg = I915_FENCE_REG_NONE;
1595         INIT_LIST_HEAD(&obj->mm_list);
1596         INIT_LIST_HEAD(&obj->gtt_list);
1597         INIT_LIST_HEAD(&obj->ring_list);
1598         INIT_LIST_HEAD(&obj->exec_list);
1599         INIT_LIST_HEAD(&obj->gpu_write_list);
1600         obj->madv = I915_MADV_WILLNEED;
1601         /* Avoid an unnecessary call to unbind on the first bind. */
1602         obj->map_and_fenceable = true;
1603
1604         i915_gem_info_add_obj(dev_priv, size);
1605
1606         return (obj);
1607 }
1608
1609 void
1610 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1611 {
1612
1613         /* If we don't have a page list set up, then we're not pinned
1614          * to GPU, and we can ignore the cache flush because it'll happen
1615          * again at bind time.
1616          */
1617         if (obj->pages == NULL)
1618                 return;
1619
1620         /* If the GPU is snooping the contents of the CPU cache,
1621          * we do not need to manually clear the CPU cache lines.  However,
1622          * the caches are only snooped when the render cache is
1623          * flushed/invalidated.  As we always have to emit invalidations
1624          * and flushes when moving into and out of the RENDER domain, correct
1625          * snooping behaviour occurs naturally as the result of our domain
1626          * tracking.
1627          */
1628         if (obj->cache_level != I915_CACHE_NONE)
1629                 return;
1630
1631         CTR1(KTR_DRM, "object_clflush %p", obj);
1632         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1633 }
1634
1635 static void
1636 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1637 {
1638         uint32_t old_write_domain;
1639
1640         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1641                 return;
1642
1643         i915_gem_clflush_object(obj);
1644         intel_gtt_chipset_flush();
1645         old_write_domain = obj->base.write_domain;
1646         obj->base.write_domain = 0;
1647
1648         CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
1649             obj->base.read_domains, old_write_domain);
1650 }
1651
1652 static int
1653 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
1654 {
1655
1656         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
1657                 return (0);
1658         return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
1659 }
1660
1661 static void
1662 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1663 {
1664         uint32_t old_write_domain;
1665
1666         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1667                 return;
1668
1669         wmb();
1670
1671         old_write_domain = obj->base.write_domain;
1672         obj->base.write_domain = 0;
1673
1674         CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj,
1675             obj->base.read_domains, old_write_domain);
1676 }
1677
1678 int
1679 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1680 {
1681         uint32_t old_write_domain, old_read_domains;
1682         int ret;
1683
1684         if (obj->gtt_space == NULL)
1685                 return (-EINVAL);
1686
1687         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1688                 return 0;
1689
1690         ret = i915_gem_object_flush_gpu_write_domain(obj);
1691         if (ret != 0)
1692                 return (ret);
1693
1694         if (obj->pending_gpu_write || write) {
1695                 ret = i915_gem_object_wait_rendering(obj);
1696                 if (ret != 0)
1697                         return (ret);
1698         }
1699
1700         i915_gem_object_flush_cpu_write_domain(obj);
1701
1702         old_write_domain = obj->base.write_domain;
1703         old_read_domains = obj->base.read_domains;
1704
1705         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1706             ("In GTT write domain"));
1707         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1708         if (write) {
1709                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1710                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1711                 obj->dirty = 1;
1712         }
1713
1714         CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,
1715             old_read_domains, old_write_domain);
1716         return (0);
1717 }
1718
1719 int
1720 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1721     enum i915_cache_level cache_level)
1722 {
1723         struct drm_device *dev;
1724         drm_i915_private_t *dev_priv;
1725         int ret;
1726
1727         if (obj->cache_level == cache_level)
1728                 return 0;
1729
1730         if (obj->pin_count) {
1731                 DRM_DEBUG("can not change the cache level of pinned objects\n");
1732                 return (-EBUSY);
1733         }
1734
1735         dev = obj->base.dev;
1736         dev_priv = dev->dev_private;
1737         if (obj->gtt_space) {
1738                 ret = i915_gem_object_finish_gpu(obj);
1739                 if (ret != 0)
1740                         return (ret);
1741
1742                 i915_gem_object_finish_gtt(obj);
1743
1744                 /* Before SandyBridge, you could not use tiling or fence
1745                  * registers with snooped memory, so relinquish any fences
1746                  * currently pointing to our region in the aperture.
1747                  */
1748                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1749                         ret = i915_gem_object_put_fence(obj);
1750                         if (ret != 0)
1751                                 return (ret);
1752                 }
1753
1754                 i915_gem_gtt_rebind_object(obj, cache_level);
1755                 if (obj->has_aliasing_ppgtt_mapping)
1756                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1757                             obj, cache_level);
1758         }
1759
1760         if (cache_level == I915_CACHE_NONE) {
1761                 u32 old_read_domains, old_write_domain;
1762
1763                 /* If we're coming from LLC cached, then we haven't
1764                  * actually been tracking whether the data is in the
1765                  * CPU cache or not, since we only allow one bit set
1766                  * in obj->write_domain and have been skipping the clflushes.
1767                  * Just set it to the CPU cache for now.
1768                  */
1769                 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1770                     ("obj %p in CPU write domain", obj));
1771                 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1772                     ("obj %p in CPU read domain", obj));
1773
1774                 old_read_domains = obj->base.read_domains;
1775                 old_write_domain = obj->base.write_domain;
1776
1777                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1778                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1779
1780                 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
1781                     obj, old_read_domains, old_write_domain);
1782         }
1783
1784         obj->cache_level = cache_level;
1785         return (0);
1786 }
1787
1788 int
1789 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1790     u32 alignment, struct intel_ring_buffer *pipelined)
1791 {
1792         u32 old_read_domains, old_write_domain;
1793         int ret;
1794
1795         ret = i915_gem_object_flush_gpu_write_domain(obj);
1796         if (ret != 0)
1797                 return (ret);
1798
1799         if (pipelined != obj->ring) {
1800                 ret = i915_gem_object_wait_rendering(obj);
1801                 if (ret == -ERESTART || ret == -EINTR)
1802                         return (ret);
1803         }
1804
1805         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1806         if (ret != 0)
1807                 return (ret);
1808
1809         ret = i915_gem_object_pin(obj, alignment, true);
1810         if (ret != 0)
1811                 return (ret);
1812
1813         i915_gem_object_flush_cpu_write_domain(obj);
1814
1815         old_write_domain = obj->base.write_domain;
1816         old_read_domains = obj->base.read_domains;
1817
1818         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1819             ("obj %p in GTT write domain", obj));
1820         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1821
1822         CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
1823             obj, old_read_domains, obj->base.write_domain);
1824         return (0);
1825 }
1826
1827 int
1828 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1829 {
1830         int ret;
1831
1832         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1833                 return (0);
1834
1835         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1836                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1837                 if (ret != 0)
1838                         return (ret);
1839         }
1840
1841         ret = i915_gem_object_wait_rendering(obj);
1842         if (ret != 0)
1843                 return (ret);
1844
1845         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1846
1847         return (0);
1848 }
1849
1850 static int
1851 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
1852 {
1853         uint32_t old_write_domain, old_read_domains;
1854         int ret;
1855
1856         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
1857                 return 0;
1858
1859         ret = i915_gem_object_flush_gpu_write_domain(obj);
1860         if (ret != 0)
1861                 return (ret);
1862
1863         ret = i915_gem_object_wait_rendering(obj);
1864         if (ret != 0)
1865                 return (ret);
1866
1867         i915_gem_object_flush_gtt_write_domain(obj);
1868         i915_gem_object_set_to_full_cpu_read_domain(obj);
1869
1870         old_write_domain = obj->base.write_domain;
1871         old_read_domains = obj->base.read_domains;
1872
1873         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1874                 i915_gem_clflush_object(obj);
1875                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1876         }
1877
1878         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1879             ("In cpu write domain"));
1880
1881         if (write) {
1882                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1883                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1884         }
1885
1886         CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj,
1887             old_read_domains, old_write_domain);
1888         return (0);
1889 }
1890
1891 static void
1892 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
1893 {
1894         int i;
1895
1896         if (obj->page_cpu_valid == NULL)
1897                 return;
1898
1899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) {
1900                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
1901                         if (obj->page_cpu_valid[i] != 0)
1902                                 continue;
1903                         drm_clflush_pages(obj->pages + i, 1);
1904                 }
1905         }
1906
1907         free(obj->page_cpu_valid, DRM_I915_GEM);
1908         obj->page_cpu_valid = NULL;
1909 }
1910
1911 static int
1912 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1913     uint64_t offset, uint64_t size)
1914 {
1915         uint32_t old_read_domains;
1916         int i, ret;
1917
1918         if (offset == 0 && size == obj->base.size)
1919                 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1920
1921         ret = i915_gem_object_flush_gpu_write_domain(obj);
1922         if (ret != 0)
1923                 return (ret);
1924         ret = i915_gem_object_wait_rendering(obj);
1925         if (ret != 0)
1926                 return (ret);
1927
1928         i915_gem_object_flush_gtt_write_domain(obj);
1929
1930         if (obj->page_cpu_valid == NULL &&
1931             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1932                 return (0);
1933
1934         if (obj->page_cpu_valid == NULL) {
1935                 obj->page_cpu_valid = malloc(obj->base.size / PAGE_SIZE,
1936                     DRM_I915_GEM, M_WAITOK | M_ZERO);
1937         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1938                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1939
1940         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1941              i++) {
1942                 if (obj->page_cpu_valid[i])
1943                         continue;
1944                 drm_clflush_pages(obj->pages + i, 1);
1945                 obj->page_cpu_valid[i] = 1;
1946         }
1947
1948         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1949             ("In gpu write domain"));
1950
1951         old_read_domains = obj->base.read_domains;
1952         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1953
1954         CTR3(KTR_DRM, "object_change_domain set_cpu_read %p %x %x", obj,
1955             old_read_domains, obj->base.write_domain);
1956         return (0);
1957 }
1958
1959 static uint32_t
1960 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1961 {
1962         uint32_t gtt_size;
1963
1964         if (INTEL_INFO(dev)->gen >= 4 ||
1965             tiling_mode == I915_TILING_NONE)
1966                 return (size);
1967
1968         /* Previous chips need a power-of-two fence region when tiling */
1969         if (INTEL_INFO(dev)->gen == 3)
1970                 gtt_size = 1024*1024;
1971         else
1972                 gtt_size = 512*1024;
1973
1974         while (gtt_size < size)
1975                 gtt_size <<= 1;
1976
1977         return (gtt_size);
1978 }
1979
1980 /**
1981  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1982  * @obj: object to check
1983  *
1984  * Return the required GTT alignment for an object, taking into account
1985  * potential fence register mapping.
1986  */
1987 static uint32_t
1988 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1989      int tiling_mode)
1990 {
1991
1992         /*
1993          * Minimum alignment is 4k (GTT page size), but might be greater
1994          * if a fence register is needed for the object.
1995          */
1996         if (INTEL_INFO(dev)->gen >= 4 ||
1997             tiling_mode == I915_TILING_NONE)
1998                 return (4096);
1999
2000         /*
2001          * Previous chips need to be aligned to the size of the smallest
2002          * fence register that can contain the object.
2003          */
2004         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
2005 }
2006
2007 uint32_t
2008 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
2009     int tiling_mode)
2010 {
2011
2012         if (tiling_mode == I915_TILING_NONE)
2013                 return (4096);
2014
2015         /*
2016          * Minimum alignment is 4k (GTT page size) for sane hw.
2017          */
2018         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
2019                 return (4096);
2020
2021         /*
2022          * Previous hardware however needs to be aligned to a power-of-two
2023          * tile height. The simplest method for determining this is to reuse
2024          * the power-of-tile object size.
2025          */
2026         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
2027 }
2028
2029 static int
2030 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2031     unsigned alignment, bool map_and_fenceable)
2032 {
2033         struct drm_device *dev;
2034         struct drm_i915_private *dev_priv;
2035         struct drm_mm_node *free_space;
2036         uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2037         bool mappable, fenceable;
2038         int ret;
2039
2040         dev = obj->base.dev;
2041         dev_priv = dev->dev_private;
2042
2043         if (obj->madv != I915_MADV_WILLNEED) {
2044                 DRM_ERROR("Attempting to bind a purgeable object\n");
2045                 return (-EINVAL);
2046         }
2047
2048         fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2049             obj->tiling_mode);
2050         fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2051             obj->tiling_mode);
2052         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2053             obj->base.size, obj->tiling_mode);
2054         if (alignment == 0)
2055                 alignment = map_and_fenceable ? fence_alignment :
2056                     unfenced_alignment;
2057         if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2058                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2059                 return (-EINVAL);
2060         }
2061
2062         size = map_and_fenceable ? fence_size : obj->base.size;
2063
2064         /* If the object is bigger than the entire aperture, reject it early
2065          * before evicting everything in a vain attempt to find space.
2066          */
2067         if (obj->base.size > (map_and_fenceable ?
2068             dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2069                 DRM_ERROR(
2070 "Attempting to bind an object larger than the aperture\n");
2071                 return (-E2BIG);
2072         }
2073
2074  search_free:
2075         if (map_and_fenceable)
2076                 free_space = drm_mm_search_free_in_range(
2077                     &dev_priv->mm.gtt_space, size, alignment, 0,
2078                     dev_priv->mm.gtt_mappable_end, 0);
2079         else
2080                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2081                     size, alignment, 0);
2082         if (free_space != NULL) {
2083                 if (map_and_fenceable)
2084                         obj->gtt_space = drm_mm_get_block_range_generic(
2085                             free_space, size, alignment, 0,
2086                             dev_priv->mm.gtt_mappable_end, 1);
2087                 else
2088                         obj->gtt_space = drm_mm_get_block_generic(free_space,
2089                             size, alignment, 1);
2090         }
2091         if (obj->gtt_space == NULL) {
2092                 ret = i915_gem_evict_something(dev, size, alignment,
2093                     map_and_fenceable);
2094                 if (ret != 0)
2095                         return (ret);
2096                 goto search_free;
2097         }
2098         ret = i915_gem_object_get_pages_gtt(obj, 0);
2099         if (ret != 0) {
2100                 drm_mm_put_block(obj->gtt_space);
2101                 obj->gtt_space = NULL;
2102                 /*
2103                  * i915_gem_object_get_pages_gtt() cannot return
2104                  * ENOMEM, since we use vm_page_grab().
2105                  */
2106                 return (ret);
2107         }
2108
2109         ret = i915_gem_gtt_bind_object(obj);
2110         if (ret != 0) {
2111                 i915_gem_object_put_pages_gtt(obj);
2112                 drm_mm_put_block(obj->gtt_space);
2113                 obj->gtt_space = NULL;
2114                 if (i915_gem_evict_everything(dev, false))
2115                         return (ret);
2116                 goto search_free;
2117         }
2118
2119         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2120         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2121
2122         KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2123             ("Object in gpu read domain"));
2124         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2125             ("Object in gpu write domain"));
2126
2127         obj->gtt_offset = obj->gtt_space->start;
2128
2129         fenceable =
2130                 obj->gtt_space->size == fence_size &&
2131                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2132
2133         mappable =
2134                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2135         obj->map_and_fenceable = mappable && fenceable;
2136
2137         CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
2138             obj->base.size, map_and_fenceable);
2139         return (0);
2140 }
2141
2142 static void
2143 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2144 {
2145         u32 old_write_domain, old_read_domains;
2146
2147         /* Act a barrier for all accesses through the GTT */
2148         mb();
2149
2150         /* Force a pagefault for domain tracking on next user access */
2151         i915_gem_release_mmap(obj);
2152
2153         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2154                 return;
2155
2156         old_read_domains = obj->base.read_domains;
2157         old_write_domain = obj->base.write_domain;
2158
2159         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2160         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2161
2162         CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
2163             obj, old_read_domains, old_write_domain);
2164 }
2165
2166 int
2167 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2168 {
2169         drm_i915_private_t *dev_priv;
2170         int ret;
2171
2172         dev_priv = obj->base.dev->dev_private;
2173         ret = 0;
2174         if (obj->gtt_space == NULL)
2175                 return (0);
2176         if (obj->pin_count != 0) {
2177                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2178                 return (-EINVAL);
2179         }
2180
2181         ret = i915_gem_object_finish_gpu(obj);
2182         if (ret == -ERESTART || ret == -EINTR)
2183                 return (ret);
2184
2185         i915_gem_object_finish_gtt(obj);
2186
2187         if (ret == 0)
2188                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2189         if (ret == -ERESTART || ret == -EINTR)
2190                 return (ret);
2191         if (ret != 0) {
2192                 i915_gem_clflush_object(obj);
2193                 obj->base.read_domains = obj->base.write_domain =
2194                     I915_GEM_DOMAIN_CPU;
2195         }
2196
2197         ret = i915_gem_object_put_fence(obj);
2198         if (ret == -ERESTART)
2199                 return (ret);
2200
2201         i915_gem_gtt_unbind_object(obj);
2202         if (obj->has_aliasing_ppgtt_mapping) {
2203                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2204                 obj->has_aliasing_ppgtt_mapping = 0;
2205         }
2206         i915_gem_object_put_pages_gtt(obj);
2207
2208         list_del_init(&obj->gtt_list);
2209         list_del_init(&obj->mm_list);
2210         obj->map_and_fenceable = true;
2211
2212         drm_mm_put_block(obj->gtt_space);
2213         obj->gtt_space = NULL;
2214         obj->gtt_offset = 0;
2215
2216         if (i915_gem_object_is_purgeable(obj))
2217                 i915_gem_object_truncate(obj);
2218         CTR1(KTR_DRM, "object_unbind %p", obj);
2219
2220         return (ret);
2221 }
2222
2223 static int
2224 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2225     int flags)
2226 {
2227         struct drm_device *dev;
2228         vm_object_t vm_obj;
2229         vm_page_t m;
2230         int page_count, i, j;
2231
2232         dev = obj->base.dev;
2233         KASSERT(obj->pages == NULL, ("Obj already has pages"));
2234         page_count = obj->base.size / PAGE_SIZE;
2235         obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2236             M_WAITOK);
2237         vm_obj = obj->base.vm_obj;
2238         VM_OBJECT_WLOCK(vm_obj);
2239         for (i = 0; i < page_count; i++) {
2240                 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2241                         goto failed;
2242         }
2243         VM_OBJECT_WUNLOCK(vm_obj);
2244         if (i915_gem_object_needs_bit17_swizzle(obj))
2245                 i915_gem_object_do_bit_17_swizzle(obj);
2246         return (0);
2247
2248 failed:
2249         for (j = 0; j < i; j++) {
2250                 m = obj->pages[j];
2251                 vm_page_lock(m);
2252                 vm_page_unwire(m, PQ_INACTIVE);
2253                 vm_page_unlock(m);
2254                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2255         }
2256         VM_OBJECT_WUNLOCK(vm_obj);
2257         free(obj->pages, DRM_I915_GEM);
2258         obj->pages = NULL;
2259         return (-EIO);
2260 }
2261
2262 #define GEM_PARANOID_CHECK_GTT 0
2263 #if GEM_PARANOID_CHECK_GTT
2264 static void
2265 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2266     int page_count)
2267 {
2268         struct drm_i915_private *dev_priv;
2269         vm_paddr_t pa;
2270         unsigned long start, end;
2271         u_int i;
2272         int j;
2273
2274         dev_priv = dev->dev_private;
2275         start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2276         end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2277         for (i = start; i < end; i++) {
2278                 pa = intel_gtt_read_pte_paddr(i);
2279                 for (j = 0; j < page_count; j++) {
2280                         if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2281                                 panic("Page %p in GTT pte index %d pte %x",
2282                                     ma[i], i, intel_gtt_read_pte(i));
2283                         }
2284                 }
2285         }
2286 }
2287 #endif
2288
2289 static void
2290 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2291 {
2292         vm_page_t m;
2293         int page_count, i;
2294
2295         KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
2296
2297         if (obj->tiling_mode != I915_TILING_NONE)
2298                 i915_gem_object_save_bit_17_swizzle(obj);
2299         if (obj->madv == I915_MADV_DONTNEED)
2300                 obj->dirty = 0;
2301         page_count = obj->base.size / PAGE_SIZE;
2302         VM_OBJECT_WLOCK(obj->base.vm_obj);
2303 #if GEM_PARANOID_CHECK_GTT
2304         i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2305 #endif
2306         for (i = 0; i < page_count; i++) {
2307                 m = obj->pages[i];
2308                 if (obj->dirty)
2309                         vm_page_dirty(m);
2310                 if (obj->madv == I915_MADV_WILLNEED)
2311                         vm_page_reference(m);
2312                 vm_page_lock(m);
2313                 vm_page_unwire(obj->pages[i], PQ_ACTIVE);
2314                 vm_page_unlock(m);
2315                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2316         }
2317         VM_OBJECT_WUNLOCK(obj->base.vm_obj);
2318         obj->dirty = 0;
2319         free(obj->pages, DRM_I915_GEM);
2320         obj->pages = NULL;
2321 }
2322
2323 void
2324 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2325 {
2326         vm_object_t devobj;
2327         vm_page_t m;
2328         int i, page_count;
2329
2330         if (!obj->fault_mappable)
2331                 return;
2332
2333         CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset,
2334             OFF_TO_IDX(obj->base.size));
2335         devobj = cdev_pager_lookup(obj);
2336         if (devobj != NULL) {
2337                 page_count = OFF_TO_IDX(obj->base.size);
2338
2339                 VM_OBJECT_WLOCK(devobj);
2340 retry:
2341                 for (i = 0; i < page_count; i++) {
2342                         m = vm_page_lookup(devobj, i);
2343                         if (m == NULL)
2344                                 continue;
2345                         if (vm_page_sleep_if_busy(m, "915unm"))
2346                                 goto retry;
2347                         cdev_pager_free_page(devobj, m);
2348                 }
2349                 VM_OBJECT_WUNLOCK(devobj);
2350                 vm_object_deallocate(devobj);
2351         }
2352
2353         obj->fault_mappable = false;
2354 }
2355
2356 int
2357 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2358 {
2359         int ret;
2360
2361         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2362             ("In GPU write domain"));
2363
2364         CTR5(KTR_DRM, "object_wait_rendering %p %s %x %d %d", obj,
2365             obj->ring != NULL ? obj->ring->name : "none", obj->gtt_offset,
2366             obj->active, obj->last_rendering_seqno);
2367         if (obj->active) {
2368                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2369                     true);
2370                 if (ret != 0)
2371                         return (ret);
2372         }
2373         return (0);
2374 }
2375
2376 void
2377 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2378     struct intel_ring_buffer *ring, uint32_t seqno)
2379 {
2380         struct drm_device *dev = obj->base.dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         struct drm_i915_fence_reg *reg;
2383
2384         obj->ring = ring;
2385         KASSERT(ring != NULL, ("NULL ring"));
2386
2387         /* Add a reference if we're newly entering the active list. */
2388         if (!obj->active) {
2389                 drm_gem_object_reference(&obj->base);
2390                 obj->active = 1;
2391         }
2392
2393         /* Move from whatever list we were on to the tail of execution. */
2394         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2395         list_move_tail(&obj->ring_list, &ring->active_list);
2396
2397         obj->last_rendering_seqno = seqno;
2398         if (obj->fenced_gpu_access) {
2399                 obj->last_fenced_seqno = seqno;
2400                 obj->last_fenced_ring = ring;
2401
2402                 /* Bump MRU to take account of the delayed flush */
2403                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2404                         reg = &dev_priv->fence_regs[obj->fence_reg];
2405                         list_move_tail(&reg->lru_list,
2406                                        &dev_priv->mm.fence_list);
2407                 }
2408         }
2409 }
2410
2411 static void
2412 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2413 {
2414         list_del_init(&obj->ring_list);
2415         obj->last_rendering_seqno = 0;
2416         obj->last_fenced_seqno = 0;
2417 }
2418
2419 static void
2420 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2421 {
2422         struct drm_device *dev = obj->base.dev;
2423         drm_i915_private_t *dev_priv = dev->dev_private;
2424
2425         KASSERT(obj->active, ("Object not active"));
2426         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2427
2428         i915_gem_object_move_off_active(obj);
2429 }
2430
2431 static void
2432 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2433 {
2434         struct drm_device *dev = obj->base.dev;
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436
2437         if (obj->pin_count != 0)
2438                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2439         else
2440                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2441
2442         KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2443         KASSERT(obj->active, ("Object not active"));
2444         obj->ring = NULL;
2445         obj->last_fenced_ring = NULL;
2446
2447         i915_gem_object_move_off_active(obj);
2448         obj->fenced_gpu_access = false;
2449
2450         obj->active = 0;
2451         obj->pending_gpu_write = false;
2452         drm_gem_object_unreference(&obj->base);
2453
2454 #if 1
2455         KIB_NOTYET();
2456 #else
2457         WARN_ON(i915_verify_lists(dev));
2458 #endif
2459 }
2460
2461 static void
2462 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2463 {
2464         vm_object_t vm_obj;
2465
2466         vm_obj = obj->base.vm_obj;
2467         VM_OBJECT_WLOCK(vm_obj);
2468         vm_object_page_remove(vm_obj, 0, 0, false);
2469         VM_OBJECT_WUNLOCK(vm_obj);
2470         obj->madv = I915_MADV_PURGED_INTERNAL;
2471 }
2472
2473 static inline int
2474 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2475 {
2476
2477         return (obj->madv == I915_MADV_DONTNEED);
2478 }
2479
2480 static void
2481 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2482     uint32_t flush_domains)
2483 {
2484         struct drm_i915_gem_object *obj, *next;
2485         uint32_t old_write_domain;
2486
2487         list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2488             gpu_write_list) {
2489                 if (obj->base.write_domain & flush_domains) {
2490                         old_write_domain = obj->base.write_domain;
2491                         obj->base.write_domain = 0;
2492                         list_del_init(&obj->gpu_write_list);
2493                         i915_gem_object_move_to_active(obj, ring,
2494                             i915_gem_next_request_seqno(ring));
2495
2496         CTR3(KTR_DRM, "object_change_domain process_flush %p %x %x",
2497                             obj, obj->base.read_domains, old_write_domain);
2498                 }
2499         }
2500 }
2501
2502 static int
2503 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2504 {
2505         drm_i915_private_t *dev_priv;
2506
2507         dev_priv = obj->base.dev->dev_private;
2508         return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2509             obj->tiling_mode != I915_TILING_NONE);
2510 }
2511
2512 static vm_page_t
2513 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2514 {
2515         vm_page_t m;
2516         int rv;
2517
2518         VM_OBJECT_ASSERT_WLOCKED(object);
2519         m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL);
2520         if (m->valid != VM_PAGE_BITS_ALL) {
2521                 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
2522                         rv = vm_pager_get_pages(object, &m, 1, 0);
2523                         m = vm_page_lookup(object, pindex);
2524                         if (m == NULL)
2525                                 return (NULL);
2526                         if (rv != VM_PAGER_OK) {
2527                                 vm_page_lock(m);
2528                                 vm_page_free(m);
2529                                 vm_page_unlock(m);
2530                                 return (NULL);
2531                         }
2532                 } else {
2533                         pmap_zero_page(m);
2534                         m->valid = VM_PAGE_BITS_ALL;
2535                         m->dirty = 0;
2536                 }
2537         }
2538         vm_page_lock(m);
2539         vm_page_wire(m);
2540         vm_page_unlock(m);
2541         vm_page_xunbusy(m);
2542         atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2543         return (m);
2544 }
2545
2546 int
2547 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2548     uint32_t flush_domains)
2549 {
2550         int ret;
2551
2552         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2553                 return 0;
2554
2555         CTR3(KTR_DRM, "ring_flush %s %x %x", ring->name, invalidate_domains,
2556             flush_domains);
2557         ret = ring->flush(ring, invalidate_domains, flush_domains);
2558         if (ret)
2559                 return ret;
2560
2561         if (flush_domains & I915_GEM_GPU_DOMAINS)
2562                 i915_gem_process_flushing_list(ring, flush_domains);
2563         return 0;
2564 }
2565
2566 static int
2567 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2568 {
2569         int ret;
2570
2571         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2572                 return 0;
2573
2574         if (!list_empty(&ring->gpu_write_list)) {
2575                 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2576                     I915_GEM_GPU_DOMAINS);
2577                 if (ret != 0)
2578                         return ret;
2579         }
2580
2581         return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2582             do_retire));
2583 }
2584
2585 int
2586 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2587 {
2588         drm_i915_private_t *dev_priv = dev->dev_private;
2589         int ret, i;
2590
2591         /* Flush everything onto the inactive list. */
2592         for (i = 0; i < I915_NUM_RINGS; i++) {
2593                 ret = i915_ring_idle(&dev_priv->rings[i], do_retire);
2594                 if (ret)
2595                         return ret;
2596         }
2597
2598         return 0;
2599 }
2600
2601 int
2602 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2603 {
2604         drm_i915_private_t *dev_priv;
2605         struct drm_i915_gem_request *request;
2606         uint32_t ier;
2607         int flags, ret;
2608         bool recovery_complete;
2609
2610         KASSERT(seqno != 0, ("Zero seqno"));
2611
2612         dev_priv = ring->dev->dev_private;
2613         ret = 0;
2614
2615         if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
2616                 /* Give the error handler a chance to run. */
2617                 mtx_lock(&dev_priv->error_completion_lock);
2618                 recovery_complete = (&dev_priv->error_completion) > 0;
2619                 mtx_unlock(&dev_priv->error_completion_lock);
2620                 return (recovery_complete ? -EIO : -EAGAIN);
2621         }
2622
2623         if (seqno == ring->outstanding_lazy_request) {
2624                 request = malloc(sizeof(*request), DRM_I915_GEM,
2625                     M_WAITOK | M_ZERO);
2626                 if (request == NULL)
2627                         return (-ENOMEM);
2628
2629                 ret = i915_add_request(ring, NULL, request);
2630                 if (ret != 0) {
2631                         free(request, DRM_I915_GEM);
2632                         return (ret);
2633                 }
2634
2635                 seqno = request->seqno;
2636         }
2637
2638         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2639                 if (HAS_PCH_SPLIT(ring->dev))
2640                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2641                 else
2642                         ier = I915_READ(IER);
2643                 if (!ier) {
2644                         DRM_ERROR("something (likely vbetool) disabled "
2645                                   "interrupts, re-enabling\n");
2646                         ring->dev->driver->irq_preinstall(ring->dev);
2647                         ring->dev->driver->irq_postinstall(ring->dev);
2648                 }
2649
2650                 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
2651
2652                 ring->waiting_seqno = seqno;
2653                 mtx_lock(&ring->irq_lock);
2654                 if (ring->irq_get(ring)) {
2655                         flags = dev_priv->mm.interruptible ? PCATCH : 0;
2656                         while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2657                             && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
2658                             ret == 0) {
2659                                 ret = -msleep(ring, &ring->irq_lock, flags,
2660                                     "915gwr", 0);
2661                         }
2662                         ring->irq_put(ring);
2663                         mtx_unlock(&ring->irq_lock);
2664                 } else {
2665                         mtx_unlock(&ring->irq_lock);
2666                         if (_intel_wait_for(ring->dev,
2667                             i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2668                             atomic_load_acq_int(&dev_priv->mm.wedged), 3000,
2669                             0, "i915wrq") != 0)
2670                                 ret = -EBUSY;
2671                 }
2672                 ring->waiting_seqno = 0;
2673
2674                 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno,
2675                     ret);
2676         }
2677         if (atomic_load_acq_int(&dev_priv->mm.wedged))
2678                 ret = -EAGAIN;
2679
2680         /* Directly dispatch request retiring.  While we have the work queue
2681          * to handle this, the waiter on a request often wants an associated
2682          * buffer to have made it to the inactive list, and we would need
2683          * a separate wait queue to handle that.
2684          */
2685         if (ret == 0 && do_retire)
2686                 i915_gem_retire_requests_ring(ring);
2687
2688         return (ret);
2689 }
2690
2691 static u32
2692 i915_gem_get_seqno(struct drm_device *dev)
2693 {
2694         drm_i915_private_t *dev_priv = dev->dev_private;
2695         u32 seqno = dev_priv->next_seqno;
2696
2697         /* reserve 0 for non-seqno */
2698         if (++dev_priv->next_seqno == 0)
2699                 dev_priv->next_seqno = 1;
2700
2701         return seqno;
2702 }
2703
2704 u32
2705 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2706 {
2707         if (ring->outstanding_lazy_request == 0)
2708                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2709
2710         return ring->outstanding_lazy_request;
2711 }
2712
2713 int
2714 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2715      struct drm_i915_gem_request *request)
2716 {
2717         drm_i915_private_t *dev_priv;
2718         struct drm_i915_file_private *file_priv;
2719         uint32_t seqno;
2720         u32 request_ring_position;
2721         int was_empty;
2722         int ret;
2723
2724         KASSERT(request != NULL, ("NULL request in add"));
2725         DRM_LOCK_ASSERT(ring->dev);
2726         dev_priv = ring->dev->dev_private;
2727
2728         seqno = i915_gem_next_request_seqno(ring);
2729         request_ring_position = intel_ring_get_tail(ring);
2730
2731         ret = ring->add_request(ring, &seqno);
2732         if (ret != 0)
2733             return ret;
2734
2735         CTR2(KTR_DRM, "request_add %s %d", ring->name, seqno);
2736
2737         request->seqno = seqno;
2738         request->ring = ring;
2739         request->tail = request_ring_position;
2740         request->emitted_jiffies = ticks;
2741         was_empty = list_empty(&ring->request_list);
2742         list_add_tail(&request->list, &ring->request_list);
2743
2744         if (file != NULL) {
2745                 file_priv = file->driver_priv;
2746
2747                 mtx_lock(&file_priv->mm.lck);
2748                 request->file_priv = file_priv;
2749                 list_add_tail(&request->client_list,
2750                     &file_priv->mm.request_list);
2751                 mtx_unlock(&file_priv->mm.lck);
2752         }
2753
2754         ring->outstanding_lazy_request = 0;
2755
2756         if (!dev_priv->mm.suspended) {
2757                 if (i915_enable_hangcheck) {
2758                         callout_schedule(&dev_priv->hangcheck_timer,
2759                             DRM_I915_HANGCHECK_PERIOD);
2760                 }
2761                 if (was_empty)
2762                         taskqueue_enqueue_timeout(dev_priv->tq,
2763                             &dev_priv->mm.retire_task, hz);
2764         }
2765         return (0);
2766 }
2767
2768 static inline void
2769 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2770 {
2771         struct drm_i915_file_private *file_priv = request->file_priv;
2772
2773         if (!file_priv)
2774                 return;
2775
2776         DRM_LOCK_ASSERT(request->ring->dev);
2777
2778         mtx_lock(&file_priv->mm.lck);
2779         if (request->file_priv != NULL) {
2780                 list_del(&request->client_list);
2781                 request->file_priv = NULL;
2782         }
2783         mtx_unlock(&file_priv->mm.lck);
2784 }
2785
2786 void
2787 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2788 {
2789         struct drm_i915_file_private *file_priv;
2790         struct drm_i915_gem_request *request;
2791
2792         file_priv = file->driver_priv;
2793
2794         /* Clean up our request list when the client is going away, so that
2795          * later retire_requests won't dereference our soon-to-be-gone
2796          * file_priv.
2797          */
2798         mtx_lock(&file_priv->mm.lck);
2799         while (!list_empty(&file_priv->mm.request_list)) {
2800                 request = list_first_entry(&file_priv->mm.request_list,
2801                                            struct drm_i915_gem_request,
2802                                            client_list);
2803                 list_del(&request->client_list);
2804                 request->file_priv = NULL;
2805         }
2806         mtx_unlock(&file_priv->mm.lck);
2807 }
2808
2809 static void
2810 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2811     struct intel_ring_buffer *ring)
2812 {
2813
2814         if (ring->dev != NULL)
2815                 DRM_LOCK_ASSERT(ring->dev);
2816
2817         while (!list_empty(&ring->request_list)) {
2818                 struct drm_i915_gem_request *request;
2819
2820                 request = list_first_entry(&ring->request_list,
2821                     struct drm_i915_gem_request, list);
2822
2823                 list_del(&request->list);
2824                 i915_gem_request_remove_from_client(request);
2825                 free(request, DRM_I915_GEM);
2826         }
2827
2828         while (!list_empty(&ring->active_list)) {
2829                 struct drm_i915_gem_object *obj;
2830
2831                 obj = list_first_entry(&ring->active_list,
2832                     struct drm_i915_gem_object, ring_list);
2833
2834                 obj->base.write_domain = 0;
2835                 list_del_init(&obj->gpu_write_list);
2836                 i915_gem_object_move_to_inactive(obj);
2837         }
2838 }
2839
2840 static void
2841 i915_gem_reset_fences(struct drm_device *dev)
2842 {
2843         struct drm_i915_private *dev_priv = dev->dev_private;
2844         int i;
2845
2846         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2847                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2848                 struct drm_i915_gem_object *obj = reg->obj;
2849
2850                 if (!obj)
2851                         continue;
2852
2853                 if (obj->tiling_mode)
2854                         i915_gem_release_mmap(obj);
2855
2856                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2857                 reg->obj->fenced_gpu_access = false;
2858                 reg->obj->last_fenced_seqno = 0;
2859                 reg->obj->last_fenced_ring = NULL;
2860                 i915_gem_clear_fence_reg(dev, reg);
2861         }
2862 }
2863
2864 void
2865 i915_gem_reset(struct drm_device *dev)
2866 {
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         struct drm_i915_gem_object *obj;
2869         int i;
2870
2871         for (i = 0; i < I915_NUM_RINGS; i++)
2872                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->rings[i]);
2873
2874         /* Remove anything from the flushing lists. The GPU cache is likely
2875          * to be lost on reset along with the data, so simply move the
2876          * lost bo to the inactive list.
2877          */
2878         while (!list_empty(&dev_priv->mm.flushing_list)) {
2879                 obj = list_first_entry(&dev_priv->mm.flushing_list,
2880                                       struct drm_i915_gem_object,
2881                                       mm_list);
2882
2883                 obj->base.write_domain = 0;
2884                 list_del_init(&obj->gpu_write_list);
2885                 i915_gem_object_move_to_inactive(obj);
2886         }
2887
2888         /* Move everything out of the GPU domains to ensure we do any
2889          * necessary invalidation upon reuse.
2890          */
2891         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2892                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2893         }
2894
2895         /* The fence registers are invalidated so clear them out */
2896         i915_gem_reset_fences(dev);
2897 }
2898
2899 /**
2900  * This function clears the request list as sequence numbers are passed.
2901  */
2902 void
2903 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2904 {
2905         uint32_t seqno;
2906         int i;
2907
2908         if (list_empty(&ring->request_list))
2909                 return;
2910
2911         seqno = ring->get_seqno(ring);
2912         CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2913
2914         for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2915                 if (seqno >= ring->sync_seqno[i])
2916                         ring->sync_seqno[i] = 0;
2917
2918         while (!list_empty(&ring->request_list)) {
2919                 struct drm_i915_gem_request *request;
2920
2921                 request = list_first_entry(&ring->request_list,
2922                                            struct drm_i915_gem_request,
2923                                            list);
2924
2925                 if (!i915_seqno_passed(seqno, request->seqno))
2926                         break;
2927
2928                 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2929                     ring->name, seqno);
2930                 ring->last_retired_head = request->tail;
2931
2932                 list_del(&request->list);
2933                 i915_gem_request_remove_from_client(request);
2934                 free(request, DRM_I915_GEM);
2935         }
2936
2937         /* Move any buffers on the active list that are no longer referenced
2938          * by the ringbuffer to the flushing/inactive lists as appropriate.
2939          */
2940         while (!list_empty(&ring->active_list)) {
2941                 struct drm_i915_gem_object *obj;
2942
2943                 obj = list_first_entry(&ring->active_list,
2944                                       struct drm_i915_gem_object,
2945                                       ring_list);
2946
2947                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2948                         break;
2949
2950                 if (obj->base.write_domain != 0)
2951                         i915_gem_object_move_to_flushing(obj);
2952                 else
2953                         i915_gem_object_move_to_inactive(obj);
2954         }
2955
2956         if (ring->trace_irq_seqno &&
2957             i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2958                 mtx_lock(&ring->irq_lock);
2959                 ring->irq_put(ring);
2960                 mtx_unlock(&ring->irq_lock);
2961                 ring->trace_irq_seqno = 0;
2962         }
2963 }
2964
2965 void
2966 i915_gem_retire_requests(struct drm_device *dev)
2967 {
2968         drm_i915_private_t *dev_priv = dev->dev_private;
2969         struct drm_i915_gem_object *obj, *next;
2970         int i;
2971
2972         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2973                 list_for_each_entry_safe(obj, next,
2974                     &dev_priv->mm.deferred_free_list, mm_list)
2975                         i915_gem_free_object_tail(obj);
2976         }
2977
2978         for (i = 0; i < I915_NUM_RINGS; i++)
2979                 i915_gem_retire_requests_ring(&dev_priv->rings[i]);
2980 }
2981
2982 static int
2983 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2984     struct intel_ring_buffer *pipelined)
2985 {
2986         struct drm_device *dev = obj->base.dev;
2987         drm_i915_private_t *dev_priv = dev->dev_private;
2988         u32 size = obj->gtt_space->size;
2989         int regnum = obj->fence_reg;
2990         uint64_t val;
2991
2992         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2993                          0xfffff000) << 32;
2994         val |= obj->gtt_offset & 0xfffff000;
2995         val |= (uint64_t)((obj->stride / 128) - 1) <<
2996                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2997
2998         if (obj->tiling_mode == I915_TILING_Y)
2999                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3000         val |= I965_FENCE_REG_VALID;
3001
3002         if (pipelined) {
3003                 int ret = intel_ring_begin(pipelined, 6);
3004                 if (ret)
3005                         return ret;
3006
3007                 intel_ring_emit(pipelined, MI_NOOP);
3008                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
3009                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
3010                 intel_ring_emit(pipelined, (u32)val);
3011                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
3012                 intel_ring_emit(pipelined, (u32)(val >> 32));
3013                 intel_ring_advance(pipelined);
3014         } else
3015                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
3016
3017         return 0;
3018 }
3019
3020 static int
3021 i965_write_fence_reg(struct drm_i915_gem_object *obj,
3022     struct intel_ring_buffer *pipelined)
3023 {
3024         struct drm_device *dev = obj->base.dev;
3025         drm_i915_private_t *dev_priv = dev->dev_private;
3026         u32 size = obj->gtt_space->size;
3027         int regnum = obj->fence_reg;
3028         uint64_t val;
3029
3030         val = (uint64_t)((obj->gtt_offset + size - 4096) &
3031                     0xfffff000) << 32;
3032         val |= obj->gtt_offset & 0xfffff000;
3033         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
3034         if (obj->tiling_mode == I915_TILING_Y)
3035                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3036         val |= I965_FENCE_REG_VALID;
3037
3038         if (pipelined) {
3039                 int ret = intel_ring_begin(pipelined, 6);
3040                 if (ret)
3041                         return ret;
3042
3043                 intel_ring_emit(pipelined, MI_NOOP);
3044                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
3045                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
3046                 intel_ring_emit(pipelined, (u32)val);
3047                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
3048                 intel_ring_emit(pipelined, (u32)(val >> 32));
3049                 intel_ring_advance(pipelined);
3050         } else
3051                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
3052
3053         return 0;
3054 }
3055
3056 static int
3057 i915_write_fence_reg(struct drm_i915_gem_object *obj,
3058     struct intel_ring_buffer *pipelined)
3059 {
3060         struct drm_device *dev = obj->base.dev;
3061         drm_i915_private_t *dev_priv = dev->dev_private;
3062         u32 size = obj->gtt_space->size;
3063         u32 fence_reg, val, pitch_val;
3064         int tile_width;
3065
3066         if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
3067             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3068                 printf(
3069 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3070                  obj->gtt_offset, obj->map_and_fenceable, size);
3071                 return -EINVAL;
3072         }
3073
3074         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3075                 tile_width = 128;
3076         else
3077                 tile_width = 512;
3078
3079         /* Note: pitch better be a power of two tile widths */
3080         pitch_val = obj->stride / tile_width;
3081         pitch_val = ffs(pitch_val) - 1;
3082
3083         val = obj->gtt_offset;
3084         if (obj->tiling_mode == I915_TILING_Y)
3085                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3086         val |= I915_FENCE_SIZE_BITS(size);
3087         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3088         val |= I830_FENCE_REG_VALID;
3089
3090         fence_reg = obj->fence_reg;
3091         if (fence_reg < 8)
3092                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3093         else
3094                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3095
3096         if (pipelined) {
3097                 int ret = intel_ring_begin(pipelined, 4);
3098                 if (ret)
3099                         return ret;
3100
3101                 intel_ring_emit(pipelined, MI_NOOP);
3102                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3103                 intel_ring_emit(pipelined, fence_reg);
3104                 intel_ring_emit(pipelined, val);
3105                 intel_ring_advance(pipelined);
3106         } else
3107                 I915_WRITE(fence_reg, val);
3108
3109         return 0;
3110 }
3111
3112 static int
3113 i830_write_fence_reg(struct drm_i915_gem_object *obj,
3114     struct intel_ring_buffer *pipelined)
3115 {
3116         struct drm_device *dev = obj->base.dev;
3117         drm_i915_private_t *dev_priv = dev->dev_private;
3118         u32 size = obj->gtt_space->size;
3119         int regnum = obj->fence_reg;
3120         uint32_t val;
3121         uint32_t pitch_val;
3122
3123         if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3124             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3125                 printf(
3126 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3127                     obj->gtt_offset, size);
3128                 return -EINVAL;
3129         }
3130
3131         pitch_val = obj->stride / 128;
3132         pitch_val = ffs(pitch_val) - 1;
3133
3134         val = obj->gtt_offset;
3135         if (obj->tiling_mode == I915_TILING_Y)
3136                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3137         val |= I830_FENCE_SIZE_BITS(size);
3138         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3139         val |= I830_FENCE_REG_VALID;
3140
3141         if (pipelined) {
3142                 int ret = intel_ring_begin(pipelined, 4);
3143                 if (ret)
3144                         return ret;
3145
3146                 intel_ring_emit(pipelined, MI_NOOP);
3147                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3148                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
3149                 intel_ring_emit(pipelined, val);
3150                 intel_ring_advance(pipelined);
3151         } else
3152                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
3153
3154         return 0;
3155 }
3156
3157 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
3158 {
3159         return i915_seqno_passed(ring->get_seqno(ring), seqno);
3160 }
3161
3162 static int
3163 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3164     struct intel_ring_buffer *pipelined)
3165 {
3166         int ret;
3167
3168         if (obj->fenced_gpu_access) {
3169                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3170                         ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3171                             obj->base.write_domain);
3172                         if (ret)
3173                                 return ret;
3174                 }
3175
3176                 obj->fenced_gpu_access = false;
3177         }
3178
3179         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3180                 if (!ring_passed_seqno(obj->last_fenced_ring,
3181                                        obj->last_fenced_seqno)) {
3182                         ret = i915_wait_request(obj->last_fenced_ring,
3183                                                 obj->last_fenced_seqno,
3184                                                 true);
3185                         if (ret)
3186                                 return ret;
3187                 }
3188
3189                 obj->last_fenced_seqno = 0;
3190                 obj->last_fenced_ring = NULL;
3191         }
3192
3193         /* Ensure that all CPU reads are completed before installing a fence
3194          * and all writes before removing the fence.
3195          */
3196         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3197                 mb();
3198
3199         return 0;
3200 }
3201
3202 int
3203 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3204 {
3205         int ret;
3206
3207         if (obj->tiling_mode)
3208                 i915_gem_release_mmap(obj);
3209
3210         ret = i915_gem_object_flush_fence(obj, NULL);
3211         if (ret)
3212                 return ret;
3213
3214         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3215                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3216
3217                 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3218                         printf("%s: pin_count %d\n", __func__,
3219                             dev_priv->fence_regs[obj->fence_reg].pin_count);
3220                 i915_gem_clear_fence_reg(obj->base.dev,
3221                                          &dev_priv->fence_regs[obj->fence_reg]);
3222
3223                 obj->fence_reg = I915_FENCE_REG_NONE;
3224         }
3225
3226         return 0;
3227 }
3228
3229 static struct drm_i915_fence_reg *
3230 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3231 {
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233         struct drm_i915_fence_reg *reg, *first, *avail;
3234         int i;
3235
3236         /* First try to find a free reg */
3237         avail = NULL;
3238         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3239                 reg = &dev_priv->fence_regs[i];
3240                 if (!reg->obj)
3241                         return reg;
3242
3243                 if (!reg->pin_count)
3244                         avail = reg;
3245         }
3246
3247         if (avail == NULL)
3248                 return NULL;
3249
3250         /* None available, try to steal one or wait for a user to finish */
3251         avail = first = NULL;
3252         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3253                 if (reg->pin_count)
3254                         continue;
3255
3256                 if (first == NULL)
3257                         first = reg;
3258
3259                 if (!pipelined ||
3260                     !reg->obj->last_fenced_ring ||
3261                     reg->obj->last_fenced_ring == pipelined) {
3262                         avail = reg;
3263                         break;
3264                 }
3265         }
3266
3267         if (avail == NULL)
3268                 avail = first;
3269
3270         return avail;
3271 }
3272
3273 int
3274 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3275     struct intel_ring_buffer *pipelined)
3276 {
3277         struct drm_device *dev = obj->base.dev;
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         struct drm_i915_fence_reg *reg;
3280         int ret;
3281
3282         pipelined = NULL;
3283         ret = 0;
3284
3285         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3286                 reg = &dev_priv->fence_regs[obj->fence_reg];
3287                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3288
3289                 if (obj->tiling_changed) {
3290                         ret = i915_gem_object_flush_fence(obj, pipelined);
3291                         if (ret)
3292                                 return ret;
3293
3294                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3295                                 pipelined = NULL;
3296
3297                         if (pipelined) {
3298                                 reg->setup_seqno =
3299                                         i915_gem_next_request_seqno(pipelined);
3300                                 obj->last_fenced_seqno = reg->setup_seqno;
3301                                 obj->last_fenced_ring = pipelined;
3302                         }
3303
3304                         goto update;
3305                 }
3306
3307                 if (!pipelined) {
3308                         if (reg->setup_seqno) {
3309                                 if (!ring_passed_seqno(obj->last_fenced_ring,
3310                                     reg->setup_seqno)) {
3311                                         ret = i915_wait_request(
3312                                             obj->last_fenced_ring,
3313                                             reg->setup_seqno,
3314                                             true);
3315                                         if (ret)
3316                                                 return ret;
3317                                 }
3318
3319                                 reg->setup_seqno = 0;
3320                         }
3321                 } else if (obj->last_fenced_ring &&
3322                            obj->last_fenced_ring != pipelined) {
3323                         ret = i915_gem_object_flush_fence(obj, pipelined);
3324                         if (ret)
3325                                 return ret;
3326                 }
3327
3328                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3329                         pipelined = NULL;
3330                 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3331
3332                 if (obj->tiling_changed) {
3333                         if (pipelined) {
3334                                 reg->setup_seqno =
3335                                         i915_gem_next_request_seqno(pipelined);
3336                                 obj->last_fenced_seqno = reg->setup_seqno;
3337                                 obj->last_fenced_ring = pipelined;
3338                         }
3339                         goto update;
3340                 }
3341
3342                 return 0;
3343         }
3344
3345         reg = i915_find_fence_reg(dev, pipelined);
3346         if (reg == NULL)
3347                 return -EDEADLK;
3348
3349         ret = i915_gem_object_flush_fence(obj, pipelined);
3350         if (ret)
3351                 return ret;
3352
3353         if (reg->obj) {
3354                 struct drm_i915_gem_object *old = reg->obj;
3355
3356                 drm_gem_object_reference(&old->base);
3357
3358                 if (old->tiling_mode)
3359                         i915_gem_release_mmap(old);
3360
3361                 ret = i915_gem_object_flush_fence(old, pipelined);
3362                 if (ret) {
3363                         drm_gem_object_unreference(&old->base);
3364                         return ret;
3365                 }
3366
3367                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3368                         pipelined = NULL;
3369
3370                 old->fence_reg = I915_FENCE_REG_NONE;
3371                 old->last_fenced_ring = pipelined;
3372                 old->last_fenced_seqno =
3373                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3374
3375                 drm_gem_object_unreference(&old->base);
3376         } else if (obj->last_fenced_seqno == 0)
3377                 pipelined = NULL;
3378
3379         reg->obj = obj;
3380         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3381         obj->fence_reg = reg - dev_priv->fence_regs;
3382         obj->last_fenced_ring = pipelined;
3383
3384         reg->setup_seqno =
3385                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3386         obj->last_fenced_seqno = reg->setup_seqno;
3387
3388 update:
3389         obj->tiling_changed = false;
3390         switch (INTEL_INFO(dev)->gen) {
3391         case 7:
3392         case 6:
3393                 ret = sandybridge_write_fence_reg(obj, pipelined);
3394                 break;
3395         case 5:
3396         case 4:
3397                 ret = i965_write_fence_reg(obj, pipelined);
3398                 break;
3399         case 3:
3400                 ret = i915_write_fence_reg(obj, pipelined);
3401                 break;
3402         case 2:
3403                 ret = i830_write_fence_reg(obj, pipelined);
3404                 break;
3405         }
3406
3407         return ret;
3408 }
3409
3410 static void
3411 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3412 {
3413         drm_i915_private_t *dev_priv = dev->dev_private;
3414         uint32_t fence_reg = reg - dev_priv->fence_regs;
3415
3416         switch (INTEL_INFO(dev)->gen) {
3417         case 7:
3418         case 6:
3419                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3420                 break;
3421         case 5:
3422         case 4:
3423                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3424                 break;
3425         case 3:
3426                 if (fence_reg >= 8)
3427                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3428                 else
3429         case 2:
3430                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3431
3432                 I915_WRITE(fence_reg, 0);
3433                 break;
3434         }
3435
3436         list_del_init(&reg->lru_list);
3437         reg->obj = NULL;
3438         reg->setup_seqno = 0;
3439         reg->pin_count = 0;
3440 }
3441
3442 int
3443 i915_gem_init_object(struct drm_gem_object *obj)
3444 {
3445
3446         printf("i915_gem_init_object called\n");
3447         return (0);
3448 }
3449
3450 static bool
3451 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3452 {
3453
3454         return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3455 }
3456
3457 static void
3458 i915_gem_retire_task_handler(void *arg, int pending)
3459 {
3460         drm_i915_private_t *dev_priv;
3461         struct drm_device *dev;
3462         bool idle;
3463         int i;
3464
3465         dev_priv = arg;
3466         dev = dev_priv->dev;
3467
3468         /* Come back later if the device is busy... */
3469         if (!sx_try_xlock(&dev->dev_struct_lock)) {
3470                 taskqueue_enqueue_timeout(dev_priv->tq,
3471                     &dev_priv->mm.retire_task, hz);
3472                 return;
3473         }
3474
3475         CTR0(KTR_DRM, "retire_task");
3476
3477         i915_gem_retire_requests(dev);
3478
3479         /* Send a periodic flush down the ring so we don't hold onto GEM
3480          * objects indefinitely.
3481          */
3482         idle = true;
3483         for (i = 0; i < I915_NUM_RINGS; i++) {
3484                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
3485
3486                 if (!list_empty(&ring->gpu_write_list)) {
3487                         struct drm_i915_gem_request *request;
3488                         int ret;
3489
3490                         ret = i915_gem_flush_ring(ring,
3491                                                   0, I915_GEM_GPU_DOMAINS);
3492                         request = malloc(sizeof(*request), DRM_I915_GEM,
3493                             M_WAITOK | M_ZERO);
3494                         if (ret || request == NULL ||
3495                             i915_add_request(ring, NULL, request))
3496                                 free(request, DRM_I915_GEM);
3497                 }
3498
3499                 idle &= list_empty(&ring->request_list);
3500         }
3501
3502         if (!dev_priv->mm.suspended && !idle)
3503                 taskqueue_enqueue_timeout(dev_priv->tq,
3504                     &dev_priv->mm.retire_task, hz);
3505
3506         DRM_UNLOCK(dev);
3507 }
3508
3509 void
3510 i915_gem_lastclose(struct drm_device *dev)
3511 {
3512         int ret;
3513
3514         if (drm_core_check_feature(dev, DRIVER_MODESET))
3515                 return;
3516
3517         ret = i915_gem_idle(dev);
3518         if (ret != 0)
3519                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3520 }
3521
3522 static int
3523 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3524 {
3525         drm_i915_private_t *dev_priv;
3526         struct drm_i915_gem_phys_object *phys_obj;
3527         int ret;
3528
3529         dev_priv = dev->dev_private;
3530         if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3531                 return (0);
3532
3533         phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3534             M_WAITOK | M_ZERO);
3535
3536         phys_obj->id = id;
3537
3538         phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3539         if (phys_obj->handle == NULL) {
3540                 ret = -ENOMEM;
3541                 goto free_obj;
3542         }
3543         pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3544             size / PAGE_SIZE, PAT_WRITE_COMBINING);
3545
3546         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3547
3548         return (0);
3549
3550 free_obj:
3551         free(phys_obj, DRM_I915_GEM);
3552         return (ret);
3553 }
3554
3555 static void
3556 i915_gem_free_phys_object(struct drm_device *dev, int id)
3557 {
3558         drm_i915_private_t *dev_priv;
3559         struct drm_i915_gem_phys_object *phys_obj;
3560
3561         dev_priv = dev->dev_private;
3562         if (dev_priv->mm.phys_objs[id - 1] == NULL)
3563                 return;
3564
3565         phys_obj = dev_priv->mm.phys_objs[id - 1];
3566         if (phys_obj->cur_obj != NULL)
3567                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3568
3569         drm_pci_free(dev, phys_obj->handle);
3570         free(phys_obj, DRM_I915_GEM);
3571         dev_priv->mm.phys_objs[id - 1] = NULL;
3572 }
3573
3574 void
3575 i915_gem_free_all_phys_object(struct drm_device *dev)
3576 {
3577         int i;
3578
3579         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3580                 i915_gem_free_phys_object(dev, i);
3581 }
3582
3583 void
3584 i915_gem_detach_phys_object(struct drm_device *dev,
3585     struct drm_i915_gem_object *obj)
3586 {
3587         vm_page_t m;
3588         struct sf_buf *sf;
3589         char *vaddr, *dst;
3590         int i, page_count;
3591
3592         if (obj->phys_obj == NULL)
3593                 return;
3594         vaddr = obj->phys_obj->handle->vaddr;
3595
3596         page_count = obj->base.size / PAGE_SIZE;
3597         VM_OBJECT_WLOCK(obj->base.vm_obj);
3598         for (i = 0; i < page_count; i++) {
3599                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3600                 if (m == NULL)
3601                         continue; /* XXX */
3602
3603                 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3604                 sf = sf_buf_alloc(m, 0);
3605                 if (sf != NULL) {
3606                         dst = (char *)sf_buf_kva(sf);
3607                         memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3608                         sf_buf_free(sf);
3609                 }
3610                 drm_clflush_pages(&m, 1);
3611
3612                 VM_OBJECT_WLOCK(obj->base.vm_obj);
3613                 vm_page_reference(m);
3614                 vm_page_lock(m);
3615                 vm_page_dirty(m);
3616                 vm_page_unwire(m, PQ_INACTIVE);
3617                 vm_page_unlock(m);
3618                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3619         }
3620         VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3621         intel_gtt_chipset_flush();
3622
3623         obj->phys_obj->cur_obj = NULL;
3624         obj->phys_obj = NULL;
3625 }
3626
3627 int
3628 i915_gem_attach_phys_object(struct drm_device *dev,
3629     struct drm_i915_gem_object *obj, int id, int align)
3630 {
3631         drm_i915_private_t *dev_priv;
3632         vm_page_t m;
3633         struct sf_buf *sf;
3634         char *dst, *src;
3635         int i, page_count, ret;
3636
3637         if (id > I915_MAX_PHYS_OBJECT)
3638                 return (-EINVAL);
3639
3640         if (obj->phys_obj != NULL) {
3641                 if (obj->phys_obj->id == id)
3642                         return (0);
3643                 i915_gem_detach_phys_object(dev, obj);
3644         }
3645
3646         dev_priv = dev->dev_private;
3647         if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3648                 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3649                 if (ret != 0) {
3650                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3651                                   id, obj->base.size);
3652                         return (ret);
3653                 }
3654         }
3655
3656         /* bind to the object */
3657         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3658         obj->phys_obj->cur_obj = obj;
3659
3660         page_count = obj->base.size / PAGE_SIZE;
3661
3662         VM_OBJECT_WLOCK(obj->base.vm_obj);
3663         ret = 0;
3664         for (i = 0; i < page_count; i++) {
3665                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3666                 if (m == NULL) {
3667                         ret = -EIO;
3668                         break;
3669                 }
3670                 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3671                 sf = sf_buf_alloc(m, 0);
3672                 src = (char *)sf_buf_kva(sf);
3673                 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3674                 memcpy(dst, src, PAGE_SIZE);
3675                 sf_buf_free(sf);
3676
3677                 VM_OBJECT_WLOCK(obj->base.vm_obj);
3678
3679                 vm_page_reference(m);
3680                 vm_page_lock(m);
3681                 vm_page_unwire(m, PQ_INACTIVE);
3682                 vm_page_unlock(m);
3683                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3684         }
3685         VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3686
3687         return (0);
3688 }
3689
3690 static int
3691 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3692     uint64_t data_ptr, uint64_t offset, uint64_t size,
3693     struct drm_file *file_priv)
3694 {
3695         char *user_data, *vaddr;
3696         int ret;
3697
3698         vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3699         user_data = (char *)(uintptr_t)data_ptr;
3700
3701         if (copyin_nofault(user_data, vaddr, size) != 0) {
3702                 /* The physical object once assigned is fixed for the lifetime
3703                  * of the obj, so we can safely drop the lock and continue
3704                  * to access vaddr.
3705                  */
3706                 DRM_UNLOCK(dev);
3707                 ret = -copyin(user_data, vaddr, size);
3708                 DRM_LOCK(dev);
3709                 if (ret != 0)
3710                         return (ret);
3711         }
3712
3713         intel_gtt_chipset_flush();
3714         return (0);
3715 }
3716
3717 static int
3718 i915_gpu_is_active(struct drm_device *dev)
3719 {
3720         drm_i915_private_t *dev_priv;
3721
3722         dev_priv = dev->dev_private;
3723         return (!list_empty(&dev_priv->mm.flushing_list) ||
3724             !list_empty(&dev_priv->mm.active_list));
3725 }
3726
3727 static void
3728 i915_gem_lowmem(void *arg)
3729 {
3730         struct drm_device *dev;
3731         struct drm_i915_private *dev_priv;
3732         struct drm_i915_gem_object *obj, *next;
3733         int cnt, cnt_fail, cnt_total;
3734
3735         dev = arg;
3736         dev_priv = dev->dev_private;
3737
3738         if (!sx_try_xlock(&dev->dev_struct_lock))
3739                 return;
3740
3741         CTR0(KTR_DRM, "gem_lowmem");
3742
3743 rescan:
3744         /* first scan for clean buffers */
3745         i915_gem_retire_requests(dev);
3746
3747         cnt_total = cnt_fail = cnt = 0;
3748
3749         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3750             mm_list) {
3751                 if (i915_gem_object_is_purgeable(obj)) {
3752                         if (i915_gem_object_unbind(obj) != 0)
3753                                 cnt_total++;
3754                 } else
3755                         cnt_total++;
3756         }
3757
3758         /* second pass, evict/count anything still on the inactive list */
3759         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3760             mm_list) {
3761                 if (i915_gem_object_unbind(obj) == 0)
3762                         cnt++;
3763                 else
3764                         cnt_fail++;
3765         }
3766
3767         if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3768                 /*
3769                  * We are desperate for pages, so as a last resort, wait
3770                  * for the GPU to finish and discard whatever we can.
3771                  * This has a dramatic impact to reduce the number of
3772                  * OOM-killer events whilst running the GPU aggressively.
3773                  */
3774                 if (i915_gpu_idle(dev, true) == 0)
3775                         goto rescan;
3776         }
3777         DRM_UNLOCK(dev);
3778 }
3779
3780 void
3781 i915_gem_unload(struct drm_device *dev)
3782 {
3783         struct drm_i915_private *dev_priv;
3784
3785         dev_priv = dev->dev_private;
3786         EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
3787 }