2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 #include <sys/cdefs.h>
55 __FBSDID("$FreeBSD$");
57 #include <dev/drm2/drmP.h>
58 #include <dev/drm2/drm.h>
59 #include <dev/drm2/i915/i915_drm.h>
60 #include <dev/drm2/i915/i915_drv.h>
61 #include <dev/drm2/i915/intel_drv.h>
62 #include <dev/drm2/i915/intel_ringbuffer.h>
63 #include <sys/resourcevar.h>
64 #include <sys/sched.h>
65 #include <sys/sf_buf.h>
67 static void i915_gem_object_flush_cpu_write_domain(
68 struct drm_i915_gem_object *obj);
69 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
71 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
72 uint32_t size, int tiling_mode);
73 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
74 unsigned alignment, bool map_and_fenceable);
75 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
77 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
78 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
80 static void i915_gem_object_set_to_full_cpu_read_domain(
81 struct drm_i915_gem_object *obj);
82 static int i915_gem_object_set_cpu_read_domain_range(
83 struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
84 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
85 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
86 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
87 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
88 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
89 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
90 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
91 uint32_t flush_domains);
92 static void i915_gem_clear_fence_reg(struct drm_device *dev,
93 struct drm_i915_fence_reg *reg);
94 static void i915_gem_reset_fences(struct drm_device *dev);
95 static void i915_gem_retire_task_handler(void *arg, int pending);
96 static int i915_gem_phys_pwrite(struct drm_device *dev,
97 struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
98 uint64_t size, struct drm_file *file_priv);
99 static void i915_gem_lowmem(void *arg);
101 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
102 long i915_gem_wired_pages_cnt;
105 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
108 dev_priv->mm.object_count++;
109 dev_priv->mm.object_memory += size;
113 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
116 dev_priv->mm.object_count--;
117 dev_priv->mm.object_memory -= size;
121 i915_gem_wait_for_error(struct drm_device *dev)
123 struct drm_i915_private *dev_priv;
126 dev_priv = dev->dev_private;
127 if (!atomic_load_acq_int(&dev_priv->mm.wedged))
130 mtx_lock(&dev_priv->error_completion_lock);
131 while (dev_priv->error_completion == 0) {
132 ret = -msleep(&dev_priv->error_completion,
133 &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
135 mtx_unlock(&dev_priv->error_completion_lock);
139 mtx_unlock(&dev_priv->error_completion_lock);
141 if (atomic_read(&dev_priv->mm.wedged)) {
142 mtx_lock(&dev_priv->error_completion_lock);
143 dev_priv->error_completion++;
144 mtx_unlock(&dev_priv->error_completion_lock);
150 i915_mutex_lock_interruptible(struct drm_device *dev)
152 struct drm_i915_private *dev_priv;
155 dev_priv = dev->dev_private;
156 ret = i915_gem_wait_for_error(dev);
161 * interruptible shall it be. might indeed be if dev_lock is
164 ret = sx_xlock_sig(&dev->dev_struct_lock);
173 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
175 struct drm_device *dev;
176 drm_i915_private_t *dev_priv;
180 dev_priv = dev->dev_private;
182 ret = i915_gem_object_unbind(obj);
183 if (ret == -ERESTART) {
184 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
188 CTR1(KTR_DRM, "object_destroy_tail %p", obj);
189 drm_gem_free_mmap_offset(&obj->base);
190 drm_gem_object_release(&obj->base);
191 i915_gem_info_remove_obj(dev_priv, obj->base.size);
193 free(obj->page_cpu_valid, DRM_I915_GEM);
194 free(obj->bit_17, DRM_I915_GEM);
195 free(obj, DRM_I915_GEM);
199 i915_gem_free_object(struct drm_gem_object *gem_obj)
201 struct drm_i915_gem_object *obj;
202 struct drm_device *dev;
204 obj = to_intel_bo(gem_obj);
207 while (obj->pin_count > 0)
208 i915_gem_object_unpin(obj);
210 if (obj->phys_obj != NULL)
211 i915_gem_detach_phys_object(dev, obj);
213 i915_gem_free_object_tail(obj);
217 init_ring_lists(struct intel_ring_buffer *ring)
220 INIT_LIST_HEAD(&ring->active_list);
221 INIT_LIST_HEAD(&ring->request_list);
222 INIT_LIST_HEAD(&ring->gpu_write_list);
226 i915_gem_load(struct drm_device *dev)
228 drm_i915_private_t *dev_priv;
231 dev_priv = dev->dev_private;
233 INIT_LIST_HEAD(&dev_priv->mm.active_list);
234 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
235 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
236 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
237 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
238 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
239 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
240 for (i = 0; i < I915_NUM_RINGS; i++)
241 init_ring_lists(&dev_priv->rings[i]);
242 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
243 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
244 TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
245 i915_gem_retire_task_handler, dev_priv);
246 dev_priv->error_completion = 0;
248 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
250 u32 tmp = I915_READ(MI_ARB_STATE);
251 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
253 * arb state is a masked write, so set bit +
256 tmp = MI_ARB_C3_LP_WRITE_ENABLE |
257 (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
258 I915_WRITE(MI_ARB_STATE, tmp);
262 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
264 /* Old X drivers will take 0-2 for front, back, depth buffers */
265 if (!drm_core_check_feature(dev, DRIVER_MODESET))
266 dev_priv->fence_reg_start = 3;
268 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) ||
270 dev_priv->num_fence_regs = 16;
272 dev_priv->num_fence_regs = 8;
274 /* Initialize fence registers to zero */
275 for (i = 0; i < dev_priv->num_fence_regs; i++) {
276 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
278 i915_gem_detect_bit_6_swizzle(dev);
279 dev_priv->mm.interruptible = true;
281 dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
282 i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
286 i915_gem_do_init(struct drm_device *dev, unsigned long start,
287 unsigned long mappable_end, unsigned long end)
289 drm_i915_private_t *dev_priv;
290 unsigned long mappable;
293 dev_priv = dev->dev_private;
294 mappable = min(end, mappable_end) - start;
296 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
298 dev_priv->mm.gtt_start = start;
299 dev_priv->mm.gtt_mappable_end = mappable_end;
300 dev_priv->mm.gtt_end = end;
301 dev_priv->mm.gtt_total = end - start;
302 dev_priv->mm.mappable_gtt_total = mappable;
304 /* Take over this portion of the GTT */
305 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
306 device_printf(dev->device,
307 "taking over the fictitious range 0x%lx-0x%lx\n",
308 dev->agp->base + start, dev->agp->base + start + mappable);
309 error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
310 dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
315 i915_gem_init_ioctl(struct drm_device *dev, void *data,
316 struct drm_file *file)
318 struct drm_i915_gem_init *args;
319 drm_i915_private_t *dev_priv;
321 dev_priv = dev->dev_private;
324 if (args->gtt_start >= args->gtt_end ||
325 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
328 if (mtx_initialized(&dev_priv->mm.gtt_space.unused_lock))
331 * XXXKIB. The second-time initialization should be guarded
334 return (i915_gem_do_init(dev, args->gtt_start, args->gtt_end,
339 i915_gem_idle(struct drm_device *dev)
341 drm_i915_private_t *dev_priv;
344 dev_priv = dev->dev_private;
345 if (dev_priv->mm.suspended)
348 ret = i915_gpu_idle(dev, true);
352 /* Under UMS, be paranoid and evict. */
353 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
354 ret = i915_gem_evict_inactive(dev, false);
359 i915_gem_reset_fences(dev);
361 /* Hack! Don't let anybody do execbuf while we don't control the chip.
362 * We need to replace this with a semaphore, or something.
363 * And not confound mm.suspended!
365 dev_priv->mm.suspended = 1;
366 callout_stop(&dev_priv->hangcheck_timer);
368 i915_kernel_lost_context(dev);
369 i915_gem_cleanup_ringbuffer(dev);
371 /* Cancel the retire work handler, which should be idle now. */
372 taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
377 i915_gem_init_swizzling(struct drm_device *dev)
379 drm_i915_private_t *dev_priv;
381 dev_priv = dev->dev_private;
383 if (INTEL_INFO(dev)->gen < 5 ||
384 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
387 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
388 DISP_TILE_SURFACE_SWIZZLING);
393 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
395 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB));
397 I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB));
401 i915_gem_init_ppgtt(struct drm_device *dev)
403 drm_i915_private_t *dev_priv;
404 struct i915_hw_ppgtt *ppgtt;
405 uint32_t pd_offset, pd_entry;
407 struct intel_ring_buffer *ring;
408 u_int first_pd_entry_in_global_pt, i;
410 dev_priv = dev->dev_private;
411 ppgtt = dev_priv->mm.aliasing_ppgtt;
415 first_pd_entry_in_global_pt = 512 * 1024 - I915_PPGTT_PD_ENTRIES;
416 for (i = 0; i < ppgtt->num_pd_entries; i++) {
417 pt_addr = VM_PAGE_TO_PHYS(ppgtt->pt_pages[i]);
418 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
419 pd_entry |= GEN6_PDE_VALID;
420 intel_gtt_write(first_pd_entry_in_global_pt + i, pd_entry);
422 intel_gtt_read_pte(first_pd_entry_in_global_pt);
424 pd_offset = ppgtt->pd_offset;
425 pd_offset /= 64; /* in cachelines, */
428 if (INTEL_INFO(dev)->gen == 6) {
429 uint32_t ecochk = I915_READ(GAM_ECOCHK);
430 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
431 ECOCHK_PPGTT_CACHE64B);
432 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
433 } else if (INTEL_INFO(dev)->gen >= 7) {
434 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
435 /* GFX_MODE is per-ring on gen7+ */
438 for (i = 0; i < I915_NUM_RINGS; i++) {
439 ring = &dev_priv->rings[i];
441 if (INTEL_INFO(dev)->gen >= 7)
442 I915_WRITE(RING_MODE_GEN7(ring),
443 GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));
445 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
446 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
451 i915_gem_init_hw(struct drm_device *dev)
453 drm_i915_private_t *dev_priv;
456 dev_priv = dev->dev_private;
458 i915_gem_init_swizzling(dev);
460 ret = intel_init_render_ring_buffer(dev);
465 ret = intel_init_bsd_ring_buffer(dev);
467 goto cleanup_render_ring;
471 ret = intel_init_blt_ring_buffer(dev);
473 goto cleanup_bsd_ring;
476 dev_priv->next_seqno = 1;
477 i915_gem_init_ppgtt(dev);
481 intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
483 intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
488 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file)
491 struct drm_i915_private *dev_priv;
492 struct drm_i915_gem_get_aperture *args;
493 struct drm_i915_gem_object *obj;
496 dev_priv = dev->dev_private;
499 if (!(dev->driver->driver_features & DRIVER_GEM))
504 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
505 pinned += obj->gtt_space->size;
508 args->aper_size = dev_priv->mm.gtt_total;
509 args->aper_available_size = args->aper_size - pinned;
515 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
516 bool map_and_fenceable)
518 struct drm_device *dev;
519 struct drm_i915_private *dev_priv;
523 dev_priv = dev->dev_private;
525 KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
528 if (obj->gtt_space != NULL) {
529 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
530 (map_and_fenceable && !obj->map_and_fenceable)) {
531 DRM_DEBUG("bo is already pinned with incorrect alignment:"
532 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
533 " obj->map_and_fenceable=%d\n",
534 obj->gtt_offset, alignment,
536 obj->map_and_fenceable);
537 ret = i915_gem_object_unbind(obj);
543 if (obj->gtt_space == NULL) {
544 ret = i915_gem_object_bind_to_gtt(obj, alignment,
550 if (obj->pin_count++ == 0 && !obj->active)
551 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
552 obj->pin_mappable |= map_and_fenceable;
557 WARN_ON(i915_verify_lists(dev));
563 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
565 struct drm_device *dev;
566 drm_i915_private_t *dev_priv;
569 dev_priv = dev->dev_private;
574 WARN_ON(i915_verify_lists(dev));
577 KASSERT(obj->pin_count != 0, ("zero pin count"));
578 KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
580 if (--obj->pin_count == 0) {
582 list_move_tail(&obj->mm_list,
583 &dev_priv->mm.inactive_list);
584 obj->pin_mappable = false;
589 WARN_ON(i915_verify_lists(dev));
594 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
595 struct drm_file *file)
597 struct drm_i915_gem_pin *args;
598 struct drm_i915_gem_object *obj;
599 struct drm_gem_object *gobj;
604 ret = i915_mutex_lock_interruptible(dev);
608 gobj = drm_gem_object_lookup(dev, file, args->handle);
613 obj = to_intel_bo(gobj);
615 if (obj->madv != I915_MADV_WILLNEED) {
616 DRM_ERROR("Attempting to pin a purgeable buffer\n");
621 if (obj->pin_filp != NULL && obj->pin_filp != file) {
622 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
628 obj->user_pin_count++;
629 obj->pin_filp = file;
630 if (obj->user_pin_count == 1) {
631 ret = i915_gem_object_pin(obj, args->alignment, true);
636 /* XXX - flush the CPU caches for pinned objects
637 * as the X server doesn't manage domains yet
639 i915_gem_object_flush_cpu_write_domain(obj);
640 args->offset = obj->gtt_offset;
642 drm_gem_object_unreference(&obj->base);
649 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
650 struct drm_file *file)
652 struct drm_i915_gem_pin *args;
653 struct drm_i915_gem_object *obj;
657 ret = i915_mutex_lock_interruptible(dev);
661 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
662 if (&obj->base == NULL) {
667 if (obj->pin_filp != file) {
668 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
673 obj->user_pin_count--;
674 if (obj->user_pin_count == 0) {
675 obj->pin_filp = NULL;
676 i915_gem_object_unpin(obj);
680 drm_gem_object_unreference(&obj->base);
687 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *file)
690 struct drm_i915_gem_busy *args;
691 struct drm_i915_gem_object *obj;
692 struct drm_i915_gem_request *request;
697 ret = i915_mutex_lock_interruptible(dev);
701 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
702 if (&obj->base == NULL) {
707 args->busy = obj->active;
709 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
710 ret = i915_gem_flush_ring(obj->ring,
711 0, obj->base.write_domain);
712 } else if (obj->ring->outstanding_lazy_request ==
713 obj->last_rendering_seqno) {
714 request = malloc(sizeof(*request), DRM_I915_GEM,
716 ret = i915_add_request(obj->ring, NULL, request);
718 free(request, DRM_I915_GEM);
721 i915_gem_retire_requests_ring(obj->ring);
722 args->busy = obj->active;
725 drm_gem_object_unreference(&obj->base);
732 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
734 struct drm_i915_private *dev_priv;
735 struct drm_i915_file_private *file_priv;
736 unsigned long recent_enough;
737 struct drm_i915_gem_request *request;
738 struct intel_ring_buffer *ring;
742 dev_priv = dev->dev_private;
743 if (atomic_read(&dev_priv->mm.wedged))
746 file_priv = file->driver_priv;
747 recent_enough = ticks - (20 * hz / 1000);
751 mtx_lock(&file_priv->mm.lck);
752 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
753 if (time_after_eq(request->emitted_jiffies, recent_enough))
755 ring = request->ring;
756 seqno = request->seqno;
758 mtx_unlock(&file_priv->mm.lck);
763 mtx_lock(&ring->irq_lock);
764 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
765 if (ring->irq_get(ring)) {
767 !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
768 atomic_read(&dev_priv->mm.wedged)))
769 ret = -msleep(ring, &ring->irq_lock, PCATCH,
772 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
774 } else if (_intel_wait_for(dev,
775 i915_seqno_passed(ring->get_seqno(ring), seqno) ||
776 atomic_read(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
780 mtx_unlock(&ring->irq_lock);
783 taskqueue_enqueue_timeout(dev_priv->tq,
784 &dev_priv->mm.retire_task, 0);
790 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
791 struct drm_file *file_priv)
794 return (i915_gem_ring_throttle(dev, file_priv));
798 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
799 struct drm_file *file_priv)
801 struct drm_i915_gem_madvise *args;
802 struct drm_i915_gem_object *obj;
806 switch (args->madv) {
807 case I915_MADV_DONTNEED:
808 case I915_MADV_WILLNEED:
814 ret = i915_mutex_lock_interruptible(dev);
818 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
819 if (&obj->base == NULL) {
824 if (obj->pin_count != 0) {
829 if (obj->madv != I915_MADV_PURGED_INTERNAL)
830 obj->madv = args->madv;
831 if (i915_gem_object_is_purgeable(obj) && obj->gtt_space == NULL)
832 i915_gem_object_truncate(obj);
833 args->retained = obj->madv != I915_MADV_PURGED_INTERNAL;
836 drm_gem_object_unreference(&obj->base);
843 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
845 drm_i915_private_t *dev_priv;
848 dev_priv = dev->dev_private;
849 for (i = 0; i < I915_NUM_RINGS; i++)
850 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
854 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
855 struct drm_file *file_priv)
857 drm_i915_private_t *dev_priv;
860 if (drm_core_check_feature(dev, DRIVER_MODESET))
862 dev_priv = dev->dev_private;
863 if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
864 DRM_ERROR("Reenabling wedged hardware, good luck\n");
865 atomic_store_rel_int(&dev_priv->mm.wedged, 0);
868 dev_priv->mm.suspended = 0;
870 ret = i915_gem_init_hw(dev);
875 KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
876 KASSERT(list_empty(&dev_priv->mm.flushing_list), ("flushing list"));
877 KASSERT(list_empty(&dev_priv->mm.inactive_list), ("inactive list"));
878 for (i = 0; i < I915_NUM_RINGS; i++) {
879 KASSERT(list_empty(&dev_priv->rings[i].active_list),
880 ("ring %d active list", i));
881 KASSERT(list_empty(&dev_priv->rings[i].request_list),
882 ("ring %d request list", i));
886 ret = drm_irq_install(dev);
889 goto cleanup_ringbuffer;
894 i915_gem_cleanup_ringbuffer(dev);
895 dev_priv->mm.suspended = 1;
901 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
902 struct drm_file *file_priv)
905 if (drm_core_check_feature(dev, DRIVER_MODESET))
908 drm_irq_uninstall(dev);
909 return (i915_gem_idle(dev));
913 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
916 struct drm_i915_gem_object *obj;
920 size = roundup(size, PAGE_SIZE);
924 obj = i915_gem_alloc_object(dev, size);
929 ret = drm_gem_handle_create(file, &obj->base, &handle);
931 drm_gem_object_release(&obj->base);
932 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
933 free(obj, DRM_I915_GEM);
937 /* drop reference from allocate - handle holds it now */
938 drm_gem_object_unreference(&obj->base);
939 CTR2(KTR_DRM, "object_create %p %x", obj, size);
945 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
946 struct drm_mode_create_dumb *args)
949 /* have to work out size/pitch and return them */
950 args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
951 args->size = args->pitch * args->height;
952 return (i915_gem_create(file, dev, args->size, &args->handle));
956 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
960 return (drm_gem_handle_delete(file, handle));
964 i915_gem_create_ioctl(struct drm_device *dev, void *data,
965 struct drm_file *file)
967 struct drm_i915_gem_create *args = data;
969 return (i915_gem_create(file, dev, args->size, &args->handle));
973 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
974 uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
975 struct drm_file *file)
982 int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
984 if (obj->gtt_offset != 0 && rw == UIO_READ)
985 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
987 do_bit17_swizzling = 0;
990 vm_obj = obj->base.vm_obj;
993 VM_OBJECT_WLOCK(vm_obj);
994 vm_object_pip_add(vm_obj, 1);
996 obj_pi = OFF_TO_IDX(offset);
997 obj_po = offset & PAGE_MASK;
999 m = i915_gem_wire_page(vm_obj, obj_pi);
1000 VM_OBJECT_WUNLOCK(vm_obj);
1003 sf = sf_buf_alloc(m, SFB_CPUPRIVATE);
1004 mkva = sf_buf_kva(sf);
1005 length = min(size, PAGE_SIZE - obj_po);
1006 while (length > 0) {
1007 if (do_bit17_swizzling &&
1008 (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
1009 cnt = roundup2(obj_po + 1, 64);
1010 cnt = min(cnt - obj_po, length);
1011 swizzled_po = obj_po ^ 64;
1014 swizzled_po = obj_po;
1017 ret = -copyout_nofault(
1018 (char *)mkva + swizzled_po,
1019 (void *)(uintptr_t)data_ptr, cnt);
1021 ret = -copyin_nofault(
1022 (void *)(uintptr_t)data_ptr,
1023 (char *)mkva + swizzled_po, cnt);
1034 VM_OBJECT_WLOCK(vm_obj);
1035 if (rw == UIO_WRITE)
1037 vm_page_reference(m);
1039 vm_page_unwire(m, 1);
1041 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
1046 vm_object_pip_wakeup(vm_obj);
1047 VM_OBJECT_WUNLOCK(vm_obj);
1053 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1054 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1060 obj_pi = OFF_TO_IDX(offset);
1061 obj_po = offset & PAGE_MASK;
1063 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1064 IDX_TO_OFF(obj_pi), size, PAT_WRITE_COMBINING);
1065 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva +
1067 pmap_unmapdev(mkva, size);
1072 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1073 uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1075 struct drm_i915_gem_object *obj;
1077 vm_offset_t start, end;
1082 start = trunc_page(data_ptr);
1083 end = round_page(data_ptr + size);
1084 npages = howmany(end - start, PAGE_SIZE);
1085 ma = malloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1087 npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1088 (vm_offset_t)data_ptr, size,
1089 (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1095 ret = i915_mutex_lock_interruptible(dev);
1099 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1100 if (&obj->base == NULL) {
1104 if (offset > obj->base.size || size > obj->base.size - offset) {
1109 if (rw == UIO_READ) {
1110 CTR3(KTR_DRM, "object_pread %p %jx %jx", obj, offset, size);
1111 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1115 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1118 if (obj->phys_obj) {
1119 CTR3(KTR_DRM, "object_phys_write %p %jx %jx", obj,
1121 ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1123 } else if (obj->gtt_space &&
1124 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1125 CTR3(KTR_DRM, "object_gtt_write %p %jx %jx", obj,
1127 ret = i915_gem_object_pin(obj, 0, true);
1130 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1133 ret = i915_gem_object_put_fence(obj);
1136 ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1139 i915_gem_object_unpin(obj);
1141 CTR3(KTR_DRM, "object_pwrite %p %jx %jx", obj,
1143 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1146 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1151 drm_gem_object_unreference(&obj->base);
1155 vm_page_unhold_pages(ma, npages);
1157 free(ma, DRM_I915_GEM);
1162 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1164 struct drm_i915_gem_pread *args;
1167 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1168 args->offset, UIO_READ, file));
1172 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1174 struct drm_i915_gem_pwrite *args;
1177 return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1178 args->offset, UIO_WRITE, file));
1182 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1183 struct drm_file *file)
1185 struct drm_i915_gem_set_domain *args;
1186 struct drm_i915_gem_object *obj;
1187 uint32_t read_domains;
1188 uint32_t write_domain;
1191 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1195 read_domains = args->read_domains;
1196 write_domain = args->write_domain;
1198 if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1199 (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1200 (write_domain != 0 && read_domains != write_domain))
1203 ret = i915_mutex_lock_interruptible(dev);
1207 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1208 if (&obj->base == NULL) {
1213 if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1214 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1218 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1220 drm_gem_object_unreference(&obj->base);
1227 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1228 struct drm_file *file)
1230 struct drm_i915_gem_sw_finish *args;
1231 struct drm_i915_gem_object *obj;
1236 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1238 ret = i915_mutex_lock_interruptible(dev);
1241 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1242 if (&obj->base == NULL) {
1246 if (obj->pin_count != 0)
1247 i915_gem_object_flush_cpu_write_domain(obj);
1248 drm_gem_object_unreference(&obj->base);
1255 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1256 struct drm_file *file)
1258 struct drm_i915_gem_mmap *args;
1259 struct drm_gem_object *obj;
1268 if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1271 obj = drm_gem_object_lookup(dev, file, args->handle);
1275 if (args->size == 0)
1278 map = &p->p_vmspace->vm_map;
1279 size = round_page(args->size);
1281 if (map->size + size > lim_cur(p, RLIMIT_VMEM)) {
1289 vm_object_reference(obj->vm_obj);
1291 rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
1292 VMFS_ANY_SPACE, VM_PROT_READ | VM_PROT_WRITE,
1293 VM_PROT_READ | VM_PROT_WRITE, MAP_SHARED);
1294 if (rv != KERN_SUCCESS) {
1295 vm_object_deallocate(obj->vm_obj);
1296 error = -vm_mmap_to_errno(rv);
1298 args->addr_ptr = (uint64_t)addr;
1302 drm_gem_object_unreference(obj);
1307 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1308 vm_ooffset_t foff, struct ucred *cred, u_short *color)
1311 *color = 0; /* XXXKIB */
1318 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1321 struct drm_gem_object *gem_obj;
1322 struct drm_i915_gem_object *obj;
1323 struct drm_device *dev;
1324 drm_i915_private_t *dev_priv;
1329 gem_obj = vm_obj->handle;
1330 obj = to_intel_bo(gem_obj);
1331 dev = obj->base.dev;
1332 dev_priv = dev->dev_private;
1334 write = (prot & VM_PROT_WRITE) != 0;
1338 vm_object_pip_add(vm_obj, 1);
1341 * Remove the placeholder page inserted by vm_fault() from the
1342 * object before dropping the object lock. If
1343 * i915_gem_release_mmap() is active in parallel on this gem
1344 * object, then it owns the drm device sx and might find the
1345 * placeholder already. Then, since the page is busy,
1346 * i915_gem_release_mmap() sleeps waiting for the busy state
1347 * of the page cleared. We will be not able to acquire drm
1348 * device lock until i915_gem_release_mmap() is able to make a
1351 if (*mres != NULL) {
1354 vm_page_remove(oldm);
1355 vm_page_unlock(oldm);
1360 VM_OBJECT_WUNLOCK(vm_obj);
1367 ret = i915_mutex_lock_interruptible(dev);
1375 /* Now bind it into the GTT if needed */
1376 if (!obj->map_and_fenceable) {
1377 ret = i915_gem_object_unbind(obj);
1383 if (!obj->gtt_space) {
1384 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1390 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1397 if (obj->tiling_mode == I915_TILING_NONE)
1398 ret = i915_gem_object_put_fence(obj);
1400 ret = i915_gem_object_get_fence(obj, NULL);
1406 if (i915_gem_object_is_inactive(obj))
1407 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1409 obj->fault_mappable = true;
1410 VM_OBJECT_WLOCK(vm_obj);
1411 m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1418 KASSERT((m->flags & PG_FICTITIOUS) != 0,
1419 ("not fictitious %p", m));
1420 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1422 if ((m->flags & VPO_BUSY) != 0) {
1424 vm_page_sleep(m, "915pbs");
1427 m->valid = VM_PAGE_BITS_ALL;
1429 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1432 CTR4(KTR_DRM, "fault %p %jx %x phys %x", gem_obj, offset, prot,
1438 vm_page_unlock(oldm);
1440 vm_object_pip_wakeup(vm_obj);
1441 return (VM_PAGER_OK);
1446 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1447 CTR5(KTR_DRM, "fault_fail %p %jx %x err %d %d", gem_obj, offset, prot,
1449 if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1450 kern_yield(PRI_USER);
1451 goto unlocked_vmobj;
1453 VM_OBJECT_WLOCK(vm_obj);
1454 vm_object_pip_wakeup(vm_obj);
1455 return (VM_PAGER_ERROR);
1459 i915_gem_pager_dtor(void *handle)
1461 struct drm_gem_object *obj;
1462 struct drm_device *dev;
1468 drm_gem_free_mmap_offset(obj);
1469 i915_gem_release_mmap(to_intel_bo(obj));
1470 drm_gem_object_unreference(obj);
1474 struct cdev_pager_ops i915_gem_pager_ops = {
1475 .cdev_pg_fault = i915_gem_pager_fault,
1476 .cdev_pg_ctor = i915_gem_pager_ctor,
1477 .cdev_pg_dtor = i915_gem_pager_dtor
1481 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1482 uint32_t handle, uint64_t *offset)
1484 struct drm_i915_private *dev_priv;
1485 struct drm_i915_gem_object *obj;
1488 if (!(dev->driver->driver_features & DRIVER_GEM))
1491 dev_priv = dev->dev_private;
1493 ret = i915_mutex_lock_interruptible(dev);
1497 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1498 if (&obj->base == NULL) {
1503 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1508 if (obj->madv != I915_MADV_WILLNEED) {
1509 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1514 ret = drm_gem_create_mmap_offset(&obj->base);
1518 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1519 DRM_GEM_MAPPING_KEY;
1521 drm_gem_object_unreference(&obj->base);
1528 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1529 struct drm_file *file)
1531 struct drm_i915_private *dev_priv;
1532 struct drm_i915_gem_mmap_gtt *args;
1534 dev_priv = dev->dev_private;
1537 return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1540 struct drm_i915_gem_object *
1541 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1543 struct drm_i915_private *dev_priv;
1544 struct drm_i915_gem_object *obj;
1546 dev_priv = dev->dev_private;
1548 obj = malloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1550 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1551 free(obj, DRM_I915_GEM);
1555 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1556 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1559 obj->cache_level = I915_CACHE_LLC;
1561 obj->cache_level = I915_CACHE_NONE;
1562 obj->base.driver_private = NULL;
1563 obj->fence_reg = I915_FENCE_REG_NONE;
1564 INIT_LIST_HEAD(&obj->mm_list);
1565 INIT_LIST_HEAD(&obj->gtt_list);
1566 INIT_LIST_HEAD(&obj->ring_list);
1567 INIT_LIST_HEAD(&obj->exec_list);
1568 INIT_LIST_HEAD(&obj->gpu_write_list);
1569 obj->madv = I915_MADV_WILLNEED;
1570 /* Avoid an unnecessary call to unbind on the first bind. */
1571 obj->map_and_fenceable = true;
1573 i915_gem_info_add_obj(dev_priv, size);
1579 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1582 /* If we don't have a page list set up, then we're not pinned
1583 * to GPU, and we can ignore the cache flush because it'll happen
1584 * again at bind time.
1586 if (obj->pages == NULL)
1589 /* If the GPU is snooping the contents of the CPU cache,
1590 * we do not need to manually clear the CPU cache lines. However,
1591 * the caches are only snooped when the render cache is
1592 * flushed/invalidated. As we always have to emit invalidations
1593 * and flushes when moving into and out of the RENDER domain, correct
1594 * snooping behaviour occurs naturally as the result of our domain
1597 if (obj->cache_level != I915_CACHE_NONE)
1600 CTR1(KTR_DRM, "object_clflush %p", obj);
1601 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1605 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1607 uint32_t old_write_domain;
1609 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1612 i915_gem_clflush_object(obj);
1613 intel_gtt_chipset_flush();
1614 old_write_domain = obj->base.write_domain;
1615 obj->base.write_domain = 0;
1617 CTR3(KTR_DRM, "object_change_domain flush_cpu_write %p %x %x", obj,
1618 obj->base.read_domains, old_write_domain);
1622 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
1625 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
1627 return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
1631 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1633 uint32_t old_write_domain;
1635 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1640 old_write_domain = obj->base.write_domain;
1641 obj->base.write_domain = 0;
1643 CTR3(KTR_DRM, "object_change_domain flush gtt_write %p %x %x", obj,
1644 obj->base.read_domains, old_write_domain);
1648 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1650 uint32_t old_write_domain, old_read_domains;
1653 if (obj->gtt_space == NULL)
1656 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1659 ret = i915_gem_object_flush_gpu_write_domain(obj);
1663 if (obj->pending_gpu_write || write) {
1664 ret = i915_gem_object_wait_rendering(obj);
1669 i915_gem_object_flush_cpu_write_domain(obj);
1671 old_write_domain = obj->base.write_domain;
1672 old_read_domains = obj->base.read_domains;
1674 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1675 ("In GTT write domain"));
1676 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1678 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1679 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1683 CTR3(KTR_DRM, "object_change_domain set_to_gtt %p %x %x", obj,
1684 old_read_domains, old_write_domain);
1689 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1690 enum i915_cache_level cache_level)
1692 struct drm_device *dev;
1693 drm_i915_private_t *dev_priv;
1696 if (obj->cache_level == cache_level)
1699 if (obj->pin_count) {
1700 DRM_DEBUG("can not change the cache level of pinned objects\n");
1704 dev = obj->base.dev;
1705 dev_priv = dev->dev_private;
1706 if (obj->gtt_space) {
1707 ret = i915_gem_object_finish_gpu(obj);
1711 i915_gem_object_finish_gtt(obj);
1713 /* Before SandyBridge, you could not use tiling or fence
1714 * registers with snooped memory, so relinquish any fences
1715 * currently pointing to our region in the aperture.
1717 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1718 ret = i915_gem_object_put_fence(obj);
1723 i915_gem_gtt_rebind_object(obj, cache_level);
1724 if (obj->has_aliasing_ppgtt_mapping)
1725 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1729 if (cache_level == I915_CACHE_NONE) {
1730 u32 old_read_domains, old_write_domain;
1732 /* If we're coming from LLC cached, then we haven't
1733 * actually been tracking whether the data is in the
1734 * CPU cache or not, since we only allow one bit set
1735 * in obj->write_domain and have been skipping the clflushes.
1736 * Just set it to the CPU cache for now.
1738 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1739 ("obj %p in CPU write domain", obj));
1740 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1741 ("obj %p in CPU read domain", obj));
1743 old_read_domains = obj->base.read_domains;
1744 old_write_domain = obj->base.write_domain;
1746 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1747 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1749 CTR3(KTR_DRM, "object_change_domain set_cache_level %p %x %x",
1750 obj, old_read_domains, old_write_domain);
1753 obj->cache_level = cache_level;
1758 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1759 u32 alignment, struct intel_ring_buffer *pipelined)
1761 u32 old_read_domains, old_write_domain;
1764 ret = i915_gem_object_flush_gpu_write_domain(obj);
1768 if (pipelined != obj->ring) {
1769 ret = i915_gem_object_wait_rendering(obj);
1770 if (ret == -ERESTART || ret == -EINTR)
1774 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1778 ret = i915_gem_object_pin(obj, alignment, true);
1782 i915_gem_object_flush_cpu_write_domain(obj);
1784 old_write_domain = obj->base.write_domain;
1785 old_read_domains = obj->base.read_domains;
1787 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1788 ("obj %p in GTT write domain", obj));
1789 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1791 CTR3(KTR_DRM, "object_change_domain pin_to_display_plan %p %x %x",
1792 obj, old_read_domains, obj->base.write_domain);
1797 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1801 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1804 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1805 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1810 ret = i915_gem_object_wait_rendering(obj);
1814 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1820 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
1822 uint32_t old_write_domain, old_read_domains;
1825 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
1828 ret = i915_gem_object_flush_gpu_write_domain(obj);
1832 ret = i915_gem_object_wait_rendering(obj);
1836 i915_gem_object_flush_gtt_write_domain(obj);
1837 i915_gem_object_set_to_full_cpu_read_domain(obj);
1839 old_write_domain = obj->base.write_domain;
1840 old_read_domains = obj->base.read_domains;
1842 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1843 i915_gem_clflush_object(obj);
1844 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1847 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1848 ("In cpu write domain"));
1851 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1852 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1855 CTR3(KTR_DRM, "object_change_domain set_to_cpu %p %x %x", obj,
1856 old_read_domains, old_write_domain);
1861 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
1865 if (obj->page_cpu_valid == NULL)
1868 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) {
1869 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
1870 if (obj->page_cpu_valid[i] != 0)
1872 drm_clflush_pages(obj->pages + i, 1);
1876 free(obj->page_cpu_valid, DRM_I915_GEM);
1877 obj->page_cpu_valid = NULL;
1881 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1882 uint64_t offset, uint64_t size)
1884 uint32_t old_read_domains;
1887 if (offset == 0 && size == obj->base.size)
1888 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1890 ret = i915_gem_object_flush_gpu_write_domain(obj);
1893 ret = i915_gem_object_wait_rendering(obj);
1897 i915_gem_object_flush_gtt_write_domain(obj);
1899 if (obj->page_cpu_valid == NULL &&
1900 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1903 if (obj->page_cpu_valid == NULL) {
1904 obj->page_cpu_valid = malloc(obj->base.size / PAGE_SIZE,
1905 DRM_I915_GEM, M_WAITOK | M_ZERO);
1906 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1907 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1909 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1911 if (obj->page_cpu_valid[i])
1913 drm_clflush_pages(obj->pages + i, 1);
1914 obj->page_cpu_valid[i] = 1;
1917 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1918 ("In gpu write domain"));
1920 old_read_domains = obj->base.read_domains;
1921 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1923 CTR3(KTR_DRM, "object_change_domain set_cpu_read %p %x %x", obj,
1924 old_read_domains, obj->base.write_domain);
1929 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1933 if (INTEL_INFO(dev)->gen >= 4 ||
1934 tiling_mode == I915_TILING_NONE)
1937 /* Previous chips need a power-of-two fence region when tiling */
1938 if (INTEL_INFO(dev)->gen == 3)
1939 gtt_size = 1024*1024;
1941 gtt_size = 512*1024;
1943 while (gtt_size < size)
1950 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1951 * @obj: object to check
1953 * Return the required GTT alignment for an object, taking into account
1954 * potential fence register mapping.
1957 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1962 * Minimum alignment is 4k (GTT page size), but might be greater
1963 * if a fence register is needed for the object.
1965 if (INTEL_INFO(dev)->gen >= 4 ||
1966 tiling_mode == I915_TILING_NONE)
1970 * Previous chips need to be aligned to the size of the smallest
1971 * fence register that can contain the object.
1973 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1977 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
1981 if (tiling_mode == I915_TILING_NONE)
1985 * Minimum alignment is 4k (GTT page size) for sane hw.
1987 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
1991 * Previous hardware however needs to be aligned to a power-of-two
1992 * tile height. The simplest method for determining this is to reuse
1993 * the power-of-tile object size.
1995 return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1999 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2000 unsigned alignment, bool map_and_fenceable)
2002 struct drm_device *dev;
2003 struct drm_i915_private *dev_priv;
2004 struct drm_mm_node *free_space;
2005 uint32_t size, fence_size, fence_alignment, unfenced_alignment;
2006 bool mappable, fenceable;
2009 dev = obj->base.dev;
2010 dev_priv = dev->dev_private;
2012 if (obj->madv != I915_MADV_WILLNEED) {
2013 DRM_ERROR("Attempting to bind a purgeable object\n");
2017 fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
2019 fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
2021 unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
2022 obj->base.size, obj->tiling_mode);
2024 alignment = map_and_fenceable ? fence_alignment :
2026 if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
2027 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2031 size = map_and_fenceable ? fence_size : obj->base.size;
2033 /* If the object is bigger than the entire aperture, reject it early
2034 * before evicting everything in a vain attempt to find space.
2036 if (obj->base.size > (map_and_fenceable ?
2037 dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2039 "Attempting to bind an object larger than the aperture\n");
2044 if (map_and_fenceable)
2045 free_space = drm_mm_search_free_in_range(
2046 &dev_priv->mm.gtt_space, size, alignment, 0,
2047 dev_priv->mm.gtt_mappable_end, 0);
2049 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2050 size, alignment, 0);
2051 if (free_space != NULL) {
2052 if (map_and_fenceable)
2053 obj->gtt_space = drm_mm_get_block_range_generic(
2054 free_space, size, alignment, 0,
2055 dev_priv->mm.gtt_mappable_end, 1);
2057 obj->gtt_space = drm_mm_get_block_generic(free_space,
2058 size, alignment, 1);
2060 if (obj->gtt_space == NULL) {
2061 ret = i915_gem_evict_something(dev, size, alignment,
2067 ret = i915_gem_object_get_pages_gtt(obj, 0);
2069 drm_mm_put_block(obj->gtt_space);
2070 obj->gtt_space = NULL;
2072 * i915_gem_object_get_pages_gtt() cannot return
2073 * ENOMEM, since we use vm_page_grab(VM_ALLOC_RETRY)
2074 * (which does not support operation without a flag
2080 ret = i915_gem_gtt_bind_object(obj);
2082 i915_gem_object_put_pages_gtt(obj);
2083 drm_mm_put_block(obj->gtt_space);
2084 obj->gtt_space = NULL;
2085 if (i915_gem_evict_everything(dev, false))
2090 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2091 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2093 KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2094 ("Object in gpu read domain"));
2095 KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2096 ("Object in gpu write domain"));
2098 obj->gtt_offset = obj->gtt_space->start;
2101 obj->gtt_space->size == fence_size &&
2102 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2105 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2106 obj->map_and_fenceable = mappable && fenceable;
2108 CTR4(KTR_DRM, "object_bind %p %x %x %d", obj, obj->gtt_offset,
2109 obj->base.size, map_and_fenceable);
2114 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2116 u32 old_write_domain, old_read_domains;
2118 /* Act a barrier for all accesses through the GTT */
2121 /* Force a pagefault for domain tracking on next user access */
2122 i915_gem_release_mmap(obj);
2124 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2127 old_read_domains = obj->base.read_domains;
2128 old_write_domain = obj->base.write_domain;
2130 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2131 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2133 CTR3(KTR_DRM, "object_change_domain finish gtt %p %x %x",
2134 obj, old_read_domains, old_write_domain);
2138 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2140 drm_i915_private_t *dev_priv;
2143 dev_priv = obj->base.dev->dev_private;
2145 if (obj->gtt_space == NULL)
2147 if (obj->pin_count != 0) {
2148 DRM_ERROR("Attempting to unbind pinned buffer\n");
2152 ret = i915_gem_object_finish_gpu(obj);
2153 if (ret == -ERESTART || ret == -EINTR)
2156 i915_gem_object_finish_gtt(obj);
2159 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2160 if (ret == -ERESTART || ret == -EINTR)
2163 i915_gem_clflush_object(obj);
2164 obj->base.read_domains = obj->base.write_domain =
2165 I915_GEM_DOMAIN_CPU;
2168 ret = i915_gem_object_put_fence(obj);
2169 if (ret == -ERESTART)
2172 i915_gem_gtt_unbind_object(obj);
2173 if (obj->has_aliasing_ppgtt_mapping) {
2174 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2175 obj->has_aliasing_ppgtt_mapping = 0;
2177 i915_gem_object_put_pages_gtt(obj);
2179 list_del_init(&obj->gtt_list);
2180 list_del_init(&obj->mm_list);
2181 obj->map_and_fenceable = true;
2183 drm_mm_put_block(obj->gtt_space);
2184 obj->gtt_space = NULL;
2185 obj->gtt_offset = 0;
2187 if (i915_gem_object_is_purgeable(obj))
2188 i915_gem_object_truncate(obj);
2189 CTR1(KTR_DRM, "object_unbind %p", obj);
2195 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2198 struct drm_device *dev;
2201 int page_count, i, j;
2203 dev = obj->base.dev;
2204 KASSERT(obj->pages == NULL, ("Obj already has pages"));
2205 page_count = obj->base.size / PAGE_SIZE;
2206 obj->pages = malloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2208 vm_obj = obj->base.vm_obj;
2209 VM_OBJECT_WLOCK(vm_obj);
2210 for (i = 0; i < page_count; i++) {
2211 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2214 VM_OBJECT_WUNLOCK(vm_obj);
2215 if (i915_gem_object_needs_bit17_swizzle(obj))
2216 i915_gem_object_do_bit_17_swizzle(obj);
2220 for (j = 0; j < i; j++) {
2223 vm_page_unwire(m, 0);
2225 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2227 VM_OBJECT_WUNLOCK(vm_obj);
2228 free(obj->pages, DRM_I915_GEM);
2233 #define GEM_PARANOID_CHECK_GTT 0
2234 #if GEM_PARANOID_CHECK_GTT
2236 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2239 struct drm_i915_private *dev_priv;
2241 unsigned long start, end;
2245 dev_priv = dev->dev_private;
2246 start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2247 end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2248 for (i = start; i < end; i++) {
2249 pa = intel_gtt_read_pte_paddr(i);
2250 for (j = 0; j < page_count; j++) {
2251 if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2252 panic("Page %p in GTT pte index %d pte %x",
2253 ma[i], i, intel_gtt_read_pte(i));
2261 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2266 KASSERT(obj->madv != I915_MADV_PURGED_INTERNAL, ("Purged object"));
2268 if (obj->tiling_mode != I915_TILING_NONE)
2269 i915_gem_object_save_bit_17_swizzle(obj);
2270 if (obj->madv == I915_MADV_DONTNEED)
2272 page_count = obj->base.size / PAGE_SIZE;
2273 VM_OBJECT_WLOCK(obj->base.vm_obj);
2274 #if GEM_PARANOID_CHECK_GTT
2275 i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2277 for (i = 0; i < page_count; i++) {
2281 if (obj->madv == I915_MADV_WILLNEED)
2282 vm_page_reference(m);
2284 vm_page_unwire(obj->pages[i], 1);
2286 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2288 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
2290 free(obj->pages, DRM_I915_GEM);
2295 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2301 if (!obj->fault_mappable)
2304 CTR3(KTR_DRM, "release_mmap %p %x %x", obj, obj->gtt_offset,
2305 OFF_TO_IDX(obj->base.size));
2306 devobj = cdev_pager_lookup(obj);
2307 if (devobj != NULL) {
2308 page_count = OFF_TO_IDX(obj->base.size);
2310 VM_OBJECT_WLOCK(devobj);
2312 for (i = 0; i < page_count; i++) {
2313 m = vm_page_lookup(devobj, i);
2316 if (vm_page_sleep_if_busy(m, true, "915unm"))
2318 cdev_pager_free_page(devobj, m);
2320 VM_OBJECT_WUNLOCK(devobj);
2321 vm_object_deallocate(devobj);
2324 obj->fault_mappable = false;
2328 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2332 KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2333 ("In GPU write domain"));
2335 CTR5(KTR_DRM, "object_wait_rendering %p %s %x %d %d", obj,
2336 obj->ring != NULL ? obj->ring->name : "none", obj->gtt_offset,
2337 obj->active, obj->last_rendering_seqno);
2339 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2348 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2349 struct intel_ring_buffer *ring, uint32_t seqno)
2351 struct drm_device *dev = obj->base.dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct drm_i915_fence_reg *reg;
2356 KASSERT(ring != NULL, ("NULL ring"));
2358 /* Add a reference if we're newly entering the active list. */
2360 drm_gem_object_reference(&obj->base);
2364 /* Move from whatever list we were on to the tail of execution. */
2365 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2366 list_move_tail(&obj->ring_list, &ring->active_list);
2368 obj->last_rendering_seqno = seqno;
2369 if (obj->fenced_gpu_access) {
2370 obj->last_fenced_seqno = seqno;
2371 obj->last_fenced_ring = ring;
2373 /* Bump MRU to take account of the delayed flush */
2374 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2375 reg = &dev_priv->fence_regs[obj->fence_reg];
2376 list_move_tail(®->lru_list,
2377 &dev_priv->mm.fence_list);
2383 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2385 list_del_init(&obj->ring_list);
2386 obj->last_rendering_seqno = 0;
2387 obj->last_fenced_seqno = 0;
2391 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2393 struct drm_device *dev = obj->base.dev;
2394 drm_i915_private_t *dev_priv = dev->dev_private;
2396 KASSERT(obj->active, ("Object not active"));
2397 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2399 i915_gem_object_move_off_active(obj);
2403 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2405 struct drm_device *dev = obj->base.dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2408 if (obj->pin_count != 0)
2409 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2411 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2413 KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2414 KASSERT(obj->active, ("Object not active"));
2416 obj->last_fenced_ring = NULL;
2418 i915_gem_object_move_off_active(obj);
2419 obj->fenced_gpu_access = false;
2422 obj->pending_gpu_write = false;
2423 drm_gem_object_unreference(&obj->base);
2428 WARN_ON(i915_verify_lists(dev));
2433 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2437 vm_obj = obj->base.vm_obj;
2438 VM_OBJECT_WLOCK(vm_obj);
2439 vm_object_page_remove(vm_obj, 0, 0, false);
2440 VM_OBJECT_WUNLOCK(vm_obj);
2441 obj->madv = I915_MADV_PURGED_INTERNAL;
2445 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2448 return (obj->madv == I915_MADV_DONTNEED);
2452 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2453 uint32_t flush_domains)
2455 struct drm_i915_gem_object *obj, *next;
2456 uint32_t old_write_domain;
2458 list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2460 if (obj->base.write_domain & flush_domains) {
2461 old_write_domain = obj->base.write_domain;
2462 obj->base.write_domain = 0;
2463 list_del_init(&obj->gpu_write_list);
2464 i915_gem_object_move_to_active(obj, ring,
2465 i915_gem_next_request_seqno(ring));
2467 CTR3(KTR_DRM, "object_change_domain process_flush %p %x %x",
2468 obj, obj->base.read_domains, old_write_domain);
2474 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2476 drm_i915_private_t *dev_priv;
2478 dev_priv = obj->base.dev->dev_private;
2479 return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2480 obj->tiling_mode != I915_TILING_NONE);
2484 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2489 VM_OBJECT_ASSERT_WLOCKED(object);
2490 m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY |
2492 if (m->valid != VM_PAGE_BITS_ALL) {
2494 if (vm_pager_has_page(object, pindex, NULL, NULL)) {
2495 rv = vm_pager_get_pages(object, &m, 1, 0);
2496 m = vm_page_lookup(object, pindex);
2499 if (rv != VM_PAGER_OK) {
2507 m->valid = VM_PAGE_BITS_ALL;
2515 atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2520 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2521 uint32_t flush_domains)
2525 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2528 CTR3(KTR_DRM, "ring_flush %s %x %x", ring->name, invalidate_domains,
2530 ret = ring->flush(ring, invalidate_domains, flush_domains);
2534 if (flush_domains & I915_GEM_GPU_DOMAINS)
2535 i915_gem_process_flushing_list(ring, flush_domains);
2540 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2544 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2547 if (!list_empty(&ring->gpu_write_list)) {
2548 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2549 I915_GEM_GPU_DOMAINS);
2554 return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2559 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2561 drm_i915_private_t *dev_priv = dev->dev_private;
2564 /* Flush everything onto the inactive list. */
2565 for (i = 0; i < I915_NUM_RINGS; i++) {
2566 ret = i915_ring_idle(&dev_priv->rings[i], do_retire);
2575 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2577 drm_i915_private_t *dev_priv;
2578 struct drm_i915_gem_request *request;
2581 bool recovery_complete;
2583 KASSERT(seqno != 0, ("Zero seqno"));
2585 dev_priv = ring->dev->dev_private;
2588 if (atomic_load_acq_int(&dev_priv->mm.wedged) != 0) {
2589 /* Give the error handler a chance to run. */
2590 mtx_lock(&dev_priv->error_completion_lock);
2591 recovery_complete = (&dev_priv->error_completion) > 0;
2592 mtx_unlock(&dev_priv->error_completion_lock);
2593 return (recovery_complete ? -EIO : -EAGAIN);
2596 if (seqno == ring->outstanding_lazy_request) {
2597 request = malloc(sizeof(*request), DRM_I915_GEM,
2599 if (request == NULL)
2602 ret = i915_add_request(ring, NULL, request);
2604 free(request, DRM_I915_GEM);
2608 seqno = request->seqno;
2611 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2612 if (HAS_PCH_SPLIT(ring->dev))
2613 ier = I915_READ(DEIER) | I915_READ(GTIER);
2615 ier = I915_READ(IER);
2617 DRM_ERROR("something (likely vbetool) disabled "
2618 "interrupts, re-enabling\n");
2619 ring->dev->driver->irq_preinstall(ring->dev);
2620 ring->dev->driver->irq_postinstall(ring->dev);
2623 CTR2(KTR_DRM, "request_wait_begin %s %d", ring->name, seqno);
2625 ring->waiting_seqno = seqno;
2626 mtx_lock(&ring->irq_lock);
2627 if (ring->irq_get(ring)) {
2628 flags = dev_priv->mm.interruptible ? PCATCH : 0;
2629 while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2630 && !atomic_load_acq_int(&dev_priv->mm.wedged) &&
2632 ret = -msleep(ring, &ring->irq_lock, flags,
2635 ring->irq_put(ring);
2636 mtx_unlock(&ring->irq_lock);
2638 mtx_unlock(&ring->irq_lock);
2639 if (_intel_wait_for(ring->dev,
2640 i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2641 atomic_load_acq_int(&dev_priv->mm.wedged), 3000,
2645 ring->waiting_seqno = 0;
2647 CTR3(KTR_DRM, "request_wait_end %s %d %d", ring->name, seqno,
2650 if (atomic_load_acq_int(&dev_priv->mm.wedged))
2653 /* Directly dispatch request retiring. While we have the work queue
2654 * to handle this, the waiter on a request often wants an associated
2655 * buffer to have made it to the inactive list, and we would need
2656 * a separate wait queue to handle that.
2658 if (ret == 0 && do_retire)
2659 i915_gem_retire_requests_ring(ring);
2665 i915_gem_get_seqno(struct drm_device *dev)
2667 drm_i915_private_t *dev_priv = dev->dev_private;
2668 u32 seqno = dev_priv->next_seqno;
2670 /* reserve 0 for non-seqno */
2671 if (++dev_priv->next_seqno == 0)
2672 dev_priv->next_seqno = 1;
2678 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2680 if (ring->outstanding_lazy_request == 0)
2681 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2683 return ring->outstanding_lazy_request;
2687 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2688 struct drm_i915_gem_request *request)
2690 drm_i915_private_t *dev_priv;
2691 struct drm_i915_file_private *file_priv;
2693 u32 request_ring_position;
2697 KASSERT(request != NULL, ("NULL request in add"));
2698 DRM_LOCK_ASSERT(ring->dev);
2699 dev_priv = ring->dev->dev_private;
2701 seqno = i915_gem_next_request_seqno(ring);
2702 request_ring_position = intel_ring_get_tail(ring);
2704 ret = ring->add_request(ring, &seqno);
2708 CTR2(KTR_DRM, "request_add %s %d", ring->name, seqno);
2710 request->seqno = seqno;
2711 request->ring = ring;
2712 request->tail = request_ring_position;
2713 request->emitted_jiffies = ticks;
2714 was_empty = list_empty(&ring->request_list);
2715 list_add_tail(&request->list, &ring->request_list);
2718 file_priv = file->driver_priv;
2720 mtx_lock(&file_priv->mm.lck);
2721 request->file_priv = file_priv;
2722 list_add_tail(&request->client_list,
2723 &file_priv->mm.request_list);
2724 mtx_unlock(&file_priv->mm.lck);
2727 ring->outstanding_lazy_request = 0;
2729 if (!dev_priv->mm.suspended) {
2730 if (i915_enable_hangcheck) {
2731 callout_schedule(&dev_priv->hangcheck_timer,
2732 DRM_I915_HANGCHECK_PERIOD);
2735 taskqueue_enqueue_timeout(dev_priv->tq,
2736 &dev_priv->mm.retire_task, hz);
2742 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2744 struct drm_i915_file_private *file_priv = request->file_priv;
2749 DRM_LOCK_ASSERT(request->ring->dev);
2751 mtx_lock(&file_priv->mm.lck);
2752 if (request->file_priv != NULL) {
2753 list_del(&request->client_list);
2754 request->file_priv = NULL;
2756 mtx_unlock(&file_priv->mm.lck);
2760 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2762 struct drm_i915_file_private *file_priv;
2763 struct drm_i915_gem_request *request;
2765 file_priv = file->driver_priv;
2767 /* Clean up our request list when the client is going away, so that
2768 * later retire_requests won't dereference our soon-to-be-gone
2771 mtx_lock(&file_priv->mm.lck);
2772 while (!list_empty(&file_priv->mm.request_list)) {
2773 request = list_first_entry(&file_priv->mm.request_list,
2774 struct drm_i915_gem_request,
2776 list_del(&request->client_list);
2777 request->file_priv = NULL;
2779 mtx_unlock(&file_priv->mm.lck);
2783 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2784 struct intel_ring_buffer *ring)
2787 if (ring->dev != NULL)
2788 DRM_LOCK_ASSERT(ring->dev);
2790 while (!list_empty(&ring->request_list)) {
2791 struct drm_i915_gem_request *request;
2793 request = list_first_entry(&ring->request_list,
2794 struct drm_i915_gem_request, list);
2796 list_del(&request->list);
2797 i915_gem_request_remove_from_client(request);
2798 free(request, DRM_I915_GEM);
2801 while (!list_empty(&ring->active_list)) {
2802 struct drm_i915_gem_object *obj;
2804 obj = list_first_entry(&ring->active_list,
2805 struct drm_i915_gem_object, ring_list);
2807 obj->base.write_domain = 0;
2808 list_del_init(&obj->gpu_write_list);
2809 i915_gem_object_move_to_inactive(obj);
2814 i915_gem_reset_fences(struct drm_device *dev)
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2819 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2820 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2821 struct drm_i915_gem_object *obj = reg->obj;
2826 if (obj->tiling_mode)
2827 i915_gem_release_mmap(obj);
2829 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2830 reg->obj->fenced_gpu_access = false;
2831 reg->obj->last_fenced_seqno = 0;
2832 reg->obj->last_fenced_ring = NULL;
2833 i915_gem_clear_fence_reg(dev, reg);
2838 i915_gem_reset(struct drm_device *dev)
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841 struct drm_i915_gem_object *obj;
2844 for (i = 0; i < I915_NUM_RINGS; i++)
2845 i915_gem_reset_ring_lists(dev_priv, &dev_priv->rings[i]);
2847 /* Remove anything from the flushing lists. The GPU cache is likely
2848 * to be lost on reset along with the data, so simply move the
2849 * lost bo to the inactive list.
2851 while (!list_empty(&dev_priv->mm.flushing_list)) {
2852 obj = list_first_entry(&dev_priv->mm.flushing_list,
2853 struct drm_i915_gem_object,
2856 obj->base.write_domain = 0;
2857 list_del_init(&obj->gpu_write_list);
2858 i915_gem_object_move_to_inactive(obj);
2861 /* Move everything out of the GPU domains to ensure we do any
2862 * necessary invalidation upon reuse.
2864 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2865 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2868 /* The fence registers are invalidated so clear them out */
2869 i915_gem_reset_fences(dev);
2873 * This function clears the request list as sequence numbers are passed.
2876 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2881 if (list_empty(&ring->request_list))
2884 seqno = ring->get_seqno(ring);
2885 CTR2(KTR_DRM, "retire_request_ring %s %d", ring->name, seqno);
2887 for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2888 if (seqno >= ring->sync_seqno[i])
2889 ring->sync_seqno[i] = 0;
2891 while (!list_empty(&ring->request_list)) {
2892 struct drm_i915_gem_request *request;
2894 request = list_first_entry(&ring->request_list,
2895 struct drm_i915_gem_request,
2898 if (!i915_seqno_passed(seqno, request->seqno))
2901 CTR2(KTR_DRM, "retire_request_seqno_passed %s %d",
2903 ring->last_retired_head = request->tail;
2905 list_del(&request->list);
2906 i915_gem_request_remove_from_client(request);
2907 free(request, DRM_I915_GEM);
2910 /* Move any buffers on the active list that are no longer referenced
2911 * by the ringbuffer to the flushing/inactive lists as appropriate.
2913 while (!list_empty(&ring->active_list)) {
2914 struct drm_i915_gem_object *obj;
2916 obj = list_first_entry(&ring->active_list,
2917 struct drm_i915_gem_object,
2920 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2923 if (obj->base.write_domain != 0)
2924 i915_gem_object_move_to_flushing(obj);
2926 i915_gem_object_move_to_inactive(obj);
2929 if (ring->trace_irq_seqno &&
2930 i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2931 mtx_lock(&ring->irq_lock);
2932 ring->irq_put(ring);
2933 mtx_unlock(&ring->irq_lock);
2934 ring->trace_irq_seqno = 0;
2939 i915_gem_retire_requests(struct drm_device *dev)
2941 drm_i915_private_t *dev_priv = dev->dev_private;
2942 struct drm_i915_gem_object *obj, *next;
2945 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2946 list_for_each_entry_safe(obj, next,
2947 &dev_priv->mm.deferred_free_list, mm_list)
2948 i915_gem_free_object_tail(obj);
2951 for (i = 0; i < I915_NUM_RINGS; i++)
2952 i915_gem_retire_requests_ring(&dev_priv->rings[i]);
2956 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2957 struct intel_ring_buffer *pipelined)
2959 struct drm_device *dev = obj->base.dev;
2960 drm_i915_private_t *dev_priv = dev->dev_private;
2961 u32 size = obj->gtt_space->size;
2962 int regnum = obj->fence_reg;
2965 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2967 val |= obj->gtt_offset & 0xfffff000;
2968 val |= (uint64_t)((obj->stride / 128) - 1) <<
2969 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2971 if (obj->tiling_mode == I915_TILING_Y)
2972 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2973 val |= I965_FENCE_REG_VALID;
2976 int ret = intel_ring_begin(pipelined, 6);
2980 intel_ring_emit(pipelined, MI_NOOP);
2981 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2982 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2983 intel_ring_emit(pipelined, (u32)val);
2984 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2985 intel_ring_emit(pipelined, (u32)(val >> 32));
2986 intel_ring_advance(pipelined);
2988 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2994 i965_write_fence_reg(struct drm_i915_gem_object *obj,
2995 struct intel_ring_buffer *pipelined)
2997 struct drm_device *dev = obj->base.dev;
2998 drm_i915_private_t *dev_priv = dev->dev_private;
2999 u32 size = obj->gtt_space->size;
3000 int regnum = obj->fence_reg;
3003 val = (uint64_t)((obj->gtt_offset + size - 4096) &
3005 val |= obj->gtt_offset & 0xfffff000;
3006 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
3007 if (obj->tiling_mode == I915_TILING_Y)
3008 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3009 val |= I965_FENCE_REG_VALID;
3012 int ret = intel_ring_begin(pipelined, 6);
3016 intel_ring_emit(pipelined, MI_NOOP);
3017 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
3018 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
3019 intel_ring_emit(pipelined, (u32)val);
3020 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
3021 intel_ring_emit(pipelined, (u32)(val >> 32));
3022 intel_ring_advance(pipelined);
3024 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
3030 i915_write_fence_reg(struct drm_i915_gem_object *obj,
3031 struct intel_ring_buffer *pipelined)
3033 struct drm_device *dev = obj->base.dev;
3034 drm_i915_private_t *dev_priv = dev->dev_private;
3035 u32 size = obj->gtt_space->size;
3036 u32 fence_reg, val, pitch_val;
3039 if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
3040 (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3042 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3043 obj->gtt_offset, obj->map_and_fenceable, size);
3047 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3052 /* Note: pitch better be a power of two tile widths */
3053 pitch_val = obj->stride / tile_width;
3054 pitch_val = ffs(pitch_val) - 1;
3056 val = obj->gtt_offset;
3057 if (obj->tiling_mode == I915_TILING_Y)
3058 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3059 val |= I915_FENCE_SIZE_BITS(size);
3060 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3061 val |= I830_FENCE_REG_VALID;
3063 fence_reg = obj->fence_reg;
3065 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3067 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3070 int ret = intel_ring_begin(pipelined, 4);
3074 intel_ring_emit(pipelined, MI_NOOP);
3075 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3076 intel_ring_emit(pipelined, fence_reg);
3077 intel_ring_emit(pipelined, val);
3078 intel_ring_advance(pipelined);
3080 I915_WRITE(fence_reg, val);
3086 i830_write_fence_reg(struct drm_i915_gem_object *obj,
3087 struct intel_ring_buffer *pipelined)
3089 struct drm_device *dev = obj->base.dev;
3090 drm_i915_private_t *dev_priv = dev->dev_private;
3091 u32 size = obj->gtt_space->size;
3092 int regnum = obj->fence_reg;
3096 if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3097 (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3099 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3100 obj->gtt_offset, size);
3104 pitch_val = obj->stride / 128;
3105 pitch_val = ffs(pitch_val) - 1;
3107 val = obj->gtt_offset;
3108 if (obj->tiling_mode == I915_TILING_Y)
3109 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3110 val |= I830_FENCE_SIZE_BITS(size);
3111 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3112 val |= I830_FENCE_REG_VALID;
3115 int ret = intel_ring_begin(pipelined, 4);
3119 intel_ring_emit(pipelined, MI_NOOP);
3120 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3121 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
3122 intel_ring_emit(pipelined, val);
3123 intel_ring_advance(pipelined);
3125 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
3130 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
3132 return i915_seqno_passed(ring->get_seqno(ring), seqno);
3136 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3137 struct intel_ring_buffer *pipelined)
3141 if (obj->fenced_gpu_access) {
3142 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3143 ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3144 obj->base.write_domain);
3149 obj->fenced_gpu_access = false;
3152 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3153 if (!ring_passed_seqno(obj->last_fenced_ring,
3154 obj->last_fenced_seqno)) {
3155 ret = i915_wait_request(obj->last_fenced_ring,
3156 obj->last_fenced_seqno,
3162 obj->last_fenced_seqno = 0;
3163 obj->last_fenced_ring = NULL;
3166 /* Ensure that all CPU reads are completed before installing a fence
3167 * and all writes before removing the fence.
3169 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3176 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3180 if (obj->tiling_mode)
3181 i915_gem_release_mmap(obj);
3183 ret = i915_gem_object_flush_fence(obj, NULL);
3187 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3188 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3190 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3191 printf("%s: pin_count %d\n", __func__,
3192 dev_priv->fence_regs[obj->fence_reg].pin_count);
3193 i915_gem_clear_fence_reg(obj->base.dev,
3194 &dev_priv->fence_regs[obj->fence_reg]);
3196 obj->fence_reg = I915_FENCE_REG_NONE;
3202 static struct drm_i915_fence_reg *
3203 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 struct drm_i915_fence_reg *reg, *first, *avail;
3209 /* First try to find a free reg */
3211 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3212 reg = &dev_priv->fence_regs[i];
3216 if (!reg->pin_count)
3223 /* None available, try to steal one or wait for a user to finish */
3224 avail = first = NULL;
3225 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3233 !reg->obj->last_fenced_ring ||
3234 reg->obj->last_fenced_ring == pipelined) {
3247 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3248 struct intel_ring_buffer *pipelined)
3250 struct drm_device *dev = obj->base.dev;
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 struct drm_i915_fence_reg *reg;
3258 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3259 reg = &dev_priv->fence_regs[obj->fence_reg];
3260 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
3262 if (obj->tiling_changed) {
3263 ret = i915_gem_object_flush_fence(obj, pipelined);
3267 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3272 i915_gem_next_request_seqno(pipelined);
3273 obj->last_fenced_seqno = reg->setup_seqno;
3274 obj->last_fenced_ring = pipelined;
3281 if (reg->setup_seqno) {
3282 if (!ring_passed_seqno(obj->last_fenced_ring,
3283 reg->setup_seqno)) {
3284 ret = i915_wait_request(
3285 obj->last_fenced_ring,
3292 reg->setup_seqno = 0;
3294 } else if (obj->last_fenced_ring &&
3295 obj->last_fenced_ring != pipelined) {
3296 ret = i915_gem_object_flush_fence(obj, pipelined);
3301 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3303 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3305 if (obj->tiling_changed) {
3308 i915_gem_next_request_seqno(pipelined);
3309 obj->last_fenced_seqno = reg->setup_seqno;
3310 obj->last_fenced_ring = pipelined;
3318 reg = i915_find_fence_reg(dev, pipelined);
3322 ret = i915_gem_object_flush_fence(obj, pipelined);
3327 struct drm_i915_gem_object *old = reg->obj;
3329 drm_gem_object_reference(&old->base);
3331 if (old->tiling_mode)
3332 i915_gem_release_mmap(old);
3334 ret = i915_gem_object_flush_fence(old, pipelined);
3336 drm_gem_object_unreference(&old->base);
3340 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3343 old->fence_reg = I915_FENCE_REG_NONE;
3344 old->last_fenced_ring = pipelined;
3345 old->last_fenced_seqno =
3346 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3348 drm_gem_object_unreference(&old->base);
3349 } else if (obj->last_fenced_seqno == 0)
3353 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
3354 obj->fence_reg = reg - dev_priv->fence_regs;
3355 obj->last_fenced_ring = pipelined;
3358 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3359 obj->last_fenced_seqno = reg->setup_seqno;
3362 obj->tiling_changed = false;
3363 switch (INTEL_INFO(dev)->gen) {
3366 ret = sandybridge_write_fence_reg(obj, pipelined);
3370 ret = i965_write_fence_reg(obj, pipelined);
3373 ret = i915_write_fence_reg(obj, pipelined);
3376 ret = i830_write_fence_reg(obj, pipelined);
3384 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3386 drm_i915_private_t *dev_priv = dev->dev_private;
3387 uint32_t fence_reg = reg - dev_priv->fence_regs;
3389 switch (INTEL_INFO(dev)->gen) {
3392 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3396 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3400 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3403 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3405 I915_WRITE(fence_reg, 0);
3409 list_del_init(®->lru_list);
3411 reg->setup_seqno = 0;
3416 i915_gem_init_object(struct drm_gem_object *obj)
3419 printf("i915_gem_init_object called\n");
3424 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3427 return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3431 i915_gem_retire_task_handler(void *arg, int pending)
3433 drm_i915_private_t *dev_priv;
3434 struct drm_device *dev;
3439 dev = dev_priv->dev;
3441 /* Come back later if the device is busy... */
3442 if (!sx_try_xlock(&dev->dev_struct_lock)) {
3443 taskqueue_enqueue_timeout(dev_priv->tq,
3444 &dev_priv->mm.retire_task, hz);
3448 CTR0(KTR_DRM, "retire_task");
3450 i915_gem_retire_requests(dev);
3452 /* Send a periodic flush down the ring so we don't hold onto GEM
3453 * objects indefinitely.
3456 for (i = 0; i < I915_NUM_RINGS; i++) {
3457 struct intel_ring_buffer *ring = &dev_priv->rings[i];
3459 if (!list_empty(&ring->gpu_write_list)) {
3460 struct drm_i915_gem_request *request;
3463 ret = i915_gem_flush_ring(ring,
3464 0, I915_GEM_GPU_DOMAINS);
3465 request = malloc(sizeof(*request), DRM_I915_GEM,
3467 if (ret || request == NULL ||
3468 i915_add_request(ring, NULL, request))
3469 free(request, DRM_I915_GEM);
3472 idle &= list_empty(&ring->request_list);
3475 if (!dev_priv->mm.suspended && !idle)
3476 taskqueue_enqueue_timeout(dev_priv->tq,
3477 &dev_priv->mm.retire_task, hz);
3483 i915_gem_lastclose(struct drm_device *dev)
3487 if (drm_core_check_feature(dev, DRIVER_MODESET))
3490 ret = i915_gem_idle(dev);
3492 DRM_ERROR("failed to idle hardware: %d\n", ret);
3496 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3498 drm_i915_private_t *dev_priv;
3499 struct drm_i915_gem_phys_object *phys_obj;
3502 dev_priv = dev->dev_private;
3503 if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3506 phys_obj = malloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3511 phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3512 if (phys_obj->handle == NULL) {
3516 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3517 size / PAGE_SIZE, PAT_WRITE_COMBINING);
3519 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3524 free(phys_obj, DRM_I915_GEM);
3529 i915_gem_free_phys_object(struct drm_device *dev, int id)
3531 drm_i915_private_t *dev_priv;
3532 struct drm_i915_gem_phys_object *phys_obj;
3534 dev_priv = dev->dev_private;
3535 if (dev_priv->mm.phys_objs[id - 1] == NULL)
3538 phys_obj = dev_priv->mm.phys_objs[id - 1];
3539 if (phys_obj->cur_obj != NULL)
3540 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3542 drm_pci_free(dev, phys_obj->handle);
3543 free(phys_obj, DRM_I915_GEM);
3544 dev_priv->mm.phys_objs[id - 1] = NULL;
3548 i915_gem_free_all_phys_object(struct drm_device *dev)
3552 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3553 i915_gem_free_phys_object(dev, i);
3557 i915_gem_detach_phys_object(struct drm_device *dev,
3558 struct drm_i915_gem_object *obj)
3565 if (obj->phys_obj == NULL)
3567 vaddr = obj->phys_obj->handle->vaddr;
3569 page_count = obj->base.size / PAGE_SIZE;
3570 VM_OBJECT_WLOCK(obj->base.vm_obj);
3571 for (i = 0; i < page_count; i++) {
3572 m = i915_gem_wire_page(obj->base.vm_obj, i);
3576 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3577 sf = sf_buf_alloc(m, 0);
3579 dst = (char *)sf_buf_kva(sf);
3580 memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3583 drm_clflush_pages(&m, 1);
3585 VM_OBJECT_WLOCK(obj->base.vm_obj);
3586 vm_page_reference(m);
3589 vm_page_unwire(m, 0);
3591 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3593 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3594 intel_gtt_chipset_flush();
3596 obj->phys_obj->cur_obj = NULL;
3597 obj->phys_obj = NULL;
3601 i915_gem_attach_phys_object(struct drm_device *dev,
3602 struct drm_i915_gem_object *obj, int id, int align)
3604 drm_i915_private_t *dev_priv;
3608 int i, page_count, ret;
3610 if (id > I915_MAX_PHYS_OBJECT)
3613 if (obj->phys_obj != NULL) {
3614 if (obj->phys_obj->id == id)
3616 i915_gem_detach_phys_object(dev, obj);
3619 dev_priv = dev->dev_private;
3620 if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3621 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3623 DRM_ERROR("failed to init phys object %d size: %zu\n",
3624 id, obj->base.size);
3629 /* bind to the object */
3630 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3631 obj->phys_obj->cur_obj = obj;
3633 page_count = obj->base.size / PAGE_SIZE;
3635 VM_OBJECT_WLOCK(obj->base.vm_obj);
3637 for (i = 0; i < page_count; i++) {
3638 m = i915_gem_wire_page(obj->base.vm_obj, i);
3643 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3644 sf = sf_buf_alloc(m, 0);
3645 src = (char *)sf_buf_kva(sf);
3646 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3647 memcpy(dst, src, PAGE_SIZE);
3650 VM_OBJECT_WLOCK(obj->base.vm_obj);
3652 vm_page_reference(m);
3654 vm_page_unwire(m, 0);
3656 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3658 VM_OBJECT_WUNLOCK(obj->base.vm_obj);
3664 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3665 uint64_t data_ptr, uint64_t offset, uint64_t size,
3666 struct drm_file *file_priv)
3668 char *user_data, *vaddr;
3671 vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3672 user_data = (char *)(uintptr_t)data_ptr;
3674 if (copyin_nofault(user_data, vaddr, size) != 0) {
3675 /* The physical object once assigned is fixed for the lifetime
3676 * of the obj, so we can safely drop the lock and continue
3680 ret = -copyin(user_data, vaddr, size);
3686 intel_gtt_chipset_flush();
3691 i915_gpu_is_active(struct drm_device *dev)
3693 drm_i915_private_t *dev_priv;
3695 dev_priv = dev->dev_private;
3696 return (!list_empty(&dev_priv->mm.flushing_list) ||
3697 !list_empty(&dev_priv->mm.active_list));
3701 i915_gem_lowmem(void *arg)
3703 struct drm_device *dev;
3704 struct drm_i915_private *dev_priv;
3705 struct drm_i915_gem_object *obj, *next;
3706 int cnt, cnt_fail, cnt_total;
3709 dev_priv = dev->dev_private;
3711 if (!sx_try_xlock(&dev->dev_struct_lock))
3714 CTR0(KTR_DRM, "gem_lowmem");
3717 /* first scan for clean buffers */
3718 i915_gem_retire_requests(dev);
3720 cnt_total = cnt_fail = cnt = 0;
3722 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3724 if (i915_gem_object_is_purgeable(obj)) {
3725 if (i915_gem_object_unbind(obj) != 0)
3731 /* second pass, evict/count anything still on the inactive list */
3732 list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3734 if (i915_gem_object_unbind(obj) == 0)
3740 if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3742 * We are desperate for pages, so as a last resort, wait
3743 * for the GPU to finish and discard whatever we can.
3744 * This has a dramatic impact to reduce the number of
3745 * OOM-killer events whilst running the GPU aggressively.
3747 if (i915_gpu_idle(dev, true) == 0)
3754 i915_gem_unload(struct drm_device *dev)
3756 struct drm_i915_private *dev_priv;
3758 dev_priv = dev->dev_private;
3759 EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);