2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm.h>
34 #include <dev/drm2/i915/i915_drm.h>
35 #include <dev/drm2/i915/i915_drv.h>
36 #include <dev/drm2/i915/intel_drv.h>
37 #include <sys/limits.h>
38 #include <sys/sf_buf.h>
40 struct change_domains {
41 uint32_t invalidate_domains;
42 uint32_t flush_domains;
48 * Set the next domain for the specified object. This
49 * may not actually perform the necessary flushing/invaliding though,
50 * as that may want to be batched with other set_domain operations
52 * This is (we hope) the only really tricky part of gem. The goal
53 * is fairly simple -- track which caches hold bits of the object
54 * and make sure they remain coherent. A few concrete examples may
55 * help to explain how it works. For shorthand, we use the notation
56 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
57 * a pair of read and write domain masks.
59 * Case 1: the batch buffer
65 * 5. Unmapped from GTT
68 * Let's take these a step at a time
71 * Pages allocated from the kernel may still have
72 * cache contents, so we set them to (CPU, CPU) always.
73 * 2. Written by CPU (using pwrite)
74 * The pwrite function calls set_domain (CPU, CPU) and
75 * this function does nothing (as nothing changes)
77 * This function asserts that the object is not
78 * currently in any GPU-based read or write domains
80 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
81 * As write_domain is zero, this function adds in the
82 * current read domains (CPU+COMMAND, 0).
83 * flush_domains is set to CPU.
84 * invalidate_domains is set to COMMAND
85 * clflush is run to get data out of the CPU caches
86 * then i915_dev_set_domain calls i915_gem_flush to
87 * emit an MI_FLUSH and drm_agp_chipset_flush
88 * 5. Unmapped from GTT
89 * i915_gem_object_unbind calls set_domain (CPU, CPU)
90 * flush_domains and invalidate_domains end up both zero
91 * so no flushing/invalidating happens
95 * Case 2: The shared render buffer
99 * 3. Read/written by GPU
100 * 4. set_domain to (CPU,CPU)
101 * 5. Read/written by CPU
102 * 6. Read/written by GPU
105 * Same as last example, (CPU, CPU)
107 * Nothing changes (assertions find that it is not in the GPU)
108 * 3. Read/written by GPU
109 * execbuffer calls set_domain (RENDER, RENDER)
110 * flush_domains gets CPU
111 * invalidate_domains gets GPU
113 * MI_FLUSH and drm_agp_chipset_flush
114 * 4. set_domain (CPU, CPU)
115 * flush_domains gets GPU
116 * invalidate_domains gets CPU
117 * wait_rendering (obj) to make sure all drawing is complete.
118 * This will include an MI_FLUSH to get the data from GPU
120 * clflush (obj) to invalidate the CPU cache
121 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
122 * 5. Read/written by CPU
123 * cache lines are loaded and dirtied
124 * 6. Read written by GPU
125 * Same as last GPU access
127 * Case 3: The constant buffer
132 * 4. Updated (written) by CPU again
141 * flush_domains = CPU
142 * invalidate_domains = RENDER
145 * drm_agp_chipset_flush
146 * 4. Updated (written) by CPU again
148 * flush_domains = 0 (no previous write domain)
149 * invalidate_domains = 0 (no new read domains)
152 * flush_domains = CPU
153 * invalidate_domains = RENDER
156 * drm_agp_chipset_flush
159 i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj,
160 struct intel_ring_buffer *ring,
161 struct change_domains *cd)
163 uint32_t invalidate_domains = 0, flush_domains = 0;
166 * If the object isn't moving to a new write domain,
167 * let the object stay in multiple read domains
169 if (obj->base.pending_write_domain == 0)
170 obj->base.pending_read_domains |= obj->base.read_domains;
173 * Flush the current write domain if
174 * the new read domains don't match. Invalidate
175 * any read domains which differ from the old
178 if (obj->base.write_domain &&
179 (((obj->base.write_domain != obj->base.pending_read_domains ||
180 obj->ring != ring)) ||
181 (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) {
182 flush_domains |= obj->base.write_domain;
183 invalidate_domains |=
184 obj->base.pending_read_domains & ~obj->base.write_domain;
187 * Invalidate any read caches which may have
188 * stale data. That is, any new read domains.
190 invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains;
191 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
192 i915_gem_clflush_object(obj);
194 if (obj->base.pending_write_domain)
195 cd->flips |= atomic_load_acq_int(&obj->pending_flip);
197 /* The actual obj->write_domain will be updated with
198 * pending_write_domain after we emit the accumulated flush for all
199 * of our domain changes in execbuffers (which clears objects'
200 * write_domains). So if we have a current write domain that we
201 * aren't changing, set pending_write_domain to that.
203 if (flush_domains == 0 && obj->base.pending_write_domain == 0)
204 obj->base.pending_write_domain = obj->base.write_domain;
206 cd->invalidate_domains |= invalidate_domains;
207 cd->flush_domains |= flush_domains;
208 if (flush_domains & I915_GEM_GPU_DOMAINS)
209 cd->flush_rings |= intel_ring_flag(obj->ring);
210 if (invalidate_domains & I915_GEM_GPU_DOMAINS)
211 cd->flush_rings |= intel_ring_flag(ring);
216 LIST_HEAD(, drm_i915_gem_object) *buckets;
219 static struct eb_objects *
222 struct eb_objects *eb;
224 eb = malloc(sizeof(*eb), DRM_I915_GEM, M_WAITOK | M_ZERO);
225 eb->buckets = hashinit(size, DRM_I915_GEM, &eb->hashmask);
230 eb_reset(struct eb_objects *eb)
234 for (i = 0; i <= eb->hashmask; i++)
235 LIST_INIT(&eb->buckets[i]);
239 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
242 LIST_INSERT_HEAD(&eb->buckets[obj->exec_handle & eb->hashmask],
246 static struct drm_i915_gem_object *
247 eb_get_object(struct eb_objects *eb, unsigned long handle)
249 struct drm_i915_gem_object *obj;
251 LIST_FOREACH(obj, &eb->buckets[handle & eb->hashmask], exec_node) {
252 if (obj->exec_handle == handle)
259 eb_destroy(struct eb_objects *eb)
262 free(eb->buckets, DRM_I915_GEM);
263 free(eb, DRM_I915_GEM);
267 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
268 struct eb_objects *eb,
269 struct drm_i915_gem_relocation_entry *reloc)
271 struct drm_device *dev = obj->base.dev;
272 struct drm_gem_object *target_obj;
273 uint32_t target_offset;
276 /* we've already hold a reference to all valid objects */
277 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
278 if (unlikely(target_obj == NULL))
281 target_offset = to_intel_bo(target_obj)->gtt_offset;
284 DRM_INFO("%s: obj %p offset %08x target %d "
285 "read %08x write %08x gtt %08x "
286 "presumed %08x delta %08x\n",
290 (int) reloc->target_handle,
291 (int) reloc->read_domains,
292 (int) reloc->write_domain,
294 (int) reloc->presumed_offset,
298 /* The target buffer should have appeared before us in the
299 * exec_object list, so it should have a GTT space bound by now.
301 if (unlikely(target_offset == 0)) {
302 DRM_DEBUG("No GTT space found for object %d\n",
303 reloc->target_handle);
307 /* Validate that the target is in a valid r/w GPU domain */
308 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
309 DRM_DEBUG("reloc with multiple write domains: "
310 "obj %p target %d offset %d "
311 "read %08x write %08x",
312 obj, reloc->target_handle,
315 reloc->write_domain);
318 if (unlikely((reloc->write_domain | reloc->read_domains)
319 & ~I915_GEM_GPU_DOMAINS)) {
320 DRM_DEBUG("reloc with read/write non-GPU domains: "
321 "obj %p target %d offset %d "
322 "read %08x write %08x",
323 obj, reloc->target_handle,
326 reloc->write_domain);
329 if (unlikely(reloc->write_domain && target_obj->pending_write_domain &&
330 reloc->write_domain != target_obj->pending_write_domain)) {
331 DRM_DEBUG("Write domain conflict: "
332 "obj %p target %d offset %d "
333 "new %08x old %08x\n",
334 obj, reloc->target_handle,
337 target_obj->pending_write_domain);
341 target_obj->pending_read_domains |= reloc->read_domains;
342 target_obj->pending_write_domain |= reloc->write_domain;
344 /* If the relocation already has the right value in it, no
345 * more work needs to be done.
347 if (target_offset == reloc->presumed_offset)
350 /* Check that the relocation address is valid... */
351 if (unlikely(reloc->offset > obj->base.size - 4)) {
352 DRM_DEBUG("Relocation beyond object bounds: "
353 "obj %p target %d offset %d size %d.\n",
354 obj, reloc->target_handle,
356 (int) obj->base.size);
359 if (unlikely(reloc->offset & 3)) {
360 DRM_DEBUG("Relocation not 4-byte aligned: "
361 "obj %p target %d offset %d.\n",
362 obj, reloc->target_handle,
363 (int) reloc->offset);
367 reloc->delta += target_offset;
368 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
369 uint32_t page_offset = reloc->offset & PAGE_MASK;
373 sf = sf_buf_alloc(obj->pages[OFF_TO_IDX(reloc->offset)],
377 vaddr = (void *)sf_buf_kva(sf);
378 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
381 uint32_t *reloc_entry;
384 /* We can't wait for rendering with pagefaults disabled */
385 if (obj->active && (curthread->td_pflags & TDP_NOFAULTING) != 0)
387 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
392 * Map the page containing the relocation we're going
395 reloc->offset += obj->gtt_offset;
396 reloc_page = pmap_mapdev_attr(dev->agp->base + (reloc->offset &
397 ~PAGE_MASK), PAGE_SIZE, PAT_WRITE_COMBINING);
398 reloc_entry = (uint32_t *)(reloc_page + (reloc->offset &
400 *(volatile uint32_t *)reloc_entry = reloc->delta;
401 pmap_unmapdev((vm_offset_t)reloc_page, PAGE_SIZE);
404 /* and update the user's relocation entry */
405 reloc->presumed_offset = target_offset;
411 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
412 struct eb_objects *eb)
414 struct drm_i915_gem_relocation_entry *user_relocs;
415 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
416 struct drm_i915_gem_relocation_entry reloc;
419 user_relocs = (void *)(uintptr_t)entry->relocs_ptr;
420 for (i = 0; i < entry->relocation_count; i++) {
421 ret = -copyin_nofault(user_relocs + i, &reloc, sizeof(reloc));
425 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &reloc);
429 ret = -copyout_nofault(&reloc.presumed_offset,
430 &user_relocs[i].presumed_offset,
431 sizeof(reloc.presumed_offset));
440 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
441 struct eb_objects *eb, struct drm_i915_gem_relocation_entry *relocs)
443 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
446 for (i = 0; i < entry->relocation_count; i++) {
447 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
456 i915_gem_execbuffer_relocate(struct drm_device *dev,
457 struct eb_objects *eb,
458 struct list_head *objects)
460 struct drm_i915_gem_object *obj;
463 /* Try to move as many of the relocation targets off the active list
464 * to avoid unnecessary fallbacks to the slow path, as we cannot wait
465 * for the retirement with pagefaults disabled.
467 i915_gem_retire_requests(dev);
470 pflags = vm_fault_disable_pagefaults();
471 /* This is the fast path and we cannot handle a pagefault whilst
472 * holding the device lock lest the user pass in the relocations
473 * contained within a mmaped bo. For in such a case we, the page
474 * fault handler would call i915_gem_fault() and we would try to
475 * acquire the device lock again. Obviously this is bad.
478 list_for_each_entry(obj, objects, exec_list) {
479 ret = i915_gem_execbuffer_relocate_object(obj, eb);
483 vm_fault_enable_pagefaults(pflags);
487 #define __EXEC_OBJECT_HAS_FENCE (1<<31)
490 pin_and_fence_object(struct drm_i915_gem_object *obj,
491 struct intel_ring_buffer *ring)
493 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
494 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
495 bool need_fence, need_mappable;
499 has_fenced_gpu_access &&
500 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
501 obj->tiling_mode != I915_TILING_NONE;
503 entry->relocation_count ? true : need_fence;
505 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable);
509 if (has_fenced_gpu_access) {
510 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
511 if (obj->tiling_mode) {
512 ret = i915_gem_object_get_fence(obj, ring);
516 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
517 i915_gem_object_pin_fence(obj);
519 ret = i915_gem_object_put_fence(obj);
523 obj->pending_fenced_gpu_access = true;
527 entry->offset = obj->gtt_offset;
531 i915_gem_object_unpin(obj);
536 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
537 struct drm_file *file,
538 struct list_head *objects)
540 drm_i915_private_t *dev_priv;
541 struct drm_i915_gem_object *obj;
543 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
544 struct list_head ordered_objects;
546 dev_priv = ring->dev->dev_private;
547 INIT_LIST_HEAD(&ordered_objects);
548 while (!list_empty(objects)) {
549 struct drm_i915_gem_exec_object2 *entry;
550 bool need_fence, need_mappable;
552 obj = list_first_entry(objects,
553 struct drm_i915_gem_object,
555 entry = obj->exec_entry;
558 has_fenced_gpu_access &&
559 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
560 obj->tiling_mode != I915_TILING_NONE;
562 entry->relocation_count ? true : need_fence;
565 list_move(&obj->exec_list, &ordered_objects);
567 list_move_tail(&obj->exec_list, &ordered_objects);
569 obj->base.pending_read_domains = 0;
570 obj->base.pending_write_domain = 0;
572 list_splice(&ordered_objects, objects);
574 /* Attempt to pin all of the buffers into the GTT.
575 * This is done in 3 phases:
577 * 1a. Unbind all objects that do not match the GTT constraints for
578 * the execbuffer (fenceable, mappable, alignment etc).
579 * 1b. Increment pin count for already bound objects and obtain
580 * a fence register if required.
581 * 2. Bind new objects.
582 * 3. Decrement pin count.
584 * This avoid unnecessary unbinding of later objects in order to makr
585 * room for the earlier objects *unless* we need to defragment.
591 /* Unbind any ill-fitting objects or pin. */
592 list_for_each_entry(obj, objects, exec_list) {
593 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
594 bool need_fence, need_mappable;
600 has_fenced_gpu_access &&
601 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
602 obj->tiling_mode != I915_TILING_NONE;
604 entry->relocation_count ? true : need_fence;
606 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
607 (need_mappable && !obj->map_and_fenceable))
608 ret = i915_gem_object_unbind(obj);
610 ret = pin_and_fence_object(obj, ring);
615 /* Bind fresh objects */
616 list_for_each_entry(obj, objects, exec_list) {
620 ret = pin_and_fence_object(obj, ring);
624 /* This can potentially raise a harmless
625 * -EINVAL if we failed to bind in the above
626 * call. It cannot raise -EINTR since we know
627 * that the bo is freshly bound and so will
628 * not need to be flushed or waited upon.
630 ret_ignore = i915_gem_object_unbind(obj);
632 if (obj->gtt_space != NULL)
633 printf("%s: gtt_space\n", __func__);
638 /* Decrement pin count for bound objects */
639 list_for_each_entry(obj, objects, exec_list) {
640 struct drm_i915_gem_exec_object2 *entry;
645 entry = obj->exec_entry;
646 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
647 i915_gem_object_unpin_fence(obj);
648 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
651 i915_gem_object_unpin(obj);
653 /* ... and ensure ppgtt mapping exist if needed. */
654 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
655 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
656 obj, obj->cache_level);
658 obj->has_aliasing_ppgtt_mapping = 1;
662 if (ret != -ENOSPC || retry > 1)
665 /* First attempt, just clear anything that is purgeable.
666 * Second attempt, clear the entire GTT.
668 ret = i915_gem_evict_everything(ring->dev, retry == 0);
676 list_for_each_entry_continue_reverse(obj, objects, exec_list) {
677 struct drm_i915_gem_exec_object2 *entry;
682 entry = obj->exec_entry;
683 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
684 i915_gem_object_unpin_fence(obj);
685 entry->flags &= ~__EXEC_OBJECT_HAS_FENCE;
688 i915_gem_object_unpin(obj);
695 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
696 struct drm_file *file, struct intel_ring_buffer *ring,
697 struct list_head *objects, struct eb_objects *eb,
698 struct drm_i915_gem_exec_object2 *exec, int count)
700 struct drm_i915_gem_relocation_entry *reloc;
701 struct drm_i915_gem_object *obj;
705 /* We may process another execbuffer during the unlock... */
706 while (!list_empty(objects)) {
707 obj = list_first_entry(objects,
708 struct drm_i915_gem_object,
710 list_del_init(&obj->exec_list);
711 drm_gem_object_unreference(&obj->base);
717 for (i = 0; i < count; i++)
718 total += exec[i].relocation_count;
720 reloc_offset = malloc(count * sizeof(*reloc_offset), DRM_I915_GEM,
722 reloc = malloc(total * sizeof(*reloc), DRM_I915_GEM, M_WAITOK | M_ZERO);
725 for (i = 0; i < count; i++) {
726 struct drm_i915_gem_relocation_entry *user_relocs;
728 user_relocs = (void *)(uintptr_t)exec[i].relocs_ptr;
729 ret = -copyin(user_relocs, reloc + total,
730 exec[i].relocation_count * sizeof(*reloc));
736 reloc_offset[i] = total;
737 total += exec[i].relocation_count;
740 ret = i915_mutex_lock_interruptible(dev);
746 /* reacquire the objects */
748 for (i = 0; i < count; i++) {
749 struct drm_i915_gem_object *obj;
751 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
753 if (&obj->base == NULL) {
754 DRM_DEBUG("Invalid object handle %d at index %d\n",
760 list_add_tail(&obj->exec_list, objects);
761 obj->exec_handle = exec[i].handle;
762 obj->exec_entry = &exec[i];
763 eb_add_object(eb, obj);
766 ret = i915_gem_execbuffer_reserve(ring, file, objects);
770 list_for_each_entry(obj, objects, exec_list) {
771 int offset = obj->exec_entry - exec;
772 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
773 reloc + reloc_offset[offset]);
778 /* Leave the user relocations as are, this is the painfully slow path,
779 * and we want to avoid the complication of dropping the lock whilst
780 * having buffers reserved in the aperture and so causing spurious
781 * ENOSPC for random operations.
785 free(reloc, DRM_I915_GEM);
786 free(reloc_offset, DRM_I915_GEM);
791 i915_gem_execbuffer_flush(struct drm_device *dev,
792 uint32_t invalidate_domains,
793 uint32_t flush_domains,
794 uint32_t flush_rings)
796 drm_i915_private_t *dev_priv = dev->dev_private;
799 if (flush_domains & I915_GEM_DOMAIN_CPU)
800 intel_gtt_chipset_flush();
802 if (flush_domains & I915_GEM_DOMAIN_GTT)
805 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
806 for (i = 0; i < I915_NUM_RINGS; i++)
807 if (flush_rings & (1 << i)) {
808 ret = i915_gem_flush_ring(&dev_priv->rings[i],
809 invalidate_domains, flush_domains);
819 intel_enable_semaphores(struct drm_device *dev)
821 if (INTEL_INFO(dev)->gen < 6)
824 if (i915_semaphores >= 0)
825 return i915_semaphores;
827 /* Enable semaphores on SNB when IO remapping is off */
828 if (INTEL_INFO(dev)->gen == 6)
829 return !intel_iommu_enabled;
835 i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
836 struct intel_ring_buffer *to)
838 struct intel_ring_buffer *from = obj->ring;
842 if (from == NULL || to == from)
845 /* XXX gpu semaphores are implicated in various hard hangs on SNB */
846 if (!intel_enable_semaphores(obj->base.dev))
847 return i915_gem_object_wait_rendering(obj);
849 idx = intel_ring_sync_index(from, to);
851 seqno = obj->last_rendering_seqno;
852 if (seqno <= from->sync_seqno[idx])
855 if (seqno == from->outstanding_lazy_request) {
856 struct drm_i915_gem_request *request;
858 request = malloc(sizeof(*request), DRM_I915_GEM,
860 ret = i915_add_request(from, NULL, request);
862 free(request, DRM_I915_GEM);
866 seqno = request->seqno;
869 from->sync_seqno[idx] = seqno;
871 return to->sync_to(to, from, seqno - 1);
875 i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips)
877 u32 plane, flip_mask;
880 /* Check for any pending flips. As we only maintain a flip queue depth
881 * of 1, we can simply insert a WAIT for the next display flip prior
882 * to executing the batch and avoid stalling the CPU.
885 for (plane = 0; flips >> plane; plane++) {
886 if (((flips >> plane) & 1) == 0)
890 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
892 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
894 ret = intel_ring_begin(ring, 2);
898 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
899 intel_ring_emit(ring, MI_NOOP);
900 intel_ring_advance(ring);
907 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
908 struct list_head *objects)
910 struct drm_i915_gem_object *obj;
911 struct change_domains cd;
914 memset(&cd, 0, sizeof(cd));
915 list_for_each_entry(obj, objects, exec_list)
916 i915_gem_object_set_to_gpu_domain(obj, ring, &cd);
918 if (cd.invalidate_domains | cd.flush_domains) {
920 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
922 cd.invalidate_domains,
925 ret = i915_gem_execbuffer_flush(ring->dev,
926 cd.invalidate_domains,
934 ret = i915_gem_execbuffer_wait_for_flips(ring, cd.flips);
939 list_for_each_entry(obj, objects, exec_list) {
940 ret = i915_gem_execbuffer_sync_rings(obj, ring);
949 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
951 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
955 validate_exec_list(struct drm_i915_gem_exec_object2 *exec, int count,
959 int i, length, page_count;
961 /* XXXKIB various limits checking is missing there */
962 *map = malloc(count * sizeof(*ma), DRM_I915_GEM, M_WAITOK | M_ZERO);
963 for (i = 0; i < count; i++) {
964 /* First check for malicious input causing overflow */
965 if (exec[i].relocation_count >
966 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
969 length = exec[i].relocation_count *
970 sizeof(struct drm_i915_gem_relocation_entry);
976 * Since both start and end of the relocation region
977 * may be not aligned on the page boundary, be
978 * conservative and request a page slot for each
979 * partial page. Thus +2.
981 page_count = howmany(length, PAGE_SIZE) + 2;
982 ma = (*map)[i] = malloc(page_count * sizeof(vm_page_t),
983 DRM_I915_GEM, M_WAITOK | M_ZERO);
984 if (vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
985 exec[i].relocs_ptr, length, VM_PROT_READ | VM_PROT_WRITE,
986 ma, page_count) == -1) {
987 free(ma, DRM_I915_GEM);
997 i915_gem_execbuffer_move_to_active(struct list_head *objects,
998 struct intel_ring_buffer *ring,
1001 struct drm_i915_gem_object *obj;
1002 uint32_t old_read, old_write;
1004 list_for_each_entry(obj, objects, exec_list) {
1005 old_read = obj->base.read_domains;
1006 old_write = obj->base.write_domain;
1008 obj->base.read_domains = obj->base.pending_read_domains;
1009 obj->base.write_domain = obj->base.pending_write_domain;
1010 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
1012 i915_gem_object_move_to_active(obj, ring, seqno);
1013 if (obj->base.write_domain) {
1015 obj->pending_gpu_write = true;
1016 list_move_tail(&obj->gpu_write_list,
1017 &ring->gpu_write_list);
1018 intel_mark_busy(ring->dev, obj);
1020 CTR3(KTR_DRM, "object_change_domain move_to_active %p %x %x",
1021 obj, old_read, old_write);
1025 int i915_gem_sync_exec_requests;
1028 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
1029 struct drm_file *file,
1030 struct intel_ring_buffer *ring)
1032 struct drm_i915_gem_request *request;
1036 * Ensure that the commands in the batch buffer are
1037 * finished before the interrupt fires.
1039 * The sampler always gets flushed on i965 (sigh).
1041 invalidate = I915_GEM_DOMAIN_COMMAND;
1042 if (INTEL_INFO(dev)->gen >= 4)
1043 invalidate |= I915_GEM_DOMAIN_SAMPLER;
1044 if (ring->flush(ring, invalidate, 0)) {
1045 i915_gem_next_request_seqno(ring);
1049 /* Add a breadcrumb for the completion of the batch buffer */
1050 request = malloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
1051 if (request == NULL || i915_add_request(ring, file, request)) {
1052 i915_gem_next_request_seqno(ring);
1053 free(request, DRM_I915_GEM);
1054 } else if (i915_gem_sync_exec_requests)
1055 i915_wait_request(ring, request->seqno, true);
1059 i915_gem_fix_mi_batchbuffer_end(struct drm_i915_gem_object *batch_obj,
1060 uint32_t batch_start_offset, uint32_t batch_len)
1063 uint64_t po_r, po_w;
1066 po_r = batch_obj->base.dev->agp->base + batch_obj->gtt_offset +
1067 batch_start_offset + batch_len;
1070 mkva = pmap_mapdev_attr(trunc_page(po_r), 2 * PAGE_SIZE,
1071 PAT_WRITE_COMBINING);
1073 cmd = *(uint32_t *)(mkva + po_r);
1075 if (cmd != MI_BATCH_BUFFER_END) {
1077 * batch_len != 0 due to the check at the start of
1078 * i915_gem_do_execbuffer
1080 if (batch_obj->base.size > batch_start_offset + batch_len) {
1082 /* DRM_DEBUG("batchbuffer does not end by MI_BATCH_BUFFER_END !\n"); */
1085 DRM_DEBUG("batchbuffer does not end by MI_BATCH_BUFFER_END, overwriting last bo cmd !\n");
1087 *(uint32_t *)(mkva + po_w) = MI_BATCH_BUFFER_END;
1090 pmap_unmapdev((vm_offset_t)mkva, 2 * PAGE_SIZE);
1093 int i915_fix_mi_batchbuffer_end = 0;
1096 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1097 struct intel_ring_buffer *ring)
1099 drm_i915_private_t *dev_priv = dev->dev_private;
1102 if (!IS_GEN7(dev) || ring != &dev_priv->rings[RCS])
1105 ret = intel_ring_begin(ring, 4 * 3);
1109 for (i = 0; i < 4; i++) {
1110 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1111 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
1112 intel_ring_emit(ring, 0);
1115 intel_ring_advance(ring);
1121 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1122 struct drm_file *file,
1123 struct drm_i915_gem_execbuffer2 *args,
1124 struct drm_i915_gem_exec_object2 *exec)
1126 drm_i915_private_t *dev_priv = dev->dev_private;
1127 struct list_head objects;
1128 struct eb_objects *eb;
1129 struct drm_i915_gem_object *batch_obj;
1130 struct drm_clip_rect *cliprects = NULL;
1131 struct intel_ring_buffer *ring;
1132 vm_page_t **relocs_ma;
1133 u32 exec_start, exec_len;
1138 if (!i915_gem_check_execbuffer(args)) {
1139 DRM_DEBUG("execbuf with invalid offset/length\n");
1143 if (args->batch_len == 0)
1146 ret = validate_exec_list(exec, args->buffer_count, &relocs_ma);
1148 goto pre_struct_lock_err;
1150 switch (args->flags & I915_EXEC_RING_MASK) {
1151 case I915_EXEC_DEFAULT:
1152 case I915_EXEC_RENDER:
1153 ring = &dev_priv->rings[RCS];
1156 if (!HAS_BSD(dev)) {
1157 DRM_DEBUG("execbuf with invalid ring (BSD)\n");
1160 ring = &dev_priv->rings[VCS];
1163 if (!HAS_BLT(dev)) {
1164 DRM_DEBUG("execbuf with invalid ring (BLT)\n");
1167 ring = &dev_priv->rings[BCS];
1170 DRM_DEBUG("execbuf with unknown ring: %d\n",
1171 (int)(args->flags & I915_EXEC_RING_MASK));
1173 goto pre_struct_lock_err;
1176 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1177 mask = I915_EXEC_CONSTANTS_MASK;
1179 case I915_EXEC_CONSTANTS_REL_GENERAL:
1180 case I915_EXEC_CONSTANTS_ABSOLUTE:
1181 case I915_EXEC_CONSTANTS_REL_SURFACE:
1182 if (ring == &dev_priv->rings[RCS] &&
1183 mode != dev_priv->relative_constants_mode) {
1184 if (INTEL_INFO(dev)->gen < 4) {
1186 goto pre_struct_lock_err;
1189 if (INTEL_INFO(dev)->gen > 5 &&
1190 mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1192 goto pre_struct_lock_err;
1195 /* The HW changed the meaning on this bit on gen6 */
1196 if (INTEL_INFO(dev)->gen >= 6)
1197 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1201 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
1203 goto pre_struct_lock_err;
1206 if (args->buffer_count < 1) {
1207 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1209 goto pre_struct_lock_err;
1212 if (args->num_cliprects != 0) {
1213 if (ring != &dev_priv->rings[RCS]) {
1214 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
1216 goto pre_struct_lock_err;
1219 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
1220 DRM_DEBUG("execbuf with %u cliprects\n",
1221 args->num_cliprects);
1223 goto pre_struct_lock_err;
1225 cliprects = malloc( sizeof(*cliprects) * args->num_cliprects,
1226 DRM_I915_GEM, M_WAITOK | M_ZERO);
1227 ret = -copyin((void *)(uintptr_t)args->cliprects_ptr, cliprects,
1228 sizeof(*cliprects) * args->num_cliprects);
1230 goto pre_struct_lock_err;
1233 ret = i915_mutex_lock_interruptible(dev);
1235 goto pre_struct_lock_err;
1237 if (dev_priv->mm.suspended) {
1239 goto struct_lock_err;
1242 eb = eb_create(args->buffer_count);
1245 goto struct_lock_err;
1248 /* Look up object handles */
1249 INIT_LIST_HEAD(&objects);
1250 for (i = 0; i < args->buffer_count; i++) {
1251 struct drm_i915_gem_object *obj;
1252 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
1254 if (&obj->base == NULL) {
1255 DRM_DEBUG("Invalid object handle %d at index %d\n",
1257 /* prevent error path from reading uninitialized data */
1262 if (!list_empty(&obj->exec_list)) {
1263 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
1264 obj, exec[i].handle, i);
1269 list_add_tail(&obj->exec_list, &objects);
1270 obj->exec_handle = exec[i].handle;
1271 obj->exec_entry = &exec[i];
1272 eb_add_object(eb, obj);
1275 /* take note of the batch buffer before we might reorder the lists */
1276 batch_obj = list_entry(objects.prev,
1277 struct drm_i915_gem_object,
1280 /* Move the objects en-masse into the GTT, evicting if necessary. */
1281 ret = i915_gem_execbuffer_reserve(ring, file, &objects);
1285 /* The objects are in their final locations, apply the relocations. */
1286 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
1288 if (ret == -EFAULT) {
1289 ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
1290 &objects, eb, exec, args->buffer_count);
1291 DRM_LOCK_ASSERT(dev);
1297 /* Set the pending read domains for the batch buffer to COMMAND */
1298 if (batch_obj->base.pending_write_domain) {
1299 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1303 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1305 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
1309 seqno = i915_gem_next_request_seqno(ring);
1310 for (i = 0; i < I915_NUM_RINGS - 1; i++) {
1311 if (seqno < ring->sync_seqno[i]) {
1312 /* The GPU can not handle its semaphore value wrapping,
1313 * so every billion or so execbuffers, we need to stall
1314 * the GPU in order to reset the counters.
1316 ret = i915_gpu_idle(dev, true);
1320 KASSERT(ring->sync_seqno[i] == 0, ("Non-zero sync_seqno"));
1324 if (ring == &dev_priv->rings[RCS] &&
1325 mode != dev_priv->relative_constants_mode) {
1326 ret = intel_ring_begin(ring, 4);
1330 intel_ring_emit(ring, MI_NOOP);
1331 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1332 intel_ring_emit(ring, INSTPM);
1333 intel_ring_emit(ring, mask << 16 | mode);
1334 intel_ring_advance(ring);
1336 dev_priv->relative_constants_mode = mode;
1339 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1340 ret = i915_reset_gen7_sol_offsets(dev, ring);
1345 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1346 exec_len = args->batch_len;
1348 if (i915_fix_mi_batchbuffer_end) {
1349 i915_gem_fix_mi_batchbuffer_end(batch_obj,
1350 args->batch_start_offset, args->batch_len);
1353 CTR4(KTR_DRM, "ring_dispatch %s %d exec %x %x", ring->name, seqno,
1354 exec_start, exec_len);
1357 for (i = 0; i < args->num_cliprects; i++) {
1358 ret = i915_emit_box_p(dev, &cliprects[i],
1359 args->DR1, args->DR4);
1363 ret = ring->dispatch_execbuffer(ring, exec_start,
1369 ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
1374 i915_gem_execbuffer_move_to_active(&objects, ring, seqno);
1375 i915_gem_execbuffer_retire_commands(dev, file, ring);
1379 while (!list_empty(&objects)) {
1380 struct drm_i915_gem_object *obj;
1382 obj = list_first_entry(&objects, struct drm_i915_gem_object,
1384 list_del_init(&obj->exec_list);
1385 drm_gem_object_unreference(&obj->base);
1390 pre_struct_lock_err:
1391 for (i = 0; i < args->buffer_count; i++) {
1392 if (relocs_ma[i] != NULL) {
1393 vm_page_unhold_pages(relocs_ma[i], howmany(
1394 exec[i].relocation_count *
1395 sizeof(struct drm_i915_gem_relocation_entry),
1397 free(relocs_ma[i], DRM_I915_GEM);
1400 free(relocs_ma, DRM_I915_GEM);
1401 free(cliprects, DRM_I915_GEM);
1406 * Legacy execbuffer just creates an exec2 list from the original exec object
1407 * list array and passes it to the real function.
1410 i915_gem_execbuffer(struct drm_device *dev, void *data,
1411 struct drm_file *file)
1413 struct drm_i915_gem_execbuffer *args = data;
1414 struct drm_i915_gem_execbuffer2 exec2;
1415 struct drm_i915_gem_exec_object *exec_list = NULL;
1416 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1419 DRM_DEBUG("buffers_ptr %d buffer_count %d len %08x\n",
1420 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1422 if (args->buffer_count < 1) {
1423 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1427 /* Copy in the exec list from userland */
1428 /* XXXKIB user-controlled malloc size */
1429 exec_list = malloc(sizeof(*exec_list) * args->buffer_count,
1430 DRM_I915_GEM, M_WAITOK);
1431 exec2_list = malloc(sizeof(*exec2_list) * args->buffer_count,
1432 DRM_I915_GEM, M_WAITOK);
1433 ret = -copyin((void *)(uintptr_t)args->buffers_ptr, exec_list,
1434 sizeof(*exec_list) * args->buffer_count);
1436 DRM_DEBUG("copy %d exec entries failed %d\n",
1437 args->buffer_count, ret);
1438 free(exec_list, DRM_I915_GEM);
1439 free(exec2_list, DRM_I915_GEM);
1443 for (i = 0; i < args->buffer_count; i++) {
1444 exec2_list[i].handle = exec_list[i].handle;
1445 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1446 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1447 exec2_list[i].alignment = exec_list[i].alignment;
1448 exec2_list[i].offset = exec_list[i].offset;
1449 if (INTEL_INFO(dev)->gen < 4)
1450 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1452 exec2_list[i].flags = 0;
1455 exec2.buffers_ptr = args->buffers_ptr;
1456 exec2.buffer_count = args->buffer_count;
1457 exec2.batch_start_offset = args->batch_start_offset;
1458 exec2.batch_len = args->batch_len;
1459 exec2.DR1 = args->DR1;
1460 exec2.DR4 = args->DR4;
1461 exec2.num_cliprects = args->num_cliprects;
1462 exec2.cliprects_ptr = args->cliprects_ptr;
1463 exec2.flags = I915_EXEC_RENDER;
1465 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1467 /* Copy the new buffer offsets back to the user's exec list. */
1468 for (i = 0; i < args->buffer_count; i++)
1469 exec_list[i].offset = exec2_list[i].offset;
1470 /* ... and back out to userspace */
1471 ret = -copyout(exec_list, (void *)(uintptr_t)args->buffers_ptr,
1472 sizeof(*exec_list) * args->buffer_count);
1474 DRM_DEBUG("failed to copy %d exec entries "
1475 "back to user (%d)\n",
1476 args->buffer_count, ret);
1480 free(exec_list, DRM_I915_GEM);
1481 free(exec2_list, DRM_I915_GEM);
1486 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1487 struct drm_file *file)
1489 struct drm_i915_gem_execbuffer2 *args = data;
1490 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1493 DRM_DEBUG("buffers_ptr %jx buffer_count %d len %08x\n",
1494 (uintmax_t)args->buffers_ptr, args->buffer_count, args->batch_len);
1496 if (args->buffer_count < 1 ||
1497 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1498 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1502 /* XXXKIB user-controllable malloc size */
1503 exec2_list = malloc(sizeof(*exec2_list) * args->buffer_count,
1504 DRM_I915_GEM, M_WAITOK);
1505 ret = -copyin((void *)(uintptr_t)args->buffers_ptr, exec2_list,
1506 sizeof(*exec2_list) * args->buffer_count);
1508 DRM_DEBUG("copy %d exec entries failed %d\n",
1509 args->buffer_count, ret);
1510 free(exec2_list, DRM_I915_GEM);
1514 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1516 /* Copy the new buffer offsets back to the user's exec list. */
1517 ret = -copyout(exec2_list, (void *)(uintptr_t)args->buffers_ptr,
1518 sizeof(*exec2_list) * args->buffer_count);
1520 DRM_DEBUG("failed to copy %d exec entries "
1521 "back to user (%d)\n",
1522 args->buffer_count, ret);
1526 free(exec2_list, DRM_I915_GEM);