sys/dev/drm2/i915/i915_gem_tiling.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include <dev/drm2/drmP.h>
  32 #include <dev/drm2/i915/i915_drm.h>
  33 #include <dev/drm2/i915/i915_drv.h>
  34
  35 #include <sys/sf_buf.h>
  36
  37 /** @file i915_gem_tiling.c
  38  *
  39  * Support for managing tiling state of buffer objects.
  40  *
  41  * The idea behind tiling is to increase cache hit rates by rearranging
  42  * pixel data so that a group of pixel accesses are in the same cacheline.
  43  * Performance improvement from doing this on the back/depth buffer are on
  44  * the order of 30%.
  45  *
  46  * Intel architectures make this somewhat more complicated, though, by
  47  * adjustments made to addressing of data when the memory is in interleaved
  48  * mode (matched pairs of DIMMS) to improve memory bandwidth.
  49  * For interleaved memory, the CPU sends every sequential 64 bytes
  50  * to an alternate memory channel so it can get the bandwidth from both.
  51  *
  52  * The GPU also rearranges its accesses for increased bandwidth to interleaved
  53  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
  54  * it does it a little differently, since one walks addresses not just in the
  55  * X direction but also Y.  So, along with alternating channels when bit
  56  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
  57  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
  58  * are common to both the 915 and 965-class hardware.
  59  *
  60  * The CPU also sometimes XORs in higher bits as well, to improve
  61  * bandwidth doing strided access like we do so frequently in graphics.  This
  62  * is called "Channel XOR Randomization" in the MCH documentation.  The result
  63  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
  64  * decode.
  65  *
  66  * All of this bit 6 XORing has an effect on our memory management,
  67  * as we need to make sure that the 3d driver can correctly address object
  68  * contents.
  69  *
  70  * If we don't have interleaved memory, all tiling is safe and no swizzling is
  71  * required.
  72  *
  73  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
  74  * 17 is not just a page offset, so as we page an objet out and back in,
  75  * individual pages in it will have different bit 17 addresses, resulting in
  76  * each 64 bytes being swapped with its neighbor!
  77  *
  78  * Otherwise, if interleaved, we have to tell the 3d driver what the address
  79  * swizzling it needs to do is, since it's writing with the CPU to the pages
  80  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
  81  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
  82  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
  83  * to match what the GPU expects.
  84  */
  85
  86 /**
  87  * Detects bit 6 swizzling of address lookup between IGD access and CPU
  88  * access through main memory.
  89  */
  90 void
  91 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
  92 {
  93         drm_i915_private_t *dev_priv = dev->dev_private;
  94         uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
  95         uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
  96
  97         if (IS_VALLEYVIEW(dev)) {
  98                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
  99                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 100         } else if (INTEL_INFO(dev)->gen >= 6) {
 101                 uint32_t dimm_c0, dimm_c1;
 102                 dimm_c0 = I915_READ(MAD_DIMM_C0);
 103                 dimm_c1 = I915_READ(MAD_DIMM_C1);
 104                 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 105                 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
 106                 /* Enable swizzling when the channels are populated with
 107                  * identically sized dimms. We don't need to check the 3rd
 108                  * channel because no cpu with gpu attached ships in that
 109                  * configuration. Also, swizzling only makes sense for 2
 110                  * channels anyway. */
 111                 if (dimm_c0 == dimm_c1) {
 112                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 113                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 114                 } else {
 115                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 116                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 117                 }
 118         } else if (IS_GEN5(dev)) {
 119                 /* On Ironlake whatever DRAM config, GPU always do
 120                  * same swizzling setup.
 121                  */
 122                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 123                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 124         } else if (IS_GEN2(dev)) {
 125                 /* As far as we know, the 865 doesn't have these bit 6
 126                  * swizzling issues.
 127                  */
 128                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 129                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 130         } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
 131                 uint32_t dcc;
 132
 133                 /* On 9xx chipsets, channel interleave by the CPU is
 134                  * determined by DCC.  For single-channel, neither the CPU
 135                  * nor the GPU do swizzling.  For dual channel interleaved,
 136                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
 137                  * 9 for Y tiled.  The CPU's interleave is independent, and
 138                  * can be based on either bit 11 (haven't seen this yet) or
 139                  * bit 17 (common).
 140                  */
 141                 dcc = I915_READ(DCC);
 142                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
 143                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
 144                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
 145                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 146                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 147                         break;
 148                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
 149                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
 150                                 /* This is the base swizzling by the GPU for
 151                                  * tiled buffers.
 152                                  */
 153                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 154                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
 155                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
 156                                 /* Bit 11 swizzling by the CPU in addition. */
 157                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
 158                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
 159                         } else {
 160                                 /* Bit 17 swizzling by the CPU in addition. */
 161                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 162                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 163                         }
 164                         break;
 165                 }
 166                 if (dcc == 0xffffffff) {
 167                         DRM_ERROR("Couldn't read from MCHBAR.  "
 168                                   "Disabling tiling.\n");
 169                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 170                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 171                 }
 172         } else {
 173                 /* The 965, G33, and newer, have a very flexible memory
 174                  * configuration.  It will enable dual-channel mode
 175                  * (interleaving) on as much memory as it can, and the GPU
 176                  * will additionally sometimes enable different bit 6
 177                  * swizzling for tiled objects from the CPU.
 178                  *
 179                  * Here's what I found on the G965:
 180                  *    slot fill         memory size  swizzling
 181                  * 0A   0B   1A   1B    1-ch   2-ch
 182                  * 512  0    0    0     512    0     O
 183                  * 512  0    512  0     16     1008  X
 184                  * 512  0    0    512   16     1008  X
 185                  * 0    512  0    512   16     1008  X
 186                  * 1024 1024 1024 0     2048   1024  O
 187                  *
 188                  * We could probably detect this based on either the DRB
 189                  * matching, which was the case for the swizzling required in
 190                  * the table above, or from the 1-ch value being less than
 191                  * the minimum size of a rank.
 192                  */
 193                 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
 194                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
 195                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
 196                 } else {
 197                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
 198                         swizzle_y = I915_BIT_6_SWIZZLE_9;
 199                 }
 200         }
 201
 202         dev_priv->mm.bit_6_swizzle_x = swizzle_x;
 203         dev_priv->mm.bit_6_swizzle_y = swizzle_y;
 204 }
 205
 206 /* Check pitch constriants for all chips & tiling formats */
 207 static bool
 208 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 209 {
 210         int tile_width;
 211
 212         /* Linear is always fine */
 213         if (tiling_mode == I915_TILING_NONE)
 214                 return true;
 215
 216         if (IS_GEN2(dev) ||
 217             (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
 218                 tile_width = 128;
 219         else
 220                 tile_width = 512;
 221
 222         /* check maximum stride & object size */
 223         if (INTEL_INFO(dev)->gen >= 4) {
 224                 /* i965 stores the end address of the gtt mapping in the fence
 225                  * reg, so dont bother to check the size */
 226                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
 227                         return false;
 228         } else {
 229                 if (stride > 8192)
 230                         return false;
 231
 232                 if (IS_GEN3(dev)) {
 233                         if (size > I830_FENCE_MAX_SIZE_VAL << 20)
 234                                 return false;
 235                 } else {
 236                         if (size > I830_FENCE_MAX_SIZE_VAL << 19)
 237                                 return false;
 238                 }
 239         }
 240
 241         /* 965+ just needs multiples of tile width */
 242         if (INTEL_INFO(dev)->gen >= 4) {
 243                 if (stride & (tile_width - 1))
 244                         return false;
 245                 return true;
 246         }
 247
 248         /* Pre-965 needs power of two tile widths */
 249         if (stride < tile_width)
 250                 return false;
 251
 252         if (stride & (stride - 1))
 253                 return false;
 254
 255         return true;
 256 }
 257
 258 /* Is the current GTT allocation valid for the change in tiling? */
 259 static bool
 260 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 261 {
 262         u32 size;
 263
 264         if (tiling_mode == I915_TILING_NONE)
 265                 return true;
 266
 267         if (INTEL_INFO(obj->base.dev)->gen >= 4)
 268                 return true;
 269
 270         if (INTEL_INFO(obj->base.dev)->gen == 3) {
 271                 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
 272                         return false;
 273         } else {
 274                 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
 275                         return false;
 276         }
 277
 278         /*
 279          * Previous chips need to be aligned to the size of the smallest
 280          * fence register that can contain the object.
 281          */
 282         if (INTEL_INFO(obj->base.dev)->gen == 3)
 283                 size = 1024*1024;
 284         else
 285                 size = 512*1024;
 286
 287         while (size < obj->base.size)
 288                 size <<= 1;
 289
 290         if (obj->gtt_space->size != size)
 291                 return false;
 292
 293         if (obj->gtt_offset & (size - 1))
 294                 return false;
 295
 296         return true;
 297 }
 298
 299 /**
 300  * Sets the tiling mode of an object, returning the required swizzling of
 301  * bit 6 of addresses in the object.
 302  */
 303 int
 304 i915_gem_set_tiling(struct drm_device *dev, void *data,
 305                    struct drm_file *file)
 306 {
 307         struct drm_i915_gem_set_tiling *args = data;
 308         drm_i915_private_t *dev_priv = dev->dev_private;
 309         struct drm_i915_gem_object *obj;
 310         int ret = 0;
 311
 312         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 313         if (&obj->base == NULL)
 314                 return -ENOENT;
 315
 316         if (!i915_tiling_ok(dev,
 317                             args->stride, obj->base.size, args->tiling_mode)) {
 318                 drm_gem_object_unreference_unlocked(&obj->base);
 319                 return -EINVAL;
 320         }
 321
 322         if (obj->pin_count) {
 323                 drm_gem_object_unreference_unlocked(&obj->base);
 324                 return -EBUSY;
 325         }
 326
 327         if (args->tiling_mode == I915_TILING_NONE) {
 328                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 329                 args->stride = 0;
 330         } else {
 331                 if (args->tiling_mode == I915_TILING_X)
 332                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 333                 else
 334                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 335
 336                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
 337                  * from aborting the application on sw fallbacks to bit 17,
 338                  * and we use the pread/pwrite bit17 paths to swizzle for it.
 339                  * If there was a user that was relying on the swizzle
 340                  * information for drm_intel_bo_map()ed reads/writes this would
 341                  * break it, but we don't have any of those.
 342                  */
 343                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 344                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 345                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 346                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 347
 348                 /* If we can't handle the swizzling, make it untiled. */
 349                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 350                         args->tiling_mode = I915_TILING_NONE;
 351                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 352                         args->stride = 0;
 353                 }
 354         }
 355
 356         DRM_LOCK(dev);
 357         if (args->tiling_mode != obj->tiling_mode ||
 358             args->stride != obj->stride) {
 359                 /* We need to rebind the object if its current allocation
 360                  * no longer meets the alignment restrictions for its new
 361                  * tiling mode. Otherwise we can just leave it alone, but
 362                  * need to ensure that any fence register is updated before
 363                  * the next fenced (either through the GTT or by the BLT unit
 364                  * on older GPUs) access.
 365                  *
 366                  * After updating the tiling parameters, we then flag whether
 367                  * we need to update an associated fence register. Note this
 368                  * has to also include the unfenced register the GPU uses
 369                  * whilst executing a fenced command for an untiled object.
 370                  */
 371
 372                 obj->map_and_fenceable =
 373                         obj->gtt_space == NULL ||
 374                         (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
 375                          i915_gem_object_fence_ok(obj, args->tiling_mode));
 376
 377                 /* Rebind if we need a change of alignment */
 378                 if (!obj->map_and_fenceable) {
 379                         u32 unfenced_alignment =
 380                                 i915_gem_get_unfenced_gtt_alignment(dev,
 381                                                                     obj->base.size,
 382                                                                     args->tiling_mode);
 383                         if (obj->gtt_offset & (unfenced_alignment - 1))
 384                                 ret = i915_gem_object_unbind(obj);
 385                 }
 386
 387                 if (ret == 0) {
 388                         obj->fence_dirty =
 389                                 obj->fenced_gpu_access ||
 390                                 obj->fence_reg != I915_FENCE_REG_NONE;
 391
 392                         obj->tiling_mode = args->tiling_mode;
 393                         obj->stride = args->stride;
 394
 395                         /* Force the fence to be reacquired for GTT access */
 396                         i915_gem_release_mmap(obj);
 397                 }
 398         }
 399         /* we have to maintain this existing ABI... */
 400         args->stride = obj->stride;
 401         args->tiling_mode = obj->tiling_mode;
 402         drm_gem_object_unreference(&obj->base);
 403         DRM_UNLOCK(dev);
 404
 405         return ret;
 406 }
 407
 408 /**
 409  * Returns the current tiling mode and required bit 6 swizzling for the object.
 410  */
 411 int
 412 i915_gem_get_tiling(struct drm_device *dev, void *data,
 413                    struct drm_file *file)
 414 {
 415         struct drm_i915_gem_get_tiling *args = data;
 416         drm_i915_private_t *dev_priv = dev->dev_private;
 417         struct drm_i915_gem_object *obj;
 418
 419         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 420         if (&obj->base == NULL)
 421                 return -ENOENT;
 422
 423         DRM_LOCK(dev);
 424
 425         args->tiling_mode = obj->tiling_mode;
 426         switch (obj->tiling_mode) {
 427         case I915_TILING_X:
 428                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 429                 break;
 430         case I915_TILING_Y:
 431                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 432                 break;
 433         case I915_TILING_NONE:
 434                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 435                 break;
 436         default:
 437                 DRM_ERROR("unknown tiling mode\n");
 438         }
 439
 440         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
 441         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 442                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 443         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 444                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 445
 446         drm_gem_object_unreference(&obj->base);
 447         DRM_UNLOCK(dev);
 448
 449         return 0;
 450 }
 451
 452 /**
 453  * Swap every 64 bytes of this page around, to account for it having a new
 454  * bit 17 of its physical address and therefore being interpreted differently
 455  * by the GPU.
 456  */
 457 static void
 458 i915_gem_swizzle_page(vm_page_t page)
 459 {
 460         char temp[64];
 461         struct sf_buf *sf;
 462         char *vaddr;
 463         int i;
 464
 465         /* XXXKIB sleep */
 466         sf = sf_buf_alloc(page, SFB_DEFAULT);
 467         vaddr = (char *)sf_buf_kva(sf);
 468
 469         for (i = 0; i < PAGE_SIZE; i += 128) {
 470                 memcpy(temp, &vaddr[i], 64);
 471                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
 472                 memcpy(&vaddr[i + 64], temp, 64);
 473         }
 474
 475         sf_buf_free(sf);
 476 }
 477
 478 void
 479 i915_gem_object_do_bit_17_swizzle_page(struct drm_i915_gem_object *obj,
 480     vm_page_t m)
 481 {
 482         char new_bit_17;
 483
 484         if (obj->bit_17 == NULL)
 485                 return;
 486
 487         new_bit_17 = VM_PAGE_TO_PHYS(m) >> 17;
 488         if ((new_bit_17 & 0x1) !=
 489             (test_bit(m->pindex, obj->bit_17) != 0)) {
 490                 i915_gem_swizzle_page(m);
 491                 vm_page_dirty(m);
 492         }
 493 }
 494
 495 void
 496 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
 497 {
 498         int page_count = obj->base.size >> PAGE_SHIFT;
 499         int i;
 500
 501         if (obj->bit_17 == NULL)
 502                 return;
 503
 504         for (i = 0; i < page_count; i++) {
 505                 vm_page_t page = obj->pages[i];
 506                 char new_bit_17 = VM_PAGE_TO_PHYS(page) >> 17;
 507                 if ((new_bit_17 & 0x1) !=
 508                     (test_bit(i, obj->bit_17) != 0)) {
 509                         i915_gem_swizzle_page(page);
 510                         vm_page_dirty(page);
 511                 }
 512         }
 513 }
 514
 515 void
 516 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
 517 {
 518         int page_count = obj->base.size >> PAGE_SHIFT;
 519         int i;
 520
 521         if (obj->bit_17 == NULL) {
 522                 obj->bit_17 = malloc(BITS_TO_LONGS(page_count) *
 523                                            sizeof(long), DRM_I915_GEM, M_WAITOK);
 524                 if (obj->bit_17 == NULL) {
 525                         DRM_ERROR("Failed to allocate memory for bit 17 "
 526                                   "record\n");
 527                         return;
 528                 }
 529         }
 530
 531         /* XXXKIB: review locking, atomics might be not needed there */
 532         for (i = 0; i < page_count; i++) {
 533                 vm_page_t page = obj->pages[i];
 534                 if (VM_PAGE_TO_PHYS(page) & (1 << 17))
 535                         __set_bit(i, obj->bit_17);
 536                 else
 537                         __clear_bit(i, obj->bit_17);
 538         }
 539 }