1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
31 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
34 * The Bridge device's PCI config space has information about the
35 * fb aperture size and the amount of pre-reserved memory.
36 * This is all handled in the intel-gtt.ko module. i915.ko only
37 * cares about the vga bit for the vga rbiter.
39 #define INTEL_GMCH_CTRL 0x52
40 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
42 /* PCI config space */
44 #define HPLLCC 0xc0 /* 855 only */
45 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
46 #define GC_CLOCK_133_200 (0 << 0)
47 #define GC_CLOCK_100_200 (1 << 0)
48 #define GC_CLOCK_100_133 (2 << 0)
49 #define GC_CLOCK_166_250 (3 << 0)
51 #define GCFGC 0xf0 /* 915+ only */
52 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
53 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
54 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
55 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
56 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
57 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
58 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
59 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
60 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
61 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
62 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
63 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
64 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
65 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
66 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
67 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
68 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
69 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
70 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
71 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
72 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
73 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
74 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
77 /* Graphics reset regs */
78 #define I965_GDRST 0xc0 /* PCI config register */
79 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
80 #define GRDOM_FULL (0<<2)
81 #define GRDOM_RENDER (1<<2)
82 #define GRDOM_MEDIA (3<<2)
83 #define GRDOM_RESET_ENABLE (1<<0)
85 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
86 #define GEN6_MBC_SNPCR_SHIFT 21
87 #define GEN6_MBC_SNPCR_MASK (3<<21)
88 #define GEN6_MBC_SNPCR_MAX (0<<21)
89 #define GEN6_MBC_SNPCR_MED (1<<21)
90 #define GEN6_MBC_SNPCR_LOW (2<<21)
91 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
93 #define GEN6_MBCTL 0x0907c
94 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
95 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
96 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
97 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
98 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
100 #define GEN6_GDRST 0x941c
101 #define GEN6_GRDOM_FULL (1 << 0)
102 #define GEN6_GRDOM_RENDER (1 << 1)
103 #define GEN6_GRDOM_MEDIA (1 << 2)
104 #define GEN6_GRDOM_BLT (1 << 3)
107 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
109 #define GEN6_PDE_VALID (1 << 0)
110 #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
111 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
112 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
114 #define GEN6_PTE_VALID (1 << 0)
115 #define GEN6_PTE_UNCACHED (1 << 1)
116 #define GEN6_PTE_CACHE_LLC (2 << 1)
117 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
118 #define GEN6_PTE_CACHE_BITS (3 << 1)
119 #define GEN6_PTE_GFDT (1 << 3)
120 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
122 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
123 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
124 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
125 #define PP_DIR_DCLV_2G 0xffffffff
127 #define GAM_ECOCHK 0x4090
128 #define ECOCHK_SNB_BIT (1<<10)
129 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
130 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
134 #define VGA_ST01_MDA 0x3ba
135 #define VGA_ST01_CGA 0x3da
137 #define VGA_MSR_WRITE 0x3c2
138 #define VGA_MSR_READ 0x3cc
139 #define VGA_MSR_MEM_EN (1<<1)
140 #define VGA_MSR_CGA_MODE (1<<0)
142 #define VGA_SR_INDEX 0x3c4
143 #define VGA_SR_DATA 0x3c5
145 #define VGA_AR_INDEX 0x3c0
146 #define VGA_AR_VID_EN (1<<5)
147 #define VGA_AR_DATA_WRITE 0x3c0
148 #define VGA_AR_DATA_READ 0x3c1
150 #define VGA_GR_INDEX 0x3ce
151 #define VGA_GR_DATA 0x3cf
153 #define VGA_GR_MEM_READ_MODE_SHIFT 3
154 #define VGA_GR_MEM_READ_MODE_PLANE 1
156 #define VGA_GR_MEM_MODE_MASK 0xc
157 #define VGA_GR_MEM_MODE_SHIFT 2
158 #define VGA_GR_MEM_A0000_AFFFF 0
159 #define VGA_GR_MEM_A0000_BFFFF 1
160 #define VGA_GR_MEM_B0000_B7FFF 2
161 #define VGA_GR_MEM_B0000_BFFFF 3
163 #define VGA_DACMASK 0x3c6
164 #define VGA_DACRX 0x3c7
165 #define VGA_DACWX 0x3c8
166 #define VGA_DACDATA 0x3c9
168 #define VGA_CR_INDEX_MDA 0x3b4
169 #define VGA_CR_DATA_MDA 0x3b5
170 #define VGA_CR_INDEX_CGA 0x3d4
171 #define VGA_CR_DATA_CGA 0x3d5
174 * Memory interface instructions used by the kernel
176 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
178 #define MI_NOOP MI_INSTR(0, 0)
179 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
180 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
181 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
182 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
183 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
184 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
185 #define MI_FLUSH MI_INSTR(0x04, 0)
186 #define MI_READ_FLUSH (1 << 0)
187 #define MI_EXE_FLUSH (1 << 1)
188 #define MI_NO_WRITE_FLUSH (1 << 2)
189 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
190 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
191 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
192 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
193 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
194 #define MI_SUSPEND_FLUSH_EN (1<<0)
195 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
196 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
197 #define MI_OVERLAY_CONTINUE (0x0<<21)
198 #define MI_OVERLAY_ON (0x1<<21)
199 #define MI_OVERLAY_OFF (0x2<<21)
200 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
201 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
202 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
203 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
204 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
205 #define MI_ARB_ENABLE (1<<0)
206 #define MI_ARB_DISABLE (0<<0)
208 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
209 #define MI_MM_SPACE_GTT (1<<8)
210 #define MI_MM_SPACE_PHYSICAL (0<<8)
211 #define MI_SAVE_EXT_STATE_EN (1<<3)
212 #define MI_RESTORE_EXT_STATE_EN (1<<2)
213 #define MI_FORCE_RESTORE (1<<1)
214 #define MI_RESTORE_INHIBIT (1<<0)
215 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
216 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
217 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
218 #define MI_STORE_DWORD_INDEX_SHIFT 2
219 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
220 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
221 * simply ignores the register load under certain conditions.
222 * - One can actually load arbitrary many arbitrary registers: Simply issue x
223 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
225 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
226 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
227 #define MI_INVALIDATE_TLB (1<<18)
228 #define MI_INVALIDATE_BSD (1<<7)
229 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
230 #define MI_BATCH_NON_SECURE (1)
231 #define MI_BATCH_NON_SECURE_I965 (1<<8)
232 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
233 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
234 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
235 #define MI_SEMAPHORE_UPDATE (1<<21)
236 #define MI_SEMAPHORE_COMPARE (1<<20)
237 #define MI_SEMAPHORE_REGISTER (1<<18)
238 #define MI_SEMAPHORE_SYNC_RV (2<<16)
239 #define MI_SEMAPHORE_SYNC_RB (0<<16)
240 #define MI_SEMAPHORE_SYNC_VR (0<<16)
241 #define MI_SEMAPHORE_SYNC_VB (2<<16)
242 #define MI_SEMAPHORE_SYNC_BR (2<<16)
243 #define MI_SEMAPHORE_SYNC_BV (0<<16)
244 #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
246 * 3D instructions used by the kernel
248 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
250 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
251 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
252 #define SC_UPDATE_SCISSOR (0x1<<1)
253 #define SC_ENABLE_MASK (0x1<<0)
254 #define SC_ENABLE (0x1<<0)
255 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
256 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
257 #define SCI_YMIN_MASK (0xffff<<16)
258 #define SCI_XMIN_MASK (0xffff<<0)
259 #define SCI_YMAX_MASK (0xffff<<16)
260 #define SCI_XMAX_MASK (0xffff<<0)
261 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
262 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
263 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
264 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
265 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
266 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
267 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
268 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
269 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
270 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
271 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
272 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
273 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
274 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
275 #define BLT_DEPTH_8 (0<<24)
276 #define BLT_DEPTH_16_565 (1<<24)
277 #define BLT_DEPTH_16_1555 (2<<24)
278 #define BLT_DEPTH_32 (3<<24)
279 #define BLT_ROP_GXCOPY (0xcc<<16)
280 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
281 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
282 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
283 #define ASYNC_FLIP (1<<22)
284 #define DISPLAY_PLANE_A (0<<20)
285 #define DISPLAY_PLANE_B (1<<20)
286 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
287 #define PIPE_CONTROL_CS_STALL (1<<20)
288 #define PIPE_CONTROL_QW_WRITE (1<<14)
289 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
290 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
291 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
292 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
293 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
294 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
295 #define PIPE_CONTROL_NOTIFY (1<<8)
296 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
297 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
298 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
299 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
300 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
301 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
307 #define DEBUG_RESET_I830 0x6070
308 #define DEBUG_RESET_FULL (1<<7)
309 #define DEBUG_RESET_RENDER (1<<8)
310 #define DEBUG_RESET_DISPLAY (1<<9)
316 #define FENCE_REG_830_0 0x2000
317 #define FENCE_REG_945_8 0x3000
318 #define I830_FENCE_START_MASK 0x07f80000
319 #define I830_FENCE_TILING_Y_SHIFT 12
320 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
321 #define I830_FENCE_PITCH_SHIFT 4
322 #define I830_FENCE_REG_VALID (1<<0)
323 #define I915_FENCE_MAX_PITCH_VAL 4
324 #define I830_FENCE_MAX_PITCH_VAL 6
325 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
327 #define I915_FENCE_START_MASK 0x0ff00000
328 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
330 #define FENCE_REG_965_0 0x03000
331 #define I965_FENCE_PITCH_SHIFT 2
332 #define I965_FENCE_TILING_Y_SHIFT 1
333 #define I965_FENCE_REG_VALID (1<<0)
334 #define I965_FENCE_MAX_PITCH_VAL 0x0400
336 #define FENCE_REG_SANDYBRIDGE_0 0x100000
337 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
339 /* control register for cpu gtt access */
340 #define TILECTL 0x101000
341 #define TILECTL_SWZCTL (1 << 0)
342 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
343 #define TILECTL_BACKSNOOP_DIS (1 << 3)
346 * Instruction and interrupt control regs
348 #define PGTBL_ER 0x02024
349 #define RENDER_RING_BASE 0x02000
350 #define BSD_RING_BASE 0x04000
351 #define GEN6_BSD_RING_BASE 0x12000
352 #define BLT_RING_BASE 0x22000
353 #define RING_TAIL(base) ((base)+0x30)
354 #define RING_HEAD(base) ((base)+0x34)
355 #define RING_START(base) ((base)+0x38)
356 #define RING_CTL(base) ((base)+0x3c)
357 #define RING_SYNC_0(base) ((base)+0x40)
358 #define RING_SYNC_1(base) ((base)+0x44)
359 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
360 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
361 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
362 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
363 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
364 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
365 #define RING_MAX_IDLE(base) ((base)+0x54)
366 #define RING_HWS_PGA(base) ((base)+0x80)
367 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
368 #define ARB_MODE 0x04030
369 #define ARB_MODE_SWIZZLE_SNB (1<<4)
370 #define ARB_MODE_SWIZZLE_IVB (1<<5)
371 #define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
372 #define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x)
373 #define RENDER_HWS_PGA_GEN7 (0x04080)
374 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
375 #define DONE_REG 0x40b0
376 #define BSD_HWS_PGA_GEN7 (0x04180)
377 #define BLT_HWS_PGA_GEN7 (0x04280)
378 #define RING_ACTHD(base) ((base)+0x74)
379 #define RING_NOPID(base) ((base)+0x94)
380 #define RING_IMR(base) ((base)+0xa8)
381 #define TAIL_ADDR 0x001FFFF8
382 #define HEAD_WRAP_COUNT 0xFFE00000
383 #define HEAD_WRAP_ONE 0x00200000
384 #define HEAD_ADDR 0x001FFFFC
385 #define RING_NR_PAGES 0x001FF000
386 #define RING_REPORT_MASK 0x00000006
387 #define RING_REPORT_64K 0x00000002
388 #define RING_REPORT_128K 0x00000004
389 #define RING_NO_REPORT 0x00000000
390 #define RING_VALID_MASK 0x00000001
391 #define RING_VALID 0x00000001
392 #define RING_INVALID 0x00000000
393 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
394 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
395 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
397 #define PRB0_TAIL 0x02030
398 #define PRB0_HEAD 0x02034
399 #define PRB0_START 0x02038
400 #define PRB0_CTL 0x0203c
401 #define PRB1_TAIL 0x02040 /* 915+ only */
402 #define PRB1_HEAD 0x02044 /* 915+ only */
403 #define PRB1_START 0x02048 /* 915+ only */
404 #define PRB1_CTL 0x0204c /* 915+ only */
406 #define IPEIR_I965 0x02064
407 #define IPEHR_I965 0x02068
408 #define INSTDONE_I965 0x0206c
409 #define RING_IPEIR(base) ((base)+0x64)
410 #define RING_IPEHR(base) ((base)+0x68)
411 #define RING_INSTDONE(base) ((base)+0x6c)
412 #define RING_INSTPS(base) ((base)+0x70)
413 #define RING_DMA_FADD(base) ((base)+0x78)
414 #define RING_INSTPM(base) ((base)+0xc0)
415 #define INSTPS 0x02070 /* 965+ only */
416 #define INSTDONE1 0x0207c /* 965+ only */
417 #define ACTHD_I965 0x02074
418 #define HWS_PGA 0x02080
419 #define HWS_ADDRESS_MASK 0xfffff000
420 #define HWS_START_ADDRESS_SHIFT 4
421 #define PWRCTXA 0x2088 /* 965GM+ only */
422 #define PWRCTX_EN (1<<0)
423 #define IPEIR 0x02088
424 #define IPEHR 0x0208c
425 #define INSTDONE 0x02090
426 #define NOPID 0x02094
427 #define HWSTAM 0x02098
429 #define ERROR_GEN6 0x040a0
431 /* GM45+ chicken bits -- debug workaround bits that may be required
432 * for various sorts of correct behavior. The top 16 bits of each are
433 * the enables for writing to the corresponding low bit.
435 #define _3D_CHICKEN 0x02084
436 #define _3D_CHICKEN2 0x0208c
437 /* Disables pipelining of read flushes past the SF-WIZ interface.
438 * Required on all Ironlake steppings according to the B-Spec, but the
439 * particular danger of not doing so is not specified.
441 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
442 #define _3D_CHICKEN3 0x02090
444 #define MI_MODE 0x0209c
445 # define VS_TIMER_DISPATCH (1 << 6)
446 # define MI_FLUSH_ENABLE (1 << 12)
448 #define GFX_MODE 0x02520
449 #define GFX_MODE_GEN7 0x0229c
450 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
451 #define GFX_RUN_LIST_ENABLE (1<<15)
452 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
453 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
454 #define GFX_REPLAY_MODE (1<<11)
455 #define GFX_PSMI_GRANULARITY (1<<10)
456 #define GFX_PPGTT_ENABLE (1<<9)
458 #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
459 #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
461 #define SCPD0 0x0209c /* 915+ only */
466 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
467 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
468 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
469 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
470 #define I915_HWB_OOM_INTERRUPT (1<<13)
471 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
472 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
473 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
474 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
475 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
476 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
477 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
478 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
479 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
480 #define I915_DEBUG_INTERRUPT (1<<2)
481 #define I915_USER_INTERRUPT (1<<1)
482 #define I915_ASLE_INTERRUPT (1<<0)
483 #define I915_BSD_USER_INTERRUPT (1<<25)
487 #define GM45_ERROR_PAGE_TABLE (1<<5)
488 #define GM45_ERROR_MEM_PRIV (1<<4)
489 #define I915_ERROR_PAGE_TABLE (1<<4)
490 #define GM45_ERROR_CP_PRIV (1<<3)
491 #define I915_ERROR_MEMORY_REFRESH (1<<1)
492 #define I915_ERROR_INSTRUCTION (1<<0)
493 #define INSTPM 0x020c0
494 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
495 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
496 will not assert AGPBUSY# and will only
497 be delivered when out of C3. */
498 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
499 #define ACTHD 0x020c8
500 #define FW_BLC 0x020d8
501 #define FW_BLC2 0x020dc
502 #define FW_BLC_SELF 0x020e0 /* 915+ only */
503 #define FW_BLC_SELF_EN_MASK (1<<31)
504 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
505 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
506 #define MM_BURST_LENGTH 0x00700000
507 #define MM_FIFO_WATERMARK 0x0001F000
508 #define LM_BURST_LENGTH 0x00000700
509 #define LM_FIFO_WATERMARK 0x0000001F
510 #define MI_ARB_STATE 0x020e4 /* 915+ only */
511 #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
513 /* Make render/texture TLB fetches lower priorty than associated data
514 * fetches. This is not turned on by default
516 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
518 /* Isoch request wait on GTT enable (Display A/B/C streams).
519 * Make isoch requests stall on the TLB update. May cause
520 * display underruns (test mode only)
522 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
524 /* Block grant count for isoch requests when block count is
525 * set to a finite value.
527 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
528 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
529 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
530 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
531 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
533 /* Enable render writes to complete in C2/C3/C4 power states.
534 * If this isn't enabled, render writes are prevented in low
535 * power states. That seems bad to me.
537 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
539 /* This acknowledges an async flip immediately instead
540 * of waiting for 2TLB fetches.
542 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
544 /* Enables non-sequential data reads through arbiter
546 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
548 /* Disable FSB snooping of cacheable write cycles from binner/render
551 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
553 /* Arbiter time slice for non-isoch streams */
554 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
555 #define MI_ARB_TIME_SLICE_1 (0 << 5)
556 #define MI_ARB_TIME_SLICE_2 (1 << 5)
557 #define MI_ARB_TIME_SLICE_4 (2 << 5)
558 #define MI_ARB_TIME_SLICE_6 (3 << 5)
559 #define MI_ARB_TIME_SLICE_8 (4 << 5)
560 #define MI_ARB_TIME_SLICE_10 (5 << 5)
561 #define MI_ARB_TIME_SLICE_14 (6 << 5)
562 #define MI_ARB_TIME_SLICE_16 (7 << 5)
564 /* Low priority grace period page size */
565 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
566 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
568 /* Disable display A/B trickle feed */
569 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
571 /* Set display plane priority */
572 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
573 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
575 #define CACHE_MODE_0 0x02120 /* 915+ only */
576 #define CM0_MASK_SHIFT 16
577 #define CM0_IZ_OPT_DISABLE (1<<6)
578 #define CM0_ZR_OPT_DISABLE (1<<5)
579 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
580 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
581 #define CM0_COLOR_EVICT_DISABLE (1<<3)
582 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
583 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
584 #define BB_ADDR 0x02140 /* 8 bytes */
585 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
586 #define ECOSKPD 0x021d0
587 #define ECO_GATING_CX_ONLY (1<<3)
588 #define ECO_FLIP_DONE (1<<0)
590 /* GEN6 interrupt control */
591 #define GEN6_RENDER_HWSTAM 0x2098
592 #define GEN6_RENDER_IMR 0x20a8
593 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
594 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
595 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
596 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
597 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
598 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
599 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
600 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
601 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
603 #define GEN6_BLITTER_HWSTAM 0x22098
604 #define GEN6_BLITTER_IMR 0x220a8
605 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
606 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
607 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
608 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
610 #define GEN6_BLITTER_ECOSKPD 0x221d0
611 #define GEN6_BLITTER_LOCK_SHIFT 16
612 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
614 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
615 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
616 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
617 #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
618 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
620 #define GEN6_BSD_HWSTAM 0x12098
621 #define GEN6_BSD_IMR 0x120a8
622 #define GEN6_BSD_USER_INTERRUPT (1 << 12)
624 #define GEN6_BSD_RNCID 0x12198
627 * Framebuffer compression (915+ only)
630 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
631 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
632 #define FBC_CONTROL 0x03208
633 #define FBC_CTL_EN (1<<31)
634 #define FBC_CTL_PERIODIC (1<<30)
635 #define FBC_CTL_INTERVAL_SHIFT (16)
636 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
637 #define FBC_CTL_C3_IDLE (1<<13)
638 #define FBC_CTL_STRIDE_SHIFT (5)
639 #define FBC_CTL_FENCENO (1<<0)
640 #define FBC_COMMAND 0x0320c
641 #define FBC_CMD_COMPRESS (1<<0)
642 #define FBC_STATUS 0x03210
643 #define FBC_STAT_COMPRESSING (1<<31)
644 #define FBC_STAT_COMPRESSED (1<<30)
645 #define FBC_STAT_MODIFIED (1<<29)
646 #define FBC_STAT_CURRENT_LINE (1<<0)
647 #define FBC_CONTROL2 0x03214
648 #define FBC_CTL_FENCE_DBL (0<<4)
649 #define FBC_CTL_IDLE_IMM (0<<2)
650 #define FBC_CTL_IDLE_FULL (1<<2)
651 #define FBC_CTL_IDLE_LINE (2<<2)
652 #define FBC_CTL_IDLE_DEBUG (3<<2)
653 #define FBC_CTL_CPU_FENCE (1<<1)
654 #define FBC_CTL_PLANEA (0<<0)
655 #define FBC_CTL_PLANEB (1<<0)
656 #define FBC_FENCE_OFF 0x0321b
657 #define FBC_TAG 0x03300
659 #define FBC_LL_SIZE (1536)
661 /* Framebuffer compression for GM45+ */
662 #define DPFC_CB_BASE 0x3200
663 #define DPFC_CONTROL 0x3208
664 #define DPFC_CTL_EN (1<<31)
665 #define DPFC_CTL_PLANEA (0<<30)
666 #define DPFC_CTL_PLANEB (1<<30)
667 #define DPFC_CTL_FENCE_EN (1<<29)
668 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
669 #define DPFC_SR_EN (1<<10)
670 #define DPFC_CTL_LIMIT_1X (0<<6)
671 #define DPFC_CTL_LIMIT_2X (1<<6)
672 #define DPFC_CTL_LIMIT_4X (2<<6)
673 #define DPFC_RECOMP_CTL 0x320c
674 #define DPFC_RECOMP_STALL_EN (1<<27)
675 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
676 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
677 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
678 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
679 #define DPFC_STATUS 0x3210
680 #define DPFC_INVAL_SEG_SHIFT (16)
681 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
682 #define DPFC_COMP_SEG_SHIFT (0)
683 #define DPFC_COMP_SEG_MASK (0x000003ff)
684 #define DPFC_STATUS2 0x3214
685 #define DPFC_FENCE_YOFF 0x3218
686 #define DPFC_CHICKEN 0x3224
687 #define DPFC_HT_MODIFY (1<<31)
689 /* Framebuffer compression for Ironlake */
690 #define ILK_DPFC_CB_BASE 0x43200
691 #define ILK_DPFC_CONTROL 0x43208
692 /* The bit 28-8 is reserved */
693 #define DPFC_RESERVED (0x1FFFFF00)
694 #define ILK_DPFC_RECOMP_CTL 0x4320c
695 #define ILK_DPFC_STATUS 0x43210
696 #define ILK_DPFC_FENCE_YOFF 0x43218
697 #define ILK_DPFC_CHICKEN 0x43224
698 #define ILK_FBC_RT_BASE 0x2128
699 #define ILK_FBC_RT_VALID (1<<0)
701 #define ILK_DISPLAY_CHICKEN1 0x42000
702 #define ILK_FBCQ_DIS (1<<22)
703 #define ILK_PABSTRETCH_DIS (1<<21)
707 * Framebuffer compression for Sandybridge
709 * The following two registers are of type GTTMMADR
711 #define SNB_DPFC_CTL_SA 0x100100
712 #define SNB_CPU_FENCE_ENABLE (1<<29)
713 #define DPFC_CPU_FENCE_OFFSET 0x100104
727 # define GPIO_CLOCK_DIR_MASK (1 << 0)
728 # define GPIO_CLOCK_DIR_IN (0 << 1)
729 # define GPIO_CLOCK_DIR_OUT (1 << 1)
730 # define GPIO_CLOCK_VAL_MASK (1 << 2)
731 # define GPIO_CLOCK_VAL_OUT (1 << 3)
732 # define GPIO_CLOCK_VAL_IN (1 << 4)
733 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
734 # define GPIO_DATA_DIR_MASK (1 << 8)
735 # define GPIO_DATA_DIR_IN (0 << 9)
736 # define GPIO_DATA_DIR_OUT (1 << 9)
737 # define GPIO_DATA_VAL_MASK (1 << 10)
738 # define GPIO_DATA_VAL_OUT (1 << 11)
739 # define GPIO_DATA_VAL_IN (1 << 12)
740 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
742 #define GMBUS0 0x5100 /* clock/port select */
743 #define GMBUS_RATE_100KHZ (0<<8)
744 #define GMBUS_RATE_50KHZ (1<<8)
745 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
746 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
747 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
748 #define GMBUS_PORT_DISABLED 0
749 #define GMBUS_PORT_SSC 1
750 #define GMBUS_PORT_VGADDC 2
751 #define GMBUS_PORT_PANEL 3
752 #define GMBUS_PORT_DPC 4 /* HDMIC */
753 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
755 #define GMBUS_PORT_DPD 7 /* HDMID */
756 #define GMBUS_NUM_PORTS 8
757 #define GMBUS1 0x5104 /* command/status */
758 #define GMBUS_SW_CLR_INT (1<<31)
759 #define GMBUS_SW_RDY (1<<30)
760 #define GMBUS_ENT (1<<29) /* enable timeout */
761 #define GMBUS_CYCLE_NONE (0<<25)
762 #define GMBUS_CYCLE_WAIT (1<<25)
763 #define GMBUS_CYCLE_INDEX (2<<25)
764 #define GMBUS_CYCLE_STOP (4<<25)
765 #define GMBUS_BYTE_COUNT_SHIFT 16
766 #define GMBUS_SLAVE_INDEX_SHIFT 8
767 #define GMBUS_SLAVE_ADDR_SHIFT 1
768 #define GMBUS_SLAVE_READ (1<<0)
769 #define GMBUS_SLAVE_WRITE (0<<0)
770 #define GMBUS2 0x5108 /* status */
771 #define GMBUS_INUSE (1<<15)
772 #define GMBUS_HW_WAIT_PHASE (1<<14)
773 #define GMBUS_STALL_TIMEOUT (1<<13)
774 #define GMBUS_INT (1<<12)
775 #define GMBUS_HW_RDY (1<<11)
776 #define GMBUS_SATOER (1<<10)
777 #define GMBUS_ACTIVE (1<<9)
778 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
779 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
780 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
781 #define GMBUS_NAK_EN (1<<3)
782 #define GMBUS_IDLE_EN (1<<2)
783 #define GMBUS_HW_WAIT_EN (1<<1)
784 #define GMBUS_HW_RDY_EN (1<<0)
785 #define GMBUS5 0x5120 /* byte index */
786 #define GMBUS_2BYTE_INDEX_EN (1<<31)
789 * Clock control & power management
794 #define VGA_PD 0x6010
795 #define VGA0_PD_P2_DIV_4 (1 << 7)
796 #define VGA0_PD_P1_DIV_2 (1 << 5)
797 #define VGA0_PD_P1_SHIFT 0
798 #define VGA0_PD_P1_MASK (0x1f << 0)
799 #define VGA1_PD_P2_DIV_4 (1 << 15)
800 #define VGA1_PD_P1_DIV_2 (1 << 13)
801 #define VGA1_PD_P1_SHIFT 8
802 #define VGA1_PD_P1_MASK (0x1f << 8)
803 #define _DPLL_A 0x06014
804 #define _DPLL_B 0x06018
805 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
806 #define DPLL_VCO_ENABLE (1 << 31)
807 #define DPLL_DVO_HIGH_SPEED (1 << 30)
808 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
809 #define DPLL_VGA_MODE_DIS (1 << 28)
810 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
811 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
812 #define DPLL_MODE_MASK (3 << 26)
813 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
814 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
815 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
816 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
817 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
818 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
819 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
821 #define SRX_INDEX 0x3c4
822 #define SRX_DATA 0x3c5
824 #define SR01_SCREEN_OFF (1<<5)
827 #define PPCR_ON (1<<0)
830 #define DVOB_ON (1<<31)
832 #define DVOC_ON (1<<31)
834 #define LVDS_ON (1<<31)
836 /* Scratch pad debug 0 reg:
838 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
840 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
841 * this field (only one bit may be set).
843 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
844 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
845 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
846 /* i830, required in DVO non-gang */
847 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
848 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
849 #define PLL_REF_INPUT_DREFCLK (0 << 13)
850 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
851 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
852 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
853 #define PLL_REF_INPUT_MASK (3 << 13)
854 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
856 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
857 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
858 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
859 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
860 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
863 * Parallel to Serial Load Pulse phase selection.
864 * Selects the phase for the 10X DPLL clock for the PCIe
865 * digital display port. The range is 4 to 13; 10 or more
866 * is just a flip delay. The default is 6
868 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
869 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
871 * SDVO multiplier for 945G/GM. Not used on 965.
873 #define SDVO_MULTIPLIER_MASK 0x000000ff
874 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
875 #define SDVO_MULTIPLIER_SHIFT_VGA 0
876 #define _DPLL_A_MD 0x0601c /* 965+ only */
878 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
880 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
882 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
883 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
884 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
885 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
886 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
888 * SDVO/UDI pixel multiplier.
890 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
891 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
892 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
893 * dummy bytes in the datastream at an increased clock rate, with both sides of
894 * the link knowing how many bytes are fill.
896 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
897 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
898 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
899 * through an SDVO command.
901 * This register field has values of multiplication factor minus 1, with
902 * a maximum multiplier of 5 for SDVO.
904 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
905 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
907 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
908 * This best be set to the default value (3) or the CRT won't work. No,
909 * I don't entirely understand what this does...
911 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
912 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
913 #define _DPLL_B_MD 0x06020 /* 965+ only */
914 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
915 #define _FPA0 0x06040
916 #define _FPA1 0x06044
917 #define _FPB0 0x06048
918 #define _FPB1 0x0604c
919 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
920 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
921 #define FP_N_DIV_MASK 0x003f0000
922 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
923 #define FP_N_DIV_SHIFT 16
924 #define FP_M1_DIV_MASK 0x00003f00
925 #define FP_M1_DIV_SHIFT 8
926 #define FP_M2_DIV_MASK 0x0000003f
927 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
928 #define FP_M2_DIV_SHIFT 0
929 #define DPLL_TEST 0x606c
930 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
931 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
932 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
933 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
934 #define DPLLB_TEST_N_BYPASS (1 << 19)
935 #define DPLLB_TEST_M_BYPASS (1 << 18)
936 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
937 #define DPLLA_TEST_N_BYPASS (1 << 3)
938 #define DPLLA_TEST_M_BYPASS (1 << 2)
939 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
940 #define D_STATE 0x6104
941 #define DSTATE_GFX_RESET_I830 (1<<6)
942 #define DSTATE_PLL_D3_OFF (1<<3)
943 #define DSTATE_GFX_CLOCK_GATING (1<<1)
944 #define DSTATE_DOT_CLOCK_GATING (1<<0)
945 #define DSPCLK_GATE_D 0x6200
946 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
947 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
948 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
949 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
950 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
951 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
952 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
953 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
954 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
955 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
956 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
957 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
958 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
959 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
960 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
961 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
962 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
963 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
964 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
965 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
966 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
967 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
968 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
969 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
970 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
971 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
972 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
973 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
975 * This bit must be set on the 830 to prevent hangs when turning off the
978 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
979 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
980 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
981 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
982 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
984 #define RENCLK_GATE_D1 0x6204
985 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
986 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
987 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
988 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
989 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
990 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
991 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
992 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
993 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
994 /** This bit must be unset on 855,865 */
995 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
996 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
997 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
998 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
999 /** This bit must be set on 855,865. */
1000 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1001 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1002 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1003 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1004 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1005 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1006 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1007 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1008 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1009 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1010 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1011 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1012 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1013 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1014 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1015 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1016 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1017 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1019 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1020 /** This bit must always be set on 965G/965GM */
1021 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1022 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1023 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1024 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1025 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1026 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1027 /** This bit must always be set on 965G */
1028 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1029 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1030 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1031 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1032 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1033 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1034 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1035 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1036 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1037 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1038 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1039 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1040 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1041 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1042 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1043 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1044 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1045 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1046 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1048 #define RENCLK_GATE_D2 0x6208
1049 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1050 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1051 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1052 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1053 #define DEUC 0x6214 /* CRL only */
1059 #define _PALETTE_A 0x0a000
1060 #define _PALETTE_B 0x0a800
1061 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1063 /* MCH MMIO space */
1068 * This mirrors the MCHBAR MMIO space whose location is determined by
1069 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1070 * every way. It is not accessible from the CP register read instructions.
1073 #define MCHBAR_MIRROR_BASE 0x10000
1075 #define MCHBAR_MIRROR_BASE_SNB 0x140000
1077 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1079 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1080 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1081 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1082 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
1083 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1084 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1086 /** Pineview MCH register contains DDR3 setting */
1087 #define CSHRDDR3CTL 0x101a8
1088 #define CSHRDDR3CTL_DDR3 (1 << 2)
1090 /** 965 MCH register controlling DRAM channel configuration */
1091 #define C0DRB3 0x10206
1092 #define C1DRB3 0x10606
1094 /** snb MCH registers for reading the DRAM channel configuration */
1095 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1096 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1097 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1098 #define MAD_DIMM_ECC_MASK (0x3 << 24)
1099 #define MAD_DIMM_ECC_OFF (0x0 << 24)
1100 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1101 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1102 #define MAD_DIMM_ECC_ON (0x3 << 24)
1103 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1104 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1105 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1106 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1107 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1108 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1109 #define MAD_DIMM_A_SELECT (0x1 << 16)
1110 /* DIMM sizes are in multiples of 256mb. */
1111 #define MAD_DIMM_B_SIZE_SHIFT 8
1112 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1113 #define MAD_DIMM_A_SIZE_SHIFT 0
1114 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1117 /* Clocking configuration register */
1118 #define CLKCFG 0x10c00
1119 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1120 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1121 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1122 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1123 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1124 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1125 /* Note, below two are guess */
1126 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1127 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1128 #define CLKCFG_FSB_MASK (7 << 0)
1129 #define CLKCFG_MEM_533 (1 << 4)
1130 #define CLKCFG_MEM_667 (2 << 4)
1131 #define CLKCFG_MEM_800 (3 << 4)
1132 #define CLKCFG_MEM_MASK (7 << 4)
1134 #define TSC1 0x11001
1136 #define I915_TR1 0x11006
1137 #define TSFS 0x11020
1138 #define TSFS_SLOPE_MASK 0x0000ff00
1139 #define TSFS_SLOPE_SHIFT 8
1140 #define TSFS_INTR_MASK 0x000000ff
1142 #define CRSTANDVID 0x11100
1143 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1144 #define PXVFREQ_PX_MASK 0x7f000000
1145 #define PXVFREQ_PX_SHIFT 24
1146 #define VIDFREQ_BASE 0x11110
1147 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1148 #define VIDFREQ2 0x11114
1149 #define VIDFREQ3 0x11118
1150 #define VIDFREQ4 0x1111c
1151 #define VIDFREQ_P0_MASK 0x1f000000
1152 #define VIDFREQ_P0_SHIFT 24
1153 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1154 #define VIDFREQ_P0_CSCLK_SHIFT 20
1155 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1156 #define VIDFREQ_P0_CRCLK_SHIFT 16
1157 #define VIDFREQ_P1_MASK 0x00001f00
1158 #define VIDFREQ_P1_SHIFT 8
1159 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1160 #define VIDFREQ_P1_CSCLK_SHIFT 4
1161 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1162 #define INTTOEXT_BASE_ILK 0x11300
1163 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1164 #define INTTOEXT_MAP3_SHIFT 24
1165 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1166 #define INTTOEXT_MAP2_SHIFT 16
1167 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1168 #define INTTOEXT_MAP1_SHIFT 8
1169 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1170 #define INTTOEXT_MAP0_SHIFT 0
1171 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1172 #define MEMSWCTL 0x11170 /* Ironlake only */
1173 #define MEMCTL_CMD_MASK 0xe000
1174 #define MEMCTL_CMD_SHIFT 13
1175 #define MEMCTL_CMD_RCLK_OFF 0
1176 #define MEMCTL_CMD_RCLK_ON 1
1177 #define MEMCTL_CMD_CHFREQ 2
1178 #define MEMCTL_CMD_CHVID 3
1179 #define MEMCTL_CMD_VMMOFF 4
1180 #define MEMCTL_CMD_VMMON 5
1181 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1182 when command complete */
1183 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1184 #define MEMCTL_FREQ_SHIFT 8
1185 #define MEMCTL_SFCAVM (1<<7)
1186 #define MEMCTL_TGT_VID_MASK 0x007f
1187 #define MEMIHYST 0x1117c
1188 #define MEMINTREN 0x11180 /* 16 bits */
1189 #define MEMINT_RSEXIT_EN (1<<8)
1190 #define MEMINT_CX_SUPR_EN (1<<7)
1191 #define MEMINT_CONT_BUSY_EN (1<<6)
1192 #define MEMINT_AVG_BUSY_EN (1<<5)
1193 #define MEMINT_EVAL_CHG_EN (1<<4)
1194 #define MEMINT_MON_IDLE_EN (1<<3)
1195 #define MEMINT_UP_EVAL_EN (1<<2)
1196 #define MEMINT_DOWN_EVAL_EN (1<<1)
1197 #define MEMINT_SW_CMD_EN (1<<0)
1198 #define MEMINTRSTR 0x11182 /* 16 bits */
1199 #define MEM_RSEXIT_MASK 0xc000
1200 #define MEM_RSEXIT_SHIFT 14
1201 #define MEM_CONT_BUSY_MASK 0x3000
1202 #define MEM_CONT_BUSY_SHIFT 12
1203 #define MEM_AVG_BUSY_MASK 0x0c00
1204 #define MEM_AVG_BUSY_SHIFT 10
1205 #define MEM_EVAL_CHG_MASK 0x0300
1206 #define MEM_EVAL_BUSY_SHIFT 8
1207 #define MEM_MON_IDLE_MASK 0x00c0
1208 #define MEM_MON_IDLE_SHIFT 6
1209 #define MEM_UP_EVAL_MASK 0x0030
1210 #define MEM_UP_EVAL_SHIFT 4
1211 #define MEM_DOWN_EVAL_MASK 0x000c
1212 #define MEM_DOWN_EVAL_SHIFT 2
1213 #define MEM_SW_CMD_MASK 0x0003
1214 #define MEM_INT_STEER_GFX 0
1215 #define MEM_INT_STEER_CMR 1
1216 #define MEM_INT_STEER_SMI 2
1217 #define MEM_INT_STEER_SCI 3
1218 #define MEMINTRSTS 0x11184
1219 #define MEMINT_RSEXIT (1<<7)
1220 #define MEMINT_CONT_BUSY (1<<6)
1221 #define MEMINT_AVG_BUSY (1<<5)
1222 #define MEMINT_EVAL_CHG (1<<4)
1223 #define MEMINT_MON_IDLE (1<<3)
1224 #define MEMINT_UP_EVAL (1<<2)
1225 #define MEMINT_DOWN_EVAL (1<<1)
1226 #define MEMINT_SW_CMD (1<<0)
1227 #define MEMMODECTL 0x11190
1228 #define MEMMODE_BOOST_EN (1<<31)
1229 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1230 #define MEMMODE_BOOST_FREQ_SHIFT 24
1231 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1232 #define MEMMODE_IDLE_MODE_SHIFT 16
1233 #define MEMMODE_IDLE_MODE_EVAL 0
1234 #define MEMMODE_IDLE_MODE_CONT 1
1235 #define MEMMODE_HWIDLE_EN (1<<15)
1236 #define MEMMODE_SWMODE_EN (1<<14)
1237 #define MEMMODE_RCLK_GATE (1<<13)
1238 #define MEMMODE_HW_UPDATE (1<<12)
1239 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1240 #define MEMMODE_FSTART_SHIFT 8
1241 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1242 #define MEMMODE_FMAX_SHIFT 4
1243 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1244 #define RCBMAXAVG 0x1119c
1245 #define MEMSWCTL2 0x1119e /* Cantiga only */
1246 #define SWMEMCMD_RENDER_OFF (0 << 13)
1247 #define SWMEMCMD_RENDER_ON (1 << 13)
1248 #define SWMEMCMD_SWFREQ (2 << 13)
1249 #define SWMEMCMD_TARVID (3 << 13)
1250 #define SWMEMCMD_VRM_OFF (4 << 13)
1251 #define SWMEMCMD_VRM_ON (5 << 13)
1252 #define CMDSTS (1<<12)
1253 #define SFCAVM (1<<11)
1254 #define SWFREQ_MASK 0x0380 /* P0-7 */
1255 #define SWFREQ_SHIFT 7
1256 #define TARVID_MASK 0x001f
1257 #define MEMSTAT_CTG 0x111a0
1258 #define RCBMINAVG 0x111a0
1259 #define RCUPEI 0x111b0
1260 #define RCDNEI 0x111b4
1261 #define RSTDBYCTL 0x111b8
1262 #define RS1EN (1<<31)
1263 #define RS2EN (1<<30)
1264 #define RS3EN (1<<29)
1265 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1266 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1267 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1268 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1269 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1270 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1271 #define RSX_STATUS_MASK (7<<20)
1272 #define RSX_STATUS_ON (0<<20)
1273 #define RSX_STATUS_RC1 (1<<20)
1274 #define RSX_STATUS_RC1E (2<<20)
1275 #define RSX_STATUS_RS1 (3<<20)
1276 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1277 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1278 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1279 #define RSX_STATUS_RSVD2 (7<<20)
1280 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1281 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1282 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1283 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1284 #define RS1CONTSAV_MASK (3<<14)
1285 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1286 #define RS1CONTSAV_RSVD (1<<14)
1287 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1288 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1289 #define NORMSLEXLAT_MASK (3<<12)
1290 #define SLOW_RS123 (0<<12)
1291 #define SLOW_RS23 (1<<12)
1292 #define SLOW_RS3 (2<<12)
1293 #define NORMAL_RS123 (3<<12)
1294 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1295 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1296 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1297 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1298 #define RS_CSTATE_MASK (3<<4)
1299 #define RS_CSTATE_C367_RS1 (0<<4)
1300 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1301 #define RS_CSTATE_RSVD (2<<4)
1302 #define RS_CSTATE_C367_RS2 (3<<4)
1303 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1304 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1305 #define VIDCTL 0x111c0
1306 #define VIDSTS 0x111c8
1307 #define VIDSTART 0x111cc /* 8 bits */
1308 #define MEMSTAT_ILK 0x111f8
1309 #define MEMSTAT_VID_MASK 0x7f00
1310 #define MEMSTAT_VID_SHIFT 8
1311 #define MEMSTAT_PSTATE_MASK 0x00f8
1312 #define MEMSTAT_PSTATE_SHIFT 3
1313 #define MEMSTAT_MON_ACTV (1<<2)
1314 #define MEMSTAT_SRC_CTL_MASK 0x0003
1315 #define MEMSTAT_SRC_CTL_CORE 0
1316 #define MEMSTAT_SRC_CTL_TRB 1
1317 #define MEMSTAT_SRC_CTL_THM 2
1318 #define MEMSTAT_SRC_CTL_STDBY 3
1319 #define RCPREVBSYTUPAVG 0x113b8
1320 #define RCPREVBSYTDNAVG 0x113bc
1321 #define PMMISC 0x11214
1322 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1323 #define SDEW 0x1124c
1324 #define CSIEW0 0x11250
1325 #define CSIEW1 0x11254
1326 #define CSIEW2 0x11258
1329 #define MCHAFE 0x112c0
1330 #define CSIEC 0x112e0
1331 #define DMIEC 0x112e4
1332 #define DDREC 0x112e8
1333 #define PEG0EC 0x112ec
1334 #define PEG1EC 0x112f0
1335 #define GFXEC 0x112f4
1336 #define RPPREVBSYTUPAVG 0x113b8
1337 #define RPPREVBSYTDNAVG 0x113bc
1339 #define ECR_GPFE (1<<31)
1340 #define ECR_IMONE (1<<30)
1341 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1342 #define OGW0 0x11608
1343 #define OGW1 0x1160c
1353 #define PXWL 0x11680
1354 #define LCFUSE02 0x116c0
1355 #define LCFUSE_HIV_MASK 0x000000ff
1356 #define CSIPLL0 0x12c10
1357 #define DDRMPLL1 0X12c20
1358 #define PEG_BAND_GAP_DATA 0x14d68
1360 #define GEN6_GT_PERF_STATUS 0x145948
1361 #define GEN6_RP_STATE_LIMITS 0x145994
1362 #define GEN6_RP_STATE_CAP 0x145998
1365 * Logical Context regs
1368 #define CCID_EN (1<<0)
1369 #define CXT_SIZE 0x21a0
1370 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1371 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1372 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1373 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1374 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1375 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \
1376 GEN6_CXT_RING_SIZE(cxt_reg) + \
1377 GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1378 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1379 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1380 #define GEN7_CXT_SIZE 0x21a8
1381 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1382 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1383 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1384 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1385 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1386 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1387 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \
1388 GEN7_CXT_RING_SIZE(ctx_reg) + \
1389 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1390 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1391 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1392 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1398 #define OVADD 0x30000
1399 #define DOVSTA 0x30008
1400 #define OC_BUF (0x3<<20)
1401 #define OGAMC5 0x30010
1402 #define OGAMC4 0x30014
1403 #define OGAMC3 0x30018
1404 #define OGAMC2 0x3001c
1405 #define OGAMC1 0x30020
1406 #define OGAMC0 0x30024
1409 * Display engine regs
1412 /* Pipe A timing regs */
1413 #define _HTOTAL_A 0x60000
1414 #define _HBLANK_A 0x60004
1415 #define _HSYNC_A 0x60008
1416 #define _VTOTAL_A 0x6000c
1417 #define _VBLANK_A 0x60010
1418 #define _VSYNC_A 0x60014
1419 #define _PIPEASRC 0x6001c
1420 #define _BCLRPAT_A 0x60020
1421 #define _VSYNCSHIFT_A 0x60028
1423 /* Pipe B timing regs */
1424 #define _HTOTAL_B 0x61000
1425 #define _HBLANK_B 0x61004
1426 #define _HSYNC_B 0x61008
1427 #define _VTOTAL_B 0x6100c
1428 #define _VBLANK_B 0x61010
1429 #define _VSYNC_B 0x61014
1430 #define _PIPEBSRC 0x6101c
1431 #define _BCLRPAT_B 0x61020
1432 #define _VSYNCSHIFT_B 0x61028
1435 #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1436 #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1437 #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1438 #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1439 #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1440 #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1441 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1442 #define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1444 /* VGA port control */
1445 #define ADPA 0x61100
1446 #define ADPA_DAC_ENABLE (1<<31)
1447 #define ADPA_DAC_DISABLE 0
1448 #define ADPA_PIPE_SELECT_MASK (1<<30)
1449 #define ADPA_PIPE_A_SELECT 0
1450 #define ADPA_PIPE_B_SELECT (1<<30)
1451 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1452 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1453 #define ADPA_SETS_HVPOLARITY 0
1454 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1455 #define ADPA_VSYNC_CNTL_ENABLE 0
1456 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1457 #define ADPA_HSYNC_CNTL_ENABLE 0
1458 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1459 #define ADPA_VSYNC_ACTIVE_LOW 0
1460 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1461 #define ADPA_HSYNC_ACTIVE_LOW 0
1462 #define ADPA_DPMS_MASK (~(3<<10))
1463 #define ADPA_DPMS_ON (0<<10)
1464 #define ADPA_DPMS_SUSPEND (1<<10)
1465 #define ADPA_DPMS_STANDBY (2<<10)
1466 #define ADPA_DPMS_OFF (3<<10)
1469 /* Hotplug control (945+ only) */
1470 #define PORT_HOTPLUG_EN 0x61110
1471 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1472 #define DPB_HOTPLUG_INT_EN (1 << 29)
1473 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1474 #define DPC_HOTPLUG_INT_EN (1 << 28)
1475 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1476 #define DPD_HOTPLUG_INT_EN (1 << 27)
1477 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1478 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1479 #define TV_HOTPLUG_INT_EN (1 << 18)
1480 #define CRT_HOTPLUG_INT_EN (1 << 9)
1481 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1482 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1483 /* must use period 64 on GM45 according to docs */
1484 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1485 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1486 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1487 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1488 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1489 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1490 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1491 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1492 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1493 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1494 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1495 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1497 #define PORT_HOTPLUG_STAT 0x61114
1498 #define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1499 #define DPB_HOTPLUG_INT_STATUS (1 << 29)
1500 #define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1501 #define DPC_HOTPLUG_INT_STATUS (1 << 28)
1502 #define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1503 #define DPD_HOTPLUG_INT_STATUS (1 << 27)
1504 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1505 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1506 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1507 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1508 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1509 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1510 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1511 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1513 /* SDVO port control */
1514 #define SDVOB 0x61140
1515 #define SDVOC 0x61160
1516 #define SDVO_ENABLE (1 << 31)
1517 #define SDVO_PIPE_B_SELECT (1 << 30)
1518 #define SDVO_STALL_SELECT (1 << 29)
1519 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1521 * 915G/GM SDVO pixel multiplier.
1523 * Programmed value is multiplier - 1, up to 5x.
1525 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1527 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1528 #define SDVO_PORT_MULTIPLY_SHIFT 23
1529 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1530 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1531 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1532 #define SDVOC_GANG_MODE (1 << 16)
1533 #define SDVO_ENCODING_SDVO (0x0 << 10)
1534 #define SDVO_ENCODING_HDMI (0x2 << 10)
1535 /** Requird for HDMI operation */
1536 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1537 #define SDVO_COLOR_RANGE_16_235 (1 << 8)
1538 #define SDVO_BORDER_ENABLE (1 << 7)
1539 #define SDVO_AUDIO_ENABLE (1 << 6)
1540 /** New with 965, default is to be set */
1541 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1542 /** New with 965, default is to be set */
1543 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1544 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1545 #define SDVO_DETECTED (1 << 2)
1546 /* Bits to be preserved when writing */
1547 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1548 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1550 /* DVO port control */
1551 #define DVOA 0x61120
1552 #define DVOB 0x61140
1553 #define DVOC 0x61160
1554 #define DVO_ENABLE (1 << 31)
1555 #define DVO_PIPE_B_SELECT (1 << 30)
1556 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1557 #define DVO_PIPE_STALL (1 << 28)
1558 #define DVO_PIPE_STALL_TV (2 << 28)
1559 #define DVO_PIPE_STALL_MASK (3 << 28)
1560 #define DVO_USE_VGA_SYNC (1 << 15)
1561 #define DVO_DATA_ORDER_I740 (0 << 14)
1562 #define DVO_DATA_ORDER_FP (1 << 14)
1563 #define DVO_VSYNC_DISABLE (1 << 11)
1564 #define DVO_HSYNC_DISABLE (1 << 10)
1565 #define DVO_VSYNC_TRISTATE (1 << 9)
1566 #define DVO_HSYNC_TRISTATE (1 << 8)
1567 #define DVO_BORDER_ENABLE (1 << 7)
1568 #define DVO_DATA_ORDER_GBRG (1 << 6)
1569 #define DVO_DATA_ORDER_RGGB (0 << 6)
1570 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1571 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1572 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1573 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1574 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1575 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1576 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1577 #define DVO_PRESERVE_MASK (0x7<<24)
1578 #define DVOA_SRCDIM 0x61124
1579 #define DVOB_SRCDIM 0x61144
1580 #define DVOC_SRCDIM 0x61164
1581 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1582 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1584 /* LVDS port control */
1585 #define LVDS 0x61180
1587 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1588 * the DPLL semantics change when the LVDS is assigned to that pipe.
1590 #define LVDS_PORT_EN (1 << 31)
1591 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1592 #define LVDS_PIPEB_SELECT (1 << 30)
1593 #define LVDS_PIPE_MASK (1 << 30)
1594 #define LVDS_PIPE(pipe) ((pipe) << 30)
1595 /* LVDS dithering flag on 965/g4x platform */
1596 #define LVDS_ENABLE_DITHER (1 << 25)
1597 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1598 #define LVDS_VSYNC_POLARITY (1 << 21)
1599 #define LVDS_HSYNC_POLARITY (1 << 20)
1601 /* Enable border for unscaled (or aspect-scaled) display */
1602 #define LVDS_BORDER_ENABLE (1 << 15)
1604 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1607 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1608 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1609 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1611 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1612 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1615 #define LVDS_A3_POWER_MASK (3 << 6)
1616 #define LVDS_A3_POWER_DOWN (0 << 6)
1617 #define LVDS_A3_POWER_UP (3 << 6)
1619 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1622 #define LVDS_CLKB_POWER_MASK (3 << 4)
1623 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1624 #define LVDS_CLKB_POWER_UP (3 << 4)
1626 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1627 * setting for whether we are in dual-channel mode. The B3 pair will
1628 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1630 #define LVDS_B0B3_POWER_MASK (3 << 2)
1631 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1632 #define LVDS_B0B3_POWER_UP (3 << 2)
1634 /* Video Data Island Packet control */
1635 #define VIDEO_DIP_DATA 0x61178
1636 #define VIDEO_DIP_CTL 0x61170
1637 #define VIDEO_DIP_ENABLE (1 << 31)
1638 #define VIDEO_DIP_PORT_B (1 << 29)
1639 #define VIDEO_DIP_PORT_C (2 << 29)
1640 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
1641 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1642 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
1643 #define VIDEO_DIP_SELECT_MASK (3 << 19)
1644 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1645 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1646 #define VIDEO_DIP_SELECT_SPD (3 << 19)
1647 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1648 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1649 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1651 /* Panel power sequencing */
1652 #define PP_STATUS 0x61200
1653 #define PP_ON (1 << 31)
1655 * Indicates that all dependencies of the panel are on:
1659 * - LVDS/DVOB/DVOC on
1661 #define PP_READY (1 << 30)
1662 #define PP_SEQUENCE_NONE (0 << 28)
1663 #define PP_SEQUENCE_POWER_UP (1 << 28)
1664 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
1665 #define PP_SEQUENCE_MASK (3 << 28)
1666 #define PP_SEQUENCE_SHIFT 28
1667 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1668 #define PP_SEQUENCE_STATE_MASK 0x0000000f
1669 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
1670 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
1671 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
1672 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
1673 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
1674 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
1675 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
1676 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
1677 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
1678 #define PP_CONTROL 0x61204
1679 #define POWER_TARGET_ON (1 << 0)
1680 #define PP_ON_DELAYS 0x61208
1681 #define PP_OFF_DELAYS 0x6120c
1682 #define PP_DIVISOR 0x61210
1685 #define PFIT_CONTROL 0x61230
1686 #define PFIT_ENABLE (1 << 31)
1687 #define PFIT_PIPE_MASK (3 << 29)
1688 #define PFIT_PIPE_SHIFT 29
1689 #define VERT_INTERP_DISABLE (0 << 10)
1690 #define VERT_INTERP_BILINEAR (1 << 10)
1691 #define VERT_INTERP_MASK (3 << 10)
1692 #define VERT_AUTO_SCALE (1 << 9)
1693 #define HORIZ_INTERP_DISABLE (0 << 6)
1694 #define HORIZ_INTERP_BILINEAR (1 << 6)
1695 #define HORIZ_INTERP_MASK (3 << 6)
1696 #define HORIZ_AUTO_SCALE (1 << 5)
1697 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1698 #define PFIT_FILTER_FUZZY (0 << 24)
1699 #define PFIT_SCALING_AUTO (0 << 26)
1700 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1701 #define PFIT_SCALING_PILLAR (2 << 26)
1702 #define PFIT_SCALING_LETTER (3 << 26)
1703 #define PFIT_PGM_RATIOS 0x61234
1704 #define PFIT_VERT_SCALE_MASK 0xfff00000
1705 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1707 #define PFIT_VERT_SCALE_SHIFT 20
1708 #define PFIT_VERT_SCALE_MASK 0xfff00000
1709 #define PFIT_HORIZ_SCALE_SHIFT 4
1710 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1712 #define PFIT_VERT_SCALE_SHIFT_965 16
1713 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1714 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1715 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1717 #define PFIT_AUTO_RATIOS 0x61238
1719 /* Backlight control */
1720 #define BLC_PWM_CTL 0x61254
1721 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1722 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1723 #define BLM_COMBINATION_MODE (1 << 30)
1725 * This is the most significant 15 bits of the number of backlight cycles in a
1726 * complete cycle of the modulated backlight control.
1728 * The actual value is this field multiplied by two.
1730 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1731 #define BLM_LEGACY_MODE (1 << 16)
1733 * This is the number of cycles out of the backlight modulation cycle for which
1734 * the backlight is on.
1736 * This field must be no greater than the number of cycles in the complete
1737 * backlight modulation cycle.
1739 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1740 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1742 #define BLC_HIST_CTL 0x61260
1744 /* TV port control */
1745 #define TV_CTL 0x68000
1746 /** Enables the TV encoder */
1747 # define TV_ENC_ENABLE (1 << 31)
1748 /** Sources the TV encoder input from pipe B instead of A. */
1749 # define TV_ENC_PIPEB_SELECT (1 << 30)
1750 /** Outputs composite video (DAC A only) */
1751 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1752 /** Outputs SVideo video (DAC B/C) */
1753 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1754 /** Outputs Component video (DAC A/B/C) */
1755 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1756 /** Outputs Composite and SVideo (DAC A/B/C) */
1757 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1758 # define TV_TRILEVEL_SYNC (1 << 21)
1759 /** Enables slow sync generation (945GM only) */
1760 # define TV_SLOW_SYNC (1 << 20)
1761 /** Selects 4x oversampling for 480i and 576p */
1762 # define TV_OVERSAMPLE_4X (0 << 18)
1763 /** Selects 2x oversampling for 720p and 1080i */
1764 # define TV_OVERSAMPLE_2X (1 << 18)
1765 /** Selects no oversampling for 1080p */
1766 # define TV_OVERSAMPLE_NONE (2 << 18)
1767 /** Selects 8x oversampling */
1768 # define TV_OVERSAMPLE_8X (3 << 18)
1769 /** Selects progressive mode rather than interlaced */
1770 # define TV_PROGRESSIVE (1 << 17)
1771 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1772 # define TV_PAL_BURST (1 << 16)
1773 /** Field for setting delay of Y compared to C */
1774 # define TV_YC_SKEW_MASK (7 << 12)
1775 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1776 # define TV_ENC_SDP_FIX (1 << 11)
1778 * Enables a fix for the 915GM only.
1780 * Not sure what it does.
1782 # define TV_ENC_C0_FIX (1 << 10)
1783 /** Bits that must be preserved by software */
1784 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1785 # define TV_FUSE_STATE_MASK (3 << 4)
1786 /** Read-only state that reports all features enabled */
1787 # define TV_FUSE_STATE_ENABLED (0 << 4)
1788 /** Read-only state that reports that Macrovision is disabled in hardware*/
1789 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1790 /** Read-only state that reports that TV-out is disabled in hardware. */
1791 # define TV_FUSE_STATE_DISABLED (2 << 4)
1792 /** Normal operation */
1793 # define TV_TEST_MODE_NORMAL (0 << 0)
1794 /** Encoder test pattern 1 - combo pattern */
1795 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
1796 /** Encoder test pattern 2 - full screen vertical 75% color bars */
1797 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
1798 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
1799 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
1800 /** Encoder test pattern 4 - random noise */
1801 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
1802 /** Encoder test pattern 5 - linear color ramps */
1803 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
1805 * This test mode forces the DACs to 50% of full output.
1807 * This is used for load detection in combination with TVDAC_SENSE_MASK
1809 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1810 # define TV_TEST_MODE_MASK (7 << 0)
1812 #define TV_DAC 0x68004
1813 # define TV_DAC_SAVE 0x00ffff00
1815 * Reports that DAC state change logic has reported change (RO).
1817 * This gets cleared when TV_DAC_STATE_EN is cleared
1819 # define TVDAC_STATE_CHG (1 << 31)
1820 # define TVDAC_SENSE_MASK (7 << 28)
1821 /** Reports that DAC A voltage is above the detect threshold */
1822 # define TVDAC_A_SENSE (1 << 30)
1823 /** Reports that DAC B voltage is above the detect threshold */
1824 # define TVDAC_B_SENSE (1 << 29)
1825 /** Reports that DAC C voltage is above the detect threshold */
1826 # define TVDAC_C_SENSE (1 << 28)
1828 * Enables DAC state detection logic, for load-based TV detection.
1830 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1831 * to off, for load detection to work.
1833 # define TVDAC_STATE_CHG_EN (1 << 27)
1834 /** Sets the DAC A sense value to high */
1835 # define TVDAC_A_SENSE_CTL (1 << 26)
1836 /** Sets the DAC B sense value to high */
1837 # define TVDAC_B_SENSE_CTL (1 << 25)
1838 /** Sets the DAC C sense value to high */
1839 # define TVDAC_C_SENSE_CTL (1 << 24)
1840 /** Overrides the ENC_ENABLE and DAC voltage levels */
1841 # define DAC_CTL_OVERRIDE (1 << 7)
1842 /** Sets the slew rate. Must be preserved in software */
1843 # define ENC_TVDAC_SLEW_FAST (1 << 6)
1844 # define DAC_A_1_3_V (0 << 4)
1845 # define DAC_A_1_1_V (1 << 4)
1846 # define DAC_A_0_7_V (2 << 4)
1847 # define DAC_A_MASK (3 << 4)
1848 # define DAC_B_1_3_V (0 << 2)
1849 # define DAC_B_1_1_V (1 << 2)
1850 # define DAC_B_0_7_V (2 << 2)
1851 # define DAC_B_MASK (3 << 2)
1852 # define DAC_C_1_3_V (0 << 0)
1853 # define DAC_C_1_1_V (1 << 0)
1854 # define DAC_C_0_7_V (2 << 0)
1855 # define DAC_C_MASK (3 << 0)
1858 * CSC coefficients are stored in a floating point format with 9 bits of
1859 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1860 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1861 * -1 (0x3) being the only legal negative value.
1863 #define TV_CSC_Y 0x68010
1864 # define TV_RY_MASK 0x07ff0000
1865 # define TV_RY_SHIFT 16
1866 # define TV_GY_MASK 0x00000fff
1867 # define TV_GY_SHIFT 0
1869 #define TV_CSC_Y2 0x68014
1870 # define TV_BY_MASK 0x07ff0000
1871 # define TV_BY_SHIFT 16
1873 * Y attenuation for component video.
1875 * Stored in 1.9 fixed point.
1877 # define TV_AY_MASK 0x000003ff
1878 # define TV_AY_SHIFT 0
1880 #define TV_CSC_U 0x68018
1881 # define TV_RU_MASK 0x07ff0000
1882 # define TV_RU_SHIFT 16
1883 # define TV_GU_MASK 0x000007ff
1884 # define TV_GU_SHIFT 0
1886 #define TV_CSC_U2 0x6801c
1887 # define TV_BU_MASK 0x07ff0000
1888 # define TV_BU_SHIFT 16
1890 * U attenuation for component video.
1892 * Stored in 1.9 fixed point.
1894 # define TV_AU_MASK 0x000003ff
1895 # define TV_AU_SHIFT 0
1897 #define TV_CSC_V 0x68020
1898 # define TV_RV_MASK 0x0fff0000
1899 # define TV_RV_SHIFT 16
1900 # define TV_GV_MASK 0x000007ff
1901 # define TV_GV_SHIFT 0
1903 #define TV_CSC_V2 0x68024
1904 # define TV_BV_MASK 0x07ff0000
1905 # define TV_BV_SHIFT 16
1907 * V attenuation for component video.
1909 * Stored in 1.9 fixed point.
1911 # define TV_AV_MASK 0x000007ff
1912 # define TV_AV_SHIFT 0
1914 #define TV_CLR_KNOBS 0x68028
1915 /** 2s-complement brightness adjustment */
1916 # define TV_BRIGHTNESS_MASK 0xff000000
1917 # define TV_BRIGHTNESS_SHIFT 24
1918 /** Contrast adjustment, as a 2.6 unsigned floating point number */
1919 # define TV_CONTRAST_MASK 0x00ff0000
1920 # define TV_CONTRAST_SHIFT 16
1921 /** Saturation adjustment, as a 2.6 unsigned floating point number */
1922 # define TV_SATURATION_MASK 0x0000ff00
1923 # define TV_SATURATION_SHIFT 8
1924 /** Hue adjustment, as an integer phase angle in degrees */
1925 # define TV_HUE_MASK 0x000000ff
1926 # define TV_HUE_SHIFT 0
1928 #define TV_CLR_LEVEL 0x6802c
1929 /** Controls the DAC level for black */
1930 # define TV_BLACK_LEVEL_MASK 0x01ff0000
1931 # define TV_BLACK_LEVEL_SHIFT 16
1932 /** Controls the DAC level for blanking */
1933 # define TV_BLANK_LEVEL_MASK 0x000001ff
1934 # define TV_BLANK_LEVEL_SHIFT 0
1936 #define TV_H_CTL_1 0x68030
1937 /** Number of pixels in the hsync. */
1938 # define TV_HSYNC_END_MASK 0x1fff0000
1939 # define TV_HSYNC_END_SHIFT 16
1940 /** Total number of pixels minus one in the line (display and blanking). */
1941 # define TV_HTOTAL_MASK 0x00001fff
1942 # define TV_HTOTAL_SHIFT 0
1944 #define TV_H_CTL_2 0x68034
1945 /** Enables the colorburst (needed for non-component color) */
1946 # define TV_BURST_ENA (1 << 31)
1947 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
1948 # define TV_HBURST_START_SHIFT 16
1949 # define TV_HBURST_START_MASK 0x1fff0000
1950 /** Length of the colorburst */
1951 # define TV_HBURST_LEN_SHIFT 0
1952 # define TV_HBURST_LEN_MASK 0x0001fff
1954 #define TV_H_CTL_3 0x68038
1955 /** End of hblank, measured in pixels minus one from start of hsync */
1956 # define TV_HBLANK_END_SHIFT 16
1957 # define TV_HBLANK_END_MASK 0x1fff0000
1958 /** Start of hblank, measured in pixels minus one from start of hsync */
1959 # define TV_HBLANK_START_SHIFT 0
1960 # define TV_HBLANK_START_MASK 0x0001fff
1962 #define TV_V_CTL_1 0x6803c
1964 # define TV_NBR_END_SHIFT 16
1965 # define TV_NBR_END_MASK 0x07ff0000
1967 # define TV_VI_END_F1_SHIFT 8
1968 # define TV_VI_END_F1_MASK 0x00003f00
1970 # define TV_VI_END_F2_SHIFT 0
1971 # define TV_VI_END_F2_MASK 0x0000003f
1973 #define TV_V_CTL_2 0x68040
1974 /** Length of vsync, in half lines */
1975 # define TV_VSYNC_LEN_MASK 0x07ff0000
1976 # define TV_VSYNC_LEN_SHIFT 16
1977 /** Offset of the start of vsync in field 1, measured in one less than the
1978 * number of half lines.
1980 # define TV_VSYNC_START_F1_MASK 0x00007f00
1981 # define TV_VSYNC_START_F1_SHIFT 8
1983 * Offset of the start of vsync in field 2, measured in one less than the
1984 * number of half lines.
1986 # define TV_VSYNC_START_F2_MASK 0x0000007f
1987 # define TV_VSYNC_START_F2_SHIFT 0
1989 #define TV_V_CTL_3 0x68044
1990 /** Enables generation of the equalization signal */
1991 # define TV_EQUAL_ENA (1 << 31)
1992 /** Length of vsync, in half lines */
1993 # define TV_VEQ_LEN_MASK 0x007f0000
1994 # define TV_VEQ_LEN_SHIFT 16
1995 /** Offset of the start of equalization in field 1, measured in one less than
1996 * the number of half lines.
1998 # define TV_VEQ_START_F1_MASK 0x0007f00
1999 # define TV_VEQ_START_F1_SHIFT 8
2001 * Offset of the start of equalization in field 2, measured in one less than
2002 * the number of half lines.
2004 # define TV_VEQ_START_F2_MASK 0x000007f
2005 # define TV_VEQ_START_F2_SHIFT 0
2007 #define TV_V_CTL_4 0x68048
2009 * Offset to start of vertical colorburst, measured in one less than the
2010 * number of lines from vertical start.
2012 # define TV_VBURST_START_F1_MASK 0x003f0000
2013 # define TV_VBURST_START_F1_SHIFT 16
2015 * Offset to the end of vertical colorburst, measured in one less than the
2016 * number of lines from the start of NBR.
2018 # define TV_VBURST_END_F1_MASK 0x000000ff
2019 # define TV_VBURST_END_F1_SHIFT 0
2021 #define TV_V_CTL_5 0x6804c
2023 * Offset to start of vertical colorburst, measured in one less than the
2024 * number of lines from vertical start.
2026 # define TV_VBURST_START_F2_MASK 0x003f0000
2027 # define TV_VBURST_START_F2_SHIFT 16
2029 * Offset to the end of vertical colorburst, measured in one less than the
2030 * number of lines from the start of NBR.
2032 # define TV_VBURST_END_F2_MASK 0x000000ff
2033 # define TV_VBURST_END_F2_SHIFT 0
2035 #define TV_V_CTL_6 0x68050
2037 * Offset to start of vertical colorburst, measured in one less than the
2038 * number of lines from vertical start.
2040 # define TV_VBURST_START_F3_MASK 0x003f0000
2041 # define TV_VBURST_START_F3_SHIFT 16
2043 * Offset to the end of vertical colorburst, measured in one less than the
2044 * number of lines from the start of NBR.
2046 # define TV_VBURST_END_F3_MASK 0x000000ff
2047 # define TV_VBURST_END_F3_SHIFT 0
2049 #define TV_V_CTL_7 0x68054
2051 * Offset to start of vertical colorburst, measured in one less than the
2052 * number of lines from vertical start.
2054 # define TV_VBURST_START_F4_MASK 0x003f0000
2055 # define TV_VBURST_START_F4_SHIFT 16
2057 * Offset to the end of vertical colorburst, measured in one less than the
2058 * number of lines from the start of NBR.
2060 # define TV_VBURST_END_F4_MASK 0x000000ff
2061 # define TV_VBURST_END_F4_SHIFT 0
2063 #define TV_SC_CTL_1 0x68060
2064 /** Turns on the first subcarrier phase generation DDA */
2065 # define TV_SC_DDA1_EN (1 << 31)
2066 /** Turns on the first subcarrier phase generation DDA */
2067 # define TV_SC_DDA2_EN (1 << 30)
2068 /** Turns on the first subcarrier phase generation DDA */
2069 # define TV_SC_DDA3_EN (1 << 29)
2070 /** Sets the subcarrier DDA to reset frequency every other field */
2071 # define TV_SC_RESET_EVERY_2 (0 << 24)
2072 /** Sets the subcarrier DDA to reset frequency every fourth field */
2073 # define TV_SC_RESET_EVERY_4 (1 << 24)
2074 /** Sets the subcarrier DDA to reset frequency every eighth field */
2075 # define TV_SC_RESET_EVERY_8 (2 << 24)
2076 /** Sets the subcarrier DDA to never reset the frequency */
2077 # define TV_SC_RESET_NEVER (3 << 24)
2078 /** Sets the peak amplitude of the colorburst.*/
2079 # define TV_BURST_LEVEL_MASK 0x00ff0000
2080 # define TV_BURST_LEVEL_SHIFT 16
2081 /** Sets the increment of the first subcarrier phase generation DDA */
2082 # define TV_SCDDA1_INC_MASK 0x00000fff
2083 # define TV_SCDDA1_INC_SHIFT 0
2085 #define TV_SC_CTL_2 0x68064
2086 /** Sets the rollover for the second subcarrier phase generation DDA */
2087 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2088 # define TV_SCDDA2_SIZE_SHIFT 16
2089 /** Sets the increent of the second subcarrier phase generation DDA */
2090 # define TV_SCDDA2_INC_MASK 0x00007fff
2091 # define TV_SCDDA2_INC_SHIFT 0
2093 #define TV_SC_CTL_3 0x68068
2094 /** Sets the rollover for the third subcarrier phase generation DDA */
2095 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2096 # define TV_SCDDA3_SIZE_SHIFT 16
2097 /** Sets the increent of the third subcarrier phase generation DDA */
2098 # define TV_SCDDA3_INC_MASK 0x00007fff
2099 # define TV_SCDDA3_INC_SHIFT 0
2101 #define TV_WIN_POS 0x68070
2102 /** X coordinate of the display from the start of horizontal active */
2103 # define TV_XPOS_MASK 0x1fff0000
2104 # define TV_XPOS_SHIFT 16
2105 /** Y coordinate of the display from the start of vertical active (NBR) */
2106 # define TV_YPOS_MASK 0x00000fff
2107 # define TV_YPOS_SHIFT 0
2109 #define TV_WIN_SIZE 0x68074
2110 /** Horizontal size of the display window, measured in pixels*/
2111 # define TV_XSIZE_MASK 0x1fff0000
2112 # define TV_XSIZE_SHIFT 16
2114 * Vertical size of the display window, measured in pixels.
2116 * Must be even for interlaced modes.
2118 # define TV_YSIZE_MASK 0x00000fff
2119 # define TV_YSIZE_SHIFT 0
2121 #define TV_FILTER_CTL_1 0x68080
2123 * Enables automatic scaling calculation.
2125 * If set, the rest of the registers are ignored, and the calculated values can
2126 * be read back from the register.
2128 # define TV_AUTO_SCALE (1 << 31)
2130 * Disables the vertical filter.
2132 * This is required on modes more than 1024 pixels wide */
2133 # define TV_V_FILTER_BYPASS (1 << 29)
2134 /** Enables adaptive vertical filtering */
2135 # define TV_VADAPT (1 << 28)
2136 # define TV_VADAPT_MODE_MASK (3 << 26)
2137 /** Selects the least adaptive vertical filtering mode */
2138 # define TV_VADAPT_MODE_LEAST (0 << 26)
2139 /** Selects the moderately adaptive vertical filtering mode */
2140 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2141 /** Selects the most adaptive vertical filtering mode */
2142 # define TV_VADAPT_MODE_MOST (3 << 26)
2144 * Sets the horizontal scaling factor.
2146 * This should be the fractional part of the horizontal scaling factor divided
2147 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2149 * (src width - 1) / ((oversample * dest width) - 1)
2151 # define TV_HSCALE_FRAC_MASK 0x00003fff
2152 # define TV_HSCALE_FRAC_SHIFT 0
2154 #define TV_FILTER_CTL_2 0x68084
2156 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2158 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2160 # define TV_VSCALE_INT_MASK 0x00038000
2161 # define TV_VSCALE_INT_SHIFT 15
2163 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2165 * \sa TV_VSCALE_INT_MASK
2167 # define TV_VSCALE_FRAC_MASK 0x00007fff
2168 # define TV_VSCALE_FRAC_SHIFT 0
2170 #define TV_FILTER_CTL_3 0x68088
2172 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2174 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2176 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2178 # define TV_VSCALE_IP_INT_MASK 0x00038000
2179 # define TV_VSCALE_IP_INT_SHIFT 15
2181 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2183 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2185 * \sa TV_VSCALE_IP_INT_MASK
2187 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2188 # define TV_VSCALE_IP_FRAC_SHIFT 0
2190 #define TV_CC_CONTROL 0x68090
2191 # define TV_CC_ENABLE (1 << 31)
2193 * Specifies which field to send the CC data in.
2195 * CC data is usually sent in field 0.
2197 # define TV_CC_FID_MASK (1 << 27)
2198 # define TV_CC_FID_SHIFT 27
2199 /** Sets the horizontal position of the CC data. Usually 135. */
2200 # define TV_CC_HOFF_MASK 0x03ff0000
2201 # define TV_CC_HOFF_SHIFT 16
2202 /** Sets the vertical position of the CC data. Usually 21 */
2203 # define TV_CC_LINE_MASK 0x0000003f
2204 # define TV_CC_LINE_SHIFT 0
2206 #define TV_CC_DATA 0x68094
2207 # define TV_CC_RDY (1 << 31)
2208 /** Second word of CC data to be transmitted. */
2209 # define TV_CC_DATA_2_MASK 0x007f0000
2210 # define TV_CC_DATA_2_SHIFT 16
2211 /** First word of CC data to be transmitted. */
2212 # define TV_CC_DATA_1_MASK 0x0000007f
2213 # define TV_CC_DATA_1_SHIFT 0
2215 #define TV_H_LUMA_0 0x68100
2216 #define TV_H_LUMA_59 0x681ec
2217 #define TV_H_CHROMA_0 0x68200
2218 #define TV_H_CHROMA_59 0x682ec
2219 #define TV_V_LUMA_0 0x68300
2220 #define TV_V_LUMA_42 0x683a8
2221 #define TV_V_CHROMA_0 0x68400
2222 #define TV_V_CHROMA_42 0x684a8
2225 #define DP_A 0x64000 /* eDP */
2226 #define DP_B 0x64100
2227 #define DP_C 0x64200
2228 #define DP_D 0x64300
2230 #define DP_PORT_EN (1 << 31)
2231 #define DP_PIPEB_SELECT (1 << 30)
2232 #define DP_PIPE_MASK (1 << 30)
2234 /* Link training mode - select a suitable mode for each stage */
2235 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2236 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2237 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2238 #define DP_LINK_TRAIN_OFF (3 << 28)
2239 #define DP_LINK_TRAIN_MASK (3 << 28)
2240 #define DP_LINK_TRAIN_SHIFT 28
2242 /* CPT Link training mode */
2243 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2244 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2245 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2246 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2247 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2248 #define DP_LINK_TRAIN_SHIFT_CPT 8
2250 /* Signal voltages. These are mostly controlled by the other end */
2251 #define DP_VOLTAGE_0_4 (0 << 25)
2252 #define DP_VOLTAGE_0_6 (1 << 25)
2253 #define DP_VOLTAGE_0_8 (2 << 25)
2254 #define DP_VOLTAGE_1_2 (3 << 25)
2255 #define DP_VOLTAGE_MASK (7 << 25)
2256 #define DP_VOLTAGE_SHIFT 25
2258 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2261 #define DP_PRE_EMPHASIS_0 (0 << 22)
2262 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2263 #define DP_PRE_EMPHASIS_6 (2 << 22)
2264 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2265 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2266 #define DP_PRE_EMPHASIS_SHIFT 22
2268 /* How many wires to use. I guess 3 was too hard */
2269 #define DP_PORT_WIDTH_1 (0 << 19)
2270 #define DP_PORT_WIDTH_2 (1 << 19)
2271 #define DP_PORT_WIDTH_4 (3 << 19)
2272 #define DP_PORT_WIDTH_MASK (7 << 19)
2274 /* Mystic DPCD version 1.1 special mode */
2275 #define DP_ENHANCED_FRAMING (1 << 18)
2278 #define DP_PLL_FREQ_270MHZ (0 << 16)
2279 #define DP_PLL_FREQ_160MHZ (1 << 16)
2280 #define DP_PLL_FREQ_MASK (3 << 16)
2282 /** locked once port is enabled */
2283 #define DP_PORT_REVERSAL (1 << 15)
2286 #define DP_PLL_ENABLE (1 << 14)
2288 /** sends the clock on lane 15 of the PEG for debug */
2289 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2291 #define DP_SCRAMBLING_DISABLE (1 << 12)
2292 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2294 /** limit RGB values to avoid confusing TVs */
2295 #define DP_COLOR_RANGE_16_235 (1 << 8)
2297 /** Turn on the audio link */
2298 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2300 /** vs and hs sync polarity */
2301 #define DP_SYNC_VS_HIGH (1 << 4)
2302 #define DP_SYNC_HS_HIGH (1 << 3)
2305 #define DP_DETECTED (1 << 2)
2307 /** The aux channel provides a way to talk to the
2308 * signal sink for DDC etc. Max packet size supported
2309 * is 20 bytes in each direction, hence the 5 fixed
2312 #define DPA_AUX_CH_CTL 0x64010
2313 #define DPA_AUX_CH_DATA1 0x64014
2314 #define DPA_AUX_CH_DATA2 0x64018
2315 #define DPA_AUX_CH_DATA3 0x6401c
2316 #define DPA_AUX_CH_DATA4 0x64020
2317 #define DPA_AUX_CH_DATA5 0x64024
2319 #define DPB_AUX_CH_CTL 0x64110
2320 #define DPB_AUX_CH_DATA1 0x64114
2321 #define DPB_AUX_CH_DATA2 0x64118
2322 #define DPB_AUX_CH_DATA3 0x6411c
2323 #define DPB_AUX_CH_DATA4 0x64120
2324 #define DPB_AUX_CH_DATA5 0x64124
2326 #define DPC_AUX_CH_CTL 0x64210
2327 #define DPC_AUX_CH_DATA1 0x64214
2328 #define DPC_AUX_CH_DATA2 0x64218
2329 #define DPC_AUX_CH_DATA3 0x6421c
2330 #define DPC_AUX_CH_DATA4 0x64220
2331 #define DPC_AUX_CH_DATA5 0x64224
2333 #define DPD_AUX_CH_CTL 0x64310
2334 #define DPD_AUX_CH_DATA1 0x64314
2335 #define DPD_AUX_CH_DATA2 0x64318
2336 #define DPD_AUX_CH_DATA3 0x6431c
2337 #define DPD_AUX_CH_DATA4 0x64320
2338 #define DPD_AUX_CH_DATA5 0x64324
2340 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2341 #define DP_AUX_CH_CTL_DONE (1 << 30)
2342 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2343 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2344 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2345 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2346 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2347 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2348 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2349 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2350 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2351 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2352 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2353 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2354 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2355 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2356 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2357 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2358 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2359 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2360 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2363 * Computing GMCH M and N values for the Display Port link
2365 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2367 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2369 * The GMCH value is used internally
2371 * bytes_per_pixel is the number of bytes coming out of the plane,
2372 * which is after the LUTs, so we want the bytes for our color format.
2373 * For our current usage, this is always 3, one byte for R, G and B.
2375 #define _PIPEA_GMCH_DATA_M 0x70050
2376 #define _PIPEB_GMCH_DATA_M 0x71050
2378 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2379 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2380 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2382 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2384 #define _PIPEA_GMCH_DATA_N 0x70054
2385 #define _PIPEB_GMCH_DATA_N 0x71054
2386 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2389 * Computing Link M and N values for the Display Port link
2391 * Link M / N = pixel_clock / ls_clk
2393 * (the DP spec calls pixel_clock the 'strm_clk')
2395 * The Link value is transmitted in the Main Stream
2396 * Attributes and VB-ID.
2399 #define _PIPEA_DP_LINK_M 0x70060
2400 #define _PIPEB_DP_LINK_M 0x71060
2401 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2403 #define _PIPEA_DP_LINK_N 0x70064
2404 #define _PIPEB_DP_LINK_N 0x71064
2405 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2407 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2408 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2409 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2410 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2412 /* Display & cursor control */
2415 #define _PIPEADSL 0x70000
2416 #define DSL_LINEMASK 0x00000fff
2417 #define _PIPEACONF 0x70008
2418 #define PIPECONF_ENABLE (1<<31)
2419 #define PIPECONF_DISABLE 0
2420 #define PIPECONF_DOUBLE_WIDE (1<<30)
2421 #define I965_PIPECONF_ACTIVE (1<<30)
2422 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2423 #define PIPECONF_SINGLE_WIDE 0
2424 #define PIPECONF_PIPE_UNLOCKED 0
2425 #define PIPECONF_PIPE_LOCKED (1<<25)
2426 #define PIPECONF_PALETTE 0
2427 #define PIPECONF_GAMMA (1<<24)
2428 #define PIPECONF_FORCE_BORDER (1<<25)
2429 #define PIPECONF_INTERLACE_MASK (7 << 21)
2430 /* Note that pre-gen3 does not support interlaced display directly. Panel
2431 * fitting must be disabled on pre-ilk for interlaced. */
2432 #define PIPECONF_PROGRESSIVE (0 << 21)
2433 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2434 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2435 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2436 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2437 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2438 * means panel fitter required, PF means progressive fetch, DBL means power
2439 * saving pixel doubling. */
2440 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2441 #define PIPECONF_INTERLACED_ILK (3 << 21)
2442 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2443 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
2444 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2445 #define PIPECONF_BPP_MASK (0x000000e0)
2446 #define PIPECONF_BPP_8 (0<<5)
2447 #define PIPECONF_BPP_10 (1<<5)
2448 #define PIPECONF_BPP_6 (2<<5)
2449 #define PIPECONF_BPP_12 (3<<5)
2450 #define PIPECONF_DITHER_EN (1<<4)
2451 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2452 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2453 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2454 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2455 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2456 #define _PIPEASTAT 0x70024
2457 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2458 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2459 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2460 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2461 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2462 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2463 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2464 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2465 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2466 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2467 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2468 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2469 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2470 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2471 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2472 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2473 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2474 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2475 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2476 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2477 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2478 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2479 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2480 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2481 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2482 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2483 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2484 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2485 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2486 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2487 #define PIPE_8BPC (0 << 5)
2488 #define PIPE_10BPC (1 << 5)
2489 #define PIPE_6BPC (2 << 5)
2490 #define PIPE_12BPC (3 << 5)
2492 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2493 #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2494 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2495 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2496 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2497 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2499 #define DSPARB 0x70030
2500 #define DSPARB_CSTART_MASK (0x7f << 7)
2501 #define DSPARB_CSTART_SHIFT 7
2502 #define DSPARB_BSTART_MASK (0x7f)
2503 #define DSPARB_BSTART_SHIFT 0
2504 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2505 #define DSPARB_AEND_SHIFT 0
2507 #define DSPFW1 0x70034
2508 #define DSPFW_SR_SHIFT 23
2509 #define DSPFW_SR_MASK (0x1ff<<23)
2510 #define DSPFW_CURSORB_SHIFT 16
2511 #define DSPFW_CURSORB_MASK (0x3f<<16)
2512 #define DSPFW_PLANEB_SHIFT 8
2513 #define DSPFW_PLANEB_MASK (0x7f<<8)
2514 #define DSPFW_PLANEA_MASK (0x7f)
2515 #define DSPFW2 0x70038
2516 #define DSPFW_CURSORA_MASK 0x00003f00
2517 #define DSPFW_CURSORA_SHIFT 8
2518 #define DSPFW_PLANEC_MASK (0x7f)
2519 #define DSPFW3 0x7003c
2520 #define DSPFW_HPLL_SR_EN (1<<31)
2521 #define DSPFW_CURSOR_SR_SHIFT 24
2522 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2523 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2524 #define DSPFW_HPLL_CURSOR_SHIFT 16
2525 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2526 #define DSPFW_HPLL_SR_MASK (0x1ff)
2528 /* FIFO watermark sizes etc */
2529 #define G4X_FIFO_LINE_SIZE 64
2530 #define I915_FIFO_LINE_SIZE 64
2531 #define I830_FIFO_LINE_SIZE 32
2533 #define G4X_FIFO_SIZE 127
2534 #define I965_FIFO_SIZE 512
2535 #define I945_FIFO_SIZE 127
2536 #define I915_FIFO_SIZE 95
2537 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2538 #define I830_FIFO_SIZE 95
2540 #define G4X_MAX_WM 0x3f
2541 #define I915_MAX_WM 0x3f
2543 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2544 #define PINEVIEW_FIFO_LINE_SIZE 64
2545 #define PINEVIEW_MAX_WM 0x1ff
2546 #define PINEVIEW_DFT_WM 0x3f
2547 #define PINEVIEW_DFT_HPLLOFF_WM 0
2548 #define PINEVIEW_GUARD_WM 10
2549 #define PINEVIEW_CURSOR_FIFO 64
2550 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2551 #define PINEVIEW_CURSOR_DFT_WM 0
2552 #define PINEVIEW_CURSOR_GUARD_WM 5
2554 #define I965_CURSOR_FIFO 64
2555 #define I965_CURSOR_MAX_WM 32
2556 #define I965_CURSOR_DFT_WM 8
2558 /* define the Watermark register on Ironlake */
2559 #define WM0_PIPEA_ILK 0x45100
2560 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2561 #define WM0_PIPE_PLANE_SHIFT 16
2562 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2563 #define WM0_PIPE_SPRITE_SHIFT 8
2564 #define WM0_PIPE_CURSOR_MASK (0x1f)
2566 #define WM0_PIPEB_ILK 0x45104
2567 #define WM0_PIPEC_IVB 0x45200
2568 #define WM1_LP_ILK 0x45108
2569 #define WM1_LP_SR_EN (1<<31)
2570 #define WM1_LP_LATENCY_SHIFT 24
2571 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2572 #define WM1_LP_FBC_MASK (0xf<<20)
2573 #define WM1_LP_FBC_SHIFT 20
2574 #define WM1_LP_SR_MASK (0x1ff<<8)
2575 #define WM1_LP_SR_SHIFT 8
2576 #define WM1_LP_CURSOR_MASK (0x3f)
2577 #define WM2_LP_ILK 0x4510c
2578 #define WM2_LP_EN (1<<31)
2579 #define WM3_LP_ILK 0x45110
2580 #define WM3_LP_EN (1<<31)
2581 #define WM1S_LP_ILK 0x45120
2582 #define WM2S_LP_IVB 0x45124
2583 #define WM3S_LP_IVB 0x45128
2584 #define WM1S_LP_EN (1<<31)
2586 /* Memory latency timer register */
2587 #define MLTR_ILK 0x11222
2588 #define MLTR_WM1_SHIFT 0
2589 #define MLTR_WM2_SHIFT 8
2590 /* the unit of memory self-refresh latency time is 0.5us */
2591 #define ILK_SRLT_MASK 0x3f
2592 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2593 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2594 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2596 /* define the fifo size on Ironlake */
2597 #define ILK_DISPLAY_FIFO 128
2598 #define ILK_DISPLAY_MAXWM 64
2599 #define ILK_DISPLAY_DFTWM 8
2600 #define ILK_CURSOR_FIFO 32
2601 #define ILK_CURSOR_MAXWM 16
2602 #define ILK_CURSOR_DFTWM 8
2604 #define ILK_DISPLAY_SR_FIFO 512
2605 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2606 #define ILK_DISPLAY_DFT_SRWM 0x3f
2607 #define ILK_CURSOR_SR_FIFO 64
2608 #define ILK_CURSOR_MAX_SRWM 0x3f
2609 #define ILK_CURSOR_DFT_SRWM 8
2611 #define ILK_FIFO_LINE_SIZE 64
2613 /* define the WM info on Sandybridge */
2614 #define SNB_DISPLAY_FIFO 128
2615 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2616 #define SNB_DISPLAY_DFTWM 8
2617 #define SNB_CURSOR_FIFO 32
2618 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2619 #define SNB_CURSOR_DFTWM 8
2621 #define SNB_DISPLAY_SR_FIFO 512
2622 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2623 #define SNB_DISPLAY_DFT_SRWM 0x3f
2624 #define SNB_CURSOR_SR_FIFO 64
2625 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2626 #define SNB_CURSOR_DFT_SRWM 8
2628 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2630 #define SNB_FIFO_LINE_SIZE 64
2633 /* the address where we get all kinds of latency value */
2634 #define SSKPD 0x5d10
2635 #define SSKPD_WM_MASK 0x3f
2636 #define SSKPD_WM0_SHIFT 0
2637 #define SSKPD_WM1_SHIFT 8
2638 #define SSKPD_WM2_SHIFT 16
2639 #define SSKPD_WM3_SHIFT 24
2641 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2642 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2643 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2644 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2645 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2648 * The two pipe frame counter registers are not synchronized, so
2649 * reading a stable value is somewhat tricky. The following code
2653 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2654 * PIPE_FRAME_HIGH_SHIFT;
2655 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2656 * PIPE_FRAME_LOW_SHIFT);
2657 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2658 * PIPE_FRAME_HIGH_SHIFT);
2659 * } while (high1 != high2);
2660 * frame = (high1 << 8) | low1;
2662 #define _PIPEAFRAMEHIGH 0x70040
2663 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2664 #define PIPE_FRAME_HIGH_SHIFT 0
2665 #define _PIPEAFRAMEPIXEL 0x70044
2666 #define PIPE_FRAME_LOW_MASK 0xff000000
2667 #define PIPE_FRAME_LOW_SHIFT 24
2668 #define PIPE_PIXEL_MASK 0x00ffffff
2669 #define PIPE_PIXEL_SHIFT 0
2670 /* GM45+ just has to be different */
2671 #define _PIPEA_FRMCOUNT_GM45 0x70040
2672 #define _PIPEA_FLIPCOUNT_GM45 0x70044
2673 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2675 /* Cursor A & B regs */
2676 #define _CURACNTR 0x70080
2677 /* Old style CUR*CNTR flags (desktop 8xx) */
2678 #define CURSOR_ENABLE 0x80000000
2679 #define CURSOR_GAMMA_ENABLE 0x40000000
2680 #define CURSOR_STRIDE_MASK 0x30000000
2681 #define CURSOR_FORMAT_SHIFT 24
2682 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2683 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2684 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2685 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2686 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2687 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2688 /* New style CUR*CNTR flags */
2689 #define CURSOR_MODE 0x27
2690 #define CURSOR_MODE_DISABLE 0x00
2691 #define CURSOR_MODE_64_32B_AX 0x07
2692 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2693 #define MCURSOR_PIPE_SELECT (1 << 28)
2694 #define MCURSOR_PIPE_A 0x00
2695 #define MCURSOR_PIPE_B (1 << 28)
2696 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2697 #define _CURABASE 0x70084
2698 #define _CURAPOS 0x70088
2699 #define CURSOR_POS_MASK 0x007FF
2700 #define CURSOR_POS_SIGN 0x8000
2701 #define CURSOR_X_SHIFT 0
2702 #define CURSOR_Y_SHIFT 16
2703 #define CURSIZE 0x700a0
2704 #define _CURBCNTR 0x700c0
2705 #define _CURBBASE 0x700c4
2706 #define _CURBPOS 0x700c8
2708 #define _CURBCNTR_IVB 0x71080
2709 #define _CURBBASE_IVB 0x71084
2710 #define _CURBPOS_IVB 0x71088
2712 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2713 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2714 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2716 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
2717 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
2718 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
2720 /* Display A control */
2721 #define _DSPACNTR 0x70180
2722 #define DISPLAY_PLANE_ENABLE (1<<31)
2723 #define DISPLAY_PLANE_DISABLE 0
2724 #define DISPPLANE_GAMMA_ENABLE (1<<30)
2725 #define DISPPLANE_GAMMA_DISABLE 0
2726 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2727 #define DISPPLANE_8BPP (0x2<<26)
2728 #define DISPPLANE_15_16BPP (0x4<<26)
2729 #define DISPPLANE_16BPP (0x5<<26)
2730 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2731 #define DISPPLANE_32BPP (0x7<<26)
2732 #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2733 #define DISPPLANE_STEREO_ENABLE (1<<25)
2734 #define DISPPLANE_STEREO_DISABLE 0
2735 #define DISPPLANE_SEL_PIPE_SHIFT 24
2736 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2737 #define DISPPLANE_SEL_PIPE_A 0
2738 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2739 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2740 #define DISPPLANE_SRC_KEY_DISABLE 0
2741 #define DISPPLANE_LINE_DOUBLE (1<<20)
2742 #define DISPPLANE_NO_LINE_DOUBLE 0
2743 #define DISPPLANE_STEREO_POLARITY_FIRST 0
2744 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2745 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2746 #define DISPPLANE_TILED (1<<10)
2747 #define _DSPAADDR 0x70184
2748 #define _DSPASTRIDE 0x70188
2749 #define _DSPAPOS 0x7018C /* reserved */
2750 #define _DSPASIZE 0x70190
2751 #define _DSPASURF 0x7019C /* 965+ only */
2752 #define _DSPATILEOFF 0x701A4 /* 965+ only */
2754 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2755 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2756 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2757 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2758 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2759 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2760 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2763 #define SWF00 0x71410
2764 #define SWF01 0x71414
2765 #define SWF02 0x71418
2766 #define SWF03 0x7141c
2767 #define SWF04 0x71420
2768 #define SWF05 0x71424
2769 #define SWF06 0x71428
2770 #define SWF10 0x70410
2771 #define SWF11 0x70414
2772 #define SWF14 0x71420
2773 #define SWF30 0x72414
2774 #define SWF31 0x72418
2775 #define SWF32 0x7241c
2778 #define _PIPEBDSL 0x71000
2779 #define _PIPEBCONF 0x71008
2780 #define _PIPEBSTAT 0x71024
2781 #define _PIPEBFRAMEHIGH 0x71040
2782 #define _PIPEBFRAMEPIXEL 0x71044
2783 #define _PIPEB_FRMCOUNT_GM45 0x71040
2784 #define _PIPEB_FLIPCOUNT_GM45 0x71044
2787 /* Display B control */
2788 #define _DSPBCNTR 0x71180
2789 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2790 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
2791 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2792 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2793 #define _DSPBADDR 0x71184
2794 #define _DSPBSTRIDE 0x71188
2795 #define _DSPBPOS 0x7118C
2796 #define _DSPBSIZE 0x71190
2797 #define _DSPBSURF 0x7119C
2798 #define _DSPBTILEOFF 0x711A4
2800 /* Sprite A control */
2801 #define _DVSACNTR 0x72180
2802 #define DVS_ENABLE (1<<31)
2803 #define DVS_GAMMA_ENABLE (1<<30)
2804 #define DVS_PIXFORMAT_MASK (3<<25)
2805 #define DVS_FORMAT_YUV422 (0<<25)
2806 #define DVS_FORMAT_RGBX101010 (1<<25)
2807 #define DVS_FORMAT_RGBX888 (2<<25)
2808 #define DVS_FORMAT_RGBX161616 (3<<25)
2809 #define DVS_SOURCE_KEY (1<<22)
2810 #define DVS_RGB_ORDER_XBGR (1<<20)
2811 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
2812 #define DVS_YUV_ORDER_YUYV (0<<16)
2813 #define DVS_YUV_ORDER_UYVY (1<<16)
2814 #define DVS_YUV_ORDER_YVYU (2<<16)
2815 #define DVS_YUV_ORDER_VYUY (3<<16)
2816 #define DVS_DEST_KEY (1<<2)
2817 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
2818 #define DVS_TILED (1<<10)
2819 #define _DVSALINOFF 0x72184
2820 #define _DVSASTRIDE 0x72188
2821 #define _DVSAPOS 0x7218c
2822 #define _DVSASIZE 0x72190
2823 #define _DVSAKEYVAL 0x72194
2824 #define _DVSAKEYMSK 0x72198
2825 #define _DVSASURF 0x7219c
2826 #define _DVSAKEYMAXVAL 0x721a0
2827 #define _DVSATILEOFF 0x721a4
2828 #define _DVSASURFLIVE 0x721ac
2829 #define _DVSASCALE 0x72204
2830 #define DVS_SCALE_ENABLE (1<<31)
2831 #define DVS_FILTER_MASK (3<<29)
2832 #define DVS_FILTER_MEDIUM (0<<29)
2833 #define DVS_FILTER_ENHANCING (1<<29)
2834 #define DVS_FILTER_SOFTENING (2<<29)
2835 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2836 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
2837 #define _DVSAGAMC 0x72300
2839 #define _DVSBCNTR 0x73180
2840 #define _DVSBLINOFF 0x73184
2841 #define _DVSBSTRIDE 0x73188
2842 #define _DVSBPOS 0x7318c
2843 #define _DVSBSIZE 0x73190
2844 #define _DVSBKEYVAL 0x73194
2845 #define _DVSBKEYMSK 0x73198
2846 #define _DVSBSURF 0x7319c
2847 #define _DVSBKEYMAXVAL 0x731a0
2848 #define _DVSBTILEOFF 0x731a4
2849 #define _DVSBSURFLIVE 0x731ac
2850 #define _DVSBSCALE 0x73204
2851 #define _DVSBGAMC 0x73300
2853 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
2854 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
2855 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
2856 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
2857 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
2858 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
2859 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
2860 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
2861 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
2862 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
2863 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
2865 #define _SPRA_CTL 0x70280
2866 #define SPRITE_ENABLE (1<<31)
2867 #define SPRITE_GAMMA_ENABLE (1<<30)
2868 #define SPRITE_PIXFORMAT_MASK (7<<25)
2869 #define SPRITE_FORMAT_YUV422 (0<<25)
2870 #define SPRITE_FORMAT_RGBX101010 (1<<25)
2871 #define SPRITE_FORMAT_RGBX888 (2<<25)
2872 #define SPRITE_FORMAT_RGBX161616 (3<<25)
2873 #define SPRITE_FORMAT_YUV444 (4<<25)
2874 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
2875 #define SPRITE_CSC_ENABLE (1<<24)
2876 #define SPRITE_SOURCE_KEY (1<<22)
2877 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
2878 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
2879 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
2880 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
2881 #define SPRITE_YUV_ORDER_YUYV (0<<16)
2882 #define SPRITE_YUV_ORDER_UYVY (1<<16)
2883 #define SPRITE_YUV_ORDER_YVYU (2<<16)
2884 #define SPRITE_YUV_ORDER_VYUY (3<<16)
2885 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
2886 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
2887 #define SPRITE_TILED (1<<10)
2888 #define SPRITE_DEST_KEY (1<<2)
2889 #define _SPRA_LINOFF 0x70284
2890 #define _SPRA_STRIDE 0x70288
2891 #define _SPRA_POS 0x7028c
2892 #define _SPRA_SIZE 0x70290
2893 #define _SPRA_KEYVAL 0x70294
2894 #define _SPRA_KEYMSK 0x70298
2895 #define _SPRA_SURF 0x7029c
2896 #define _SPRA_KEYMAX 0x702a0
2897 #define _SPRA_TILEOFF 0x702a4
2898 #define _SPRA_SCALE 0x70304
2899 #define SPRITE_SCALE_ENABLE (1<<31)
2900 #define SPRITE_FILTER_MASK (3<<29)
2901 #define SPRITE_FILTER_MEDIUM (0<<29)
2902 #define SPRITE_FILTER_ENHANCING (1<<29)
2903 #define SPRITE_FILTER_SOFTENING (2<<29)
2904 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2905 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
2906 #define _SPRA_GAMC 0x70400
2908 #define _SPRB_CTL 0x71280
2909 #define _SPRB_LINOFF 0x71284
2910 #define _SPRB_STRIDE 0x71288
2911 #define _SPRB_POS 0x7128c
2912 #define _SPRB_SIZE 0x71290
2913 #define _SPRB_KEYVAL 0x71294
2914 #define _SPRB_KEYMSK 0x71298
2915 #define _SPRB_SURF 0x7129c
2916 #define _SPRB_KEYMAX 0x712a0
2917 #define _SPRB_TILEOFF 0x712a4
2918 #define _SPRB_SCALE 0x71304
2919 #define _SPRB_GAMC 0x71400
2921 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
2922 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
2923 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
2924 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
2925 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
2926 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
2927 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
2928 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
2929 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
2930 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
2931 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
2932 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
2935 #define VGACNTRL 0x71400
2936 # define VGA_DISP_DISABLE (1 << 31)
2937 # define VGA_2X_MODE (1 << 30)
2938 # define VGA_PIPE_B_SELECT (1 << 29)
2942 #define CPU_VGACNTRL 0x41000
2944 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2945 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2946 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2947 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2948 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2949 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2950 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
2951 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2952 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2954 /* refresh rate hardware control */
2955 #define RR_HW_CTL 0x45300
2956 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2957 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2959 #define FDI_PLL_BIOS_0 0x46000
2960 #define FDI_PLL_FB_CLOCK_MASK 0xff
2961 #define FDI_PLL_BIOS_1 0x46004
2962 #define FDI_PLL_BIOS_2 0x46008
2963 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2964 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
2965 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
2967 #define PCH_DSPCLK_GATE_D 0x42020
2968 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2969 # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2970 # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2971 # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2973 #define PCH_3DCGDIS0 0x46020
2974 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2975 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2977 #define PCH_3DCGDIS1 0x46024
2978 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2980 #define FDI_PLL_FREQ_CTL 0x46030
2981 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2982 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2983 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2986 #define _PIPEA_DATA_M1 0x60030
2987 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2988 #define TU_SIZE_MASK 0x7e000000
2989 #define PIPE_DATA_M1_OFFSET 0
2990 #define _PIPEA_DATA_N1 0x60034
2991 #define PIPE_DATA_N1_OFFSET 0
2993 #define _PIPEA_DATA_M2 0x60038
2994 #define PIPE_DATA_M2_OFFSET 0
2995 #define _PIPEA_DATA_N2 0x6003c
2996 #define PIPE_DATA_N2_OFFSET 0
2998 #define _PIPEA_LINK_M1 0x60040
2999 #define PIPE_LINK_M1_OFFSET 0
3000 #define _PIPEA_LINK_N1 0x60044
3001 #define PIPE_LINK_N1_OFFSET 0
3003 #define _PIPEA_LINK_M2 0x60048
3004 #define PIPE_LINK_M2_OFFSET 0
3005 #define _PIPEA_LINK_N2 0x6004c
3006 #define PIPE_LINK_N2_OFFSET 0
3008 /* PIPEB timing regs are same start from 0x61000 */
3010 #define _PIPEB_DATA_M1 0x61030
3011 #define _PIPEB_DATA_N1 0x61034
3013 #define _PIPEB_DATA_M2 0x61038
3014 #define _PIPEB_DATA_N2 0x6103c
3016 #define _PIPEB_LINK_M1 0x61040
3017 #define _PIPEB_LINK_N1 0x61044
3019 #define _PIPEB_LINK_M2 0x61048
3020 #define _PIPEB_LINK_N2 0x6104c
3022 #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3023 #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3024 #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3025 #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3026 #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3027 #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3028 #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3029 #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3031 /* CPU panel fitter */
3032 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3033 #define _PFA_CTL_1 0x68080
3034 #define _PFB_CTL_1 0x68880
3035 #define PF_ENABLE (1<<31)
3036 #define PF_FILTER_MASK (3<<23)
3037 #define PF_FILTER_PROGRAMMED (0<<23)
3038 #define PF_FILTER_MED_3x3 (1<<23)
3039 #define PF_FILTER_EDGE_ENHANCE (2<<23)
3040 #define PF_FILTER_EDGE_SOFTEN (3<<23)
3041 #define _PFA_WIN_SZ 0x68074
3042 #define _PFB_WIN_SZ 0x68874
3043 #define _PFA_WIN_POS 0x68070
3044 #define _PFB_WIN_POS 0x68870
3045 #define _PFA_VSCALE 0x68084
3046 #define _PFB_VSCALE 0x68884
3047 #define _PFA_HSCALE 0x68090
3048 #define _PFB_HSCALE 0x68890
3050 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3051 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3052 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3053 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3054 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3056 /* legacy palette */
3057 #define _LGC_PALETTE_A 0x4a000
3058 #define _LGC_PALETTE_B 0x4a800
3059 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3062 #define DE_MASTER_IRQ_CONTROL (1 << 31)
3063 #define DE_SPRITEB_FLIP_DONE (1 << 29)
3064 #define DE_SPRITEA_FLIP_DONE (1 << 28)
3065 #define DE_PLANEB_FLIP_DONE (1 << 27)
3066 #define DE_PLANEA_FLIP_DONE (1 << 26)
3067 #define DE_PCU_EVENT (1 << 25)
3068 #define DE_GTT_FAULT (1 << 24)
3069 #define DE_POISON (1 << 23)
3070 #define DE_PERFORM_COUNTER (1 << 22)
3071 #define DE_PCH_EVENT (1 << 21)
3072 #define DE_AUX_CHANNEL_A (1 << 20)
3073 #define DE_DP_A_HOTPLUG (1 << 19)
3074 #define DE_GSE (1 << 18)
3075 #define DE_PIPEB_VBLANK (1 << 15)
3076 #define DE_PIPEB_EVEN_FIELD (1 << 14)
3077 #define DE_PIPEB_ODD_FIELD (1 << 13)
3078 #define DE_PIPEB_LINE_COMPARE (1 << 12)
3079 #define DE_PIPEB_VSYNC (1 << 11)
3080 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3081 #define DE_PIPEA_VBLANK (1 << 7)
3082 #define DE_PIPEA_EVEN_FIELD (1 << 6)
3083 #define DE_PIPEA_ODD_FIELD (1 << 5)
3084 #define DE_PIPEA_LINE_COMPARE (1 << 4)
3085 #define DE_PIPEA_VSYNC (1 << 3)
3086 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3088 /* More Ivybridge lolz */
3089 #define DE_ERR_DEBUG_IVB (1<<30)
3090 #define DE_GSE_IVB (1<<29)
3091 #define DE_PCH_EVENT_IVB (1<<28)
3092 #define DE_DP_A_HOTPLUG_IVB (1<<27)
3093 #define DE_AUX_CHANNEL_A_IVB (1<<26)
3094 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3095 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3096 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3097 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
3098 #define DE_PIPEB_VBLANK_IVB (1<<5)
3099 #define DE_PIPEA_VBLANK_IVB (1<<0)
3101 #define DEISR 0x44000
3102 #define DEIMR 0x44004
3103 #define DEIIR 0x44008
3104 #define DEIER 0x4400c
3107 #define GT_PIPE_NOTIFY (1 << 4)
3108 #define GT_RENDER_CS_ERROR (1 << 3)
3109 #define GT_SYNC_STATUS (1 << 2)
3110 #define GT_USER_INTERRUPT (1 << 0)
3111 #define GT_BSD_USER_INTERRUPT (1 << 5)
3112 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
3113 #define GT_BLT_USER_INTERRUPT (1 << 22)
3115 #define GTISR 0x44010
3116 #define GTIMR 0x44014
3117 #define GTIIR 0x44018
3118 #define GTIER 0x4401c
3120 #define ILK_DISPLAY_CHICKEN2 0x42004
3121 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3122 #define ILK_ELPIN_409_SELECT (1 << 25)
3123 #define ILK_DPARB_GATE (1<<22)
3124 #define ILK_VSDPFD_FULL (1<<21)
3125 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
3126 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
3127 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
3128 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
3129 #define ILK_HDCP_DISABLE (1<<25)
3130 #define ILK_eDP_A_DISABLE (1<<24)
3131 #define ILK_DESKTOP (1<<23)
3132 #define ILK_DSPCLK_GATE 0x42020
3133 #define IVB_VRHUNIT_CLK_GATE (1<<28)
3134 #define ILK_DPARB_CLK_GATE (1<<5)
3135 #define ILK_DPFD_CLK_GATE (1<<7)
3137 /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
3138 #define ILK_CLK_FBC (1<<7)
3139 #define ILK_DPFC_DIS1 (1<<8)
3140 #define ILK_DPFC_DIS2 (1<<9)
3142 #define IVB_CHICKEN3 0x4200c
3143 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
3144 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
3146 #define DISP_ARB_CTL 0x45000
3147 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
3148 #define DISP_FBC_WM_DIS (1<<15)
3151 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
3152 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
3154 #define GEN7_L3CNTLREG1 0xB01C
3155 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
3157 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
3158 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
3160 /* WaCatErrorRejectionIssue */
3161 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3162 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3166 /* south display engine interrupt */
3167 #define SDE_AUDIO_POWER_D (1 << 27)
3168 #define SDE_AUDIO_POWER_C (1 << 26)
3169 #define SDE_AUDIO_POWER_B (1 << 25)
3170 #define SDE_AUDIO_POWER_SHIFT (25)
3171 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
3172 #define SDE_GMBUS (1 << 24)
3173 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
3174 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
3175 #define SDE_AUDIO_HDCP_MASK (3 << 22)
3176 #define SDE_AUDIO_TRANSB (1 << 21)
3177 #define SDE_AUDIO_TRANSA (1 << 20)
3178 #define SDE_AUDIO_TRANS_MASK (3 << 20)
3179 #define SDE_POISON (1 << 19)
3181 #define SDE_FDI_RXB (1 << 17)
3182 #define SDE_FDI_RXA (1 << 16)
3183 #define SDE_FDI_MASK (3 << 16)
3184 #define SDE_AUXD (1 << 15)
3185 #define SDE_AUXC (1 << 14)
3186 #define SDE_AUXB (1 << 13)
3187 #define SDE_AUX_MASK (7 << 13)
3189 #define SDE_CRT_HOTPLUG (1 << 11)
3190 #define SDE_PORTD_HOTPLUG (1 << 10)
3191 #define SDE_PORTC_HOTPLUG (1 << 9)
3192 #define SDE_PORTB_HOTPLUG (1 << 8)
3193 #define SDE_SDVOB_HOTPLUG (1 << 6)
3194 #define SDE_HOTPLUG_MASK (0xf << 8)
3195 #define SDE_TRANSB_CRC_DONE (1 << 5)
3196 #define SDE_TRANSB_CRC_ERR (1 << 4)
3197 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
3198 #define SDE_TRANSA_CRC_DONE (1 << 2)
3199 #define SDE_TRANSA_CRC_ERR (1 << 1)
3200 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
3201 #define SDE_TRANS_MASK (0x3f)
3203 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
3204 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3205 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3206 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3207 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3208 SDE_PORTD_HOTPLUG_CPT | \
3209 SDE_PORTC_HOTPLUG_CPT | \
3210 SDE_PORTB_HOTPLUG_CPT)
3212 #define SDEISR 0xc4000
3213 #define SDEIMR 0xc4004
3214 #define SDEIIR 0xc4008
3215 #define SDEIER 0xc400c
3217 /* digital port hotplug */
3218 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
3219 #define PORTD_HOTPLUG_ENABLE (1 << 20)
3220 #define PORTD_PULSE_DURATION_2ms (0)
3221 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3222 #define PORTD_PULSE_DURATION_6ms (2 << 18)
3223 #define PORTD_PULSE_DURATION_100ms (3 << 18)
3224 #define PORTD_PULSE_DURATION_MASK (3 << 18)
3225 #define PORTD_HOTPLUG_NO_DETECT (0)
3226 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3227 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3228 #define PORTC_HOTPLUG_ENABLE (1 << 12)
3229 #define PORTC_PULSE_DURATION_2ms (0)
3230 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3231 #define PORTC_PULSE_DURATION_6ms (2 << 10)
3232 #define PORTC_PULSE_DURATION_100ms (3 << 10)
3233 #define PORTC_PULSE_DURATION_MASK (3 << 10)
3234 #define PORTC_HOTPLUG_NO_DETECT (0)
3235 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3236 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3237 #define PORTB_HOTPLUG_ENABLE (1 << 4)
3238 #define PORTB_PULSE_DURATION_2ms (0)
3239 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3240 #define PORTB_PULSE_DURATION_6ms (2 << 2)
3241 #define PORTB_PULSE_DURATION_100ms (3 << 2)
3242 #define PORTB_PULSE_DURATION_MASK (3 << 2)
3243 #define PORTB_HOTPLUG_NO_DETECT (0)
3244 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3245 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3247 #define PCH_GPIOA 0xc5010
3248 #define PCH_GPIOB 0xc5014
3249 #define PCH_GPIOC 0xc5018
3250 #define PCH_GPIOD 0xc501c
3251 #define PCH_GPIOE 0xc5020
3252 #define PCH_GPIOF 0xc5024
3254 #define PCH_GMBUS0 0xc5100
3255 #define PCH_GMBUS1 0xc5104
3256 #define PCH_GMBUS2 0xc5108
3257 #define PCH_GMBUS3 0xc510c
3258 #define PCH_GMBUS4 0xc5110
3259 #define PCH_GMBUS5 0xc5120
3261 #define _PCH_DPLL_A 0xc6014
3262 #define _PCH_DPLL_B 0xc6018
3263 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3265 #define _PCH_FPA0 0xc6040
3266 #define FP_CB_TUNE (0x3<<22)
3267 #define _PCH_FPA1 0xc6044
3268 #define _PCH_FPB0 0xc6048
3269 #define _PCH_FPB1 0xc604c
3270 #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0)
3271 #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
3273 #define PCH_DPLL_TEST 0xc606c
3275 #define PCH_DREF_CONTROL 0xC6200
3276 #define DREF_CONTROL_MASK 0x7fc3
3277 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3278 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3279 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3280 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
3281 #define DREF_SSC_SOURCE_DISABLE (0<<11)
3282 #define DREF_SSC_SOURCE_ENABLE (2<<11)
3283 #define DREF_SSC_SOURCE_MASK (3<<11)
3284 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3285 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
3286 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3287 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
3288 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3289 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3290 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
3291 #define DREF_SSC4_DOWNSPREAD (0<<6)
3292 #define DREF_SSC4_CENTERSPREAD (1<<6)
3293 #define DREF_SSC1_DISABLE (0<<1)
3294 #define DREF_SSC1_ENABLE (1<<1)
3295 #define DREF_SSC4_DISABLE (0)
3296 #define DREF_SSC4_ENABLE (1)
3298 #define PCH_RAWCLK_FREQ 0xc6204
3299 #define FDL_TP1_TIMER_SHIFT 12
3300 #define FDL_TP1_TIMER_MASK (3<<12)
3301 #define FDL_TP2_TIMER_SHIFT 10
3302 #define FDL_TP2_TIMER_MASK (3<<10)
3303 #define RAWCLK_FREQ_MASK 0x3ff
3305 #define PCH_DPLL_TMR_CFG 0xc6208
3307 #define PCH_SSC4_PARMS 0xc6210
3308 #define PCH_SSC4_AUX_PARMS 0xc6214
3310 #define PCH_DPLL_SEL 0xc7000
3311 #define TRANSA_DPLL_ENABLE (1<<3)
3312 #define TRANSA_DPLLB_SEL (1<<0)
3313 #define TRANSA_DPLLA_SEL 0
3314 #define TRANSB_DPLL_ENABLE (1<<7)
3315 #define TRANSB_DPLLB_SEL (1<<4)
3316 #define TRANSB_DPLLA_SEL (0)
3317 #define TRANSC_DPLL_ENABLE (1<<11)
3318 #define TRANSC_DPLLB_SEL (1<<8)
3319 #define TRANSC_DPLLA_SEL (0)
3323 #define _TRANS_HTOTAL_A 0xe0000
3324 #define TRANS_HTOTAL_SHIFT 16
3325 #define TRANS_HACTIVE_SHIFT 0
3326 #define _TRANS_HBLANK_A 0xe0004
3327 #define TRANS_HBLANK_END_SHIFT 16
3328 #define TRANS_HBLANK_START_SHIFT 0
3329 #define _TRANS_HSYNC_A 0xe0008
3330 #define TRANS_HSYNC_END_SHIFT 16
3331 #define TRANS_HSYNC_START_SHIFT 0
3332 #define _TRANS_VTOTAL_A 0xe000c
3333 #define TRANS_VTOTAL_SHIFT 16
3334 #define TRANS_VACTIVE_SHIFT 0
3335 #define _TRANS_VBLANK_A 0xe0010
3336 #define TRANS_VBLANK_END_SHIFT 16
3337 #define TRANS_VBLANK_START_SHIFT 0
3338 #define _TRANS_VSYNC_A 0xe0014
3339 #define TRANS_VSYNC_END_SHIFT 16
3340 #define TRANS_VSYNC_START_SHIFT 0
3341 #define _TRANS_VSYNCSHIFT_A 0xe0028
3343 #define _TRANSA_DATA_M1 0xe0030
3344 #define _TRANSA_DATA_N1 0xe0034
3345 #define _TRANSA_DATA_M2 0xe0038
3346 #define _TRANSA_DATA_N2 0xe003c
3347 #define _TRANSA_DP_LINK_M1 0xe0040
3348 #define _TRANSA_DP_LINK_N1 0xe0044
3349 #define _TRANSA_DP_LINK_M2 0xe0048
3350 #define _TRANSA_DP_LINK_N2 0xe004c
3352 /* Per-transcoder DIP controls */
3354 #define _VIDEO_DIP_CTL_A 0xe0200
3355 #define _VIDEO_DIP_DATA_A 0xe0208
3356 #define _VIDEO_DIP_GCP_A 0xe0210
3358 #define _VIDEO_DIP_CTL_B 0xe1200
3359 #define _VIDEO_DIP_DATA_B 0xe1208
3360 #define _VIDEO_DIP_GCP_B 0xe1210
3362 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3363 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3364 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3366 #define _TRANS_HTOTAL_B 0xe1000
3367 #define _TRANS_HBLANK_B 0xe1004
3368 #define _TRANS_HSYNC_B 0xe1008
3369 #define _TRANS_VTOTAL_B 0xe100c
3370 #define _TRANS_VBLANK_B 0xe1010
3371 #define _TRANS_VSYNC_B 0xe1014
3372 #define _TRANS_VSYNCSHIFT_B 0xe1028
3374 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3375 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3376 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3377 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3378 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3379 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3380 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3381 _TRANS_VSYNCSHIFT_B)
3383 #define _TRANSB_DATA_M1 0xe1030
3384 #define _TRANSB_DATA_N1 0xe1034
3385 #define _TRANSB_DATA_M2 0xe1038
3386 #define _TRANSB_DATA_N2 0xe103c
3387 #define _TRANSB_DP_LINK_M1 0xe1040
3388 #define _TRANSB_DP_LINK_N1 0xe1044
3389 #define _TRANSB_DP_LINK_M2 0xe1048
3390 #define _TRANSB_DP_LINK_N2 0xe104c
3392 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3393 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3394 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3395 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3396 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3397 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3398 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3399 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3401 #define _TRANSACONF 0xf0008
3402 #define _TRANSBCONF 0xf1008
3403 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3404 #define TRANS_DISABLE (0<<31)
3405 #define TRANS_ENABLE (1<<31)
3406 #define TRANS_STATE_MASK (1<<30)
3407 #define TRANS_STATE_DISABLE (0<<30)
3408 #define TRANS_STATE_ENABLE (1<<30)
3409 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
3410 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
3411 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
3412 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
3413 #define TRANS_DP_AUDIO_ONLY (1<<26)
3414 #define TRANS_DP_VIDEO_AUDIO (0<<26)
3415 #define TRANS_INTERLACE_MASK (7<<21)
3416 #define TRANS_PROGRESSIVE (0<<21)
3417 #define TRANS_INTERLACED (3<<21)
3418 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
3419 #define TRANS_8BPC (0<<5)
3420 #define TRANS_10BPC (1<<5)
3421 #define TRANS_6BPC (2<<5)
3422 #define TRANS_12BPC (3<<5)
3424 #define _TRANSA_CHICKEN2 0xf0064
3425 #define _TRANSB_CHICKEN2 0xf1064
3426 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3427 #define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3429 #define SOUTH_CHICKEN1 0xc2000
3430 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
3431 #define FDIA_PHASE_SYNC_SHIFT_EN 18
3432 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3433 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3434 #define SOUTH_CHICKEN2 0xc2004
3435 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
3437 #define _FDI_RXA_CHICKEN 0xc200c
3438 #define _FDI_RXB_CHICKEN 0xc2010
3439 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3440 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3441 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3443 #define SOUTH_DSPCLK_GATE_D 0xc2020
3444 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3447 #define _FDI_TXA_CTL 0x60100
3448 #define _FDI_TXB_CTL 0x61100
3449 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3450 #define FDI_TX_DISABLE (0<<31)
3451 #define FDI_TX_ENABLE (1<<31)
3452 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3453 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3454 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3455 #define FDI_LINK_TRAIN_NONE (3<<28)
3456 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3457 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3458 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3459 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3460 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3461 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3462 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3463 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3464 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3465 SNB has different settings. */
3466 /* SNB A-stepping */
3467 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3468 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3469 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3470 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3471 /* SNB B-stepping */
3472 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3473 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3474 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3475 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3476 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3477 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
3478 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
3479 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
3480 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
3481 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3482 /* Ironlake: hardwired to 1 */
3483 #define FDI_TX_PLL_ENABLE (1<<14)
3485 /* Ivybridge has different bits for lolz */
3486 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3487 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3488 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3489 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3491 /* both Tx and Rx */
3492 #define FDI_COMPOSITE_SYNC (1<<11)
3493 #define FDI_LINK_TRAIN_AUTO (1<<10)
3494 #define FDI_SCRAMBLING_ENABLE (0<<7)
3495 #define FDI_SCRAMBLING_DISABLE (1<<7)
3496 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3497 #define _FDI_RXA_CTL 0xf000c
3498 #define _FDI_RXB_CTL 0xf100c
3499 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3500 #define FDI_RX_ENABLE (1<<31)
3501 /* train, dp width same as FDI_TX */
3502 #define FDI_FS_ERRC_ENABLE (1<<27)
3503 #define FDI_FE_ERRC_ENABLE (1<<26)
3504 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
3505 #define FDI_8BPC (0<<16)
3506 #define FDI_10BPC (1<<16)
3507 #define FDI_6BPC (2<<16)
3508 #define FDI_12BPC (3<<16)
3509 #define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3510 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3511 #define FDI_RX_PLL_ENABLE (1<<13)
3512 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3513 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3514 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3515 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3516 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3517 #define FDI_PCDCLK (1<<4)
3519 #define FDI_AUTO_TRAINING (1<<10)
3520 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3521 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3522 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3523 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3524 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3526 #define _FDI_RXA_MISC 0xf0010
3527 #define _FDI_RXB_MISC 0xf1010
3528 #define _FDI_RXA_TUSIZE1 0xf0030
3529 #define _FDI_RXA_TUSIZE2 0xf0038
3530 #define _FDI_RXB_TUSIZE1 0xf1030
3531 #define _FDI_RXB_TUSIZE2 0xf1038
3532 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3533 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3534 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3536 /* FDI_RX interrupt register format */
3537 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3538 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3539 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3540 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3541 #define FDI_RX_FS_CODE_ERR (1<<6)
3542 #define FDI_RX_FE_CODE_ERR (1<<5)
3543 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3544 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3545 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3546 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3547 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3549 #define _FDI_RXA_IIR 0xf0014
3550 #define _FDI_RXA_IMR 0xf0018
3551 #define _FDI_RXB_IIR 0xf1014
3552 #define _FDI_RXB_IMR 0xf1018
3553 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3554 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3556 #define FDI_PLL_CTL_1 0xfe000
3557 #define FDI_PLL_CTL_2 0xfe004
3560 #define PCH_ADPA 0xe1100
3561 #define ADPA_TRANS_SELECT_MASK (1<<30)
3562 #define ADPA_TRANS_A_SELECT 0
3563 #define ADPA_TRANS_B_SELECT (1<<30)
3564 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3565 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3566 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3567 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3568 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3569 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3570 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3571 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3572 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3573 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3574 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3575 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3576 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3577 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3578 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3579 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3580 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3581 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3582 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3585 #define HDMIB 0xe1140
3586 #define PORT_ENABLE (1 << 31)
3587 #define TRANSCODER(pipe) ((pipe) << 30)
3588 #define TRANSCODER_CPT(pipe) ((pipe) << 29)
3589 #define TRANSCODER_MASK (1 << 30)
3590 #define TRANSCODER_MASK_CPT (3 << 29)
3591 #define COLOR_FORMAT_8bpc (0)
3592 #define COLOR_FORMAT_12bpc (3 << 26)
3593 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
3594 #define SDVO_ENCODING (0)
3595 #define TMDS_ENCODING (2 << 10)
3596 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3598 #define HDMI_MODE_SELECT (1 << 9)
3599 #define DVI_MODE_SELECT (0)
3600 #define SDVOB_BORDER_ENABLE (1 << 7)
3601 #define AUDIO_ENABLE (1 << 6)
3602 #define VSYNC_ACTIVE_HIGH (1 << 4)
3603 #define HSYNC_ACTIVE_HIGH (1 << 3)
3604 #define PORT_DETECTED (1 << 2)
3606 /* PCH SDVOB multiplex with HDMIB */
3607 #define PCH_SDVOB HDMIB
3609 #define HDMIC 0xe1150
3610 #define HDMID 0xe1160
3612 #define PCH_LVDS 0xe1180
3613 #define LVDS_DETECTED (1 << 1)
3615 #define BLC_PWM_CPU_CTL2 0x48250
3616 #define PWM_ENABLE (1 << 31)
3617 #define PWM_PIPE_A (0 << 29)
3618 #define PWM_PIPE_B (1 << 29)
3619 #define BLC_PWM_CPU_CTL 0x48254
3621 #define BLC_PWM_PCH_CTL1 0xc8250
3622 #define PWM_PCH_ENABLE (1 << 31)
3623 #define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3624 #define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3625 #define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3626 #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3628 #define BLC_PWM_PCH_CTL2 0xc8254
3630 #define PCH_PP_STATUS 0xc7200
3631 #define PCH_PP_CONTROL 0xc7204
3632 #define PANEL_UNLOCK_REGS (0xabcd << 16)
3633 #define PANEL_UNLOCK_MASK (0xffff << 16)
3634 #define EDP_FORCE_VDD (1 << 3)
3635 #define EDP_BLC_ENABLE (1 << 2)
3636 #define PANEL_POWER_RESET (1 << 1)
3637 #define PANEL_POWER_OFF (0 << 0)
3638 #define PANEL_POWER_ON (1 << 0)
3639 #define PCH_PP_ON_DELAYS 0xc7208
3640 #define PANEL_PORT_SELECT_MASK (3 << 30)
3641 #define PANEL_PORT_SELECT_LVDS (0 << 30)
3642 #define PANEL_PORT_SELECT_DPA (1 << 30)
3643 #define EDP_PANEL (1 << 30)
3644 #define PANEL_PORT_SELECT_DPC (2 << 30)
3645 #define PANEL_PORT_SELECT_DPD (3 << 30)
3646 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
3647 #define PANEL_POWER_UP_DELAY_SHIFT 16
3648 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
3649 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
3651 #define PCH_PP_OFF_DELAYS 0xc720c
3652 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
3653 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
3654 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
3655 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
3657 #define PCH_PP_DIVISOR 0xc7210
3658 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
3659 #define PP_REFERENCE_DIVIDER_SHIFT 8
3660 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
3661 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
3663 #define PCH_DP_B 0xe4100
3664 #define PCH_DPB_AUX_CH_CTL 0xe4110
3665 #define PCH_DPB_AUX_CH_DATA1 0xe4114
3666 #define PCH_DPB_AUX_CH_DATA2 0xe4118
3667 #define PCH_DPB_AUX_CH_DATA3 0xe411c
3668 #define PCH_DPB_AUX_CH_DATA4 0xe4120
3669 #define PCH_DPB_AUX_CH_DATA5 0xe4124
3671 #define PCH_DP_C 0xe4200
3672 #define PCH_DPC_AUX_CH_CTL 0xe4210
3673 #define PCH_DPC_AUX_CH_DATA1 0xe4214
3674 #define PCH_DPC_AUX_CH_DATA2 0xe4218
3675 #define PCH_DPC_AUX_CH_DATA3 0xe421c
3676 #define PCH_DPC_AUX_CH_DATA4 0xe4220
3677 #define PCH_DPC_AUX_CH_DATA5 0xe4224
3679 #define PCH_DP_D 0xe4300
3680 #define PCH_DPD_AUX_CH_CTL 0xe4310
3681 #define PCH_DPD_AUX_CH_DATA1 0xe4314
3682 #define PCH_DPD_AUX_CH_DATA2 0xe4318
3683 #define PCH_DPD_AUX_CH_DATA3 0xe431c
3684 #define PCH_DPD_AUX_CH_DATA4 0xe4320
3685 #define PCH_DPD_AUX_CH_DATA5 0xe4324
3688 #define PORT_TRANS_A_SEL_CPT 0
3689 #define PORT_TRANS_B_SEL_CPT (1<<29)
3690 #define PORT_TRANS_C_SEL_CPT (2<<29)
3691 #define PORT_TRANS_SEL_MASK (3<<29)
3692 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3694 #define TRANS_DP_CTL_A 0xe0300
3695 #define TRANS_DP_CTL_B 0xe1300
3696 #define TRANS_DP_CTL_C 0xe2300
3697 #define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3698 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
3699 #define TRANS_DP_PORT_SEL_B (0<<29)
3700 #define TRANS_DP_PORT_SEL_C (1<<29)
3701 #define TRANS_DP_PORT_SEL_D (2<<29)
3702 #define TRANS_DP_PORT_SEL_NONE (3<<29)
3703 #define TRANS_DP_PORT_SEL_MASK (3<<29)
3704 #define TRANS_DP_AUDIO_ONLY (1<<26)
3705 #define TRANS_DP_ENH_FRAMING (1<<18)
3706 #define TRANS_DP_8BPC (0<<9)
3707 #define TRANS_DP_10BPC (1<<9)
3708 #define TRANS_DP_6BPC (2<<9)
3709 #define TRANS_DP_12BPC (3<<9)
3710 #define TRANS_DP_BPC_MASK (3<<9)
3711 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3712 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
3713 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3714 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
3715 #define TRANS_DP_SYNC_MASK (3<<3)
3717 /* SNB eDP training params */
3718 /* SNB A-stepping */
3719 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3720 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3721 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3722 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3723 /* SNB B-stepping */
3724 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3725 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3726 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3727 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3728 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3729 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3732 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
3733 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
3734 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
3735 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
3736 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
3737 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
3738 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
3741 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
3742 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
3743 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
3744 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
3745 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
3747 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
3749 #define FORCEWAKE 0xA18C
3750 #define FORCEWAKE_ACK 0x130090
3751 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
3752 #define FORCEWAKE_MT_ACK 0x130040
3753 #define ECOBUS 0xa180
3754 #define FORCEWAKE_MT_ENABLE (1<<5)
3756 #define GTFIFODBG 0x120000
3757 #define GT_FIFO_CPU_ERROR_MASK 7
3758 #define GT_FIFO_OVFERR (1<<2)
3759 #define GT_FIFO_IAWRERR (1<<1)
3760 #define GT_FIFO_IARDERR (1<<0)
3762 #define GT_FIFO_FREE_ENTRIES 0x120008
3763 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
3765 #define GEN6_UCGCTL1 0x9400
3766 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
3768 #define GEN6_UCGCTL2 0x9404
3769 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
3770 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
3771 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
3773 #define GEN6_RPNSWREQ 0xA008
3774 #define GEN6_TURBO_DISABLE (1<<31)
3775 #define GEN6_FREQUENCY(x) ((x)<<25)
3776 #define GEN6_OFFSET(x) ((x)<<19)
3777 #define GEN6_AGGRESSIVE_TURBO (0<<15)
3778 #define GEN6_RC_VIDEO_FREQ 0xA00C
3779 #define GEN6_RC_CONTROL 0xA090
3780 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3781 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3782 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3783 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3784 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3785 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3786 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
3787 #define GEN6_RP_DOWN_TIMEOUT 0xA010
3788 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
3789 #define GEN6_RPSTAT1 0xA01C
3790 #define GEN6_CAGF_SHIFT 8
3791 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3792 #define GEN6_RP_CONTROL 0xA024
3793 #define GEN6_RP_MEDIA_TURBO (1<<11)
3794 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
3795 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
3796 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
3797 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
3798 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
3799 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
3800 #define GEN6_RP_ENABLE (1<<7)
3801 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3802 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3803 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3804 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3805 #define GEN6_RP_UP_THRESHOLD 0xA02C
3806 #define GEN6_RP_DOWN_THRESHOLD 0xA030
3807 #define GEN6_RP_CUR_UP_EI 0xA050
3808 #define GEN6_CURICONT_MASK 0xffffff
3809 #define GEN6_RP_CUR_UP 0xA054
3810 #define GEN6_CURBSYTAVG_MASK 0xffffff
3811 #define GEN6_RP_PREV_UP 0xA058
3812 #define GEN6_RP_CUR_DOWN_EI 0xA05C
3813 #define GEN6_CURIAVG_MASK 0xffffff
3814 #define GEN6_RP_CUR_DOWN 0xA060
3815 #define GEN6_RP_PREV_DOWN 0xA064
3816 #define GEN6_RP_UP_EI 0xA068
3817 #define GEN6_RP_DOWN_EI 0xA06C
3818 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
3819 #define GEN6_RC_STATE 0xA094
3820 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3821 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3822 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3823 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3824 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3825 #define GEN6_RC_SLEEP 0xA0B0
3826 #define GEN6_RC1e_THRESHOLD 0xA0B4
3827 #define GEN6_RC6_THRESHOLD 0xA0B8
3828 #define GEN6_RC6p_THRESHOLD 0xA0BC
3829 #define GEN6_RC6pp_THRESHOLD 0xA0C0
3830 #define GEN6_PMINTRMSK 0xA168
3832 #define GEN6_PMISR 0x44020
3833 #define GEN6_PMIMR 0x44024 /* rps_lock */
3834 #define GEN6_PMIIR 0x44028
3835 #define GEN6_PMIER 0x4402C
3836 #define GEN6_PM_MBOX_EVENT (1<<25)
3837 #define GEN6_PM_THERMAL_EVENT (1<<24)
3838 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3839 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3840 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3841 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3842 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3843 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3844 GEN6_PM_RP_DOWN_THRESHOLD | \
3845 GEN6_PM_RP_DOWN_TIMEOUT)
3847 #define GEN6_PCODE_MAILBOX 0x138124
3848 #define GEN6_PCODE_READY (1<<31)
3849 #define GEN6_READ_OC_PARAMS 0xc
3850 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3851 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3852 #define GEN6_PCODE_DATA 0x138128
3853 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3855 #define GEN6_GT_CORE_STATUS 0x138060
3856 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
3857 #define GEN6_RCn_MASK 7
3863 #define G4X_AUD_VID_DID 0x62020
3864 #define INTEL_AUDIO_DEVCL 0x808629FB
3865 #define INTEL_AUDIO_DEVBLC 0x80862801
3866 #define INTEL_AUDIO_DEVCTG 0x80862802
3868 #define G4X_AUD_CNTL_ST 0x620B4
3869 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
3870 #define G4X_ELDV_DEVCTG (1 << 14)
3871 #define G4X_ELD_ADDR (0xf << 5)
3872 #define G4X_ELD_ACK (1 << 4)
3873 #define G4X_HDMIW_HDMIEDID 0x6210C
3875 #define IBX_HDMIW_HDMIEDID_A 0xE2050
3876 #define IBX_AUD_CNTL_ST_A 0xE20B4
3877 #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
3878 #define IBX_ELD_ADDRESS (0x1f << 5)
3879 #define IBX_ELD_ACK (1 << 4)
3880 #define IBX_AUD_CNTL_ST2 0xE20C0
3881 #define IBX_ELD_VALIDB (1 << 0)
3882 #define IBX_CP_READYB (1 << 1)
3884 #define CPT_HDMIW_HDMIEDID_A 0xE5050
3885 #define CPT_AUD_CNTL_ST_A 0xE50B4
3886 #define CPT_AUD_CNTRL_ST2 0xE50C0
3888 /* These are the 4 32-bit write offset registers for each stream
3889 * output buffer. It determines the offset from the
3890 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
3892 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
3894 #define IBX_AUD_CONFIG_A 0xe2000
3895 #define CPT_AUD_CONFIG_A 0xe5000
3896 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
3897 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
3898 #define AUD_CONFIG_UPPER_N_SHIFT 20
3899 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
3900 #define AUD_CONFIG_LOWER_N_SHIFT 4
3901 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
3902 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
3903 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
3904 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
3906 #endif /* _I915_REG_H_ */