1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
31 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
32 #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
34 #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
36 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
37 #define _MASKED_BIT_DISABLE(a) ((a) << 16)
40 * The Bridge device's PCI config space has information about the
41 * fb aperture size and the amount of pre-reserved memory.
42 * This is all handled in the intel-gtt.ko module. i915.ko only
43 * cares about the vga bit for the vga rbiter.
45 #define INTEL_GMCH_CTRL 0x52
46 #define INTEL_GMCH_VGA_DISABLE (1 << 1)
47 #define SNB_GMCH_CTRL 0x50
48 #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
49 #define SNB_GMCH_GGMS_MASK 0x3
50 #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
51 #define SNB_GMCH_GMS_MASK 0x1f
52 #define IVB_GMCH_GMS_SHIFT 4
53 #define IVB_GMCH_GMS_MASK 0xf
56 /* PCI config space */
58 #define HPLLCC 0xc0 /* 855 only */
59 #define GC_CLOCK_CONTROL_MASK (0xf << 0)
60 #define GC_CLOCK_133_200 (0 << 0)
61 #define GC_CLOCK_100_200 (1 << 0)
62 #define GC_CLOCK_100_133 (2 << 0)
63 #define GC_CLOCK_166_250 (3 << 0)
65 #define GCFGC 0xf0 /* 915+ only */
66 #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
67 #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
68 #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
69 #define GC_DISPLAY_CLOCK_MASK (7 << 4)
70 #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
71 #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
72 #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
73 #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
74 #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
75 #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
76 #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
77 #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
78 #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
79 #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
80 #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
81 #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
82 #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
83 #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
84 #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
85 #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
86 #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
87 #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
88 #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
91 /* Graphics reset regs */
92 #define I965_GDRST 0xc0 /* PCI config register */
93 #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
94 #define GRDOM_FULL (0<<2)
95 #define GRDOM_RENDER (1<<2)
96 #define GRDOM_MEDIA (3<<2)
97 #define GRDOM_RESET_ENABLE (1<<0)
99 #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
100 #define GEN6_MBC_SNPCR_SHIFT 21
101 #define GEN6_MBC_SNPCR_MASK (3<<21)
102 #define GEN6_MBC_SNPCR_MAX (0<<21)
103 #define GEN6_MBC_SNPCR_MED (1<<21)
104 #define GEN6_MBC_SNPCR_LOW (2<<21)
105 #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
107 #define GEN6_MBCTL 0x0907c
108 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
109 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
110 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
111 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
112 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
114 #define GEN6_GDRST 0x941c
115 #define GEN6_GRDOM_FULL (1 << 0)
116 #define GEN6_GRDOM_RENDER (1 << 1)
117 #define GEN6_GRDOM_MEDIA (1 << 2)
118 #define GEN6_GRDOM_BLT (1 << 3)
120 #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
121 #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
122 #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
123 #define PP_DIR_DCLV_2G 0xffffffff
125 #define GAM_ECOCHK 0x4090
126 #define ECOCHK_SNB_BIT (1<<10)
127 #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
128 #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
130 #define GAC_ECO_BITS 0x14090
131 #define ECOBITS_PPGTT_CACHE64B (3<<8)
132 #define ECOBITS_PPGTT_CACHE4B (0<<8)
134 #define GAB_CTL 0x24000
135 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
139 #define VGA_ST01_MDA 0x3ba
140 #define VGA_ST01_CGA 0x3da
142 #define VGA_MSR_WRITE 0x3c2
143 #define VGA_MSR_READ 0x3cc
144 #define VGA_MSR_MEM_EN (1<<1)
145 #define VGA_MSR_CGA_MODE (1<<0)
147 #define VGA_SR_INDEX 0x3c4
148 #define VGA_SR_DATA 0x3c5
150 #define VGA_AR_INDEX 0x3c0
151 #define VGA_AR_VID_EN (1<<5)
152 #define VGA_AR_DATA_WRITE 0x3c0
153 #define VGA_AR_DATA_READ 0x3c1
155 #define VGA_GR_INDEX 0x3ce
156 #define VGA_GR_DATA 0x3cf
158 #define VGA_GR_MEM_READ_MODE_SHIFT 3
159 #define VGA_GR_MEM_READ_MODE_PLANE 1
161 #define VGA_GR_MEM_MODE_MASK 0xc
162 #define VGA_GR_MEM_MODE_SHIFT 2
163 #define VGA_GR_MEM_A0000_AFFFF 0
164 #define VGA_GR_MEM_A0000_BFFFF 1
165 #define VGA_GR_MEM_B0000_B7FFF 2
166 #define VGA_GR_MEM_B0000_BFFFF 3
168 #define VGA_DACMASK 0x3c6
169 #define VGA_DACRX 0x3c7
170 #define VGA_DACWX 0x3c8
171 #define VGA_DACDATA 0x3c9
173 #define VGA_CR_INDEX_MDA 0x3b4
174 #define VGA_CR_DATA_MDA 0x3b5
175 #define VGA_CR_INDEX_CGA 0x3d4
176 #define VGA_CR_DATA_CGA 0x3d5
179 * Memory interface instructions used by the kernel
181 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
183 #define MI_NOOP MI_INSTR(0, 0)
184 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
185 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
186 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
187 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
188 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
189 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
190 #define MI_FLUSH MI_INSTR(0x04, 0)
191 #define MI_READ_FLUSH (1 << 0)
192 #define MI_EXE_FLUSH (1 << 1)
193 #define MI_NO_WRITE_FLUSH (1 << 2)
194 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
195 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
196 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
197 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
198 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
199 #define MI_SUSPEND_FLUSH_EN (1<<0)
200 #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
201 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
202 #define MI_OVERLAY_CONTINUE (0x0<<21)
203 #define MI_OVERLAY_ON (0x1<<21)
204 #define MI_OVERLAY_OFF (0x2<<21)
205 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
206 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
207 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
208 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
209 /* IVB has funny definitions for which plane to flip. */
210 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
211 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
212 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
213 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
214 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
215 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
216 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
217 #define MI_ARB_ENABLE (1<<0)
218 #define MI_ARB_DISABLE (0<<0)
220 #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
221 #define MI_MM_SPACE_GTT (1<<8)
222 #define MI_MM_SPACE_PHYSICAL (0<<8)
223 #define MI_SAVE_EXT_STATE_EN (1<<3)
224 #define MI_RESTORE_EXT_STATE_EN (1<<2)
225 #define MI_FORCE_RESTORE (1<<1)
226 #define MI_RESTORE_INHIBIT (1<<0)
227 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
228 #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
229 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
230 #define MI_STORE_DWORD_INDEX_SHIFT 2
231 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
232 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
233 * simply ignores the register load under certain conditions.
234 * - One can actually load arbitrary many arbitrary registers: Simply issue x
235 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
237 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
238 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
239 #define MI_FLUSH_DW_STORE_INDEX (1<<21)
240 #define MI_INVALIDATE_TLB (1<<18)
241 #define MI_FLUSH_DW_OP_STOREDW (1<<14)
242 #define MI_INVALIDATE_BSD (1<<7)
243 #define MI_FLUSH_DW_USE_GTT (1<<2)
244 #define MI_FLUSH_DW_USE_PPGTT (0<<2)
245 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
246 #define MI_BATCH_NON_SECURE (1)
247 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
248 #define MI_BATCH_NON_SECURE_I965 (1<<8)
249 #define MI_BATCH_PPGTT_HSW (1<<8)
250 #define MI_BATCH_NON_SECURE_HSW (1<<13)
251 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
252 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
253 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
254 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
255 #define MI_SEMAPHORE_UPDATE (1<<21)
256 #define MI_SEMAPHORE_COMPARE (1<<20)
257 #define MI_SEMAPHORE_REGISTER (1<<18)
258 #define MI_SEMAPHORE_SYNC_RV (2<<16)
259 #define MI_SEMAPHORE_SYNC_RB (0<<16)
260 #define MI_SEMAPHORE_SYNC_VR (0<<16)
261 #define MI_SEMAPHORE_SYNC_VB (2<<16)
262 #define MI_SEMAPHORE_SYNC_BR (2<<16)
263 #define MI_SEMAPHORE_SYNC_BV (0<<16)
264 #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
266 * 3D instructions used by the kernel
268 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
270 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
271 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
272 #define SC_UPDATE_SCISSOR (0x1<<1)
273 #define SC_ENABLE_MASK (0x1<<0)
274 #define SC_ENABLE (0x1<<0)
275 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
276 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
277 #define SCI_YMIN_MASK (0xffff<<16)
278 #define SCI_XMIN_MASK (0xffff<<0)
279 #define SCI_YMAX_MASK (0xffff<<16)
280 #define SCI_XMAX_MASK (0xffff<<0)
281 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
282 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
283 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
284 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
285 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
286 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
287 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
288 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
289 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
290 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
291 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
292 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
293 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
294 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
295 #define BLT_DEPTH_8 (0<<24)
296 #define BLT_DEPTH_16_565 (1<<24)
297 #define BLT_DEPTH_16_1555 (2<<24)
298 #define BLT_DEPTH_32 (3<<24)
299 #define BLT_ROP_GXCOPY (0xcc<<16)
300 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
301 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
302 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
303 #define ASYNC_FLIP (1<<22)
304 #define DISPLAY_PLANE_A (0<<20)
305 #define DISPLAY_PLANE_B (1<<20)
306 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
307 #define PIPE_CONTROL_CS_STALL (1<<20)
308 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
309 #define PIPE_CONTROL_QW_WRITE (1<<14)
310 #define PIPE_CONTROL_DEPTH_STALL (1<<13)
311 #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
312 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
313 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
314 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
315 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
316 #define PIPE_CONTROL_NOTIFY (1<<8)
317 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
318 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
319 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
320 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
321 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
322 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
328 #define DEBUG_RESET_I830 0x6070
329 #define DEBUG_RESET_FULL (1<<7)
330 #define DEBUG_RESET_RENDER (1<<8)
331 #define DEBUG_RESET_DISPLAY (1<<9)
334 * DPIO - a special bus for various display related registers to hide behind:
335 * 0x800c: m1, m2, n, p1, p2, k dividers
336 * 0x8014: REF and SFR select
337 * 0x8014: N divider, VCO select
338 * 0x801c/3c: core clock bits
339 * 0x8048/68: low pass filter coefficients
340 * 0x8100: fast clock controls
342 #define DPIO_PKT 0x2100
343 #define DPIO_RID (0<<24)
344 #define DPIO_OP_WRITE (1<<16)
345 #define DPIO_OP_READ (0<<16)
346 #define DPIO_PORTID (0x12<<8)
347 #define DPIO_BYTE (0xf<<4)
348 #define DPIO_BUSY (1<<0) /* status only */
349 #define DPIO_DATA 0x2104
350 #define DPIO_REG 0x2108
351 #define DPIO_CTL 0x2110
352 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
353 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
354 #define DPIO_SFR_BYPASS (1<<1)
355 #define DPIO_RESET (1<<0)
357 #define _DPIO_DIV_A 0x800c
358 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
359 #define DPIO_K_SHIFT (24) /* 4 bits */
360 #define DPIO_P1_SHIFT (21) /* 3 bits */
361 #define DPIO_P2_SHIFT (16) /* 5 bits */
362 #define DPIO_N_SHIFT (12) /* 4 bits */
363 #define DPIO_ENABLE_CALIBRATION (1<<11)
364 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */
365 #define DPIO_M2DIV_MASK 0xff
366 #define _DPIO_DIV_B 0x802c
367 #define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
369 #define _DPIO_REFSFR_A 0x8014
370 #define DPIO_REFSEL_OVERRIDE 27
371 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
372 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
373 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
374 #define DPIO_PLL_REFCLK_SEL_MASK 3
375 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
376 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
377 #define _DPIO_REFSFR_B 0x8034
378 #define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
380 #define _DPIO_CORE_CLK_A 0x801c
381 #define _DPIO_CORE_CLK_B 0x803c
382 #define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
384 #define _DPIO_LFP_COEFF_A 0x8048
385 #define _DPIO_LFP_COEFF_B 0x8068
386 #define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
388 #define DPIO_FASTCLK_DISABLE 0x8100
390 #define DPIO_DATA_CHANNEL1 0x8220
391 #define DPIO_DATA_CHANNEL2 0x8420
396 #define FENCE_REG_830_0 0x2000
397 #define FENCE_REG_945_8 0x3000
398 #define I830_FENCE_START_MASK 0x07f80000
399 #define I830_FENCE_TILING_Y_SHIFT 12
400 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
401 #define I830_FENCE_PITCH_SHIFT 4
402 #define I830_FENCE_REG_VALID (1<<0)
403 #define I915_FENCE_MAX_PITCH_VAL 4
404 #define I830_FENCE_MAX_PITCH_VAL 6
405 #define I830_FENCE_MAX_SIZE_VAL (1<<8)
407 #define I915_FENCE_START_MASK 0x0ff00000
408 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
410 #define FENCE_REG_965_0 0x03000
411 #define I965_FENCE_PITCH_SHIFT 2
412 #define I965_FENCE_TILING_Y_SHIFT 1
413 #define I965_FENCE_REG_VALID (1<<0)
414 #define I965_FENCE_MAX_PITCH_VAL 0x0400
416 #define FENCE_REG_SANDYBRIDGE_0 0x100000
417 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
419 /* control register for cpu gtt access */
420 #define TILECTL 0x101000
421 #define TILECTL_SWZCTL (1 << 0)
422 #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
423 #define TILECTL_BACKSNOOP_DIS (1 << 3)
426 * Instruction and interrupt control regs
428 #define PGTBL_ER 0x02024
429 #define RENDER_RING_BASE 0x02000
430 #define BSD_RING_BASE 0x04000
431 #define GEN6_BSD_RING_BASE 0x12000
432 #define BLT_RING_BASE 0x22000
433 #define RING_TAIL(base) ((base)+0x30)
434 #define RING_HEAD(base) ((base)+0x34)
435 #define RING_START(base) ((base)+0x38)
436 #define RING_CTL(base) ((base)+0x3c)
437 #define RING_SYNC_0(base) ((base)+0x40)
438 #define RING_SYNC_1(base) ((base)+0x44)
439 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
440 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
441 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
442 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
443 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
444 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
445 #define RING_MAX_IDLE(base) ((base)+0x54)
446 #define RING_HWS_PGA(base) ((base)+0x80)
447 #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
448 #define ARB_MODE 0x04030
449 #define ARB_MODE_SWIZZLE_SNB (1<<4)
450 #define ARB_MODE_SWIZZLE_IVB (1<<5)
451 #define RENDER_HWS_PGA_GEN7 (0x04080)
452 #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
453 #define DONE_REG 0x40b0
454 #define BSD_HWS_PGA_GEN7 (0x04180)
455 #define BLT_HWS_PGA_GEN7 (0x04280)
456 #define RING_ACTHD(base) ((base)+0x74)
457 #define RING_NOPID(base) ((base)+0x94)
458 #define RING_IMR(base) ((base)+0xa8)
459 #define RING_TIMESTAMP(base) ((base)+0x358)
460 #define TAIL_ADDR 0x001FFFF8
461 #define HEAD_WRAP_COUNT 0xFFE00000
462 #define HEAD_WRAP_ONE 0x00200000
463 #define HEAD_ADDR 0x001FFFFC
464 #define RING_NR_PAGES 0x001FF000
465 #define RING_REPORT_MASK 0x00000006
466 #define RING_REPORT_64K 0x00000002
467 #define RING_REPORT_128K 0x00000004
468 #define RING_NO_REPORT 0x00000000
469 #define RING_VALID_MASK 0x00000001
470 #define RING_VALID 0x00000001
471 #define RING_INVALID 0x00000000
472 #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
473 #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
474 #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
476 #define PRB0_TAIL 0x02030
477 #define PRB0_HEAD 0x02034
478 #define PRB0_START 0x02038
479 #define PRB0_CTL 0x0203c
480 #define PRB1_TAIL 0x02040 /* 915+ only */
481 #define PRB1_HEAD 0x02044 /* 915+ only */
482 #define PRB1_START 0x02048 /* 915+ only */
483 #define PRB1_CTL 0x0204c /* 915+ only */
485 #define IPEIR_I965 0x02064
486 #define IPEHR_I965 0x02068
487 #define INSTDONE_I965 0x0206c
488 #define GEN7_INSTDONE_1 0x0206c
489 #define GEN7_SC_INSTDONE 0x07100
490 #define GEN7_SAMPLER_INSTDONE 0x0e160
491 #define GEN7_ROW_INSTDONE 0x0e164
492 #define I915_NUM_INSTDONE_REG 4
493 #define RING_IPEIR(base) ((base)+0x64)
494 #define RING_IPEHR(base) ((base)+0x68)
495 #define RING_INSTDONE(base) ((base)+0x6c)
496 #define RING_INSTPS(base) ((base)+0x70)
497 #define RING_DMA_FADD(base) ((base)+0x78)
498 #define RING_INSTPM(base) ((base)+0xc0)
499 #define INSTPS 0x02070 /* 965+ only */
500 #define INSTDONE1 0x0207c /* 965+ only */
501 #define ACTHD_I965 0x02074
502 #define HWS_PGA 0x02080
503 #define HWS_ADDRESS_MASK 0xfffff000
504 #define HWS_START_ADDRESS_SHIFT 4
505 #define PWRCTXA 0x2088 /* 965GM+ only */
506 #define PWRCTX_EN (1<<0)
507 #define IPEIR 0x02088
508 #define IPEHR 0x0208c
509 #define INSTDONE 0x02090
510 #define NOPID 0x02094
511 #define HWSTAM 0x02098
512 #define DMA_FADD_I8XX 0x020d0
514 #define ERROR_GEN6 0x040a0
515 #define GEN7_ERR_INT 0x44040
516 #define ERR_INT_MMIO_UNCLAIMED (1<<13)
518 #define DERRMR 0x44050
520 /* GM45+ chicken bits -- debug workaround bits that may be required
521 * for various sorts of correct behavior. The top 16 bits of each are
522 * the enables for writing to the corresponding low bit.
524 #define _3D_CHICKEN 0x02084
525 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
526 #define _3D_CHICKEN2 0x0208c
527 /* Disables pipelining of read flushes past the SF-WIZ interface.
528 * Required on all Ironlake steppings according to the B-Spec, but the
529 * particular danger of not doing so is not specified.
531 # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
532 #define _3D_CHICKEN3 0x02090
533 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
534 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
536 #define MI_MODE 0x0209c
537 # define VS_TIMER_DISPATCH (1 << 6)
538 # define MI_FLUSH_ENABLE (1 << 12)
539 # define ASYNC_FLIP_PERF_DISABLE (1 << 14)
541 #define GEN6_GT_MODE 0x20d0
542 #define GEN6_GT_MODE_HI (1 << 9)
543 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
545 #define GFX_MODE 0x02520
546 #define GFX_MODE_GEN7 0x0229c
547 #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
548 #define GFX_RUN_LIST_ENABLE (1<<15)
549 #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
550 #define GFX_SURFACE_FAULT_ENABLE (1<<12)
551 #define GFX_REPLAY_MODE (1<<11)
552 #define GFX_PSMI_GRANULARITY (1<<10)
553 #define GFX_PPGTT_ENABLE (1<<9)
555 #define VLV_DISPLAY_BASE 0x180000
557 #define SCPD0 0x0209c /* 915+ only */
562 #define VLV_GUNIT_CLOCK_GATE 0x182060
563 #define GCFG_DIS (1<<8)
564 #define VLV_IIR_RW 0x182084
565 #define VLV_IER 0x1820a0
566 #define VLV_IIR 0x1820a4
567 #define VLV_IMR 0x1820a8
568 #define VLV_ISR 0x1820ac
569 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
570 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
571 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
572 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
573 #define I915_HWB_OOM_INTERRUPT (1<<13)
574 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
575 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
576 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
577 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
578 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
579 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
580 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
581 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
582 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
583 #define I915_DEBUG_INTERRUPT (1<<2)
584 #define I915_USER_INTERRUPT (1<<1)
585 #define I915_ASLE_INTERRUPT (1<<0)
586 #define I915_BSD_USER_INTERRUPT (1<<25)
590 #define GM45_ERROR_PAGE_TABLE (1<<5)
591 #define GM45_ERROR_MEM_PRIV (1<<4)
592 #define I915_ERROR_PAGE_TABLE (1<<4)
593 #define GM45_ERROR_CP_PRIV (1<<3)
594 #define I915_ERROR_MEMORY_REFRESH (1<<1)
595 #define I915_ERROR_INSTRUCTION (1<<0)
596 #define INSTPM 0x020c0
597 #define INSTPM_SELF_EN (1<<12) /* 915GM only */
598 #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
599 will not assert AGPBUSY# and will only
600 be delivered when out of C3. */
601 #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
602 #define ACTHD 0x020c8
603 #define FW_BLC 0x020d8
604 #define FW_BLC2 0x020dc
605 #define FW_BLC_SELF 0x020e0 /* 915+ only */
606 #define FW_BLC_SELF_EN_MASK (1<<31)
607 #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
608 #define FW_BLC_SELF_EN (1<<15) /* 945 only */
609 #define MM_BURST_LENGTH 0x00700000
610 #define MM_FIFO_WATERMARK 0x0001F000
611 #define LM_BURST_LENGTH 0x00000700
612 #define LM_FIFO_WATERMARK 0x0000001F
613 #define MI_ARB_STATE 0x020e4 /* 915+ only */
615 /* Make render/texture TLB fetches lower priorty than associated data
616 * fetches. This is not turned on by default
618 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
620 /* Isoch request wait on GTT enable (Display A/B/C streams).
621 * Make isoch requests stall on the TLB update. May cause
622 * display underruns (test mode only)
624 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
626 /* Block grant count for isoch requests when block count is
627 * set to a finite value.
629 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
630 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
631 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
632 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
633 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
635 /* Enable render writes to complete in C2/C3/C4 power states.
636 * If this isn't enabled, render writes are prevented in low
637 * power states. That seems bad to me.
639 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
641 /* This acknowledges an async flip immediately instead
642 * of waiting for 2TLB fetches.
644 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
646 /* Enables non-sequential data reads through arbiter
648 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
650 /* Disable FSB snooping of cacheable write cycles from binner/render
653 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
655 /* Arbiter time slice for non-isoch streams */
656 #define MI_ARB_TIME_SLICE_MASK (7 << 5)
657 #define MI_ARB_TIME_SLICE_1 (0 << 5)
658 #define MI_ARB_TIME_SLICE_2 (1 << 5)
659 #define MI_ARB_TIME_SLICE_4 (2 << 5)
660 #define MI_ARB_TIME_SLICE_6 (3 << 5)
661 #define MI_ARB_TIME_SLICE_8 (4 << 5)
662 #define MI_ARB_TIME_SLICE_10 (5 << 5)
663 #define MI_ARB_TIME_SLICE_14 (6 << 5)
664 #define MI_ARB_TIME_SLICE_16 (7 << 5)
666 /* Low priority grace period page size */
667 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
668 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
670 /* Disable display A/B trickle feed */
671 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
673 /* Set display plane priority */
674 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
675 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
677 #define CACHE_MODE_0 0x02120 /* 915+ only */
678 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
679 #define CM0_IZ_OPT_DISABLE (1<<6)
680 #define CM0_ZR_OPT_DISABLE (1<<5)
681 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
682 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
683 #define CM0_COLOR_EVICT_DISABLE (1<<3)
684 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
685 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
686 #define BB_ADDR 0x02140 /* 8 bytes */
687 #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
688 #define GFX_FLSH_CNTL_GEN6 0x101008
689 #define GFX_FLSH_CNTL_EN (1<<0)
690 #define ECOSKPD 0x021d0
691 #define ECO_GATING_CX_ONLY (1<<3)
692 #define ECO_FLIP_DONE (1<<0)
694 #define CACHE_MODE_1 0x7004 /* IVB+ */
695 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
697 /* GEN6 interrupt control
698 * Note that the per-ring interrupt bits do alias with the global interrupt bits
700 #define GEN6_RENDER_HWSTAM 0x2098
701 #define GEN6_RENDER_IMR 0x20a8
702 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
703 #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
704 #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
705 #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
706 #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
707 #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
708 #define GEN6_RENDER_SYNC_STATUS (1 << 2)
709 #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
710 #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
712 #define GEN6_BLITTER_HWSTAM 0x22098
713 #define GEN6_BLITTER_IMR 0x220a8
714 #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
715 #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
716 #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
717 #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
719 #define GEN6_BLITTER_ECOSKPD 0x221d0
720 #define GEN6_BLITTER_LOCK_SHIFT 16
721 #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
723 #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
724 #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
725 #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
726 #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
727 #define GEN6_BSD_GO_INDICATOR (1 << 4)
729 #define GEN6_BSD_HWSTAM 0x12098
730 #define GEN6_BSD_IMR 0x120a8
731 #define GEN6_BSD_USER_INTERRUPT (1 << 12)
733 #define GEN6_BSD_RNCID 0x12198
735 #define GEN7_FF_THREAD_MODE 0x20a0
736 #define GEN7_FF_SCHED_MASK 0x0077070
737 #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
738 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
739 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
740 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
741 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
742 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
743 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
744 #define GEN7_FF_VS_SCHED_HW (0x0<<12)
745 #define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
746 #define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
747 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
748 #define GEN7_FF_DS_SCHED_HW (0x0<<4)
751 * Framebuffer compression (915+ only)
754 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
755 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
756 #define FBC_CONTROL 0x03208
757 #define FBC_CTL_EN (1<<31)
758 #define FBC_CTL_PERIODIC (1<<30)
759 #define FBC_CTL_INTERVAL_SHIFT (16)
760 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
761 #define FBC_CTL_C3_IDLE (1<<13)
762 #define FBC_CTL_STRIDE_SHIFT (5)
763 #define FBC_CTL_FENCENO (1<<0)
764 #define FBC_COMMAND 0x0320c
765 #define FBC_CMD_COMPRESS (1<<0)
766 #define FBC_STATUS 0x03210
767 #define FBC_STAT_COMPRESSING (1<<31)
768 #define FBC_STAT_COMPRESSED (1<<30)
769 #define FBC_STAT_MODIFIED (1<<29)
770 #define FBC_STAT_CURRENT_LINE (1<<0)
771 #define FBC_CONTROL2 0x03214
772 #define FBC_CTL_FENCE_DBL (0<<4)
773 #define FBC_CTL_IDLE_IMM (0<<2)
774 #define FBC_CTL_IDLE_FULL (1<<2)
775 #define FBC_CTL_IDLE_LINE (2<<2)
776 #define FBC_CTL_IDLE_DEBUG (3<<2)
777 #define FBC_CTL_CPU_FENCE (1<<1)
778 #define FBC_CTL_PLANEA (0<<0)
779 #define FBC_CTL_PLANEB (1<<0)
780 #define FBC_FENCE_OFF 0x0321b
781 #define FBC_TAG 0x03300
783 #define FBC_LL_SIZE (1536)
785 /* Framebuffer compression for GM45+ */
786 #define DPFC_CB_BASE 0x3200
787 #define DPFC_CONTROL 0x3208
788 #define DPFC_CTL_EN (1<<31)
789 #define DPFC_CTL_PLANEA (0<<30)
790 #define DPFC_CTL_PLANEB (1<<30)
791 #define DPFC_CTL_FENCE_EN (1<<29)
792 #define DPFC_CTL_PERSISTENT_MODE (1<<25)
793 #define DPFC_SR_EN (1<<10)
794 #define DPFC_CTL_LIMIT_1X (0<<6)
795 #define DPFC_CTL_LIMIT_2X (1<<6)
796 #define DPFC_CTL_LIMIT_4X (2<<6)
797 #define DPFC_RECOMP_CTL 0x320c
798 #define DPFC_RECOMP_STALL_EN (1<<27)
799 #define DPFC_RECOMP_STALL_WM_SHIFT (16)
800 #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
801 #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
802 #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
803 #define DPFC_STATUS 0x3210
804 #define DPFC_INVAL_SEG_SHIFT (16)
805 #define DPFC_INVAL_SEG_MASK (0x07ff0000)
806 #define DPFC_COMP_SEG_SHIFT (0)
807 #define DPFC_COMP_SEG_MASK (0x000003ff)
808 #define DPFC_STATUS2 0x3214
809 #define DPFC_FENCE_YOFF 0x3218
810 #define DPFC_CHICKEN 0x3224
811 #define DPFC_HT_MODIFY (1<<31)
813 /* Framebuffer compression for Ironlake */
814 #define ILK_DPFC_CB_BASE 0x43200
815 #define ILK_DPFC_CONTROL 0x43208
816 /* The bit 28-8 is reserved */
817 #define DPFC_RESERVED (0x1FFFFF00)
818 #define ILK_DPFC_RECOMP_CTL 0x4320c
819 #define ILK_DPFC_STATUS 0x43210
820 #define ILK_DPFC_FENCE_YOFF 0x43218
821 #define ILK_DPFC_CHICKEN 0x43224
822 #define ILK_FBC_RT_BASE 0x2128
823 #define ILK_FBC_RT_VALID (1<<0)
825 #define ILK_DISPLAY_CHICKEN1 0x42000
826 #define ILK_FBCQ_DIS (1<<22)
827 #define ILK_PABSTRETCH_DIS (1<<21)
831 * Framebuffer compression for Sandybridge
833 * The following two registers are of type GTTMMADR
835 #define SNB_DPFC_CTL_SA 0x100100
836 #define SNB_CPU_FENCE_ENABLE (1<<29)
837 #define DPFC_CPU_FENCE_OFFSET 0x100104
851 # define GPIO_CLOCK_DIR_MASK (1 << 0)
852 # define GPIO_CLOCK_DIR_IN (0 << 1)
853 # define GPIO_CLOCK_DIR_OUT (1 << 1)
854 # define GPIO_CLOCK_VAL_MASK (1 << 2)
855 # define GPIO_CLOCK_VAL_OUT (1 << 3)
856 # define GPIO_CLOCK_VAL_IN (1 << 4)
857 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
858 # define GPIO_DATA_DIR_MASK (1 << 8)
859 # define GPIO_DATA_DIR_IN (0 << 9)
860 # define GPIO_DATA_DIR_OUT (1 << 9)
861 # define GPIO_DATA_VAL_MASK (1 << 10)
862 # define GPIO_DATA_VAL_OUT (1 << 11)
863 # define GPIO_DATA_VAL_IN (1 << 12)
864 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
866 #define GMBUS0 0x5100 /* clock/port select */
867 #define GMBUS_RATE_100KHZ (0<<8)
868 #define GMBUS_RATE_50KHZ (1<<8)
869 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
870 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
871 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
872 #define GMBUS_PORT_DISABLED 0
873 #define GMBUS_PORT_SSC 1
874 #define GMBUS_PORT_VGADDC 2
875 #define GMBUS_PORT_PANEL 3
876 #define GMBUS_PORT_DPC 4 /* HDMIC */
877 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
878 #define GMBUS_PORT_DPD 6 /* HDMID */
879 #define GMBUS_PORT_RESERVED 7 /* 7 reserved */
880 #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
881 #define GMBUS1 0x5104 /* command/status */
882 #define GMBUS_SW_CLR_INT (1<<31)
883 #define GMBUS_SW_RDY (1<<30)
884 #define GMBUS_ENT (1<<29) /* enable timeout */
885 #define GMBUS_CYCLE_NONE (0<<25)
886 #define GMBUS_CYCLE_WAIT (1<<25)
887 #define GMBUS_CYCLE_INDEX (2<<25)
888 #define GMBUS_CYCLE_STOP (4<<25)
889 #define GMBUS_BYTE_COUNT_SHIFT 16
890 #define GMBUS_SLAVE_INDEX_SHIFT 8
891 #define GMBUS_SLAVE_ADDR_SHIFT 1
892 #define GMBUS_SLAVE_READ (1<<0)
893 #define GMBUS_SLAVE_WRITE (0<<0)
894 #define GMBUS2 0x5108 /* status */
895 #define GMBUS_INUSE (1<<15)
896 #define GMBUS_HW_WAIT_PHASE (1<<14)
897 #define GMBUS_STALL_TIMEOUT (1<<13)
898 #define GMBUS_INT (1<<12)
899 #define GMBUS_HW_RDY (1<<11)
900 #define GMBUS_SATOER (1<<10)
901 #define GMBUS_ACTIVE (1<<9)
902 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
903 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
904 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
905 #define GMBUS_NAK_EN (1<<3)
906 #define GMBUS_IDLE_EN (1<<2)
907 #define GMBUS_HW_WAIT_EN (1<<1)
908 #define GMBUS_HW_RDY_EN (1<<0)
909 #define GMBUS5 0x5120 /* byte index */
910 #define GMBUS_2BYTE_INDEX_EN (1<<31)
913 * Clock control & power management
918 #define VGA_PD 0x6010
919 #define VGA0_PD_P2_DIV_4 (1 << 7)
920 #define VGA0_PD_P1_DIV_2 (1 << 5)
921 #define VGA0_PD_P1_SHIFT 0
922 #define VGA0_PD_P1_MASK (0x1f << 0)
923 #define VGA1_PD_P2_DIV_4 (1 << 15)
924 #define VGA1_PD_P1_DIV_2 (1 << 13)
925 #define VGA1_PD_P1_SHIFT 8
926 #define VGA1_PD_P1_MASK (0x1f << 8)
927 #define _DPLL_A 0x06014
928 #define _DPLL_B 0x06018
929 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
930 #define DPLL_VCO_ENABLE (1 << 31)
931 #define DPLL_DVO_HIGH_SPEED (1 << 30)
932 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
933 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
934 #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
935 #define DPLL_VGA_MODE_DIS (1 << 28)
936 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
937 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
938 #define DPLL_MODE_MASK (3 << 26)
939 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
940 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
941 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
942 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
943 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
944 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
945 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
946 #define DPLL_LOCK_VLV (1<<15)
947 #define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
949 #define SRX_INDEX 0x3c4
950 #define SRX_DATA 0x3c5
952 #define SR01_SCREEN_OFF (1<<5)
955 #define PPCR_ON (1<<0)
958 #define DVOB_ON (1<<31)
960 #define DVOC_ON (1<<31)
962 #define LVDS_ON (1<<31)
964 /* Scratch pad debug 0 reg:
966 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
968 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
969 * this field (only one bit may be set).
971 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
972 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
973 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
974 /* i830, required in DVO non-gang */
975 #define PLL_P2_DIVIDE_BY_4 (1 << 23)
976 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
977 #define PLL_REF_INPUT_DREFCLK (0 << 13)
978 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
979 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
980 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
981 #define PLL_REF_INPUT_MASK (3 << 13)
982 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
984 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
985 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
986 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
987 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
988 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
991 * Parallel to Serial Load Pulse phase selection.
992 * Selects the phase for the 10X DPLL clock for the PCIe
993 * digital display port. The range is 4 to 13; 10 or more
994 * is just a flip delay. The default is 6
996 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
997 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
999 * SDVO multiplier for 945G/GM. Not used on 965.
1001 #define SDVO_MULTIPLIER_MASK 0x000000ff
1002 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
1003 #define SDVO_MULTIPLIER_SHIFT_VGA 0
1004 #define _DPLL_A_MD 0x0601c /* 965+ only */
1006 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1008 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1010 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1011 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
1012 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1013 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1014 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1016 * SDVO/UDI pixel multiplier.
1018 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1019 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1020 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1021 * dummy bytes in the datastream at an increased clock rate, with both sides of
1022 * the link knowing how many bytes are fill.
1024 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1025 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1026 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1027 * through an SDVO command.
1029 * This register field has values of multiplication factor minus 1, with
1030 * a maximum multiplier of 5 for SDVO.
1032 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1033 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1035 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1036 * This best be set to the default value (3) or the CRT won't work. No,
1037 * I don't entirely understand what this does...
1039 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1040 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1041 #define _DPLL_B_MD 0x06020 /* 965+ only */
1042 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1044 #define _FPA0 0x06040
1045 #define _FPA1 0x06044
1046 #define _FPB0 0x06048
1047 #define _FPB1 0x0604c
1048 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1049 #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1050 #define FP_N_DIV_MASK 0x003f0000
1051 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1052 #define FP_N_DIV_SHIFT 16
1053 #define FP_M1_DIV_MASK 0x00003f00
1054 #define FP_M1_DIV_SHIFT 8
1055 #define FP_M2_DIV_MASK 0x0000003f
1056 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1057 #define FP_M2_DIV_SHIFT 0
1058 #define DPLL_TEST 0x606c
1059 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1060 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1061 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1062 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1063 #define DPLLB_TEST_N_BYPASS (1 << 19)
1064 #define DPLLB_TEST_M_BYPASS (1 << 18)
1065 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1066 #define DPLLA_TEST_N_BYPASS (1 << 3)
1067 #define DPLLA_TEST_M_BYPASS (1 << 2)
1068 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1069 #define D_STATE 0x6104
1070 #define DSTATE_GFX_RESET_I830 (1<<6)
1071 #define DSTATE_PLL_D3_OFF (1<<3)
1072 #define DSTATE_GFX_CLOCK_GATING (1<<1)
1073 #define DSTATE_DOT_CLOCK_GATING (1<<0)
1074 #define DSPCLK_GATE_D 0x6200
1075 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1076 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1077 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1078 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1079 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1080 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1081 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1082 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1083 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1084 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1085 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1086 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1087 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1088 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1089 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1090 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1091 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1092 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1093 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1094 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1095 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1096 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1097 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1098 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1099 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1100 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1101 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1102 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1104 * This bit must be set on the 830 to prevent hangs when turning off the
1107 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1108 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1109 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1110 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1111 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1113 #define RENCLK_GATE_D1 0x6204
1114 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1115 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1116 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1117 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1118 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1119 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1120 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1121 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1122 # define MAG_CLOCK_GATE_DISABLE (1 << 5)
1123 /** This bit must be unset on 855,865 */
1124 # define MECI_CLOCK_GATE_DISABLE (1 << 4)
1125 # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1126 # define MEC_CLOCK_GATE_DISABLE (1 << 2)
1127 # define MECO_CLOCK_GATE_DISABLE (1 << 1)
1128 /** This bit must be set on 855,865. */
1129 # define SV_CLOCK_GATE_DISABLE (1 << 0)
1130 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1131 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1132 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1133 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1134 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1135 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1136 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1137 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1138 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1139 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1140 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1141 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1142 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1143 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1144 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1145 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1146 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1148 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1149 /** This bit must always be set on 965G/965GM */
1150 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1151 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1152 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1153 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1154 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1155 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1156 /** This bit must always be set on 965G */
1157 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1158 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1159 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1160 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1161 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1162 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1163 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1164 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1165 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1166 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1167 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1168 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1169 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1170 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1171 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1172 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1173 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1174 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1175 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1177 #define RENCLK_GATE_D2 0x6208
1178 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1179 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1180 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1181 #define RAMCLK_GATE_D 0x6210 /* CRL only */
1182 #define DEUC 0x6214 /* CRL only */
1184 #define FW_BLC_SELF_VLV 0x6500
1185 #define FW_CSPWRDWNEN (1<<15)
1191 #define _PALETTE_A 0x0a000
1192 #define _PALETTE_B 0x0a800
1193 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
1195 /* MCH MMIO space */
1200 * This mirrors the MCHBAR MMIO space whose location is determined by
1201 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1202 * every way. It is not accessible from the CP register read instructions.
1205 #define MCHBAR_MIRROR_BASE 0x10000
1207 #define MCHBAR_MIRROR_BASE_SNB 0x140000
1209 /** 915-945 and GM965 MCH register controlling DRAM channel access */
1211 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1212 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1213 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1214 #define DCC_ADDRESSING_MODE_MASK (3 << 0)
1215 #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1216 #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1218 /** Pineview MCH register contains DDR3 setting */
1219 #define CSHRDDR3CTL 0x101a8
1220 #define CSHRDDR3CTL_DDR3 (1 << 2)
1222 /** 965 MCH register controlling DRAM channel configuration */
1223 #define C0DRB3 0x10206
1224 #define C1DRB3 0x10606
1226 /** snb MCH registers for reading the DRAM channel configuration */
1227 #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1228 #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1229 #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1230 #define MAD_DIMM_ECC_MASK (0x3 << 24)
1231 #define MAD_DIMM_ECC_OFF (0x0 << 24)
1232 #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1233 #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1234 #define MAD_DIMM_ECC_ON (0x3 << 24)
1235 #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1236 #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1237 #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1238 #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1239 #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1240 #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1241 #define MAD_DIMM_A_SELECT (0x1 << 16)
1242 /* DIMM sizes are in multiples of 256mb. */
1243 #define MAD_DIMM_B_SIZE_SHIFT 8
1244 #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1245 #define MAD_DIMM_A_SIZE_SHIFT 0
1246 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1249 /* Clocking configuration register */
1250 #define CLKCFG 0x10c00
1251 #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1252 #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1253 #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1254 #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1255 #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1256 #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1257 /* Note, below two are guess */
1258 #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1259 #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1260 #define CLKCFG_FSB_MASK (7 << 0)
1261 #define CLKCFG_MEM_533 (1 << 4)
1262 #define CLKCFG_MEM_667 (2 << 4)
1263 #define CLKCFG_MEM_800 (3 << 4)
1264 #define CLKCFG_MEM_MASK (7 << 4)
1266 #define TSC1 0x11001
1268 #define I915_TR1 0x11006
1269 #define TSFS 0x11020
1270 #define TSFS_SLOPE_MASK 0x0000ff00
1271 #define TSFS_SLOPE_SHIFT 8
1272 #define TSFS_INTR_MASK 0x000000ff
1274 #define CRSTANDVID 0x11100
1275 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1276 #define PXVFREQ_PX_MASK 0x7f000000
1277 #define PXVFREQ_PX_SHIFT 24
1278 #define VIDFREQ_BASE 0x11110
1279 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1280 #define VIDFREQ2 0x11114
1281 #define VIDFREQ3 0x11118
1282 #define VIDFREQ4 0x1111c
1283 #define VIDFREQ_P0_MASK 0x1f000000
1284 #define VIDFREQ_P0_SHIFT 24
1285 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1286 #define VIDFREQ_P0_CSCLK_SHIFT 20
1287 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1288 #define VIDFREQ_P0_CRCLK_SHIFT 16
1289 #define VIDFREQ_P1_MASK 0x00001f00
1290 #define VIDFREQ_P1_SHIFT 8
1291 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1292 #define VIDFREQ_P1_CSCLK_SHIFT 4
1293 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1294 #define INTTOEXT_BASE_ILK 0x11300
1295 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1296 #define INTTOEXT_MAP3_SHIFT 24
1297 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1298 #define INTTOEXT_MAP2_SHIFT 16
1299 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1300 #define INTTOEXT_MAP1_SHIFT 8
1301 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1302 #define INTTOEXT_MAP0_SHIFT 0
1303 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1304 #define MEMSWCTL 0x11170 /* Ironlake only */
1305 #define MEMCTL_CMD_MASK 0xe000
1306 #define MEMCTL_CMD_SHIFT 13
1307 #define MEMCTL_CMD_RCLK_OFF 0
1308 #define MEMCTL_CMD_RCLK_ON 1
1309 #define MEMCTL_CMD_CHFREQ 2
1310 #define MEMCTL_CMD_CHVID 3
1311 #define MEMCTL_CMD_VMMOFF 4
1312 #define MEMCTL_CMD_VMMON 5
1313 #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1314 when command complete */
1315 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1316 #define MEMCTL_FREQ_SHIFT 8
1317 #define MEMCTL_SFCAVM (1<<7)
1318 #define MEMCTL_TGT_VID_MASK 0x007f
1319 #define MEMIHYST 0x1117c
1320 #define MEMINTREN 0x11180 /* 16 bits */
1321 #define MEMINT_RSEXIT_EN (1<<8)
1322 #define MEMINT_CX_SUPR_EN (1<<7)
1323 #define MEMINT_CONT_BUSY_EN (1<<6)
1324 #define MEMINT_AVG_BUSY_EN (1<<5)
1325 #define MEMINT_EVAL_CHG_EN (1<<4)
1326 #define MEMINT_MON_IDLE_EN (1<<3)
1327 #define MEMINT_UP_EVAL_EN (1<<2)
1328 #define MEMINT_DOWN_EVAL_EN (1<<1)
1329 #define MEMINT_SW_CMD_EN (1<<0)
1330 #define MEMINTRSTR 0x11182 /* 16 bits */
1331 #define MEM_RSEXIT_MASK 0xc000
1332 #define MEM_RSEXIT_SHIFT 14
1333 #define MEM_CONT_BUSY_MASK 0x3000
1334 #define MEM_CONT_BUSY_SHIFT 12
1335 #define MEM_AVG_BUSY_MASK 0x0c00
1336 #define MEM_AVG_BUSY_SHIFT 10
1337 #define MEM_EVAL_CHG_MASK 0x0300
1338 #define MEM_EVAL_BUSY_SHIFT 8
1339 #define MEM_MON_IDLE_MASK 0x00c0
1340 #define MEM_MON_IDLE_SHIFT 6
1341 #define MEM_UP_EVAL_MASK 0x0030
1342 #define MEM_UP_EVAL_SHIFT 4
1343 #define MEM_DOWN_EVAL_MASK 0x000c
1344 #define MEM_DOWN_EVAL_SHIFT 2
1345 #define MEM_SW_CMD_MASK 0x0003
1346 #define MEM_INT_STEER_GFX 0
1347 #define MEM_INT_STEER_CMR 1
1348 #define MEM_INT_STEER_SMI 2
1349 #define MEM_INT_STEER_SCI 3
1350 #define MEMINTRSTS 0x11184
1351 #define MEMINT_RSEXIT (1<<7)
1352 #define MEMINT_CONT_BUSY (1<<6)
1353 #define MEMINT_AVG_BUSY (1<<5)
1354 #define MEMINT_EVAL_CHG (1<<4)
1355 #define MEMINT_MON_IDLE (1<<3)
1356 #define MEMINT_UP_EVAL (1<<2)
1357 #define MEMINT_DOWN_EVAL (1<<1)
1358 #define MEMINT_SW_CMD (1<<0)
1359 #define MEMMODECTL 0x11190
1360 #define MEMMODE_BOOST_EN (1<<31)
1361 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1362 #define MEMMODE_BOOST_FREQ_SHIFT 24
1363 #define MEMMODE_IDLE_MODE_MASK 0x00030000
1364 #define MEMMODE_IDLE_MODE_SHIFT 16
1365 #define MEMMODE_IDLE_MODE_EVAL 0
1366 #define MEMMODE_IDLE_MODE_CONT 1
1367 #define MEMMODE_HWIDLE_EN (1<<15)
1368 #define MEMMODE_SWMODE_EN (1<<14)
1369 #define MEMMODE_RCLK_GATE (1<<13)
1370 #define MEMMODE_HW_UPDATE (1<<12)
1371 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1372 #define MEMMODE_FSTART_SHIFT 8
1373 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1374 #define MEMMODE_FMAX_SHIFT 4
1375 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1376 #define RCBMAXAVG 0x1119c
1377 #define MEMSWCTL2 0x1119e /* Cantiga only */
1378 #define SWMEMCMD_RENDER_OFF (0 << 13)
1379 #define SWMEMCMD_RENDER_ON (1 << 13)
1380 #define SWMEMCMD_SWFREQ (2 << 13)
1381 #define SWMEMCMD_TARVID (3 << 13)
1382 #define SWMEMCMD_VRM_OFF (4 << 13)
1383 #define SWMEMCMD_VRM_ON (5 << 13)
1384 #define CMDSTS (1<<12)
1385 #define SFCAVM (1<<11)
1386 #define SWFREQ_MASK 0x0380 /* P0-7 */
1387 #define SWFREQ_SHIFT 7
1388 #define TARVID_MASK 0x001f
1389 #define MEMSTAT_CTG 0x111a0
1390 #define RCBMINAVG 0x111a0
1391 #define RCUPEI 0x111b0
1392 #define RCDNEI 0x111b4
1393 #define RSTDBYCTL 0x111b8
1394 #define RS1EN (1<<31)
1395 #define RS2EN (1<<30)
1396 #define RS3EN (1<<29)
1397 #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1398 #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1399 #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1400 #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1401 #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1402 #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1403 #define RSX_STATUS_MASK (7<<20)
1404 #define RSX_STATUS_ON (0<<20)
1405 #define RSX_STATUS_RC1 (1<<20)
1406 #define RSX_STATUS_RC1E (2<<20)
1407 #define RSX_STATUS_RS1 (3<<20)
1408 #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1409 #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1410 #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1411 #define RSX_STATUS_RSVD2 (7<<20)
1412 #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1413 #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1414 #define JRSC (1<<17) /* rsx coupled to cpu c-state */
1415 #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1416 #define RS1CONTSAV_MASK (3<<14)
1417 #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1418 #define RS1CONTSAV_RSVD (1<<14)
1419 #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1420 #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1421 #define NORMSLEXLAT_MASK (3<<12)
1422 #define SLOW_RS123 (0<<12)
1423 #define SLOW_RS23 (1<<12)
1424 #define SLOW_RS3 (2<<12)
1425 #define NORMAL_RS123 (3<<12)
1426 #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1427 #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1428 #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1429 #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1430 #define RS_CSTATE_MASK (3<<4)
1431 #define RS_CSTATE_C367_RS1 (0<<4)
1432 #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1433 #define RS_CSTATE_RSVD (2<<4)
1434 #define RS_CSTATE_C367_RS2 (3<<4)
1435 #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1436 #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1437 #define VIDCTL 0x111c0
1438 #define VIDSTS 0x111c8
1439 #define VIDSTART 0x111cc /* 8 bits */
1440 #define MEMSTAT_ILK 0x111f8
1441 #define MEMSTAT_VID_MASK 0x7f00
1442 #define MEMSTAT_VID_SHIFT 8
1443 #define MEMSTAT_PSTATE_MASK 0x00f8
1444 #define MEMSTAT_PSTATE_SHIFT 3
1445 #define MEMSTAT_MON_ACTV (1<<2)
1446 #define MEMSTAT_SRC_CTL_MASK 0x0003
1447 #define MEMSTAT_SRC_CTL_CORE 0
1448 #define MEMSTAT_SRC_CTL_TRB 1
1449 #define MEMSTAT_SRC_CTL_THM 2
1450 #define MEMSTAT_SRC_CTL_STDBY 3
1451 #define RCPREVBSYTUPAVG 0x113b8
1452 #define RCPREVBSYTDNAVG 0x113bc
1453 #define PMMISC 0x11214
1454 #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1455 #define SDEW 0x1124c
1456 #define CSIEW0 0x11250
1457 #define CSIEW1 0x11254
1458 #define CSIEW2 0x11258
1461 #define MCHAFE 0x112c0
1462 #define CSIEC 0x112e0
1463 #define DMIEC 0x112e4
1464 #define DDREC 0x112e8
1465 #define PEG0EC 0x112ec
1466 #define PEG1EC 0x112f0
1467 #define GFXEC 0x112f4
1468 #define RPPREVBSYTUPAVG 0x113b8
1469 #define RPPREVBSYTDNAVG 0x113bc
1471 #define ECR_GPFE (1<<31)
1472 #define ECR_IMONE (1<<30)
1473 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1474 #define OGW0 0x11608
1475 #define OGW1 0x1160c
1485 #define PXWL 0x11680
1486 #define LCFUSE02 0x116c0
1487 #define LCFUSE_HIV_MASK 0x000000ff
1488 #define CSIPLL0 0x12c10
1489 #define DDRMPLL1 0X12c20
1490 #define PEG_BAND_GAP_DATA 0x14d68
1492 #define GEN6_GT_THREAD_STATUS_REG 0x13805c
1493 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1494 #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1496 #define GEN6_GT_PERF_STATUS 0x145948
1497 #define GEN6_RP_STATE_LIMITS 0x145994
1498 #define GEN6_RP_STATE_CAP 0x145998
1501 * Logical Context regs
1504 #define CCID_EN (1<<0)
1505 #define CXT_SIZE 0x21a0
1506 #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1507 #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1508 #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1509 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1510 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1511 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_POWER_SIZE(cxt_reg) + \
1512 GEN6_CXT_RING_SIZE(cxt_reg) + \
1513 GEN6_CXT_RENDER_SIZE(cxt_reg) + \
1514 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1515 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1516 #define GEN7_CXT_SIZE 0x21a8
1517 #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1518 #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1519 #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1520 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1521 #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1522 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1523 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_POWER_SIZE(ctx_reg) + \
1524 GEN7_CXT_RING_SIZE(ctx_reg) + \
1525 GEN7_CXT_RENDER_SIZE(ctx_reg) + \
1526 GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1527 GEN7_CXT_GT1_SIZE(ctx_reg) + \
1528 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1529 #define HSW_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 26) & 0x3f)
1530 #define HSW_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 23) & 0x7)
1531 #define HSW_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 15) & 0xff)
1532 #define HSW_CXT_TOTAL_SIZE(ctx_reg) (HSW_CXT_POWER_SIZE(ctx_reg) + \
1533 HSW_CXT_RING_SIZE(ctx_reg) + \
1534 HSW_CXT_RENDER_SIZE(ctx_reg) + \
1535 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1542 #define OVADD 0x30000
1543 #define DOVSTA 0x30008
1544 #define OC_BUF (0x3<<20)
1545 #define OGAMC5 0x30010
1546 #define OGAMC4 0x30014
1547 #define OGAMC3 0x30018
1548 #define OGAMC2 0x3001c
1549 #define OGAMC1 0x30020
1550 #define OGAMC0 0x30024
1553 * Display engine regs
1556 /* Pipe A timing regs */
1557 #define _HTOTAL_A 0x60000
1558 #define _HBLANK_A 0x60004
1559 #define _HSYNC_A 0x60008
1560 #define _VTOTAL_A 0x6000c
1561 #define _VBLANK_A 0x60010
1562 #define _VSYNC_A 0x60014
1563 #define _PIPEASRC 0x6001c
1564 #define _BCLRPAT_A 0x60020
1565 #define _VSYNCSHIFT_A 0x60028
1567 /* Pipe B timing regs */
1568 #define _HTOTAL_B 0x61000
1569 #define _HBLANK_B 0x61004
1570 #define _HSYNC_B 0x61008
1571 #define _VTOTAL_B 0x6100c
1572 #define _VBLANK_B 0x61010
1573 #define _VSYNC_B 0x61014
1574 #define _PIPEBSRC 0x6101c
1575 #define _BCLRPAT_B 0x61020
1576 #define _VSYNCSHIFT_B 0x61028
1579 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
1580 #define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
1581 #define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
1582 #define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
1583 #define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
1584 #define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
1585 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1586 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1588 /* VGA port control */
1589 #define ADPA 0x61100
1590 #define PCH_ADPA 0xe1100
1591 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
1593 #define ADPA_DAC_ENABLE (1<<31)
1594 #define ADPA_DAC_DISABLE 0
1595 #define ADPA_PIPE_SELECT_MASK (1<<30)
1596 #define ADPA_PIPE_A_SELECT 0
1597 #define ADPA_PIPE_B_SELECT (1<<30)
1598 #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1599 /* CPT uses bits 29:30 for pch transcoder select */
1600 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1601 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
1602 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
1603 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
1604 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
1605 #define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
1606 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
1607 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
1608 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
1609 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
1610 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
1611 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
1612 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
1613 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
1614 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
1615 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
1616 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
1617 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
1618 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
1619 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1620 #define ADPA_SETS_HVPOLARITY 0
1621 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1622 #define ADPA_VSYNC_CNTL_ENABLE 0
1623 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1624 #define ADPA_HSYNC_CNTL_ENABLE 0
1625 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1626 #define ADPA_VSYNC_ACTIVE_LOW 0
1627 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1628 #define ADPA_HSYNC_ACTIVE_LOW 0
1629 #define ADPA_DPMS_MASK (~(3<<10))
1630 #define ADPA_DPMS_ON (0<<10)
1631 #define ADPA_DPMS_SUSPEND (1<<10)
1632 #define ADPA_DPMS_STANDBY (2<<10)
1633 #define ADPA_DPMS_OFF (3<<10)
1636 /* Hotplug control (945+ only) */
1637 #define PORT_HOTPLUG_EN 0x61110
1638 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
1639 #define DPB_HOTPLUG_INT_EN (1 << 29)
1640 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
1641 #define DPC_HOTPLUG_INT_EN (1 << 28)
1642 #define HDMID_HOTPLUG_INT_EN (1 << 27)
1643 #define DPD_HOTPLUG_INT_EN (1 << 27)
1644 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
1645 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
1646 #define TV_HOTPLUG_INT_EN (1 << 18)
1647 #define CRT_HOTPLUG_INT_EN (1 << 9)
1648 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1649 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1650 /* must use period 64 on GM45 according to docs */
1651 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1652 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1653 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1654 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1655 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1656 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1657 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1658 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1659 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1660 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1661 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1662 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1664 #define PORT_HOTPLUG_STAT 0x61114
1665 /* HDMI/DP bits are gen4+ */
1666 #define DPB_HOTPLUG_LIVE_STATUS (1 << 29)
1667 #define DPC_HOTPLUG_LIVE_STATUS (1 << 28)
1668 #define DPD_HOTPLUG_LIVE_STATUS (1 << 27)
1669 #define DPD_HOTPLUG_INT_STATUS (3 << 21)
1670 #define DPC_HOTPLUG_INT_STATUS (3 << 19)
1671 #define DPB_HOTPLUG_INT_STATUS (3 << 17)
1672 /* HDMI bits are shared with the DP bits */
1673 #define HDMIB_HOTPLUG_LIVE_STATUS (1 << 29)
1674 #define HDMIC_HOTPLUG_LIVE_STATUS (1 << 28)
1675 #define HDMID_HOTPLUG_LIVE_STATUS (1 << 27)
1676 #define HDMID_HOTPLUG_INT_STATUS (3 << 21)
1677 #define HDMIC_HOTPLUG_INT_STATUS (3 << 19)
1678 #define HDMIB_HOTPLUG_INT_STATUS (3 << 17)
1679 /* CRT/TV common between gen3+ */
1680 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
1681 #define TV_HOTPLUG_INT_STATUS (1 << 10)
1682 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1683 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1684 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1685 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1686 /* SDVO is different across gen3/4 */
1687 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
1688 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
1689 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
1690 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1691 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1692 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1694 /* SDVO port control */
1695 #define SDVOB 0x61140
1696 #define SDVOC 0x61160
1697 #define SDVO_ENABLE (1 << 31)
1698 #define SDVO_PIPE_B_SELECT (1 << 30)
1699 #define SDVO_STALL_SELECT (1 << 29)
1700 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1702 * 915G/GM SDVO pixel multiplier.
1704 * Programmed value is multiplier - 1, up to 5x.
1706 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1708 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1709 #define SDVO_PORT_MULTIPLY_SHIFT 23
1710 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1711 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1712 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1713 #define SDVOC_GANG_MODE (1 << 16)
1714 #define SDVO_ENCODING_SDVO (0x0 << 10)
1715 #define SDVO_ENCODING_HDMI (0x2 << 10)
1716 /** Requird for HDMI operation */
1717 #define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1718 #define SDVO_COLOR_RANGE_16_235 (1 << 8)
1719 #define SDVO_BORDER_ENABLE (1 << 7)
1720 #define SDVO_AUDIO_ENABLE (1 << 6)
1721 /** New with 965, default is to be set */
1722 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1723 /** New with 965, default is to be set */
1724 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1725 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1726 #define SDVO_DETECTED (1 << 2)
1727 /* Bits to be preserved when writing */
1728 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1729 #define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1731 /* DVO port control */
1732 #define DVOA 0x61120
1733 #define DVOB 0x61140
1734 #define DVOC 0x61160
1735 #define DVO_ENABLE (1 << 31)
1736 #define DVO_PIPE_B_SELECT (1 << 30)
1737 #define DVO_PIPE_STALL_UNUSED (0 << 28)
1738 #define DVO_PIPE_STALL (1 << 28)
1739 #define DVO_PIPE_STALL_TV (2 << 28)
1740 #define DVO_PIPE_STALL_MASK (3 << 28)
1741 #define DVO_USE_VGA_SYNC (1 << 15)
1742 #define DVO_DATA_ORDER_I740 (0 << 14)
1743 #define DVO_DATA_ORDER_FP (1 << 14)
1744 #define DVO_VSYNC_DISABLE (1 << 11)
1745 #define DVO_HSYNC_DISABLE (1 << 10)
1746 #define DVO_VSYNC_TRISTATE (1 << 9)
1747 #define DVO_HSYNC_TRISTATE (1 << 8)
1748 #define DVO_BORDER_ENABLE (1 << 7)
1749 #define DVO_DATA_ORDER_GBRG (1 << 6)
1750 #define DVO_DATA_ORDER_RGGB (0 << 6)
1751 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1752 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1753 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1754 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1755 #define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1756 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1757 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1758 #define DVO_PRESERVE_MASK (0x7<<24)
1759 #define DVOA_SRCDIM 0x61124
1760 #define DVOB_SRCDIM 0x61144
1761 #define DVOC_SRCDIM 0x61164
1762 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1763 #define DVO_SRCDIM_VERTICAL_SHIFT 0
1765 /* LVDS port control */
1766 #define LVDS 0x61180
1768 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1769 * the DPLL semantics change when the LVDS is assigned to that pipe.
1771 #define LVDS_PORT_EN (1 << 31)
1772 /* Selects pipe B for LVDS data. Must be set on pre-965. */
1773 #define LVDS_PIPEB_SELECT (1 << 30)
1774 #define LVDS_PIPE_MASK (1 << 30)
1775 #define LVDS_PIPE(pipe) ((pipe) << 30)
1776 /* LVDS dithering flag on 965/g4x platform */
1777 #define LVDS_ENABLE_DITHER (1 << 25)
1778 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
1779 #define LVDS_VSYNC_POLARITY (1 << 21)
1780 #define LVDS_HSYNC_POLARITY (1 << 20)
1782 /* Enable border for unscaled (or aspect-scaled) display */
1783 #define LVDS_BORDER_ENABLE (1 << 15)
1785 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1788 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1789 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1790 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1792 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1793 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1796 #define LVDS_A3_POWER_MASK (3 << 6)
1797 #define LVDS_A3_POWER_DOWN (0 << 6)
1798 #define LVDS_A3_POWER_UP (3 << 6)
1800 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1803 #define LVDS_CLKB_POWER_MASK (3 << 4)
1804 #define LVDS_CLKB_POWER_DOWN (0 << 4)
1805 #define LVDS_CLKB_POWER_UP (3 << 4)
1807 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1808 * setting for whether we are in dual-channel mode. The B3 pair will
1809 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1811 #define LVDS_B0B3_POWER_MASK (3 << 2)
1812 #define LVDS_B0B3_POWER_DOWN (0 << 2)
1813 #define LVDS_B0B3_POWER_UP (3 << 2)
1815 /* Video Data Island Packet control */
1816 #define VIDEO_DIP_DATA 0x61178
1817 /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
1818 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1819 * of the infoframe structure specified by CEA-861. */
1820 #define VIDEO_DIP_DATA_SIZE 32
1821 #define VIDEO_DIP_CTL 0x61170
1823 #define VIDEO_DIP_ENABLE (1 << 31)
1824 #define VIDEO_DIP_PORT_B (1 << 29)
1825 #define VIDEO_DIP_PORT_C (2 << 29)
1826 #define VIDEO_DIP_PORT_D (3 << 29)
1827 #define VIDEO_DIP_PORT_MASK (3 << 29)
1828 #define VIDEO_DIP_ENABLE_GCP (1 << 25)
1829 #define VIDEO_DIP_ENABLE_AVI (1 << 21)
1830 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1831 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
1832 #define VIDEO_DIP_ENABLE_SPD (8 << 21)
1833 #define VIDEO_DIP_SELECT_AVI (0 << 19)
1834 #define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1835 #define VIDEO_DIP_SELECT_SPD (3 << 19)
1836 #define VIDEO_DIP_SELECT_MASK (3 << 19)
1837 #define VIDEO_DIP_FREQ_ONCE (0 << 16)
1838 #define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1839 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1840 #define VIDEO_DIP_FREQ_MASK (3 << 16)
1841 /* HSW and later: */
1842 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
1843 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
1844 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
1845 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
1846 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
1847 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1849 /* Panel power sequencing */
1850 #define PP_STATUS 0x61200
1851 #define PP_ON (1 << 31)
1853 * Indicates that all dependencies of the panel are on:
1857 * - LVDS/DVOB/DVOC on
1859 #define PP_READY (1 << 30)
1860 #define PP_SEQUENCE_NONE (0 << 28)
1861 #define PP_SEQUENCE_POWER_UP (1 << 28)
1862 #define PP_SEQUENCE_POWER_DOWN (2 << 28)
1863 #define PP_SEQUENCE_MASK (3 << 28)
1864 #define PP_SEQUENCE_SHIFT 28
1865 #define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1866 #define PP_SEQUENCE_STATE_MASK 0x0000000f
1867 #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
1868 #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
1869 #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
1870 #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
1871 #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
1872 #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
1873 #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
1874 #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
1875 #define PP_SEQUENCE_STATE_RESET (0xf << 0)
1876 #define PP_CONTROL 0x61204
1877 #define POWER_TARGET_ON (1 << 0)
1878 #define PP_ON_DELAYS 0x61208
1879 #define PP_OFF_DELAYS 0x6120c
1880 #define PP_DIVISOR 0x61210
1883 #define PFIT_CONTROL 0x61230
1884 #define PFIT_ENABLE (1 << 31)
1885 #define PFIT_PIPE_MASK (3 << 29)
1886 #define PFIT_PIPE_SHIFT 29
1887 #define VERT_INTERP_DISABLE (0 << 10)
1888 #define VERT_INTERP_BILINEAR (1 << 10)
1889 #define VERT_INTERP_MASK (3 << 10)
1890 #define VERT_AUTO_SCALE (1 << 9)
1891 #define HORIZ_INTERP_DISABLE (0 << 6)
1892 #define HORIZ_INTERP_BILINEAR (1 << 6)
1893 #define HORIZ_INTERP_MASK (3 << 6)
1894 #define HORIZ_AUTO_SCALE (1 << 5)
1895 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1896 #define PFIT_FILTER_FUZZY (0 << 24)
1897 #define PFIT_SCALING_AUTO (0 << 26)
1898 #define PFIT_SCALING_PROGRAMMED (1 << 26)
1899 #define PFIT_SCALING_PILLAR (2 << 26)
1900 #define PFIT_SCALING_LETTER (3 << 26)
1901 #define PFIT_PGM_RATIOS 0x61234
1902 #define PFIT_VERT_SCALE_MASK 0xfff00000
1903 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1905 #define PFIT_VERT_SCALE_SHIFT 20
1906 #define PFIT_VERT_SCALE_MASK 0xfff00000
1907 #define PFIT_HORIZ_SCALE_SHIFT 4
1908 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1910 #define PFIT_VERT_SCALE_SHIFT_965 16
1911 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1912 #define PFIT_HORIZ_SCALE_SHIFT_965 0
1913 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1915 #define PFIT_AUTO_RATIOS 0x61238
1917 /* Backlight control */
1918 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
1919 #define BLM_PWM_ENABLE (1 << 31)
1920 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
1921 #define BLM_PIPE_SELECT (1 << 29)
1922 #define BLM_PIPE_SELECT_IVB (3 << 29)
1923 #define BLM_PIPE_A (0 << 29)
1924 #define BLM_PIPE_B (1 << 29)
1925 #define BLM_PIPE_C (2 << 29) /* ivb + */
1926 #define BLM_PIPE(pipe) ((pipe) << 29)
1927 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
1928 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
1929 #define BLM_PHASE_IN_ENABLE (1 << 25)
1930 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
1931 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
1932 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
1933 #define BLM_PHASE_IN_COUNT_SHIFT (8)
1934 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
1935 #define BLM_PHASE_IN_INCR_SHIFT (0)
1936 #define BLM_PHASE_IN_INCR_MASK (0xff << 0)
1937 #define BLC_PWM_CTL 0x61254
1939 * This is the most significant 15 bits of the number of backlight cycles in a
1940 * complete cycle of the modulated backlight control.
1942 * The actual value is this field multiplied by two.
1944 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1945 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1946 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
1948 * This is the number of cycles out of the backlight modulation cycle for which
1949 * the backlight is on.
1951 * This field must be no greater than the number of cycles in the complete
1952 * backlight modulation cycle.
1954 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1955 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1956 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
1957 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */
1959 #define BLC_HIST_CTL 0x61260
1961 /* New registers for PCH-split platforms. Safe where new bits show up, the
1962 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
1963 #define BLC_PWM_CPU_CTL2 0x48250
1964 #define BLC_PWM_CPU_CTL 0x48254
1966 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
1967 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
1968 #define BLC_PWM_PCH_CTL1 0xc8250
1969 #define BLM_PCH_PWM_ENABLE (1 << 31)
1970 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
1971 #define BLM_PCH_POLARITY (1 << 29)
1972 #define BLC_PWM_PCH_CTL2 0xc8254
1974 /* TV port control */
1975 #define TV_CTL 0x68000
1976 /** Enables the TV encoder */
1977 # define TV_ENC_ENABLE (1 << 31)
1978 /** Sources the TV encoder input from pipe B instead of A. */
1979 # define TV_ENC_PIPEB_SELECT (1 << 30)
1980 /** Outputs composite video (DAC A only) */
1981 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1982 /** Outputs SVideo video (DAC B/C) */
1983 # define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1984 /** Outputs Component video (DAC A/B/C) */
1985 # define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1986 /** Outputs Composite and SVideo (DAC A/B/C) */
1987 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1988 # define TV_TRILEVEL_SYNC (1 << 21)
1989 /** Enables slow sync generation (945GM only) */
1990 # define TV_SLOW_SYNC (1 << 20)
1991 /** Selects 4x oversampling for 480i and 576p */
1992 # define TV_OVERSAMPLE_4X (0 << 18)
1993 /** Selects 2x oversampling for 720p and 1080i */
1994 # define TV_OVERSAMPLE_2X (1 << 18)
1995 /** Selects no oversampling for 1080p */
1996 # define TV_OVERSAMPLE_NONE (2 << 18)
1997 /** Selects 8x oversampling */
1998 # define TV_OVERSAMPLE_8X (3 << 18)
1999 /** Selects progressive mode rather than interlaced */
2000 # define TV_PROGRESSIVE (1 << 17)
2001 /** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2002 # define TV_PAL_BURST (1 << 16)
2003 /** Field for setting delay of Y compared to C */
2004 # define TV_YC_SKEW_MASK (7 << 12)
2005 /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2006 # define TV_ENC_SDP_FIX (1 << 11)
2008 * Enables a fix for the 915GM only.
2010 * Not sure what it does.
2012 # define TV_ENC_C0_FIX (1 << 10)
2013 /** Bits that must be preserved by software */
2014 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2015 # define TV_FUSE_STATE_MASK (3 << 4)
2016 /** Read-only state that reports all features enabled */
2017 # define TV_FUSE_STATE_ENABLED (0 << 4)
2018 /** Read-only state that reports that Macrovision is disabled in hardware*/
2019 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2020 /** Read-only state that reports that TV-out is disabled in hardware. */
2021 # define TV_FUSE_STATE_DISABLED (2 << 4)
2022 /** Normal operation */
2023 # define TV_TEST_MODE_NORMAL (0 << 0)
2024 /** Encoder test pattern 1 - combo pattern */
2025 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
2026 /** Encoder test pattern 2 - full screen vertical 75% color bars */
2027 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
2028 /** Encoder test pattern 3 - full screen horizontal 75% color bars */
2029 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
2030 /** Encoder test pattern 4 - random noise */
2031 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
2032 /** Encoder test pattern 5 - linear color ramps */
2033 # define TV_TEST_MODE_PATTERN_5 (5 << 0)
2035 * This test mode forces the DACs to 50% of full output.
2037 * This is used for load detection in combination with TVDAC_SENSE_MASK
2039 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2040 # define TV_TEST_MODE_MASK (7 << 0)
2042 #define TV_DAC 0x68004
2043 # define TV_DAC_SAVE 0x00ffff00
2045 * Reports that DAC state change logic has reported change (RO).
2047 * This gets cleared when TV_DAC_STATE_EN is cleared
2049 # define TVDAC_STATE_CHG (1 << 31)
2050 # define TVDAC_SENSE_MASK (7 << 28)
2051 /** Reports that DAC A voltage is above the detect threshold */
2052 # define TVDAC_A_SENSE (1 << 30)
2053 /** Reports that DAC B voltage is above the detect threshold */
2054 # define TVDAC_B_SENSE (1 << 29)
2055 /** Reports that DAC C voltage is above the detect threshold */
2056 # define TVDAC_C_SENSE (1 << 28)
2058 * Enables DAC state detection logic, for load-based TV detection.
2060 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2061 * to off, for load detection to work.
2063 # define TVDAC_STATE_CHG_EN (1 << 27)
2064 /** Sets the DAC A sense value to high */
2065 # define TVDAC_A_SENSE_CTL (1 << 26)
2066 /** Sets the DAC B sense value to high */
2067 # define TVDAC_B_SENSE_CTL (1 << 25)
2068 /** Sets the DAC C sense value to high */
2069 # define TVDAC_C_SENSE_CTL (1 << 24)
2070 /** Overrides the ENC_ENABLE and DAC voltage levels */
2071 # define DAC_CTL_OVERRIDE (1 << 7)
2072 /** Sets the slew rate. Must be preserved in software */
2073 # define ENC_TVDAC_SLEW_FAST (1 << 6)
2074 # define DAC_A_1_3_V (0 << 4)
2075 # define DAC_A_1_1_V (1 << 4)
2076 # define DAC_A_0_7_V (2 << 4)
2077 # define DAC_A_MASK (3 << 4)
2078 # define DAC_B_1_3_V (0 << 2)
2079 # define DAC_B_1_1_V (1 << 2)
2080 # define DAC_B_0_7_V (2 << 2)
2081 # define DAC_B_MASK (3 << 2)
2082 # define DAC_C_1_3_V (0 << 0)
2083 # define DAC_C_1_1_V (1 << 0)
2084 # define DAC_C_0_7_V (2 << 0)
2085 # define DAC_C_MASK (3 << 0)
2088 * CSC coefficients are stored in a floating point format with 9 bits of
2089 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2090 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2091 * -1 (0x3) being the only legal negative value.
2093 #define TV_CSC_Y 0x68010
2094 # define TV_RY_MASK 0x07ff0000
2095 # define TV_RY_SHIFT 16
2096 # define TV_GY_MASK 0x00000fff
2097 # define TV_GY_SHIFT 0
2099 #define TV_CSC_Y2 0x68014
2100 # define TV_BY_MASK 0x07ff0000
2101 # define TV_BY_SHIFT 16
2103 * Y attenuation for component video.
2105 * Stored in 1.9 fixed point.
2107 # define TV_AY_MASK 0x000003ff
2108 # define TV_AY_SHIFT 0
2110 #define TV_CSC_U 0x68018
2111 # define TV_RU_MASK 0x07ff0000
2112 # define TV_RU_SHIFT 16
2113 # define TV_GU_MASK 0x000007ff
2114 # define TV_GU_SHIFT 0
2116 #define TV_CSC_U2 0x6801c
2117 # define TV_BU_MASK 0x07ff0000
2118 # define TV_BU_SHIFT 16
2120 * U attenuation for component video.
2122 * Stored in 1.9 fixed point.
2124 # define TV_AU_MASK 0x000003ff
2125 # define TV_AU_SHIFT 0
2127 #define TV_CSC_V 0x68020
2128 # define TV_RV_MASK 0x0fff0000
2129 # define TV_RV_SHIFT 16
2130 # define TV_GV_MASK 0x000007ff
2131 # define TV_GV_SHIFT 0
2133 #define TV_CSC_V2 0x68024
2134 # define TV_BV_MASK 0x07ff0000
2135 # define TV_BV_SHIFT 16
2137 * V attenuation for component video.
2139 * Stored in 1.9 fixed point.
2141 # define TV_AV_MASK 0x000007ff
2142 # define TV_AV_SHIFT 0
2144 #define TV_CLR_KNOBS 0x68028
2145 /** 2s-complement brightness adjustment */
2146 # define TV_BRIGHTNESS_MASK 0xff000000
2147 # define TV_BRIGHTNESS_SHIFT 24
2148 /** Contrast adjustment, as a 2.6 unsigned floating point number */
2149 # define TV_CONTRAST_MASK 0x00ff0000
2150 # define TV_CONTRAST_SHIFT 16
2151 /** Saturation adjustment, as a 2.6 unsigned floating point number */
2152 # define TV_SATURATION_MASK 0x0000ff00
2153 # define TV_SATURATION_SHIFT 8
2154 /** Hue adjustment, as an integer phase angle in degrees */
2155 # define TV_HUE_MASK 0x000000ff
2156 # define TV_HUE_SHIFT 0
2158 #define TV_CLR_LEVEL 0x6802c
2159 /** Controls the DAC level for black */
2160 # define TV_BLACK_LEVEL_MASK 0x01ff0000
2161 # define TV_BLACK_LEVEL_SHIFT 16
2162 /** Controls the DAC level for blanking */
2163 # define TV_BLANK_LEVEL_MASK 0x000001ff
2164 # define TV_BLANK_LEVEL_SHIFT 0
2166 #define TV_H_CTL_1 0x68030
2167 /** Number of pixels in the hsync. */
2168 # define TV_HSYNC_END_MASK 0x1fff0000
2169 # define TV_HSYNC_END_SHIFT 16
2170 /** Total number of pixels minus one in the line (display and blanking). */
2171 # define TV_HTOTAL_MASK 0x00001fff
2172 # define TV_HTOTAL_SHIFT 0
2174 #define TV_H_CTL_2 0x68034
2175 /** Enables the colorburst (needed for non-component color) */
2176 # define TV_BURST_ENA (1 << 31)
2177 /** Offset of the colorburst from the start of hsync, in pixels minus one. */
2178 # define TV_HBURST_START_SHIFT 16
2179 # define TV_HBURST_START_MASK 0x1fff0000
2180 /** Length of the colorburst */
2181 # define TV_HBURST_LEN_SHIFT 0
2182 # define TV_HBURST_LEN_MASK 0x0001fff
2184 #define TV_H_CTL_3 0x68038
2185 /** End of hblank, measured in pixels minus one from start of hsync */
2186 # define TV_HBLANK_END_SHIFT 16
2187 # define TV_HBLANK_END_MASK 0x1fff0000
2188 /** Start of hblank, measured in pixels minus one from start of hsync */
2189 # define TV_HBLANK_START_SHIFT 0
2190 # define TV_HBLANK_START_MASK 0x0001fff
2192 #define TV_V_CTL_1 0x6803c
2194 # define TV_NBR_END_SHIFT 16
2195 # define TV_NBR_END_MASK 0x07ff0000
2197 # define TV_VI_END_F1_SHIFT 8
2198 # define TV_VI_END_F1_MASK 0x00003f00
2200 # define TV_VI_END_F2_SHIFT 0
2201 # define TV_VI_END_F2_MASK 0x0000003f
2203 #define TV_V_CTL_2 0x68040
2204 /** Length of vsync, in half lines */
2205 # define TV_VSYNC_LEN_MASK 0x07ff0000
2206 # define TV_VSYNC_LEN_SHIFT 16
2207 /** Offset of the start of vsync in field 1, measured in one less than the
2208 * number of half lines.
2210 # define TV_VSYNC_START_F1_MASK 0x00007f00
2211 # define TV_VSYNC_START_F1_SHIFT 8
2213 * Offset of the start of vsync in field 2, measured in one less than the
2214 * number of half lines.
2216 # define TV_VSYNC_START_F2_MASK 0x0000007f
2217 # define TV_VSYNC_START_F2_SHIFT 0
2219 #define TV_V_CTL_3 0x68044
2220 /** Enables generation of the equalization signal */
2221 # define TV_EQUAL_ENA (1 << 31)
2222 /** Length of vsync, in half lines */
2223 # define TV_VEQ_LEN_MASK 0x007f0000
2224 # define TV_VEQ_LEN_SHIFT 16
2225 /** Offset of the start of equalization in field 1, measured in one less than
2226 * the number of half lines.
2228 # define TV_VEQ_START_F1_MASK 0x0007f00
2229 # define TV_VEQ_START_F1_SHIFT 8
2231 * Offset of the start of equalization in field 2, measured in one less than
2232 * the number of half lines.
2234 # define TV_VEQ_START_F2_MASK 0x000007f
2235 # define TV_VEQ_START_F2_SHIFT 0
2237 #define TV_V_CTL_4 0x68048
2239 * Offset to start of vertical colorburst, measured in one less than the
2240 * number of lines from vertical start.
2242 # define TV_VBURST_START_F1_MASK 0x003f0000
2243 # define TV_VBURST_START_F1_SHIFT 16
2245 * Offset to the end of vertical colorburst, measured in one less than the
2246 * number of lines from the start of NBR.
2248 # define TV_VBURST_END_F1_MASK 0x000000ff
2249 # define TV_VBURST_END_F1_SHIFT 0
2251 #define TV_V_CTL_5 0x6804c
2253 * Offset to start of vertical colorburst, measured in one less than the
2254 * number of lines from vertical start.
2256 # define TV_VBURST_START_F2_MASK 0x003f0000
2257 # define TV_VBURST_START_F2_SHIFT 16
2259 * Offset to the end of vertical colorburst, measured in one less than the
2260 * number of lines from the start of NBR.
2262 # define TV_VBURST_END_F2_MASK 0x000000ff
2263 # define TV_VBURST_END_F2_SHIFT 0
2265 #define TV_V_CTL_6 0x68050
2267 * Offset to start of vertical colorburst, measured in one less than the
2268 * number of lines from vertical start.
2270 # define TV_VBURST_START_F3_MASK 0x003f0000
2271 # define TV_VBURST_START_F3_SHIFT 16
2273 * Offset to the end of vertical colorburst, measured in one less than the
2274 * number of lines from the start of NBR.
2276 # define TV_VBURST_END_F3_MASK 0x000000ff
2277 # define TV_VBURST_END_F3_SHIFT 0
2279 #define TV_V_CTL_7 0x68054
2281 * Offset to start of vertical colorburst, measured in one less than the
2282 * number of lines from vertical start.
2284 # define TV_VBURST_START_F4_MASK 0x003f0000
2285 # define TV_VBURST_START_F4_SHIFT 16
2287 * Offset to the end of vertical colorburst, measured in one less than the
2288 * number of lines from the start of NBR.
2290 # define TV_VBURST_END_F4_MASK 0x000000ff
2291 # define TV_VBURST_END_F4_SHIFT 0
2293 #define TV_SC_CTL_1 0x68060
2294 /** Turns on the first subcarrier phase generation DDA */
2295 # define TV_SC_DDA1_EN (1 << 31)
2296 /** Turns on the first subcarrier phase generation DDA */
2297 # define TV_SC_DDA2_EN (1 << 30)
2298 /** Turns on the first subcarrier phase generation DDA */
2299 # define TV_SC_DDA3_EN (1 << 29)
2300 /** Sets the subcarrier DDA to reset frequency every other field */
2301 # define TV_SC_RESET_EVERY_2 (0 << 24)
2302 /** Sets the subcarrier DDA to reset frequency every fourth field */
2303 # define TV_SC_RESET_EVERY_4 (1 << 24)
2304 /** Sets the subcarrier DDA to reset frequency every eighth field */
2305 # define TV_SC_RESET_EVERY_8 (2 << 24)
2306 /** Sets the subcarrier DDA to never reset the frequency */
2307 # define TV_SC_RESET_NEVER (3 << 24)
2308 /** Sets the peak amplitude of the colorburst.*/
2309 # define TV_BURST_LEVEL_MASK 0x00ff0000
2310 # define TV_BURST_LEVEL_SHIFT 16
2311 /** Sets the increment of the first subcarrier phase generation DDA */
2312 # define TV_SCDDA1_INC_MASK 0x00000fff
2313 # define TV_SCDDA1_INC_SHIFT 0
2315 #define TV_SC_CTL_2 0x68064
2316 /** Sets the rollover for the second subcarrier phase generation DDA */
2317 # define TV_SCDDA2_SIZE_MASK 0x7fff0000
2318 # define TV_SCDDA2_SIZE_SHIFT 16
2319 /** Sets the increent of the second subcarrier phase generation DDA */
2320 # define TV_SCDDA2_INC_MASK 0x00007fff
2321 # define TV_SCDDA2_INC_SHIFT 0
2323 #define TV_SC_CTL_3 0x68068
2324 /** Sets the rollover for the third subcarrier phase generation DDA */
2325 # define TV_SCDDA3_SIZE_MASK 0x7fff0000
2326 # define TV_SCDDA3_SIZE_SHIFT 16
2327 /** Sets the increent of the third subcarrier phase generation DDA */
2328 # define TV_SCDDA3_INC_MASK 0x00007fff
2329 # define TV_SCDDA3_INC_SHIFT 0
2331 #define TV_WIN_POS 0x68070
2332 /** X coordinate of the display from the start of horizontal active */
2333 # define TV_XPOS_MASK 0x1fff0000
2334 # define TV_XPOS_SHIFT 16
2335 /** Y coordinate of the display from the start of vertical active (NBR) */
2336 # define TV_YPOS_MASK 0x00000fff
2337 # define TV_YPOS_SHIFT 0
2339 #define TV_WIN_SIZE 0x68074
2340 /** Horizontal size of the display window, measured in pixels*/
2341 # define TV_XSIZE_MASK 0x1fff0000
2342 # define TV_XSIZE_SHIFT 16
2344 * Vertical size of the display window, measured in pixels.
2346 * Must be even for interlaced modes.
2348 # define TV_YSIZE_MASK 0x00000fff
2349 # define TV_YSIZE_SHIFT 0
2351 #define TV_FILTER_CTL_1 0x68080
2353 * Enables automatic scaling calculation.
2355 * If set, the rest of the registers are ignored, and the calculated values can
2356 * be read back from the register.
2358 # define TV_AUTO_SCALE (1 << 31)
2360 * Disables the vertical filter.
2362 * This is required on modes more than 1024 pixels wide */
2363 # define TV_V_FILTER_BYPASS (1 << 29)
2364 /** Enables adaptive vertical filtering */
2365 # define TV_VADAPT (1 << 28)
2366 # define TV_VADAPT_MODE_MASK (3 << 26)
2367 /** Selects the least adaptive vertical filtering mode */
2368 # define TV_VADAPT_MODE_LEAST (0 << 26)
2369 /** Selects the moderately adaptive vertical filtering mode */
2370 # define TV_VADAPT_MODE_MODERATE (1 << 26)
2371 /** Selects the most adaptive vertical filtering mode */
2372 # define TV_VADAPT_MODE_MOST (3 << 26)
2374 * Sets the horizontal scaling factor.
2376 * This should be the fractional part of the horizontal scaling factor divided
2377 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2379 * (src width - 1) / ((oversample * dest width) - 1)
2381 # define TV_HSCALE_FRAC_MASK 0x00003fff
2382 # define TV_HSCALE_FRAC_SHIFT 0
2384 #define TV_FILTER_CTL_2 0x68084
2386 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2388 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2390 # define TV_VSCALE_INT_MASK 0x00038000
2391 # define TV_VSCALE_INT_SHIFT 15
2393 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2395 * \sa TV_VSCALE_INT_MASK
2397 # define TV_VSCALE_FRAC_MASK 0x00007fff
2398 # define TV_VSCALE_FRAC_SHIFT 0
2400 #define TV_FILTER_CTL_3 0x68088
2402 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2404 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2406 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2408 # define TV_VSCALE_IP_INT_MASK 0x00038000
2409 # define TV_VSCALE_IP_INT_SHIFT 15
2411 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2413 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2415 * \sa TV_VSCALE_IP_INT_MASK
2417 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2418 # define TV_VSCALE_IP_FRAC_SHIFT 0
2420 #define TV_CC_CONTROL 0x68090
2421 # define TV_CC_ENABLE (1 << 31)
2423 * Specifies which field to send the CC data in.
2425 * CC data is usually sent in field 0.
2427 # define TV_CC_FID_MASK (1 << 27)
2428 # define TV_CC_FID_SHIFT 27
2429 /** Sets the horizontal position of the CC data. Usually 135. */
2430 # define TV_CC_HOFF_MASK 0x03ff0000
2431 # define TV_CC_HOFF_SHIFT 16
2432 /** Sets the vertical position of the CC data. Usually 21 */
2433 # define TV_CC_LINE_MASK 0x0000003f
2434 # define TV_CC_LINE_SHIFT 0
2436 #define TV_CC_DATA 0x68094
2437 # define TV_CC_RDY (1 << 31)
2438 /** Second word of CC data to be transmitted. */
2439 # define TV_CC_DATA_2_MASK 0x007f0000
2440 # define TV_CC_DATA_2_SHIFT 16
2441 /** First word of CC data to be transmitted. */
2442 # define TV_CC_DATA_1_MASK 0x0000007f
2443 # define TV_CC_DATA_1_SHIFT 0
2445 #define TV_H_LUMA_0 0x68100
2446 #define TV_H_LUMA_59 0x681ec
2447 #define TV_H_CHROMA_0 0x68200
2448 #define TV_H_CHROMA_59 0x682ec
2449 #define TV_V_LUMA_0 0x68300
2450 #define TV_V_LUMA_42 0x683a8
2451 #define TV_V_CHROMA_0 0x68400
2452 #define TV_V_CHROMA_42 0x684a8
2455 #define DP_A 0x64000 /* eDP */
2456 #define DP_B 0x64100
2457 #define DP_C 0x64200
2458 #define DP_D 0x64300
2460 #define DP_PORT_EN (1 << 31)
2461 #define DP_PIPEB_SELECT (1 << 30)
2462 #define DP_PIPE_MASK (1 << 30)
2464 /* Link training mode - select a suitable mode for each stage */
2465 #define DP_LINK_TRAIN_PAT_1 (0 << 28)
2466 #define DP_LINK_TRAIN_PAT_2 (1 << 28)
2467 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2468 #define DP_LINK_TRAIN_OFF (3 << 28)
2469 #define DP_LINK_TRAIN_MASK (3 << 28)
2470 #define DP_LINK_TRAIN_SHIFT 28
2472 /* CPT Link training mode */
2473 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2474 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2475 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2476 #define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2477 #define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2478 #define DP_LINK_TRAIN_SHIFT_CPT 8
2480 /* Signal voltages. These are mostly controlled by the other end */
2481 #define DP_VOLTAGE_0_4 (0 << 25)
2482 #define DP_VOLTAGE_0_6 (1 << 25)
2483 #define DP_VOLTAGE_0_8 (2 << 25)
2484 #define DP_VOLTAGE_1_2 (3 << 25)
2485 #define DP_VOLTAGE_MASK (7 << 25)
2486 #define DP_VOLTAGE_SHIFT 25
2488 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2491 #define DP_PRE_EMPHASIS_0 (0 << 22)
2492 #define DP_PRE_EMPHASIS_3_5 (1 << 22)
2493 #define DP_PRE_EMPHASIS_6 (2 << 22)
2494 #define DP_PRE_EMPHASIS_9_5 (3 << 22)
2495 #define DP_PRE_EMPHASIS_MASK (7 << 22)
2496 #define DP_PRE_EMPHASIS_SHIFT 22
2498 /* How many wires to use. I guess 3 was too hard */
2499 #define DP_PORT_WIDTH_1 (0 << 19)
2500 #define DP_PORT_WIDTH_2 (1 << 19)
2501 #define DP_PORT_WIDTH_4 (3 << 19)
2502 #define DP_PORT_WIDTH_MASK (7 << 19)
2504 /* Mystic DPCD version 1.1 special mode */
2505 #define DP_ENHANCED_FRAMING (1 << 18)
2508 #define DP_PLL_FREQ_270MHZ (0 << 16)
2509 #define DP_PLL_FREQ_160MHZ (1 << 16)
2510 #define DP_PLL_FREQ_MASK (3 << 16)
2512 /** locked once port is enabled */
2513 #define DP_PORT_REVERSAL (1 << 15)
2516 #define DP_PLL_ENABLE (1 << 14)
2518 /** sends the clock on lane 15 of the PEG for debug */
2519 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2521 #define DP_SCRAMBLING_DISABLE (1 << 12)
2522 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2524 /** limit RGB values to avoid confusing TVs */
2525 #define DP_COLOR_RANGE_16_235 (1 << 8)
2527 /** Turn on the audio link */
2528 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2530 /** vs and hs sync polarity */
2531 #define DP_SYNC_VS_HIGH (1 << 4)
2532 #define DP_SYNC_HS_HIGH (1 << 3)
2535 #define DP_DETECTED (1 << 2)
2537 /** The aux channel provides a way to talk to the
2538 * signal sink for DDC etc. Max packet size supported
2539 * is 20 bytes in each direction, hence the 5 fixed
2542 #define DPA_AUX_CH_CTL 0x64010
2543 #define DPA_AUX_CH_DATA1 0x64014
2544 #define DPA_AUX_CH_DATA2 0x64018
2545 #define DPA_AUX_CH_DATA3 0x6401c
2546 #define DPA_AUX_CH_DATA4 0x64020
2547 #define DPA_AUX_CH_DATA5 0x64024
2549 #define DPB_AUX_CH_CTL 0x64110
2550 #define DPB_AUX_CH_DATA1 0x64114
2551 #define DPB_AUX_CH_DATA2 0x64118
2552 #define DPB_AUX_CH_DATA3 0x6411c
2553 #define DPB_AUX_CH_DATA4 0x64120
2554 #define DPB_AUX_CH_DATA5 0x64124
2556 #define DPC_AUX_CH_CTL 0x64210
2557 #define DPC_AUX_CH_DATA1 0x64214
2558 #define DPC_AUX_CH_DATA2 0x64218
2559 #define DPC_AUX_CH_DATA3 0x6421c
2560 #define DPC_AUX_CH_DATA4 0x64220
2561 #define DPC_AUX_CH_DATA5 0x64224
2563 #define DPD_AUX_CH_CTL 0x64310
2564 #define DPD_AUX_CH_DATA1 0x64314
2565 #define DPD_AUX_CH_DATA2 0x64318
2566 #define DPD_AUX_CH_DATA3 0x6431c
2567 #define DPD_AUX_CH_DATA4 0x64320
2568 #define DPD_AUX_CH_DATA5 0x64324
2570 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2571 #define DP_AUX_CH_CTL_DONE (1 << 30)
2572 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2573 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2574 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2575 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2576 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2577 #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2578 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2579 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2580 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2581 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2582 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2583 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2584 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2585 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2586 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2587 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2588 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2589 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2590 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2593 * Computing GMCH M and N values for the Display Port link
2595 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2597 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2599 * The GMCH value is used internally
2601 * bytes_per_pixel is the number of bytes coming out of the plane,
2602 * which is after the LUTs, so we want the bytes for our color format.
2603 * For our current usage, this is always 3, one byte for R, G and B.
2605 #define _PIPEA_GMCH_DATA_M 0x70050
2606 #define _PIPEB_GMCH_DATA_M 0x71050
2608 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2609 #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2610 #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2612 #define PIPE_GMCH_DATA_M_MASK (0xffffff)
2614 #define _PIPEA_GMCH_DATA_N 0x70054
2615 #define _PIPEB_GMCH_DATA_N 0x71054
2616 #define PIPE_GMCH_DATA_N_MASK (0xffffff)
2619 * Computing Link M and N values for the Display Port link
2621 * Link M / N = pixel_clock / ls_clk
2623 * (the DP spec calls pixel_clock the 'strm_clk')
2625 * The Link value is transmitted in the Main Stream
2626 * Attributes and VB-ID.
2629 #define _PIPEA_DP_LINK_M 0x70060
2630 #define _PIPEB_DP_LINK_M 0x71060
2631 #define PIPEA_DP_LINK_M_MASK (0xffffff)
2633 #define _PIPEA_DP_LINK_N 0x70064
2634 #define _PIPEB_DP_LINK_N 0x71064
2635 #define PIPEA_DP_LINK_N_MASK (0xffffff)
2637 #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2638 #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2639 #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2640 #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2642 /* Display & cursor control */
2645 #define _PIPEADSL 0x70000
2646 #define DSL_LINEMASK_GEN2 0x00000fff
2647 #define DSL_LINEMASK_GEN3 0x00001fff
2648 #define _PIPEACONF 0x70008
2649 #define PIPECONF_ENABLE (1<<31)
2650 #define PIPECONF_DISABLE 0
2651 #define PIPECONF_DOUBLE_WIDE (1<<30)
2652 #define I965_PIPECONF_ACTIVE (1<<30)
2653 #define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
2654 #define PIPECONF_SINGLE_WIDE 0
2655 #define PIPECONF_PIPE_UNLOCKED 0
2656 #define PIPECONF_PIPE_LOCKED (1<<25)
2657 #define PIPECONF_PALETTE 0
2658 #define PIPECONF_GAMMA (1<<24)
2659 #define PIPECONF_FORCE_BORDER (1<<25)
2660 #define PIPECONF_INTERLACE_MASK (7 << 21)
2661 #define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
2662 /* Note that pre-gen3 does not support interlaced display directly. Panel
2663 * fitting must be disabled on pre-ilk for interlaced. */
2664 #define PIPECONF_PROGRESSIVE (0 << 21)
2665 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2666 #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2667 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2668 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2669 /* Ironlake and later have a complete new set of values for interlaced. PFIT
2670 * means panel fitter required, PF means progressive fetch, DBL means power
2671 * saving pixel doubling. */
2672 #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2673 #define PIPECONF_INTERLACED_ILK (3 << 21)
2674 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2675 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
2676 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2677 #define PIPECONF_BPP_MASK (0x000000e0)
2678 #define PIPECONF_BPP_8 (0<<5)
2679 #define PIPECONF_BPP_10 (1<<5)
2680 #define PIPECONF_BPP_6 (2<<5)
2681 #define PIPECONF_BPP_12 (3<<5)
2682 #define PIPECONF_DITHER_EN (1<<4)
2683 #define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2684 #define PIPECONF_DITHER_TYPE_SP (0<<2)
2685 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2686 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2687 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2688 #define _PIPEASTAT 0x70024
2689 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2690 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
2691 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2692 #define PIPE_CRC_DONE_ENABLE (1UL<<28)
2693 #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2694 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
2695 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2696 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2697 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2698 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2699 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26)
2700 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2701 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2702 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2703 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2704 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2705 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2706 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
2707 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2708 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2709 #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2710 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2711 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2712 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2713 #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10)
2714 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2715 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2716 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2717 #define PIPE_DPST_EVENT_STATUS (1UL<<7)
2718 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2719 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2720 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2721 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2722 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2723 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2724 #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2725 #define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2726 #define PIPE_8BPC (0 << 5)
2727 #define PIPE_10BPC (1 << 5)
2728 #define PIPE_6BPC (2 << 5)
2729 #define PIPE_12BPC (3 << 5)
2731 #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2732 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
2733 #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2734 #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2735 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2736 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2738 #define VLV_DPFLIPSTAT 0x70028
2739 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
2740 #define PIPEB_HLINE_INT_EN (1<<28)
2741 #define PIPEB_VBLANK_INT_EN (1<<27)
2742 #define SPRITED_FLIPDONE_INT_EN (1<<26)
2743 #define SPRITEC_FLIPDONE_INT_EN (1<<25)
2744 #define PLANEB_FLIPDONE_INT_EN (1<<24)
2745 #define PIPEA_LINE_COMPARE_INT_EN (1<<21)
2746 #define PIPEA_HLINE_INT_EN (1<<20)
2747 #define PIPEA_VBLANK_INT_EN (1<<19)
2748 #define SPRITEB_FLIPDONE_INT_EN (1<<18)
2749 #define SPRITEA_FLIPDONE_INT_EN (1<<17)
2750 #define PLANEA_FLIPDONE_INT_EN (1<<16)
2752 #define DPINVGTT 0x7002c /* VLV only */
2753 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
2754 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
2755 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
2756 #define SPRITEC_INVALID_GTT_INT_EN (1<<20)
2757 #define PLANEB_INVALID_GTT_INT_EN (1<<19)
2758 #define SPRITEB_INVALID_GTT_INT_EN (1<<18)
2759 #define SPRITEA_INVALID_GTT_INT_EN (1<<17)
2760 #define PLANEA_INVALID_GTT_INT_EN (1<<16)
2761 #define DPINVGTT_EN_MASK 0xff0000
2762 #define CURSORB_INVALID_GTT_STATUS (1<<7)
2763 #define CURSORA_INVALID_GTT_STATUS (1<<6)
2764 #define SPRITED_INVALID_GTT_STATUS (1<<5)
2765 #define SPRITEC_INVALID_GTT_STATUS (1<<4)
2766 #define PLANEB_INVALID_GTT_STATUS (1<<3)
2767 #define SPRITEB_INVALID_GTT_STATUS (1<<2)
2768 #define SPRITEA_INVALID_GTT_STATUS (1<<1)
2769 #define PLANEA_INVALID_GTT_STATUS (1<<0)
2770 #define DPINVGTT_STATUS_MASK 0xff
2772 #define DSPARB 0x70030
2773 #define DSPARB_CSTART_MASK (0x7f << 7)
2774 #define DSPARB_CSTART_SHIFT 7
2775 #define DSPARB_BSTART_MASK (0x7f)
2776 #define DSPARB_BSTART_SHIFT 0
2777 #define DSPARB_BEND_SHIFT 9 /* on 855 */
2778 #define DSPARB_AEND_SHIFT 0
2780 #define DSPFW1 0x70034
2781 #define DSPFW_SR_SHIFT 23
2782 #define DSPFW_SR_MASK (0x1ff<<23)
2783 #define DSPFW_CURSORB_SHIFT 16
2784 #define DSPFW_CURSORB_MASK (0x3f<<16)
2785 #define DSPFW_PLANEB_SHIFT 8
2786 #define DSPFW_PLANEB_MASK (0x7f<<8)
2787 #define DSPFW_PLANEA_MASK (0x7f)
2788 #define DSPFW2 0x70038
2789 #define DSPFW_CURSORA_MASK 0x00003f00
2790 #define DSPFW_CURSORA_SHIFT 8
2791 #define DSPFW_PLANEC_MASK (0x7f)
2792 #define DSPFW3 0x7003c
2793 #define DSPFW_HPLL_SR_EN (1<<31)
2794 #define DSPFW_CURSOR_SR_SHIFT 24
2795 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
2796 #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2797 #define DSPFW_HPLL_CURSOR_SHIFT 16
2798 #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2799 #define DSPFW_HPLL_SR_MASK (0x1ff)
2801 /* drain latency register values*/
2802 #define DRAIN_LATENCY_PRECISION_32 32
2803 #define DRAIN_LATENCY_PRECISION_16 16
2804 #define VLV_DDL1 0x70050
2805 #define DDL_CURSORA_PRECISION_32 (1<<31)
2806 #define DDL_CURSORA_PRECISION_16 (0<<31)
2807 #define DDL_CURSORA_SHIFT 24
2808 #define DDL_PLANEA_PRECISION_32 (1<<7)
2809 #define DDL_PLANEA_PRECISION_16 (0<<7)
2810 #define VLV_DDL2 0x70054
2811 #define DDL_CURSORB_PRECISION_32 (1<<31)
2812 #define DDL_CURSORB_PRECISION_16 (0<<31)
2813 #define DDL_CURSORB_SHIFT 24
2814 #define DDL_PLANEB_PRECISION_32 (1<<7)
2815 #define DDL_PLANEB_PRECISION_16 (0<<7)
2817 /* FIFO watermark sizes etc */
2818 #define G4X_FIFO_LINE_SIZE 64
2819 #define I915_FIFO_LINE_SIZE 64
2820 #define I830_FIFO_LINE_SIZE 32
2822 #define VALLEYVIEW_FIFO_SIZE 255
2823 #define G4X_FIFO_SIZE 127
2824 #define I965_FIFO_SIZE 512
2825 #define I945_FIFO_SIZE 127
2826 #define I915_FIFO_SIZE 95
2827 #define I855GM_FIFO_SIZE 127 /* In cachelines */
2828 #define I830_FIFO_SIZE 95
2830 #define VALLEYVIEW_MAX_WM 0xff
2831 #define G4X_MAX_WM 0x3f
2832 #define I915_MAX_WM 0x3f
2834 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2835 #define PINEVIEW_FIFO_LINE_SIZE 64
2836 #define PINEVIEW_MAX_WM 0x1ff
2837 #define PINEVIEW_DFT_WM 0x3f
2838 #define PINEVIEW_DFT_HPLLOFF_WM 0
2839 #define PINEVIEW_GUARD_WM 10
2840 #define PINEVIEW_CURSOR_FIFO 64
2841 #define PINEVIEW_CURSOR_MAX_WM 0x3f
2842 #define PINEVIEW_CURSOR_DFT_WM 0
2843 #define PINEVIEW_CURSOR_GUARD_WM 5
2845 #define VALLEYVIEW_CURSOR_MAX_WM 64
2846 #define I965_CURSOR_FIFO 64
2847 #define I965_CURSOR_MAX_WM 32
2848 #define I965_CURSOR_DFT_WM 8
2850 /* define the Watermark register on Ironlake */
2851 #define WM0_PIPEA_ILK 0x45100
2852 #define WM0_PIPE_PLANE_MASK (0x7f<<16)
2853 #define WM0_PIPE_PLANE_SHIFT 16
2854 #define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2855 #define WM0_PIPE_SPRITE_SHIFT 8
2856 #define WM0_PIPE_CURSOR_MASK (0x1f)
2858 #define WM0_PIPEB_ILK 0x45104
2859 #define WM0_PIPEC_IVB 0x45200
2860 #define WM1_LP_ILK 0x45108
2861 #define WM1_LP_SR_EN (1<<31)
2862 #define WM1_LP_LATENCY_SHIFT 24
2863 #define WM1_LP_LATENCY_MASK (0x7f<<24)
2864 #define WM1_LP_FBC_MASK (0xf<<20)
2865 #define WM1_LP_FBC_SHIFT 20
2866 #define WM1_LP_SR_MASK (0x1ff<<8)
2867 #define WM1_LP_SR_SHIFT 8
2868 #define WM1_LP_CURSOR_MASK (0x3f)
2869 #define WM2_LP_ILK 0x4510c
2870 #define WM2_LP_EN (1<<31)
2871 #define WM3_LP_ILK 0x45110
2872 #define WM3_LP_EN (1<<31)
2873 #define WM1S_LP_ILK 0x45120
2874 #define WM2S_LP_IVB 0x45124
2875 #define WM3S_LP_IVB 0x45128
2876 #define WM1S_LP_EN (1<<31)
2878 /* Memory latency timer register */
2879 #define MLTR_ILK 0x11222
2880 #define MLTR_WM1_SHIFT 0
2881 #define MLTR_WM2_SHIFT 8
2882 /* the unit of memory self-refresh latency time is 0.5us */
2883 #define ILK_SRLT_MASK 0x3f
2884 #define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2885 #define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2886 #define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2888 /* define the fifo size on Ironlake */
2889 #define ILK_DISPLAY_FIFO 128
2890 #define ILK_DISPLAY_MAXWM 64
2891 #define ILK_DISPLAY_DFTWM 8
2892 #define ILK_CURSOR_FIFO 32
2893 #define ILK_CURSOR_MAXWM 16
2894 #define ILK_CURSOR_DFTWM 8
2896 #define ILK_DISPLAY_SR_FIFO 512
2897 #define ILK_DISPLAY_MAX_SRWM 0x1ff
2898 #define ILK_DISPLAY_DFT_SRWM 0x3f
2899 #define ILK_CURSOR_SR_FIFO 64
2900 #define ILK_CURSOR_MAX_SRWM 0x3f
2901 #define ILK_CURSOR_DFT_SRWM 8
2903 #define ILK_FIFO_LINE_SIZE 64
2905 /* define the WM info on Sandybridge */
2906 #define SNB_DISPLAY_FIFO 128
2907 #define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2908 #define SNB_DISPLAY_DFTWM 8
2909 #define SNB_CURSOR_FIFO 32
2910 #define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2911 #define SNB_CURSOR_DFTWM 8
2913 #define SNB_DISPLAY_SR_FIFO 512
2914 #define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2915 #define SNB_DISPLAY_DFT_SRWM 0x3f
2916 #define SNB_CURSOR_SR_FIFO 64
2917 #define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2918 #define SNB_CURSOR_DFT_SRWM 8
2920 #define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2922 #define SNB_FIFO_LINE_SIZE 64
2925 /* the address where we get all kinds of latency value */
2926 #define SSKPD 0x5d10
2927 #define SSKPD_WM_MASK 0x3f
2928 #define SSKPD_WM0_SHIFT 0
2929 #define SSKPD_WM1_SHIFT 8
2930 #define SSKPD_WM2_SHIFT 16
2931 #define SSKPD_WM3_SHIFT 24
2933 #define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2934 #define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2935 #define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2936 #define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2937 #define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2940 * The two pipe frame counter registers are not synchronized, so
2941 * reading a stable value is somewhat tricky. The following code
2945 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2946 * PIPE_FRAME_HIGH_SHIFT;
2947 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2948 * PIPE_FRAME_LOW_SHIFT);
2949 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2950 * PIPE_FRAME_HIGH_SHIFT);
2951 * } while (high1 != high2);
2952 * frame = (high1 << 8) | low1;
2954 #define _PIPEAFRAMEHIGH 0x70040
2955 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
2956 #define PIPE_FRAME_HIGH_SHIFT 0
2957 #define _PIPEAFRAMEPIXEL 0x70044
2958 #define PIPE_FRAME_LOW_MASK 0xff000000
2959 #define PIPE_FRAME_LOW_SHIFT 24
2960 #define PIPE_PIXEL_MASK 0x00ffffff
2961 #define PIPE_PIXEL_SHIFT 0
2962 /* GM45+ just has to be different */
2963 #define _PIPEA_FRMCOUNT_GM45 0x70040
2964 #define _PIPEA_FLIPCOUNT_GM45 0x70044
2965 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2967 /* Cursor A & B regs */
2968 #define _CURACNTR 0x70080
2969 /* Old style CUR*CNTR flags (desktop 8xx) */
2970 #define CURSOR_ENABLE 0x80000000
2971 #define CURSOR_GAMMA_ENABLE 0x40000000
2972 #define CURSOR_STRIDE_MASK 0x30000000
2973 #define CURSOR_FORMAT_SHIFT 24
2974 #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2975 #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2976 #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2977 #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2978 #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2979 #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2980 /* New style CUR*CNTR flags */
2981 #define CURSOR_MODE 0x27
2982 #define CURSOR_MODE_DISABLE 0x00
2983 #define CURSOR_MODE_64_32B_AX 0x07
2984 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2985 #define MCURSOR_PIPE_SELECT (1 << 28)
2986 #define MCURSOR_PIPE_A 0x00
2987 #define MCURSOR_PIPE_B (1 << 28)
2988 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2989 #define _CURABASE 0x70084
2990 #define _CURAPOS 0x70088
2991 #define CURSOR_POS_MASK 0x007FF
2992 #define CURSOR_POS_SIGN 0x8000
2993 #define CURSOR_X_SHIFT 0
2994 #define CURSOR_Y_SHIFT 16
2995 #define CURSIZE 0x700a0
2996 #define _CURBCNTR 0x700c0
2997 #define _CURBBASE 0x700c4
2998 #define _CURBPOS 0x700c8
3000 #define _CURBCNTR_IVB 0x71080
3001 #define _CURBBASE_IVB 0x71084
3002 #define _CURBPOS_IVB 0x71088
3004 #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3005 #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3006 #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3008 #define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3009 #define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3010 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3012 /* Display A control */
3013 #define _DSPACNTR 0x70180
3014 #define DISPLAY_PLANE_ENABLE (1<<31)
3015 #define DISPLAY_PLANE_DISABLE 0
3016 #define DISPPLANE_GAMMA_ENABLE (1<<30)
3017 #define DISPPLANE_GAMMA_DISABLE 0
3018 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3019 #define DISPPLANE_YUV422 (0x0<<26)
3020 #define DISPPLANE_8BPP (0x2<<26)
3021 #define DISPPLANE_BGRA555 (0x3<<26)
3022 #define DISPPLANE_BGRX555 (0x4<<26)
3023 #define DISPPLANE_BGRX565 (0x5<<26)
3024 #define DISPPLANE_BGRX888 (0x6<<26)
3025 #define DISPPLANE_BGRA888 (0x7<<26)
3026 #define DISPPLANE_RGBX101010 (0x8<<26)
3027 #define DISPPLANE_RGBA101010 (0x9<<26)
3028 #define DISPPLANE_BGRX101010 (0xa<<26)
3029 #define DISPPLANE_RGBX161616 (0xc<<26)
3030 #define DISPPLANE_RGBX888 (0xe<<26)
3031 #define DISPPLANE_RGBA888 (0xf<<26)
3032 #define DISPPLANE_STEREO_ENABLE (1<<25)
3033 #define DISPPLANE_STEREO_DISABLE 0
3034 #define DISPPLANE_SEL_PIPE_SHIFT 24
3035 #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3036 #define DISPPLANE_SEL_PIPE_A 0
3037 #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3038 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3039 #define DISPPLANE_SRC_KEY_DISABLE 0
3040 #define DISPPLANE_LINE_DOUBLE (1<<20)
3041 #define DISPPLANE_NO_LINE_DOUBLE 0
3042 #define DISPPLANE_STEREO_POLARITY_FIRST 0
3043 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3044 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3045 #define DISPPLANE_TILED (1<<10)
3046 #define _DSPAADDR 0x70184
3047 #define _DSPASTRIDE 0x70188
3048 #define _DSPAPOS 0x7018C /* reserved */
3049 #define _DSPASIZE 0x70190
3050 #define _DSPASURF 0x7019C /* 965+ only */
3051 #define _DSPATILEOFF 0x701A4 /* 965+ only */
3052 #define _DSPAOFFSET 0x701A4 /* HSW */
3053 #define _DSPASURFLIVE 0x701AC
3055 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
3056 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
3057 #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
3058 #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
3059 #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
3060 #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
3061 #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
3062 #define DSPLINOFF(plane) DSPADDR(plane)
3063 #define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)
3064 #define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE)
3066 /* Display/Sprite base address macros */
3067 #define DISP_BASEADDR_MASK (0xfffff000)
3068 #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3069 #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3070 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \
3071 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
3074 #define SWF00 0x71410
3075 #define SWF01 0x71414
3076 #define SWF02 0x71418
3077 #define SWF03 0x7141c
3078 #define SWF04 0x71420
3079 #define SWF05 0x71424
3080 #define SWF06 0x71428
3081 #define SWF10 0x70410
3082 #define SWF11 0x70414
3083 #define SWF14 0x71420
3084 #define SWF30 0x72414
3085 #define SWF31 0x72418
3086 #define SWF32 0x7241c
3089 #define _PIPEBDSL 0x71000
3090 #define _PIPEBCONF 0x71008
3091 #define _PIPEBSTAT 0x71024
3092 #define _PIPEBFRAMEHIGH 0x71040
3093 #define _PIPEBFRAMEPIXEL 0x71044
3094 #define _PIPEB_FRMCOUNT_GM45 0x71040
3095 #define _PIPEB_FLIPCOUNT_GM45 0x71044
3098 /* Display B control */
3099 #define _DSPBCNTR 0x71180
3100 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3101 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
3102 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3103 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3104 #define _DSPBADDR 0x71184
3105 #define _DSPBSTRIDE 0x71188
3106 #define _DSPBPOS 0x7118C
3107 #define _DSPBSIZE 0x71190
3108 #define _DSPBSURF 0x7119C
3109 #define _DSPBTILEOFF 0x711A4
3110 #define _DSPBOFFSET 0x711A4
3111 #define _DSPBSURFLIVE 0x711AC
3113 /* Sprite A control */
3114 #define _DVSACNTR 0x72180
3115 #define DVS_ENABLE (1<<31)
3116 #define DVS_GAMMA_ENABLE (1<<30)
3117 #define DVS_PIXFORMAT_MASK (3<<25)
3118 #define DVS_FORMAT_YUV422 (0<<25)
3119 #define DVS_FORMAT_RGBX101010 (1<<25)
3120 #define DVS_FORMAT_RGBX888 (2<<25)
3121 #define DVS_FORMAT_RGBX161616 (3<<25)
3122 #define DVS_SOURCE_KEY (1<<22)
3123 #define DVS_RGB_ORDER_XBGR (1<<20)
3124 #define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3125 #define DVS_YUV_ORDER_YUYV (0<<16)
3126 #define DVS_YUV_ORDER_UYVY (1<<16)
3127 #define DVS_YUV_ORDER_YVYU (2<<16)
3128 #define DVS_YUV_ORDER_VYUY (3<<16)
3129 #define DVS_DEST_KEY (1<<2)
3130 #define DVS_TRICKLE_FEED_DISABLE (1<<14)
3131 #define DVS_TILED (1<<10)
3132 #define _DVSALINOFF 0x72184
3133 #define _DVSASTRIDE 0x72188
3134 #define _DVSAPOS 0x7218c
3135 #define _DVSASIZE 0x72190
3136 #define _DVSAKEYVAL 0x72194
3137 #define _DVSAKEYMSK 0x72198
3138 #define _DVSASURF 0x7219c
3139 #define _DVSAKEYMAXVAL 0x721a0
3140 #define _DVSATILEOFF 0x721a4
3141 #define _DVSASURFLIVE 0x721ac
3142 #define _DVSASCALE 0x72204
3143 #define DVS_SCALE_ENABLE (1<<31)
3144 #define DVS_FILTER_MASK (3<<29)
3145 #define DVS_FILTER_MEDIUM (0<<29)
3146 #define DVS_FILTER_ENHANCING (1<<29)
3147 #define DVS_FILTER_SOFTENING (2<<29)
3148 #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3149 #define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3150 #define _DVSAGAMC 0x72300
3152 #define _DVSBCNTR 0x73180
3153 #define _DVSBLINOFF 0x73184
3154 #define _DVSBSTRIDE 0x73188
3155 #define _DVSBPOS 0x7318c
3156 #define _DVSBSIZE 0x73190
3157 #define _DVSBKEYVAL 0x73194
3158 #define _DVSBKEYMSK 0x73198
3159 #define _DVSBSURF 0x7319c
3160 #define _DVSBKEYMAXVAL 0x731a0
3161 #define _DVSBTILEOFF 0x731a4
3162 #define _DVSBSURFLIVE 0x731ac
3163 #define _DVSBSCALE 0x73204
3164 #define _DVSBGAMC 0x73300
3166 #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3167 #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3168 #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3169 #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3170 #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3171 #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3172 #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3173 #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3174 #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3175 #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3176 #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3177 #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3179 #define _SPRA_CTL 0x70280
3180 #define SPRITE_ENABLE (1<<31)
3181 #define SPRITE_GAMMA_ENABLE (1<<30)
3182 #define SPRITE_PIXFORMAT_MASK (7<<25)
3183 #define SPRITE_FORMAT_YUV422 (0<<25)
3184 #define SPRITE_FORMAT_RGBX101010 (1<<25)
3185 #define SPRITE_FORMAT_RGBX888 (2<<25)
3186 #define SPRITE_FORMAT_RGBX161616 (3<<25)
3187 #define SPRITE_FORMAT_YUV444 (4<<25)
3188 #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
3189 #define SPRITE_CSC_ENABLE (1<<24)
3190 #define SPRITE_SOURCE_KEY (1<<22)
3191 #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3192 #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3193 #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3194 #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3195 #define SPRITE_YUV_ORDER_YUYV (0<<16)
3196 #define SPRITE_YUV_ORDER_UYVY (1<<16)
3197 #define SPRITE_YUV_ORDER_YVYU (2<<16)
3198 #define SPRITE_YUV_ORDER_VYUY (3<<16)
3199 #define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3200 #define SPRITE_INT_GAMMA_ENABLE (1<<13)
3201 #define SPRITE_TILED (1<<10)
3202 #define SPRITE_DEST_KEY (1<<2)
3203 #define _SPRA_LINOFF 0x70284
3204 #define _SPRA_STRIDE 0x70288
3205 #define _SPRA_POS 0x7028c
3206 #define _SPRA_SIZE 0x70290
3207 #define _SPRA_KEYVAL 0x70294
3208 #define _SPRA_KEYMSK 0x70298
3209 #define _SPRA_SURF 0x7029c
3210 #define _SPRA_KEYMAX 0x702a0
3211 #define _SPRA_TILEOFF 0x702a4
3212 #define _SPRA_OFFSET 0x702a4
3213 #define _SPRA_SURFLIVE 0x702ac
3214 #define _SPRA_SCALE 0x70304
3215 #define SPRITE_SCALE_ENABLE (1<<31)
3216 #define SPRITE_FILTER_MASK (3<<29)
3217 #define SPRITE_FILTER_MEDIUM (0<<29)
3218 #define SPRITE_FILTER_ENHANCING (1<<29)
3219 #define SPRITE_FILTER_SOFTENING (2<<29)
3220 #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3221 #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3222 #define _SPRA_GAMC 0x70400
3224 #define _SPRB_CTL 0x71280
3225 #define _SPRB_LINOFF 0x71284
3226 #define _SPRB_STRIDE 0x71288
3227 #define _SPRB_POS 0x7128c
3228 #define _SPRB_SIZE 0x71290
3229 #define _SPRB_KEYVAL 0x71294
3230 #define _SPRB_KEYMSK 0x71298
3231 #define _SPRB_SURF 0x7129c
3232 #define _SPRB_KEYMAX 0x712a0
3233 #define _SPRB_TILEOFF 0x712a4
3234 #define _SPRB_OFFSET 0x712a4
3235 #define _SPRB_SURFLIVE 0x712ac
3236 #define _SPRB_SCALE 0x71304
3237 #define _SPRB_GAMC 0x71400
3239 #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3240 #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3241 #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3242 #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3243 #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3244 #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3245 #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3246 #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3247 #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3248 #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3249 #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3250 #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3251 #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3252 #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3255 #define VGACNTRL 0x71400
3256 # define VGA_DISP_DISABLE (1 << 31)
3257 # define VGA_2X_MODE (1 << 30)
3258 # define VGA_PIPE_B_SELECT (1 << 29)
3262 #define CPU_VGACNTRL 0x41000
3264 #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3265 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3266 #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3267 #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3268 #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3269 #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3270 #define DIGITAL_PORTA_NO_DETECT (0 << 0)
3271 #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3272 #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3274 /* refresh rate hardware control */
3275 #define RR_HW_CTL 0x45300
3276 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3277 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3279 #define FDI_PLL_BIOS_0 0x46000
3280 #define FDI_PLL_FB_CLOCK_MASK 0xff
3281 #define FDI_PLL_BIOS_1 0x46004
3282 #define FDI_PLL_BIOS_2 0x46008
3283 #define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3284 #define DISPLAY_PORT_PLL_BIOS_1 0x46010
3285 #define DISPLAY_PORT_PLL_BIOS_2 0x46014
3287 #define PCH_3DCGDIS0 0x46020
3288 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3289 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3291 #define PCH_3DCGDIS1 0x46024
3292 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3294 #define FDI_PLL_FREQ_CTL 0x46030
3295 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3296 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3297 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3300 #define _PIPEA_DATA_M1 0x60030
3301 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3302 #define TU_SIZE_MASK 0x7e000000
3303 #define PIPE_DATA_M1_OFFSET 0
3304 #define _PIPEA_DATA_N1 0x60034
3305 #define PIPE_DATA_N1_OFFSET 0
3307 #define _PIPEA_DATA_M2 0x60038
3308 #define PIPE_DATA_M2_OFFSET 0
3309 #define _PIPEA_DATA_N2 0x6003c
3310 #define PIPE_DATA_N2_OFFSET 0
3312 #define _PIPEA_LINK_M1 0x60040
3313 #define PIPE_LINK_M1_OFFSET 0
3314 #define _PIPEA_LINK_N1 0x60044
3315 #define PIPE_LINK_N1_OFFSET 0
3317 #define _PIPEA_LINK_M2 0x60048
3318 #define PIPE_LINK_M2_OFFSET 0
3319 #define _PIPEA_LINK_N2 0x6004c
3320 #define PIPE_LINK_N2_OFFSET 0
3322 /* PIPEB timing regs are same start from 0x61000 */
3324 #define _PIPEB_DATA_M1 0x61030
3325 #define _PIPEB_DATA_N1 0x61034
3327 #define _PIPEB_DATA_M2 0x61038
3328 #define _PIPEB_DATA_N2 0x6103c
3330 #define _PIPEB_LINK_M1 0x61040
3331 #define _PIPEB_LINK_N1 0x61044
3333 #define _PIPEB_LINK_M2 0x61048
3334 #define _PIPEB_LINK_N2 0x6104c
3336 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
3337 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
3338 #define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
3339 #define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
3340 #define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
3341 #define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3342 #define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3343 #define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3345 /* CPU panel fitter */
3346 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3347 #define _PFA_CTL_1 0x68080
3348 #define _PFB_CTL_1 0x68880
3349 #define PF_ENABLE (1<<31)
3350 #define PF_PIPE_SEL_MASK_IVB (3<<29)
3351 #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
3352 #define PF_FILTER_MASK (3<<23)
3353 #define PF_FILTER_PROGRAMMED (0<<23)
3354 #define PF_FILTER_MED_3x3 (1<<23)
3355 #define PF_FILTER_EDGE_ENHANCE (2<<23)
3356 #define PF_FILTER_EDGE_SOFTEN (3<<23)
3357 #define _PFA_WIN_SZ 0x68074
3358 #define _PFB_WIN_SZ 0x68874
3359 #define _PFA_WIN_POS 0x68070
3360 #define _PFB_WIN_POS 0x68870
3361 #define _PFA_VSCALE 0x68084
3362 #define _PFB_VSCALE 0x68884
3363 #define _PFA_HSCALE 0x68090
3364 #define _PFB_HSCALE 0x68890
3366 #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3367 #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3368 #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3369 #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3370 #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
3372 /* legacy palette */
3373 #define _LGC_PALETTE_A 0x4a000
3374 #define _LGC_PALETTE_B 0x4a800
3375 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
3378 #define DE_MASTER_IRQ_CONTROL (1 << 31)
3379 #define DE_SPRITEB_FLIP_DONE (1 << 29)
3380 #define DE_SPRITEA_FLIP_DONE (1 << 28)
3381 #define DE_PLANEB_FLIP_DONE (1 << 27)
3382 #define DE_PLANEA_FLIP_DONE (1 << 26)
3383 #define DE_PCU_EVENT (1 << 25)
3384 #define DE_GTT_FAULT (1 << 24)
3385 #define DE_POISON (1 << 23)
3386 #define DE_PERFORM_COUNTER (1 << 22)
3387 #define DE_PCH_EVENT (1 << 21)
3388 #define DE_AUX_CHANNEL_A (1 << 20)
3389 #define DE_DP_A_HOTPLUG (1 << 19)
3390 #define DE_GSE (1 << 18)
3391 #define DE_PIPEB_VBLANK (1 << 15)
3392 #define DE_PIPEB_EVEN_FIELD (1 << 14)
3393 #define DE_PIPEB_ODD_FIELD (1 << 13)
3394 #define DE_PIPEB_LINE_COMPARE (1 << 12)
3395 #define DE_PIPEB_VSYNC (1 << 11)
3396 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3397 #define DE_PIPEA_VBLANK (1 << 7)
3398 #define DE_PIPEA_EVEN_FIELD (1 << 6)
3399 #define DE_PIPEA_ODD_FIELD (1 << 5)
3400 #define DE_PIPEA_LINE_COMPARE (1 << 4)
3401 #define DE_PIPEA_VSYNC (1 << 3)
3402 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3404 /* More Ivybridge lolz */
3405 #define DE_ERR_DEBUG_IVB (1<<30)
3406 #define DE_GSE_IVB (1<<29)
3407 #define DE_PCH_EVENT_IVB (1<<28)
3408 #define DE_DP_A_HOTPLUG_IVB (1<<27)
3409 #define DE_AUX_CHANNEL_A_IVB (1<<26)
3410 #define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
3411 #define DE_PLANEC_FLIP_DONE_IVB (1<<13)
3412 #define DE_PIPEC_VBLANK_IVB (1<<10)
3413 #define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3414 #define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3415 #define DE_PIPEB_VBLANK_IVB (1<<5)
3416 #define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3417 #define DE_PLANEA_FLIP_DONE_IVB (1<<3)
3418 #define DE_PIPEA_VBLANK_IVB (1<<0)
3420 #define VLV_MASTER_IER 0x4400c /* Gunit master IER */
3421 #define MASTER_INTERRUPT_ENABLE (1<<31)
3423 #define DEISR 0x44000
3424 #define DEIMR 0x44004
3425 #define DEIIR 0x44008
3426 #define DEIER 0x4400c
3429 * Note that for gen6+ the ring-specific interrupt bits do alias with the
3430 * corresponding bits in the per-ring interrupt control registers. */
3431 #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
3432 #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
3433 #define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
3434 #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
3435 #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
3436 #define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
3437 #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
3438 #define GT_PIPE_NOTIFY (1 << 4)
3439 #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
3440 #define GT_SYNC_STATUS (1 << 2)
3441 #define GT_USER_INTERRUPT (1 << 0)
3443 #define GTISR 0x44010
3444 #define GTIMR 0x44014
3445 #define GTIIR 0x44018
3446 #define GTIER 0x4401c
3448 #define ILK_DISPLAY_CHICKEN2 0x42004
3449 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
3450 #define ILK_ELPIN_409_SELECT (1 << 25)
3451 #define ILK_DPARB_GATE (1<<22)
3452 #define ILK_VSDPFD_FULL (1<<21)
3453 #define ILK_DISPLAY_CHICKEN_FUSES 0x42014
3454 #define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
3455 #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
3456 #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
3457 #define ILK_HDCP_DISABLE (1<<25)
3458 #define ILK_eDP_A_DISABLE (1<<24)
3459 #define ILK_DESKTOP (1<<23)
3461 #define ILK_DSPCLK_GATE_D 0x42020
3462 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
3463 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3464 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
3465 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
3466 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
3468 #define IVB_CHICKEN3 0x4200c
3469 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
3470 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
3472 #define DISP_ARB_CTL 0x45000
3473 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
3474 #define DISP_FBC_WM_DIS (1<<15)
3477 #define GEN7_COMMON_SLICE_CHICKEN1 0x7010
3478 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
3480 #define GEN7_L3CNTLREG1 0xB01C
3481 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
3482 #define GEN7_L3AGDIS (1<<19)
3484 #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
3485 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000
3487 #define GEN7_L3SQCREG4 0xb034
3488 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
3490 /* WaCatErrorRejectionIssue */
3491 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3492 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3494 #define HSW_FUSE_STRAP 0x42014
3495 #define HSW_CDCLK_LIMIT (1 << 24)
3499 /* south display engine interrupt: IBX */
3500 #define SDE_AUDIO_POWER_D (1 << 27)
3501 #define SDE_AUDIO_POWER_C (1 << 26)
3502 #define SDE_AUDIO_POWER_B (1 << 25)
3503 #define SDE_AUDIO_POWER_SHIFT (25)
3504 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
3505 #define SDE_GMBUS (1 << 24)
3506 #define SDE_AUDIO_HDCP_TRANSB (1 << 23)
3507 #define SDE_AUDIO_HDCP_TRANSA (1 << 22)
3508 #define SDE_AUDIO_HDCP_MASK (3 << 22)
3509 #define SDE_AUDIO_TRANSB (1 << 21)
3510 #define SDE_AUDIO_TRANSA (1 << 20)
3511 #define SDE_AUDIO_TRANS_MASK (3 << 20)
3512 #define SDE_POISON (1 << 19)
3514 #define SDE_FDI_RXB (1 << 17)
3515 #define SDE_FDI_RXA (1 << 16)
3516 #define SDE_FDI_MASK (3 << 16)
3517 #define SDE_AUXD (1 << 15)
3518 #define SDE_AUXC (1 << 14)
3519 #define SDE_AUXB (1 << 13)
3520 #define SDE_AUX_MASK (7 << 13)
3522 #define SDE_CRT_HOTPLUG (1 << 11)
3523 #define SDE_PORTD_HOTPLUG (1 << 10)
3524 #define SDE_PORTC_HOTPLUG (1 << 9)
3525 #define SDE_PORTB_HOTPLUG (1 << 8)
3526 #define SDE_SDVOB_HOTPLUG (1 << 6)
3527 #define SDE_HOTPLUG_MASK (0xf << 8)
3528 #define SDE_TRANSB_CRC_DONE (1 << 5)
3529 #define SDE_TRANSB_CRC_ERR (1 << 4)
3530 #define SDE_TRANSB_FIFO_UNDER (1 << 3)
3531 #define SDE_TRANSA_CRC_DONE (1 << 2)
3532 #define SDE_TRANSA_CRC_ERR (1 << 1)
3533 #define SDE_TRANSA_FIFO_UNDER (1 << 0)
3534 #define SDE_TRANS_MASK (0x3f)
3536 /* south display engine interrupt: CPT/PPT */
3537 #define SDE_AUDIO_POWER_D_CPT (1 << 31)
3538 #define SDE_AUDIO_POWER_C_CPT (1 << 30)
3539 #define SDE_AUDIO_POWER_B_CPT (1 << 29)
3540 #define SDE_AUDIO_POWER_SHIFT_CPT 29
3541 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3542 #define SDE_AUXD_CPT (1 << 27)
3543 #define SDE_AUXC_CPT (1 << 26)
3544 #define SDE_AUXB_CPT (1 << 25)
3545 #define SDE_AUX_MASK_CPT (7 << 25)
3546 #define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3547 #define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3548 #define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3549 #define SDE_CRT_HOTPLUG_CPT (1 << 19)
3550 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3551 SDE_PORTD_HOTPLUG_CPT | \
3552 SDE_PORTC_HOTPLUG_CPT | \
3553 SDE_PORTB_HOTPLUG_CPT)
3554 #define SDE_GMBUS_CPT (1 << 17)
3555 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3556 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3557 #define SDE_FDI_RXC_CPT (1 << 8)
3558 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3559 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3560 #define SDE_FDI_RXB_CPT (1 << 4)
3561 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3562 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3563 #define SDE_FDI_RXA_CPT (1 << 0)
3564 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3565 SDE_AUDIO_CP_REQ_B_CPT | \
3566 SDE_AUDIO_CP_REQ_A_CPT)
3567 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3568 SDE_AUDIO_CP_CHG_B_CPT | \
3569 SDE_AUDIO_CP_CHG_A_CPT)
3570 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3574 #define SDEISR 0xc4000
3575 #define SDEIMR 0xc4004
3576 #define SDEIIR 0xc4008
3577 #define SDEIER 0xc400c
3579 /* digital port hotplug */
3580 #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
3581 #define PORTD_HOTPLUG_ENABLE (1 << 20)
3582 #define PORTD_PULSE_DURATION_2ms (0)
3583 #define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3584 #define PORTD_PULSE_DURATION_6ms (2 << 18)
3585 #define PORTD_PULSE_DURATION_100ms (3 << 18)
3586 #define PORTD_PULSE_DURATION_MASK (3 << 18)
3587 #define PORTD_HOTPLUG_NO_DETECT (0)
3588 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3589 #define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3590 #define PORTC_HOTPLUG_ENABLE (1 << 12)
3591 #define PORTC_PULSE_DURATION_2ms (0)
3592 #define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3593 #define PORTC_PULSE_DURATION_6ms (2 << 10)
3594 #define PORTC_PULSE_DURATION_100ms (3 << 10)
3595 #define PORTC_PULSE_DURATION_MASK (3 << 10)
3596 #define PORTC_HOTPLUG_NO_DETECT (0)
3597 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3598 #define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3599 #define PORTB_HOTPLUG_ENABLE (1 << 4)
3600 #define PORTB_PULSE_DURATION_2ms (0)
3601 #define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3602 #define PORTB_PULSE_DURATION_6ms (2 << 2)
3603 #define PORTB_PULSE_DURATION_100ms (3 << 2)
3604 #define PORTB_PULSE_DURATION_MASK (3 << 2)
3605 #define PORTB_HOTPLUG_NO_DETECT (0)
3606 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3607 #define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3609 #define PCH_GPIOA 0xc5010
3610 #define PCH_GPIOB 0xc5014
3611 #define PCH_GPIOC 0xc5018
3612 #define PCH_GPIOD 0xc501c
3613 #define PCH_GPIOE 0xc5020
3614 #define PCH_GPIOF 0xc5024
3616 #define PCH_GMBUS0 0xc5100
3617 #define PCH_GMBUS1 0xc5104
3618 #define PCH_GMBUS2 0xc5108
3619 #define PCH_GMBUS3 0xc510c
3620 #define PCH_GMBUS4 0xc5110
3621 #define PCH_GMBUS5 0xc5120
3623 #define _PCH_DPLL_A 0xc6014
3624 #define _PCH_DPLL_B 0xc6018
3625 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3627 #define _PCH_FPA0 0xc6040
3628 #define FP_CB_TUNE (0x3<<22)
3629 #define _PCH_FPA1 0xc6044
3630 #define _PCH_FPB0 0xc6048
3631 #define _PCH_FPB1 0xc604c
3632 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
3633 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
3635 #define PCH_DPLL_TEST 0xc606c
3637 #define PCH_DREF_CONTROL 0xC6200
3638 #define DREF_CONTROL_MASK 0x7fc3
3639 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3640 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3641 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3642 #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
3643 #define DREF_SSC_SOURCE_DISABLE (0<<11)
3644 #define DREF_SSC_SOURCE_ENABLE (2<<11)
3645 #define DREF_SSC_SOURCE_MASK (3<<11)
3646 #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3647 #define DREF_NONSPREAD_CK505_ENABLE (1<<9)
3648 #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3649 #define DREF_NONSPREAD_SOURCE_MASK (3<<9)
3650 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3651 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3652 #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
3653 #define DREF_SSC4_DOWNSPREAD (0<<6)
3654 #define DREF_SSC4_CENTERSPREAD (1<<6)
3655 #define DREF_SSC1_DISABLE (0<<1)
3656 #define DREF_SSC1_ENABLE (1<<1)
3657 #define DREF_SSC4_DISABLE (0)
3658 #define DREF_SSC4_ENABLE (1)
3660 #define PCH_RAWCLK_FREQ 0xc6204
3661 #define FDL_TP1_TIMER_SHIFT 12
3662 #define FDL_TP1_TIMER_MASK (3<<12)
3663 #define FDL_TP2_TIMER_SHIFT 10
3664 #define FDL_TP2_TIMER_MASK (3<<10)
3665 #define RAWCLK_FREQ_MASK 0x3ff
3667 #define PCH_DPLL_TMR_CFG 0xc6208
3669 #define PCH_SSC4_PARMS 0xc6210
3670 #define PCH_SSC4_AUX_PARMS 0xc6214
3672 #define PCH_DPLL_SEL 0xc7000
3673 #define TRANSA_DPLL_ENABLE (1<<3)
3674 #define TRANSA_DPLLB_SEL (1<<0)
3675 #define TRANSA_DPLLA_SEL 0
3676 #define TRANSB_DPLL_ENABLE (1<<7)
3677 #define TRANSB_DPLLB_SEL (1<<4)
3678 #define TRANSB_DPLLA_SEL (0)
3679 #define TRANSC_DPLL_ENABLE (1<<11)
3680 #define TRANSC_DPLLB_SEL (1<<8)
3681 #define TRANSC_DPLLA_SEL (0)
3685 #define _TRANS_HTOTAL_A 0xe0000
3686 #define TRANS_HTOTAL_SHIFT 16
3687 #define TRANS_HACTIVE_SHIFT 0
3688 #define _TRANS_HBLANK_A 0xe0004
3689 #define TRANS_HBLANK_END_SHIFT 16
3690 #define TRANS_HBLANK_START_SHIFT 0
3691 #define _TRANS_HSYNC_A 0xe0008
3692 #define TRANS_HSYNC_END_SHIFT 16
3693 #define TRANS_HSYNC_START_SHIFT 0
3694 #define _TRANS_VTOTAL_A 0xe000c
3695 #define TRANS_VTOTAL_SHIFT 16
3696 #define TRANS_VACTIVE_SHIFT 0
3697 #define _TRANS_VBLANK_A 0xe0010
3698 #define TRANS_VBLANK_END_SHIFT 16
3699 #define TRANS_VBLANK_START_SHIFT 0
3700 #define _TRANS_VSYNC_A 0xe0014
3701 #define TRANS_VSYNC_END_SHIFT 16
3702 #define TRANS_VSYNC_START_SHIFT 0
3703 #define _TRANS_VSYNCSHIFT_A 0xe0028
3705 #define _TRANSA_DATA_M1 0xe0030
3706 #define _TRANSA_DATA_N1 0xe0034
3707 #define _TRANSA_DATA_M2 0xe0038
3708 #define _TRANSA_DATA_N2 0xe003c
3709 #define _TRANSA_DP_LINK_M1 0xe0040
3710 #define _TRANSA_DP_LINK_N1 0xe0044
3711 #define _TRANSA_DP_LINK_M2 0xe0048
3712 #define _TRANSA_DP_LINK_N2 0xe004c
3714 /* Per-transcoder DIP controls */
3716 #define _VIDEO_DIP_CTL_A 0xe0200
3717 #define _VIDEO_DIP_DATA_A 0xe0208
3718 #define _VIDEO_DIP_GCP_A 0xe0210
3720 #define _VIDEO_DIP_CTL_B 0xe1200
3721 #define _VIDEO_DIP_DATA_B 0xe1208
3722 #define _VIDEO_DIP_GCP_B 0xe1210
3724 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3725 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3726 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3728 #define VLV_VIDEO_DIP_CTL_A 0x60200
3729 #define VLV_VIDEO_DIP_DATA_A 0x60208
3730 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3732 #define VLV_VIDEO_DIP_CTL_B 0x61170
3733 #define VLV_VIDEO_DIP_DATA_B 0x61174
3734 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3736 #define VLV_TVIDEO_DIP_CTL(pipe) \
3737 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
3738 #define VLV_TVIDEO_DIP_DATA(pipe) \
3739 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
3740 #define VLV_TVIDEO_DIP_GCP(pipe) \
3741 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
3743 /* Haswell DIP controls */
3744 #define HSW_VIDEO_DIP_CTL_A 0x60200
3745 #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
3746 #define HSW_VIDEO_DIP_VS_DATA_A 0x60260
3747 #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
3748 #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
3749 #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3750 #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3751 #define HSW_VIDEO_DIP_VS_ECC_A 0x60280
3752 #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3753 #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3754 #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3755 #define HSW_VIDEO_DIP_GCP_A 0x60210
3757 #define HSW_VIDEO_DIP_CTL_B 0x61200
3758 #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
3759 #define HSW_VIDEO_DIP_VS_DATA_B 0x61260
3760 #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
3761 #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3762 #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3763 #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3764 #define HSW_VIDEO_DIP_VS_ECC_B 0x61280
3765 #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3766 #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3767 #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3768 #define HSW_VIDEO_DIP_GCP_B 0x61210
3770 #define HSW_TVIDEO_DIP_CTL(pipe) \
3771 _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
3772 #define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
3773 _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
3774 #define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
3775 _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
3776 #define HSW_TVIDEO_DIP_GCP(pipe) \
3777 _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
3779 #define _TRANS_HTOTAL_B 0xe1000
3780 #define _TRANS_HBLANK_B 0xe1004
3781 #define _TRANS_HSYNC_B 0xe1008
3782 #define _TRANS_VTOTAL_B 0xe100c
3783 #define _TRANS_VBLANK_B 0xe1010
3784 #define _TRANS_VSYNC_B 0xe1014
3785 #define _TRANS_VSYNCSHIFT_B 0xe1028
3787 #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3788 #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3789 #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3790 #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3791 #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3792 #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3793 #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3794 _TRANS_VSYNCSHIFT_B)
3796 #define _TRANSB_DATA_M1 0xe1030
3797 #define _TRANSB_DATA_N1 0xe1034
3798 #define _TRANSB_DATA_M2 0xe1038
3799 #define _TRANSB_DATA_N2 0xe103c
3800 #define _TRANSB_DP_LINK_M1 0xe1040
3801 #define _TRANSB_DP_LINK_N1 0xe1044
3802 #define _TRANSB_DP_LINK_M2 0xe1048
3803 #define _TRANSB_DP_LINK_N2 0xe104c
3805 #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3806 #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3807 #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3808 #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3809 #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3810 #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3811 #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3812 #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3814 #define _TRANSACONF 0xf0008
3815 #define _TRANSBCONF 0xf1008
3816 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3817 #define TRANS_DISABLE (0<<31)
3818 #define TRANS_ENABLE (1<<31)
3819 #define TRANS_STATE_MASK (1<<30)
3820 #define TRANS_STATE_DISABLE (0<<30)
3821 #define TRANS_STATE_ENABLE (1<<30)
3822 #define TRANS_FSYNC_DELAY_HB1 (0<<27)
3823 #define TRANS_FSYNC_DELAY_HB2 (1<<27)
3824 #define TRANS_FSYNC_DELAY_HB3 (2<<27)
3825 #define TRANS_FSYNC_DELAY_HB4 (3<<27)
3826 #define TRANS_DP_AUDIO_ONLY (1<<26)
3827 #define TRANS_DP_VIDEO_AUDIO (0<<26)
3828 #define TRANS_INTERLACE_MASK (7<<21)
3829 #define TRANS_PROGRESSIVE (0<<21)
3830 #define TRANS_INTERLACED (3<<21)
3831 #define TRANS_LEGACY_INTERLACED_ILK (2<<21)
3832 #define TRANS_8BPC (0<<5)
3833 #define TRANS_10BPC (1<<5)
3834 #define TRANS_6BPC (2<<5)
3835 #define TRANS_12BPC (3<<5)
3837 #define _TRANSA_CHICKEN1 0xf0060
3838 #define _TRANSB_CHICKEN1 0xf1060
3839 #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
3840 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
3841 #define _TRANSA_CHICKEN2 0xf0064
3842 #define _TRANSB_CHICKEN2 0xf1064
3843 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3844 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
3845 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
3847 #define SOUTH_CHICKEN1 0xc2000
3848 #define FDIA_PHASE_SYNC_SHIFT_OVR 19
3849 #define FDIA_PHASE_SYNC_SHIFT_EN 18
3850 #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3851 #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3852 #define FDI_BC_BIFURCATION_SELECT (1 << 12)
3853 #define SOUTH_CHICKEN2 0xc2004
3854 #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
3855 #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
3856 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
3858 #define _FDI_RXA_CHICKEN 0xc200c
3859 #define _FDI_RXB_CHICKEN 0xc2010
3860 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3861 #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3862 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3864 #define SOUTH_DSPCLK_GATE_D 0xc2020
3865 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3866 #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
3869 #define _FDI_TXA_CTL 0x60100
3870 #define _FDI_TXB_CTL 0x61100
3871 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3872 #define FDI_TX_DISABLE (0<<31)
3873 #define FDI_TX_ENABLE (1<<31)
3874 #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3875 #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3876 #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3877 #define FDI_LINK_TRAIN_NONE (3<<28)
3878 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3879 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3880 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3881 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3882 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3883 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3884 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3885 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3886 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3887 SNB has different settings. */
3888 /* SNB A-stepping */
3889 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3890 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3891 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3892 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3893 /* SNB B-stepping */
3894 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3895 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3896 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3897 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3898 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3899 #define FDI_DP_PORT_WIDTH_X1 (0<<19)
3900 #define FDI_DP_PORT_WIDTH_X2 (1<<19)
3901 #define FDI_DP_PORT_WIDTH_X3 (2<<19)
3902 #define FDI_DP_PORT_WIDTH_X4 (3<<19)
3903 #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3904 /* Ironlake: hardwired to 1 */
3905 #define FDI_TX_PLL_ENABLE (1<<14)
3907 /* Ivybridge has different bits for lolz */
3908 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3909 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3910 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3911 #define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3913 /* both Tx and Rx */
3914 #define FDI_COMPOSITE_SYNC (1<<11)
3915 #define FDI_LINK_TRAIN_AUTO (1<<10)
3916 #define FDI_SCRAMBLING_ENABLE (0<<7)
3917 #define FDI_SCRAMBLING_DISABLE (1<<7)
3919 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3920 #define _FDI_RXA_CTL 0xf000c
3921 #define _FDI_RXB_CTL 0xf100c
3922 #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3923 #define FDI_RX_ENABLE (1<<31)
3924 /* train, dp width same as FDI_TX */
3925 #define FDI_FS_ERRC_ENABLE (1<<27)
3926 #define FDI_FE_ERRC_ENABLE (1<<26)
3927 #define FDI_DP_PORT_WIDTH_X8 (7<<19)
3928 #define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
3929 #define FDI_8BPC (0<<16)
3930 #define FDI_10BPC (1<<16)
3931 #define FDI_6BPC (2<<16)
3932 #define FDI_12BPC (3<<16)
3933 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
3934 #define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3935 #define FDI_RX_PLL_ENABLE (1<<13)
3936 #define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3937 #define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3938 #define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3939 #define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3940 #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3941 #define FDI_PCDCLK (1<<4)
3943 #define FDI_AUTO_TRAINING (1<<10)
3944 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3945 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3946 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3947 #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3948 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3950 #define FDI_PORT_WIDTH_2X_LPT (1<<19)
3951 #define FDI_PORT_WIDTH_1X_LPT (0<<19)
3953 #define _FDI_RXA_MISC 0xf0010
3954 #define _FDI_RXB_MISC 0xf1010
3955 #define FDI_RX_PWRDN_LANE1_MASK (3<<26)
3956 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
3957 #define FDI_RX_PWRDN_LANE0_MASK (3<<24)
3958 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
3959 #define FDI_RX_TP1_TO_TP2_48 (2<<20)
3960 #define FDI_RX_TP1_TO_TP2_64 (3<<20)
3961 #define FDI_RX_FDI_DELAY_90 (0x90<<0)
3962 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3964 #define _FDI_RXA_TUSIZE1 0xf0030
3965 #define _FDI_RXA_TUSIZE2 0xf0038
3966 #define _FDI_RXB_TUSIZE1 0xf1030
3967 #define _FDI_RXB_TUSIZE2 0xf1038
3968 #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3969 #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3971 /* FDI_RX interrupt register format */
3972 #define FDI_RX_INTER_LANE_ALIGN (1<<10)
3973 #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3974 #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3975 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3976 #define FDI_RX_FS_CODE_ERR (1<<6)
3977 #define FDI_RX_FE_CODE_ERR (1<<5)
3978 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3979 #define FDI_RX_HDCP_LINK_FAIL (1<<3)
3980 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3981 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3982 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3984 #define _FDI_RXA_IIR 0xf0014
3985 #define _FDI_RXA_IMR 0xf0018
3986 #define _FDI_RXB_IIR 0xf1014
3987 #define _FDI_RXB_IMR 0xf1018
3988 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3989 #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3991 #define FDI_PLL_CTL_1 0xfe000
3992 #define FDI_PLL_CTL_2 0xfe004
3995 #define HDMIB 0xe1140
3996 #define PORT_ENABLE (1 << 31)
3997 #define TRANSCODER(pipe) ((pipe) << 30)
3998 #define TRANSCODER_CPT(pipe) ((pipe) << 29)
3999 #define TRANSCODER_MASK (1 << 30)
4000 #define TRANSCODER_MASK_CPT (3 << 29)
4001 #define COLOR_FORMAT_8bpc (0)
4002 #define COLOR_FORMAT_12bpc (3 << 26)
4003 #define SDVOB_HOTPLUG_ENABLE (1 << 23)
4004 #define SDVO_ENCODING (0)
4005 #define TMDS_ENCODING (2 << 10)
4006 #define NULL_PACKET_VSYNC_ENABLE (1 << 9)
4008 #define HDMI_MODE_SELECT (1 << 9)
4009 #define DVI_MODE_SELECT (0)
4010 #define SDVOB_BORDER_ENABLE (1 << 7)
4011 #define AUDIO_ENABLE (1 << 6)
4012 #define VSYNC_ACTIVE_HIGH (1 << 4)
4013 #define HSYNC_ACTIVE_HIGH (1 << 3)
4014 #define PORT_DETECTED (1 << 2)
4016 /* PCH SDVOB multiplex with HDMIB */
4017 #define PCH_SDVOB HDMIB
4019 #define HDMIC 0xe1150
4020 #define HDMID 0xe1160
4022 #define PCH_LVDS 0xe1180
4023 #define LVDS_DETECTED (1 << 1)
4025 /* vlv has 2 sets of panel control regs. */
4026 #define PIPEA_PP_STATUS 0x61200
4027 #define PIPEA_PP_CONTROL 0x61204
4028 #define PIPEA_PP_ON_DELAYS 0x61208
4029 #define PIPEA_PP_OFF_DELAYS 0x6120c
4030 #define PIPEA_PP_DIVISOR 0x61210
4032 #define PIPEB_PP_STATUS 0x61300
4033 #define PIPEB_PP_CONTROL 0x61304
4034 #define PIPEB_PP_ON_DELAYS 0x61308
4035 #define PIPEB_PP_OFF_DELAYS 0x6130c
4036 #define PIPEB_PP_DIVISOR 0x61310
4038 #define PCH_PP_STATUS 0xc7200
4039 #define PCH_PP_CONTROL 0xc7204
4040 #define PANEL_UNLOCK_REGS (0xabcd << 16)
4041 #define PANEL_UNLOCK_MASK (0xffff << 16)
4042 #define EDP_FORCE_VDD (1 << 3)
4043 #define EDP_BLC_ENABLE (1 << 2)
4044 #define PANEL_POWER_RESET (1 << 1)
4045 #define PANEL_POWER_OFF (0 << 0)
4046 #define PANEL_POWER_ON (1 << 0)
4047 #define PCH_PP_ON_DELAYS 0xc7208
4048 #define PANEL_PORT_SELECT_MASK (3 << 30)
4049 #define PANEL_PORT_SELECT_LVDS (0 << 30)
4050 #define PANEL_PORT_SELECT_DPA (1 << 30)
4051 #define EDP_PANEL (1 << 30)
4052 #define PANEL_PORT_SELECT_DPC (2 << 30)
4053 #define PANEL_PORT_SELECT_DPD (3 << 30)
4054 #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4055 #define PANEL_POWER_UP_DELAY_SHIFT 16
4056 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4057 #define PANEL_LIGHT_ON_DELAY_SHIFT 0
4059 #define PCH_PP_OFF_DELAYS 0xc720c
4060 #define PANEL_POWER_PORT_SELECT_MASK (0x3 << 30)
4061 #define PANEL_POWER_PORT_LVDS (0 << 30)
4062 #define PANEL_POWER_PORT_DP_A (1 << 30)
4063 #define PANEL_POWER_PORT_DP_C (2 << 30)
4064 #define PANEL_POWER_PORT_DP_D (3 << 30)
4065 #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4066 #define PANEL_POWER_DOWN_DELAY_SHIFT 16
4067 #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4068 #define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4070 #define PCH_PP_DIVISOR 0xc7210
4071 #define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4072 #define PP_REFERENCE_DIVIDER_SHIFT 8
4073 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4074 #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4076 #define PCH_DP_B 0xe4100
4077 #define PCH_DPB_AUX_CH_CTL 0xe4110
4078 #define PCH_DPB_AUX_CH_DATA1 0xe4114
4079 #define PCH_DPB_AUX_CH_DATA2 0xe4118
4080 #define PCH_DPB_AUX_CH_DATA3 0xe411c
4081 #define PCH_DPB_AUX_CH_DATA4 0xe4120
4082 #define PCH_DPB_AUX_CH_DATA5 0xe4124
4084 #define PCH_DP_C 0xe4200
4085 #define PCH_DPC_AUX_CH_CTL 0xe4210
4086 #define PCH_DPC_AUX_CH_DATA1 0xe4214
4087 #define PCH_DPC_AUX_CH_DATA2 0xe4218
4088 #define PCH_DPC_AUX_CH_DATA3 0xe421c
4089 #define PCH_DPC_AUX_CH_DATA4 0xe4220
4090 #define PCH_DPC_AUX_CH_DATA5 0xe4224
4092 #define PCH_DP_D 0xe4300
4093 #define PCH_DPD_AUX_CH_CTL 0xe4310
4094 #define PCH_DPD_AUX_CH_DATA1 0xe4314
4095 #define PCH_DPD_AUX_CH_DATA2 0xe4318
4096 #define PCH_DPD_AUX_CH_DATA3 0xe431c
4097 #define PCH_DPD_AUX_CH_DATA4 0xe4320
4098 #define PCH_DPD_AUX_CH_DATA5 0xe4324
4101 #define PORT_TRANS_A_SEL_CPT 0
4102 #define PORT_TRANS_B_SEL_CPT (1<<29)
4103 #define PORT_TRANS_C_SEL_CPT (2<<29)
4104 #define PORT_TRANS_SEL_MASK (3<<29)
4105 #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4106 #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4107 #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4109 #define TRANS_DP_CTL_A 0xe0300
4110 #define TRANS_DP_CTL_B 0xe1300
4111 #define TRANS_DP_CTL_C 0xe2300
4112 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4113 #define TRANS_DP_OUTPUT_ENABLE (1<<31)
4114 #define TRANS_DP_PORT_SEL_B (0<<29)
4115 #define TRANS_DP_PORT_SEL_C (1<<29)
4116 #define TRANS_DP_PORT_SEL_D (2<<29)
4117 #define TRANS_DP_PORT_SEL_NONE (3<<29)
4118 #define TRANS_DP_PORT_SEL_MASK (3<<29)
4119 #define TRANS_DP_AUDIO_ONLY (1<<26)
4120 #define TRANS_DP_ENH_FRAMING (1<<18)
4121 #define TRANS_DP_8BPC (0<<9)
4122 #define TRANS_DP_10BPC (1<<9)
4123 #define TRANS_DP_6BPC (2<<9)
4124 #define TRANS_DP_12BPC (3<<9)
4125 #define TRANS_DP_BPC_MASK (3<<9)
4126 #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4127 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
4128 #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4129 #define TRANS_DP_HSYNC_ACTIVE_LOW 0
4130 #define TRANS_DP_SYNC_MASK (3<<3)
4132 /* SNB eDP training params */
4133 /* SNB A-stepping */
4134 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4135 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4136 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4137 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4138 /* SNB B-stepping */
4139 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4140 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4141 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4142 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4143 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4144 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4147 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4148 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4149 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4150 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4151 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4152 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4153 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
4156 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4157 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4158 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4159 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4160 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4162 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4164 #define FORCEWAKE 0xA18C
4165 #define FORCEWAKE_VLV 0x1300b0
4166 #define FORCEWAKE_ACK_VLV 0x1300b4
4167 #define FORCEWAKE_ACK_HSW 0x130044
4168 #define FORCEWAKE_ACK 0x130090
4169 #define FORCEWAKE_MT 0xa188 /* multi-threaded */
4170 #define FORCEWAKE_KERNEL 0x1
4171 #define FORCEWAKE_USER 0x2
4172 #define FORCEWAKE_MT_ACK 0x130040
4173 #define ECOBUS 0xa180
4174 #define FORCEWAKE_MT_ENABLE (1<<5)
4176 #define GTFIFODBG 0x120000
4177 #define GT_FIFO_CPU_ERROR_MASK 7
4178 #define GT_FIFO_OVFERR (1<<2)
4179 #define GT_FIFO_IAWRERR (1<<1)
4180 #define GT_FIFO_IARDERR (1<<0)
4182 #define GT_FIFO_FREE_ENTRIES 0x120008
4183 #define GT_FIFO_NUM_RESERVED_ENTRIES 20
4185 #define GEN6_UCGCTL1 0x9400
4186 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4187 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4189 #define GEN6_UCGCTL2 0x9404
4190 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4191 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4192 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4193 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4194 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4196 #define GEN7_UCGCTL4 0x940c
4197 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4199 #define GEN6_RPNSWREQ 0xA008
4200 #define GEN6_TURBO_DISABLE (1<<31)
4201 #define GEN6_FREQUENCY(x) ((x)<<25)
4202 #define GEN6_OFFSET(x) ((x)<<19)
4203 #define GEN6_AGGRESSIVE_TURBO (0<<15)
4204 #define GEN6_RC_VIDEO_FREQ 0xA00C
4205 #define GEN6_RC_CONTROL 0xA090
4206 #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4207 #define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4208 #define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4209 #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4210 #define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4211 #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4212 #define GEN6_RC_CTL_HW_ENABLE (1<<31)
4213 #define GEN6_RP_DOWN_TIMEOUT 0xA010
4214 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
4215 #define GEN6_RPSTAT1 0xA01C
4216 #define GEN6_CAGF_SHIFT 8
4217 #define HSW_CAGF_SHIFT 7
4218 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4219 #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
4220 #define GEN6_RP_CONTROL 0xA024
4221 #define GEN6_RP_MEDIA_TURBO (1<<11)
4222 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4223 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4224 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4225 #define GEN6_RP_MEDIA_HW_MODE (1<<9)
4226 #define GEN6_RP_MEDIA_SW_MODE (0<<9)
4227 #define GEN6_RP_MEDIA_IS_GFX (1<<8)
4228 #define GEN6_RP_ENABLE (1<<7)
4229 #define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4230 #define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4231 #define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4232 #define GEN7_RP_DOWN_IDLE_AVG (0x2<<0)
4233 #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4234 #define GEN6_RP_UP_THRESHOLD 0xA02C
4235 #define GEN6_RP_DOWN_THRESHOLD 0xA030
4236 #define GEN6_RP_CUR_UP_EI 0xA050
4237 #define GEN6_CURICONT_MASK 0xffffff
4238 #define GEN6_RP_CUR_UP 0xA054
4239 #define GEN6_CURBSYTAVG_MASK 0xffffff
4240 #define GEN6_RP_PREV_UP 0xA058
4241 #define GEN6_RP_CUR_DOWN_EI 0xA05C
4242 #define GEN6_CURIAVG_MASK 0xffffff
4243 #define GEN6_RP_CUR_DOWN 0xA060
4244 #define GEN6_RP_PREV_DOWN 0xA064
4245 #define GEN6_RP_UP_EI 0xA068
4246 #define GEN6_RP_DOWN_EI 0xA06C
4247 #define GEN6_RP_IDLE_HYSTERSIS 0xA070
4248 #define GEN6_RC_STATE 0xA094
4249 #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4250 #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4251 #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4252 #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
4253 #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
4254 #define GEN6_RC_SLEEP 0xA0B0
4255 #define GEN6_RC1e_THRESHOLD 0xA0B4
4256 #define GEN6_RC6_THRESHOLD 0xA0B8
4257 #define GEN6_RC6p_THRESHOLD 0xA0BC
4258 #define GEN6_RC6pp_THRESHOLD 0xA0C0
4259 #define GEN6_PMINTRMSK 0xA168
4261 #define GEN6_PMISR 0x44020
4262 #define GEN6_PMIMR 0x44024 /* rps_lock */
4263 #define GEN6_PMIIR 0x44028
4264 #define GEN6_PMIER 0x4402C
4265 #define GEN6_PM_MBOX_EVENT (1<<25)
4266 #define GEN6_PM_THERMAL_EVENT (1<<24)
4267 #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
4268 #define GEN6_PM_RP_UP_THRESHOLD (1<<5)
4269 #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
4270 #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
4271 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
4272 #define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
4273 GEN6_PM_RP_DOWN_THRESHOLD | \
4274 GEN6_PM_RP_DOWN_TIMEOUT)
4276 #define GEN6_GT_GFX_RC6_LOCKED 0x138104
4277 #define GEN6_GT_GFX_RC6 0x138108
4278 #define GEN6_GT_GFX_RC6p 0x13810C
4279 #define GEN6_GT_GFX_RC6pp 0x138110
4281 #define GEN6_PCODE_MAILBOX 0x138124
4282 #define GEN6_PCODE_READY (1<<31)
4283 #define GEN6_READ_OC_PARAMS 0xc
4284 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
4285 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
4286 #define GEN6_PCODE_WRITE_RC6VIDS 0x4
4287 #define GEN6_PCODE_READ_RC6VIDS 0x5
4288 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
4289 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
4290 #define GEN6_PCODE_DATA 0x138128
4291 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
4293 #define GEN6_GT_CORE_STATUS 0x138060
4294 #define GEN6_CORE_CPD_STATE_MASK (7<<4)
4295 #define GEN6_RCn_MASK 7
4301 #define GEN7_MISCCPCTL (0x9424)
4302 #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
4305 #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
4306 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
4307 #define GEN7_PARITY_ERROR_VALID (1<<13)
4308 #define GEN7_L3CDERRST1_BANK_MASK (3<<11)
4309 #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
4310 #define GEN7_PARITY_ERROR_ROW(reg) \
4311 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
4312 #define GEN7_PARITY_ERROR_BANK(reg) \
4313 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
4314 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
4315 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
4316 #define GEN7_L3CDERRST1_ENABLE (1<<7)
4318 #define GEN7_L3LOG_BASE 0xB070
4319 #define GEN7_L3LOG_SIZE 0x80
4321 #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
4322 #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
4323 #define GEN7_MAX_PS_THREAD_DEP (8<<12)
4324 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
4326 #define GEN7_ROW_CHICKEN2 0xe4f4
4327 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
4328 #define DOP_CLOCK_GATING_DISABLE (1<<0)
4330 #define G4X_AUD_VID_DID 0x62020
4331 #define INTEL_AUDIO_DEVCL 0x808629FB
4332 #define INTEL_AUDIO_DEVBLC 0x80862801
4333 #define INTEL_AUDIO_DEVCTG 0x80862802
4335 #define G4X_AUD_CNTL_ST 0x620B4
4336 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
4337 #define G4X_ELDV_DEVCTG (1 << 14)
4338 #define G4X_ELD_ADDR (0xf << 5)
4339 #define G4X_ELD_ACK (1 << 4)
4340 #define G4X_HDMIW_HDMIEDID 0x6210C
4342 #define IBX_HDMIW_HDMIEDID_A 0xE2050
4343 #define IBX_HDMIW_HDMIEDID_B 0xE2150
4344 #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4345 IBX_HDMIW_HDMIEDID_A, \
4346 IBX_HDMIW_HDMIEDID_B)
4347 #define IBX_AUD_CNTL_ST_A 0xE20B4
4348 #define IBX_AUD_CNTL_ST_B 0xE21B4
4349 #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4350 IBX_AUD_CNTL_ST_A, \
4352 #define IBX_ELD_BUFFER_SIZE (0x1f << 10)
4353 #define IBX_ELD_ADDRESS (0x1f << 5)
4354 #define IBX_ELD_ACK (1 << 4)
4355 #define IBX_AUD_CNTL_ST2 0xE20C0
4356 #define IBX_ELD_VALIDB (1 << 0)
4357 #define IBX_CP_READYB (1 << 1)
4359 #define CPT_HDMIW_HDMIEDID_A 0xE5050
4360 #define CPT_HDMIW_HDMIEDID_B 0xE5150
4361 #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
4362 CPT_HDMIW_HDMIEDID_A, \
4363 CPT_HDMIW_HDMIEDID_B)
4364 #define CPT_AUD_CNTL_ST_A 0xE50B4
4365 #define CPT_AUD_CNTL_ST_B 0xE51B4
4366 #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
4367 CPT_AUD_CNTL_ST_A, \
4369 #define CPT_AUD_CNTRL_ST2 0xE50C0
4371 /* These are the 4 32-bit write offset registers for each stream
4372 * output buffer. It determines the offset from the
4373 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
4375 #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
4377 #define IBX_AUD_CONFIG_A 0xe2000
4378 #define IBX_AUD_CONFIG_B 0xe2100
4379 #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
4382 #define CPT_AUD_CONFIG_A 0xe5000
4383 #define CPT_AUD_CONFIG_B 0xe5100
4384 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
4387 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
4388 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
4389 #define AUD_CONFIG_UPPER_N_SHIFT 20
4390 #define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
4391 #define AUD_CONFIG_LOWER_N_SHIFT 4
4392 #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
4393 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
4394 #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
4395 #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
4398 #define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
4399 #define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
4400 #define HSW_AUD_CFG(pipe) _PIPE(pipe, \
4404 #define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
4405 #define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
4406 #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
4407 HSW_AUD_MISC_CTRL_A, \
4408 HSW_AUD_MISC_CTRL_B)
4410 #define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
4411 #define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
4412 #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
4413 HSW_AUD_DIP_ELD_CTRL_ST_A, \
4414 HSW_AUD_DIP_ELD_CTRL_ST_B)
4416 /* Audio Digital Converter */
4417 #define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
4418 #define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
4419 #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
4420 HSW_AUD_DIG_CNVT_1, \
4422 #define DIP_PORT_SEL_MASK 0x3
4424 #define HSW_AUD_EDID_DATA_A 0x65050
4425 #define HSW_AUD_EDID_DATA_B 0x65150
4426 #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
4427 HSW_AUD_EDID_DATA_A, \
4428 HSW_AUD_EDID_DATA_B)
4430 #define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
4431 #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
4432 #define AUDIO_INACTIVE_C (1<<11)
4433 #define AUDIO_INACTIVE_B (1<<7)
4434 #define AUDIO_INACTIVE_A (1<<3)
4435 #define AUDIO_OUTPUT_ENABLE_A (1<<2)
4436 #define AUDIO_OUTPUT_ENABLE_B (1<<6)
4437 #define AUDIO_OUTPUT_ENABLE_C (1<<10)
4438 #define AUDIO_ELD_VALID_A (1<<0)
4439 #define AUDIO_ELD_VALID_B (1<<4)
4440 #define AUDIO_ELD_VALID_C (1<<8)
4441 #define AUDIO_CP_READY_A (1<<1)
4442 #define AUDIO_CP_READY_B (1<<5)
4443 #define AUDIO_CP_READY_C (1<<9)
4445 /* HSW Power Wells */
4446 #define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
4447 #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
4448 #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
4449 #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
4450 #define HSW_PWR_WELL_ENABLE (1<<31)
4451 #define HSW_PWR_WELL_STATE (1<<30)
4452 #define HSW_PWR_WELL_CTL5 0x45410
4453 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
4454 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
4455 #define HSW_PWR_WELL_FORCE_ON (1<<19)
4456 #define HSW_PWR_WELL_CTL6 0x45414
4458 /* Per-pipe DDI Function Control */
4459 #define TRANS_DDI_FUNC_CTL_A 0x60400
4460 #define TRANS_DDI_FUNC_CTL_B 0x61400
4461 #define TRANS_DDI_FUNC_CTL_C 0x62400
4462 #define TRANS_DDI_FUNC_CTL_EDP 0x6F400
4463 #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
4464 TRANS_DDI_FUNC_CTL_B)
4465 #define TRANS_DDI_FUNC_ENABLE (1<<31)
4466 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4467 #define TRANS_DDI_PORT_MASK (7<<28)
4468 #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
4469 #define TRANS_DDI_PORT_NONE (0<<28)
4470 #define TRANS_DDI_MODE_SELECT_MASK (7<<24)
4471 #define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
4472 #define TRANS_DDI_MODE_SELECT_DVI (1<<24)
4473 #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
4474 #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
4475 #define TRANS_DDI_MODE_SELECT_FDI (4<<24)
4476 #define TRANS_DDI_BPC_MASK (7<<20)
4477 #define TRANS_DDI_BPC_8 (0<<20)
4478 #define TRANS_DDI_BPC_10 (1<<20)
4479 #define TRANS_DDI_BPC_6 (2<<20)
4480 #define TRANS_DDI_BPC_12 (3<<20)
4481 #define TRANS_DDI_PVSYNC (1<<17)
4482 #define TRANS_DDI_PHSYNC (1<<16)
4483 #define TRANS_DDI_EDP_INPUT_MASK (7<<12)
4484 #define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
4485 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
4486 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
4487 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
4488 #define TRANS_DDI_BFI_ENABLE (1<<4)
4489 #define TRANS_DDI_PORT_WIDTH_X1 (0<<1)
4490 #define TRANS_DDI_PORT_WIDTH_X2 (1<<1)
4491 #define TRANS_DDI_PORT_WIDTH_X4 (3<<1)
4493 /* DisplayPort Transport Control */
4494 #define DP_TP_CTL_A 0x64040
4495 #define DP_TP_CTL_B 0x64140
4496 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
4497 #define DP_TP_CTL_ENABLE (1<<31)
4498 #define DP_TP_CTL_MODE_SST (0<<27)
4499 #define DP_TP_CTL_MODE_MST (1<<27)
4500 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
4501 #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
4502 #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
4503 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
4504 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
4505 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
4506 #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
4507 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
4508 #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
4510 /* DisplayPort Transport Status */
4511 #define DP_TP_STATUS_A 0x64044
4512 #define DP_TP_STATUS_B 0x64144
4513 #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
4514 #define DP_TP_STATUS_IDLE_DONE (1<<25)
4515 #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
4517 /* DDI Buffer Control */
4518 #define DDI_BUF_CTL_A 0x64000
4519 #define DDI_BUF_CTL_B 0x64100
4520 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
4521 #define DDI_BUF_CTL_ENABLE (1<<31)
4522 #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
4523 #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
4524 #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
4525 #define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
4526 #define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
4527 #define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
4528 #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
4529 #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
4530 #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
4531 #define DDI_BUF_EMP_MASK (0xf<<24)
4532 #define DDI_BUF_PORT_REVERSAL (1<<16)
4533 #define DDI_BUF_IS_IDLE (1<<7)
4534 #define DDI_A_4_LANES (1<<4)
4535 #define DDI_PORT_WIDTH_X1 (0<<1)
4536 #define DDI_PORT_WIDTH_X2 (1<<1)
4537 #define DDI_PORT_WIDTH_X4 (3<<1)
4538 #define DDI_INIT_DISPLAY_DETECTED (1<<0)
4540 /* DDI Buffer Translations */
4541 #define DDI_BUF_TRANS_A 0x64E00
4542 #define DDI_BUF_TRANS_B 0x64E60
4543 #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
4545 /* Sideband Interface (SBI) is programmed indirectly, via
4546 * SBI_ADDR, which contains the register offset; and SBI_DATA,
4547 * which contains the payload */
4548 #define SBI_ADDR 0xC6000
4549 #define SBI_DATA 0xC6004
4550 #define SBI_CTL_STAT 0xC6008
4551 #define SBI_CTL_DEST_ICLK (0x0<<16)
4552 #define SBI_CTL_DEST_MPHY (0x1<<16)
4553 #define SBI_CTL_OP_IORD (0x2<<8)
4554 #define SBI_CTL_OP_IOWR (0x3<<8)
4555 #define SBI_CTL_OP_CRRD (0x6<<8)
4556 #define SBI_CTL_OP_CRWR (0x7<<8)
4557 #define SBI_RESPONSE_FAIL (0x1<<1)
4558 #define SBI_RESPONSE_SUCCESS (0x0<<1)
4559 #define SBI_BUSY (0x1<<0)
4560 #define SBI_READY (0x0<<0)
4563 #define SBI_SSCDIVINTPHASE6 0x0600
4564 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
4565 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
4566 #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
4567 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
4568 #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
4569 #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
4570 #define SBI_SSCCTL 0x020c
4571 #define SBI_SSCCTL6 0x060C
4572 #define SBI_SSCCTL_PATHALT (1<<3)
4573 #define SBI_SSCCTL_DISABLE (1<<0)
4574 #define SBI_SSCAUXDIV6 0x0610
4575 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
4576 #define SBI_DBUFF0 0x2a00
4577 #define SBI_DBUFF0_ENABLE (1<<0)
4579 /* LPT PIXCLK_GATE */
4580 #define PIXCLK_GATE 0xC6020
4581 #define PIXCLK_GATE_UNGATE (1<<0)
4582 #define PIXCLK_GATE_GATE (0<<0)
4585 #define SPLL_CTL 0x46020
4586 #define SPLL_PLL_ENABLE (1<<31)
4587 #define SPLL_PLL_SSC (1<<28)
4588 #define SPLL_PLL_NON_SSC (2<<28)
4589 #define SPLL_PLL_FREQ_810MHz (0<<26)
4590 #define SPLL_PLL_FREQ_1350MHz (1<<26)
4593 #define WRPLL_CTL1 0x46040
4594 #define WRPLL_CTL2 0x46060
4595 #define WRPLL_PLL_ENABLE (1<<31)
4596 #define WRPLL_PLL_SELECT_SSC (0x01<<28)
4597 #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
4598 #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
4599 /* WRPLL divider programming */
4600 #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
4601 #define WRPLL_DIVIDER_POST(x) ((x)<<8)
4602 #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
4604 /* Port clock selection */
4605 #define PORT_CLK_SEL_A 0x46100
4606 #define PORT_CLK_SEL_B 0x46104
4607 #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
4608 #define PORT_CLK_SEL_LCPLL_2700 (0<<29)
4609 #define PORT_CLK_SEL_LCPLL_1350 (1<<29)
4610 #define PORT_CLK_SEL_LCPLL_810 (2<<29)
4611 #define PORT_CLK_SEL_SPLL (3<<29)
4612 #define PORT_CLK_SEL_WRPLL1 (4<<29)
4613 #define PORT_CLK_SEL_WRPLL2 (5<<29)
4614 #define PORT_CLK_SEL_NONE (7<<29)
4616 /* Transcoder clock selection */
4617 #define TRANS_CLK_SEL_A 0x46140
4618 #define TRANS_CLK_SEL_B 0x46144
4619 #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
4620 /* For each transcoder, we need to select the corresponding port clock */
4621 #define TRANS_CLK_SEL_DISABLED (0x0<<29)
4622 #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
4624 #define _TRANSA_MSA_MISC 0x60410
4625 #define _TRANSB_MSA_MISC 0x61410
4626 #define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \
4628 #define TRANS_MSA_SYNC_CLK (1<<0)
4629 #define TRANS_MSA_6_BPC (0<<5)
4630 #define TRANS_MSA_8_BPC (1<<5)
4631 #define TRANS_MSA_10_BPC (2<<5)
4632 #define TRANS_MSA_12_BPC (3<<5)
4633 #define TRANS_MSA_16_BPC (4<<5)
4636 #define LCPLL_CTL 0x130040
4637 #define LCPLL_PLL_DISABLE (1<<31)
4638 #define LCPLL_PLL_LOCK (1<<30)
4639 #define LCPLL_CLK_FREQ_MASK (3<<26)
4640 #define LCPLL_CLK_FREQ_450 (0<<26)
4641 #define LCPLL_CD_CLOCK_DISABLE (1<<25)
4642 #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
4643 #define LCPLL_CD_SOURCE_FCLK (1<<21)
4645 /* Pipe WM_LINETIME - watermark line time */
4646 #define PIPE_WM_LINETIME_A 0x45270
4647 #define PIPE_WM_LINETIME_B 0x45274
4648 #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
4650 #define PIPE_WM_LINETIME_MASK (0x1ff)
4651 #define PIPE_WM_LINETIME_TIME(x) ((x))
4652 #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
4653 #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
4656 #define SFUSE_STRAP 0xc2014
4657 #define SFUSE_STRAP_DDIB_DETECTED (1<<2)
4658 #define SFUSE_STRAP_DDIC_DETECTED (1<<1)
4659 #define SFUSE_STRAP_DDID_DETECTED (1<<0)
4661 #define WM_DBG 0x45280
4662 #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
4663 #define WM_DBG_DISALLOW_MAXFIFO (1<<1)
4664 #define WM_DBG_DISALLOW_SPRITE (1<<2)
4666 #endif /* _I915_REG_H_ */