2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <dev/drm2/drmP.h>
32 #include <dev/drm2/drm.h>
33 #include <dev/drm2/i915/i915_drm.h>
34 #include <dev/drm2/i915/i915_drv.h>
35 #include <dev/drm2/i915/intel_drv.h>
37 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
41 static const u32 hsw_ddi_translations_dp[] = {
42 0x00FFFFFF, 0x0006000E, /* DP parameters */
43 0x00D75FFF, 0x0005000A,
44 0x00C30FFF, 0x00040006,
45 0x80AAAFFF, 0x000B0000,
46 0x00FFFFFF, 0x0005000A,
47 0x00D75FFF, 0x000C0004,
48 0x80C30FFF, 0x000B0000,
49 0x00FFFFFF, 0x00040006,
50 0x80D75FFF, 0x000B0000,
51 0x00FFFFFF, 0x00040006 /* HDMI parameters */
54 static const u32 hsw_ddi_translations_fdi[] = {
55 0x00FFFFFF, 0x0007000E, /* FDI parameters */
56 0x00D75FFF, 0x000F000A,
57 0x00C30FFF, 0x00060006,
58 0x00AAAFFF, 0x001E0000,
59 0x00FFFFFF, 0x000F000A,
60 0x00D75FFF, 0x00160004,
61 0x00C30FFF, 0x001E0000,
62 0x00FFFFFF, 0x00060006,
63 0x00D75FFF, 0x001E0000,
64 0x00FFFFFF, 0x00040006 /* HDMI parameters */
67 /* On Haswell, DDI port buffers must be programmed with correct values
68 * in advance. The buffer values are different for FDI and DP modes,
69 * but the HDMI/DVI fields are shared among those. So we program the DDI
70 * in either FDI or DP modes only, as HDMI connections will work with both
73 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
75 struct drm_i915_private *dev_priv = dev->dev_private;
78 const u32 *ddi_translations = ((use_fdi_mode) ?
79 hsw_ddi_translations_fdi :
80 hsw_ddi_translations_dp);
82 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
84 use_fdi_mode ? "FDI" : "DP");
86 if (use_fdi_mode && (port != PORT_E))
87 DRM_DEBUG_KMS("Programming port %c in FDI mode, this probably will not work.\n",
90 for (i=0, reg=DDI_BUF_TRANS(port); i < DRM_ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
91 I915_WRITE(reg, ddi_translations[i]);
96 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
97 * mode and port E for FDI.
99 void intel_prepare_ddi(struct drm_device *dev)
103 if (IS_HASWELL(dev)) {
104 for (port = PORT_A; port < PORT_E; port++)
105 intel_prepare_ddi_buffers(dev, port, false);
107 /* DDI E is the suggested one to work in FDI mode, so program is as such by
108 * default. It will have to be re-programmed in case a digital DP output
109 * will be detected on it
111 intel_prepare_ddi_buffers(dev, PORT_E, true);
115 static const long hsw_ddi_buf_ctl_values[] = {
116 DDI_BUF_EMP_400MV_0DB_HSW,
117 DDI_BUF_EMP_400MV_3_5DB_HSW,
118 DDI_BUF_EMP_400MV_6DB_HSW,
119 DDI_BUF_EMP_400MV_9_5DB_HSW,
120 DDI_BUF_EMP_600MV_0DB_HSW,
121 DDI_BUF_EMP_600MV_3_5DB_HSW,
122 DDI_BUF_EMP_600MV_6DB_HSW,
123 DDI_BUF_EMP_800MV_0DB_HSW,
124 DDI_BUF_EMP_800MV_3_5DB_HSW
128 /* Starting with Haswell, different DDI ports can work in FDI mode for
129 * connection to the PCH-located connectors. For this, it is necessary to train
130 * both the DDI port and PCH receiver for the desired DDI buffer settings.
132 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
133 * please note that when FDI mode is active on DDI E, it shares 2 lines with
134 * DDI A (which is used for eDP)
137 void hsw_fdi_link_train(struct drm_crtc *crtc)
139 struct drm_device *dev = crtc->dev;
140 struct drm_i915_private *dev_priv = dev->dev_private;
141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
142 int pipe = intel_crtc->pipe;
145 /* Configure CPU PLL, wait for warmup */
148 SPLL_PLL_FREQ_1350MHz |
151 /* Use SPLL to drive the output when in FDI mode */
152 I915_WRITE(PORT_CLK_SEL(PORT_E),
154 I915_WRITE(PIPE_CLK_SEL(pipe),
155 PIPE_CLK_SEL_PORT(PORT_E));
159 /* Start the training iterating through available voltages and emphasis */
160 for (i=0; i < DRM_ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
161 /* Configure DP_TP_CTL with auto-training */
162 I915_WRITE(DP_TP_CTL(PORT_E),
163 DP_TP_CTL_FDI_AUTOTRAIN |
164 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
165 DP_TP_CTL_LINK_TRAIN_PAT1 |
168 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
169 temp = I915_READ(DDI_BUF_CTL(PORT_E));
170 temp = (temp & ~DDI_BUF_EMP_MASK);
171 I915_WRITE(DDI_BUF_CTL(PORT_E),
175 hsw_ddi_buf_ctl_values[i]);
179 /* Enable CPU FDI Receiver with auto-training */
180 reg = FDI_RX_CTL(pipe);
183 FDI_LINK_TRAIN_AUTO |
185 FDI_LINK_TRAIN_PATTERN_1_CPT |
186 FDI_RX_ENHANCE_FRAME_ENABLE |
187 FDI_PORT_WIDTH_2X_LPT |
192 temp = I915_READ(DP_TP_STATUS(PORT_E));
193 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
194 DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i);
196 /* Enable normal pixel sending for FDI */
197 I915_WRITE(DP_TP_CTL(PORT_E),
198 DP_TP_CTL_FDI_AUTOTRAIN |
199 DP_TP_CTL_LINK_TRAIN_NORMAL |
200 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
203 /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */
204 temp = I915_READ(DDI_FUNC_CTL(pipe));
205 temp &= ~PIPE_DDI_PORT_MASK;
206 temp |= PIPE_DDI_SELECT_PORT(PORT_E) |
207 PIPE_DDI_MODE_SELECT_FDI |
208 PIPE_DDI_FUNC_ENABLE |
209 PIPE_DDI_PORT_WIDTH_X2;
210 I915_WRITE(DDI_FUNC_CTL(pipe),
214 DRM_ERROR("Error training BUF_CTL %d\n", i);
216 /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
217 I915_WRITE(DP_TP_CTL(PORT_E),
218 I915_READ(DP_TP_CTL(PORT_E)) &
220 I915_WRITE(FDI_RX_CTL(pipe),
221 I915_READ(FDI_RX_CTL(pipe)) &
227 DRM_DEBUG_KMS("FDI train done.\n");
230 /* For DDI connections, it is possible to support different outputs over the
231 * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by
232 * the time the output is detected what exactly is on the other end of it. This
233 * function aims at providing support for this detection and proper output
236 void intel_ddi_init(struct drm_device *dev, enum port port)
238 /* For now, we don't do any proper output detection and assume that we
239 * handle HDMI only */
243 /* We don't handle eDP and DP yet */
244 DRM_DEBUG_DRIVER("Found digital output on DDI port A\n");
246 /* Assume that the ports B, C and D are working in HDMI mode for now */
250 intel_hdmi_init(dev, DDI_BUF_CTL(port));
253 DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n",
259 /* WRPLL clock dividers */
260 struct wrpll_tmds_clock {
262 u16 p; /* Post divider */
263 u16 n2; /* Feedback divider */
264 u16 r2; /* Reference divider */
267 /* Table of matching values for WRPLL clocks programming for each frequency */
268 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
284 {27027, 18, 100, 111},
312 {40541, 22, 147, 89},
322 {44900, 20, 108, 65},
338 {54054, 16, 173, 108},
390 {81081, 6, 100, 111},
435 {108108, 8, 173, 108},
443 {111264, 8, 150, 91},
487 {135250, 6, 167, 111},
510 {148352, 4, 100, 91},
532 {162162, 4, 131, 109},
540 {169000, 4, 104, 83},
587 {202000, 4, 112, 75},
589 {203000, 4, 146, 97},
647 void intel_ddi_mode_set(struct drm_encoder *encoder,
648 struct drm_display_mode *mode,
649 struct drm_display_mode *adjusted_mode)
651 struct drm_device *dev = encoder->dev;
652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct drm_crtc *crtc = encoder->crtc;
654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
656 int port = intel_hdmi->ddi_port;
657 int pipe = intel_crtc->pipe;
658 int p, n2, r2, valid=0;
661 /* On Haswell, we need to enable the clocks and prepare DDI function to
662 * work in HDMI mode for this pipe.
664 DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe %c\n", port_name(port), pipe_name(pipe));
666 for (i=0; i < DRM_ARRAY_SIZE(wrpll_tmds_clock_table); i++) {
667 if (crtc->mode.clock == wrpll_tmds_clock_table[i].clock) {
668 p = wrpll_tmds_clock_table[i].p;
669 n2 = wrpll_tmds_clock_table[i].n2;
670 r2 = wrpll_tmds_clock_table[i].r2;
672 DRM_DEBUG_KMS("WR PLL clock: found settings for %dKHz refresh rate: p=%d, n2=%d, r2=%d\n",
682 DRM_ERROR("Unable to find WR PLL clock settings for %dKHz refresh rate\n",
687 /* Enable LCPLL if disabled */
688 temp = I915_READ(LCPLL_CTL);
689 if (temp & LCPLL_PLL_DISABLE)
690 I915_WRITE(LCPLL_CTL,
691 temp & ~LCPLL_PLL_DISABLE);
693 /* Configure WR PLL 1, program the correct divider values for
694 * the desired frequency and wait for warmup */
695 I915_WRITE(WRPLL_CTL1,
697 WRPLL_PLL_SELECT_LCPLL_2700 |
698 WRPLL_DIVIDER_REFERENCE(r2) |
699 WRPLL_DIVIDER_FEEDBACK(n2) |
700 WRPLL_DIVIDER_POST(p));
704 /* Use WRPLL1 clock to drive the output to the port, and tell the pipe to use
705 * this port for connection.
707 I915_WRITE(PORT_CLK_SEL(port),
708 PORT_CLK_SEL_WRPLL1);
709 I915_WRITE(PIPE_CLK_SEL(pipe),
710 PIPE_CLK_SEL_PORT(port));
714 if (intel_hdmi->has_audio) {
715 /* Proper support for digital audio needs a new logic and a new set
716 * of registers, so we leave it for future patch bombing.
718 DRM_DEBUG_DRIVER("HDMI audio on pipe %c not yet supported on DDI\n",
719 pipe_name(intel_crtc->pipe));
722 /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
723 temp = I915_READ(DDI_FUNC_CTL(pipe));
724 temp &= ~PIPE_DDI_PORT_MASK;
725 temp &= ~PIPE_DDI_BPC_12;
726 temp |= PIPE_DDI_SELECT_PORT(port) |
727 PIPE_DDI_MODE_SELECT_HDMI |
728 ((intel_crtc->bpp > 24) ?
731 PIPE_DDI_FUNC_ENABLE;
733 I915_WRITE(DDI_FUNC_CTL(pipe), temp);
735 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
736 intel_hdmi_set_spd_infoframe(encoder);
739 void intel_ddi_dpms(struct drm_encoder *encoder, int mode)
741 struct drm_device *dev = encoder->dev;
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
744 int port = intel_hdmi->ddi_port;
747 temp = I915_READ(DDI_BUF_CTL(port));
749 if (mode != DRM_MODE_DPMS_ON) {
750 temp &= ~DDI_BUF_CTL_ENABLE;
752 temp |= DDI_BUF_CTL_ENABLE;
755 /* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
756 * and swing/emphasis values are ignored so nothing special needs
757 * to be done besides enabling the port.
759 I915_WRITE(DDI_BUF_CTL(port),