2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <dev/drm2/drmP.h>
32 #include <dev/drm2/i915/i915_drv.h>
33 #include <dev/drm2/i915/intel_drv.h>
35 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
36 * them for both DP and FDI transports, allowing those ports to
37 * automatically adapt to HDMI connections as well
39 static const u32 hsw_ddi_translations_dp[] = {
40 0x00FFFFFF, 0x0006000E, /* DP parameters */
41 0x00D75FFF, 0x0005000A,
42 0x00C30FFF, 0x00040006,
43 0x80AAAFFF, 0x000B0000,
44 0x00FFFFFF, 0x0005000A,
45 0x00D75FFF, 0x000C0004,
46 0x80C30FFF, 0x000B0000,
47 0x00FFFFFF, 0x00040006,
48 0x80D75FFF, 0x000B0000,
49 0x00FFFFFF, 0x00040006 /* HDMI parameters */
52 static const u32 hsw_ddi_translations_fdi[] = {
53 0x00FFFFFF, 0x0007000E, /* FDI parameters */
54 0x00D75FFF, 0x000F000A,
55 0x00C30FFF, 0x00060006,
56 0x00AAAFFF, 0x001E0000,
57 0x00FFFFFF, 0x000F000A,
58 0x00D75FFF, 0x00160004,
59 0x00C30FFF, 0x001E0000,
60 0x00FFFFFF, 0x00060006,
61 0x00D75FFF, 0x001E0000,
62 0x00FFFFFF, 0x00040006 /* HDMI parameters */
65 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
67 struct drm_encoder *encoder = &intel_encoder->base;
68 int type = intel_encoder->type;
70 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
71 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
72 struct intel_digital_port *intel_dig_port =
73 enc_to_dig_port(encoder);
74 return intel_dig_port->port;
76 } else if (type == INTEL_OUTPUT_ANALOG) {
80 DRM_ERROR("Invalid DDI encoder type %d\n", type);
85 /* On Haswell, DDI port buffers must be programmed with correct values
86 * in advance. The buffer values are different for FDI and DP modes,
87 * but the HDMI/DVI fields are shared among those. So we program the DDI
88 * in either FDI or DP modes only, as HDMI connections will work with both
91 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
93 struct drm_i915_private *dev_priv = dev->dev_private;
96 const u32 *ddi_translations = ((use_fdi_mode) ?
97 hsw_ddi_translations_fdi :
98 hsw_ddi_translations_dp);
100 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
102 use_fdi_mode ? "FDI" : "DP");
104 WARN((use_fdi_mode && (port != PORT_E)),
105 "Programming port %c in FDI mode, this probably will not work.\n",
108 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
109 I915_WRITE(reg, ddi_translations[i]);
114 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
115 * mode and port E for FDI.
117 void intel_prepare_ddi(struct drm_device *dev)
121 if (IS_HASWELL(dev)) {
122 for (port = PORT_A; port < PORT_E; port++)
123 intel_prepare_ddi_buffers(dev, port, false);
125 /* DDI E is the suggested one to work in FDI mode, so program is as such by
126 * default. It will have to be re-programmed in case a digital DP output
127 * will be detected on it
129 intel_prepare_ddi_buffers(dev, PORT_E, true);
133 static const long hsw_ddi_buf_ctl_values[] = {
134 DDI_BUF_EMP_400MV_0DB_HSW,
135 DDI_BUF_EMP_400MV_3_5DB_HSW,
136 DDI_BUF_EMP_400MV_6DB_HSW,
137 DDI_BUF_EMP_400MV_9_5DB_HSW,
138 DDI_BUF_EMP_600MV_0DB_HSW,
139 DDI_BUF_EMP_600MV_3_5DB_HSW,
140 DDI_BUF_EMP_600MV_6DB_HSW,
141 DDI_BUF_EMP_800MV_0DB_HSW,
142 DDI_BUF_EMP_800MV_3_5DB_HSW
145 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
148 uint32_t reg = DDI_BUF_CTL(port);
151 for (i = 0; i < 8; i++) {
153 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
156 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
159 /* Starting with Haswell, different DDI ports can work in FDI mode for
160 * connection to the PCH-located connectors. For this, it is necessary to train
161 * both the DDI port and PCH receiver for the desired DDI buffer settings.
163 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
164 * please note that when FDI mode is active on DDI E, it shares 2 lines with
165 * DDI A (which is used for eDP)
168 void hsw_fdi_link_train(struct drm_crtc *crtc)
170 struct drm_device *dev = crtc->dev;
171 struct drm_i915_private *dev_priv = dev->dev_private;
172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
173 u32 temp, i, rx_ctl_val;
175 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
176 * mode set "sequence for CRT port" document:
177 * - TP1 to TP2 time with the default value
180 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
181 FDI_RX_PWRDN_LANE0_VAL(2) |
182 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
184 /* Enable the PCH Receiver FDI PLL */
185 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
186 FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
187 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
188 POSTING_READ(_FDI_RXA_CTL);
191 /* Switch from Rawclk to PCDclk */
192 rx_ctl_val |= FDI_PCDCLK;
193 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
195 /* Configure Port Clock Select */
196 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
198 /* Start the training iterating through available voltages and emphasis,
199 * testing each value twice. */
200 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
201 /* Configure DP_TP_CTL with auto-training */
202 I915_WRITE(DP_TP_CTL(PORT_E),
203 DP_TP_CTL_FDI_AUTOTRAIN |
204 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
205 DP_TP_CTL_LINK_TRAIN_PAT1 |
208 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
209 * DDI E does not support port reversal, the functionality is
210 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
211 * port reversal bit */
212 I915_WRITE(DDI_BUF_CTL(PORT_E),
214 ((intel_crtc->fdi_lanes - 1) << 1) |
215 hsw_ddi_buf_ctl_values[i / 2]);
216 POSTING_READ(DDI_BUF_CTL(PORT_E));
220 /* Program PCH FDI Receiver TU */
221 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
223 /* Enable PCH FDI Receiver with auto-training */
224 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
225 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
226 POSTING_READ(_FDI_RXA_CTL);
228 /* Wait for FDI receiver lane calibration */
231 /* Unset FDI_RX_MISC pwrdn lanes */
232 temp = I915_READ(_FDI_RXA_MISC);
233 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
234 I915_WRITE(_FDI_RXA_MISC, temp);
235 POSTING_READ(_FDI_RXA_MISC);
237 /* Wait for FDI auto training time */
240 temp = I915_READ(DP_TP_STATUS(PORT_E));
241 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
242 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
244 /* Enable normal pixel sending for FDI */
245 I915_WRITE(DP_TP_CTL(PORT_E),
246 DP_TP_CTL_FDI_AUTOTRAIN |
247 DP_TP_CTL_LINK_TRAIN_NORMAL |
248 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
254 temp = I915_READ(DDI_BUF_CTL(PORT_E));
255 temp &= ~DDI_BUF_CTL_ENABLE;
256 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
257 POSTING_READ(DDI_BUF_CTL(PORT_E));
259 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
260 temp = I915_READ(DP_TP_CTL(PORT_E));
261 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
262 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
263 I915_WRITE(DP_TP_CTL(PORT_E), temp);
264 POSTING_READ(DP_TP_CTL(PORT_E));
266 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
268 rx_ctl_val &= ~FDI_RX_ENABLE;
269 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
270 POSTING_READ(_FDI_RXA_CTL);
272 /* Reset FDI_RX_MISC pwrdn lanes */
273 temp = I915_READ(_FDI_RXA_MISC);
274 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
275 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
276 I915_WRITE(_FDI_RXA_MISC, temp);
277 POSTING_READ(_FDI_RXA_MISC);
280 DRM_ERROR("FDI link training failed!\n");
283 /* WRPLL clock dividers */
284 struct wrpll_tmds_clock {
286 u16 p; /* Post divider */
287 u16 n2; /* Feedback divider */
288 u16 r2; /* Reference divider */
291 /* Table of matching values for WRPLL clocks programming for each frequency.
292 * The code assumes this table is sorted. */
293 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
308 {27027, 18, 100, 111},
336 {40541, 22, 147, 89},
346 {44900, 20, 108, 65},
362 {54054, 16, 173, 108},
414 {81081, 6, 100, 111},
459 {108108, 8, 173, 108},
466 {111264, 8, 150, 91},
510 {135250, 6, 167, 111},
533 {148352, 4, 100, 91},
555 {162162, 4, 131, 109},
563 {169000, 4, 104, 83},
610 {202000, 4, 112, 75},
612 {203000, 4, 146, 97},
669 static void intel_ddi_mode_set(struct drm_encoder *encoder,
670 struct drm_display_mode *mode,
671 struct drm_display_mode *adjusted_mode)
673 struct drm_crtc *crtc = encoder->crtc;
674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
675 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
676 int port = intel_ddi_get_encoder_port(intel_encoder);
677 int pipe = intel_crtc->pipe;
678 int type = intel_encoder->type;
680 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
681 port_name(port), pipe_name(pipe));
683 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
684 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
685 struct intel_digital_port *intel_dig_port =
686 enc_to_dig_port(encoder);
688 intel_dp->DP = intel_dig_port->port_reversal |
689 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
690 switch (intel_dp->lane_count) {
692 intel_dp->DP |= DDI_PORT_WIDTH_X1;
695 intel_dp->DP |= DDI_PORT_WIDTH_X2;
698 intel_dp->DP |= DDI_PORT_WIDTH_X4;
701 intel_dp->DP |= DDI_PORT_WIDTH_X4;
702 WARN(1, "Unexpected DP lane count %d\n",
703 intel_dp->lane_count);
707 if (intel_dp->has_audio) {
708 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
709 pipe_name(intel_crtc->pipe));
712 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
713 intel_write_eld(encoder, adjusted_mode);
716 intel_dp_init_link_config(intel_dp);
718 } else if (type == INTEL_OUTPUT_HDMI) {
719 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
721 if (intel_hdmi->has_audio) {
722 /* Proper support for digital audio needs a new logic
723 * and a new set of registers, so we leave it for future
726 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
727 pipe_name(intel_crtc->pipe));
730 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
731 intel_write_eld(encoder, adjusted_mode);
734 intel_hdmi->set_infoframes(encoder, adjusted_mode);
738 static struct intel_encoder *
739 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
741 struct drm_device *dev = crtc->dev;
742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743 struct intel_encoder *intel_encoder, *ret = NULL;
744 int num_encoders = 0;
746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
751 if (num_encoders != 1)
752 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
759 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
761 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
762 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
766 switch (intel_crtc->ddi_pll_sel) {
767 case PORT_CLK_SEL_SPLL:
768 plls->spll_refcount--;
769 if (plls->spll_refcount == 0) {
770 DRM_DEBUG_KMS("Disabling SPLL\n");
771 val = I915_READ(SPLL_CTL);
772 WARN_ON(!(val & SPLL_PLL_ENABLE));
773 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
774 POSTING_READ(SPLL_CTL);
777 case PORT_CLK_SEL_WRPLL1:
778 plls->wrpll1_refcount--;
779 if (plls->wrpll1_refcount == 0) {
780 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
781 val = I915_READ(WRPLL_CTL1);
782 WARN_ON(!(val & WRPLL_PLL_ENABLE));
783 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
784 POSTING_READ(WRPLL_CTL1);
787 case PORT_CLK_SEL_WRPLL2:
788 plls->wrpll2_refcount--;
789 if (plls->wrpll2_refcount == 0) {
790 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
791 val = I915_READ(WRPLL_CTL2);
792 WARN_ON(!(val & WRPLL_PLL_ENABLE));
793 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
794 POSTING_READ(WRPLL_CTL2);
799 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
800 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
801 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
803 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
806 static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
810 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
811 if (clock <= wrpll_tmds_clock_table[i].clock)
814 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
817 *p = wrpll_tmds_clock_table[i].p;
818 *n2 = wrpll_tmds_clock_table[i].n2;
819 *r2 = wrpll_tmds_clock_table[i].r2;
821 if (wrpll_tmds_clock_table[i].clock != clock)
822 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
823 wrpll_tmds_clock_table[i].clock, clock);
825 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
826 clock, *p, *n2, *r2);
829 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
832 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
833 struct drm_encoder *encoder = &intel_encoder->base;
834 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
835 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
836 int type = intel_encoder->type;
837 enum pipe pipe = intel_crtc->pipe;
840 /* TODO: reuse PLLs when possible (compare values) */
842 intel_ddi_put_crtc_pll(crtc);
844 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
845 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
847 switch (intel_dp->link_bw) {
848 case DP_LINK_BW_1_62:
849 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
852 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
855 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
858 DRM_ERROR("Link bandwidth %d unsupported\n",
863 /* We don't need to turn any PLL on because we'll use LCPLL. */
866 } else if (type == INTEL_OUTPUT_HDMI) {
869 if (plls->wrpll1_refcount == 0) {
870 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
872 plls->wrpll1_refcount++;
874 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
875 } else if (plls->wrpll2_refcount == 0) {
876 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
878 plls->wrpll2_refcount++;
880 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
882 DRM_ERROR("No WRPLLs available!\n");
886 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
887 "WRPLL already enabled\n");
889 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
891 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
892 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
893 WRPLL_DIVIDER_POST(p);
895 } else if (type == INTEL_OUTPUT_ANALOG) {
896 if (plls->spll_refcount == 0) {
897 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
899 plls->spll_refcount++;
900 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
904 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
905 "SPLL already enabled\n");
907 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
910 WARN(1, "Invalid DDI encoder type %d\n", type);
914 I915_WRITE(reg, val);
920 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
922 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
924 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
925 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
926 int type = intel_encoder->type;
929 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
931 temp = TRANS_MSA_SYNC_CLK;
932 switch (intel_crtc->bpp) {
934 temp |= TRANS_MSA_6_BPC;
937 temp |= TRANS_MSA_8_BPC;
940 temp |= TRANS_MSA_10_BPC;
943 temp |= TRANS_MSA_12_BPC;
946 temp |= TRANS_MSA_8_BPC;
947 WARN(1, "%d bpp unsupported by DDI function\n",
950 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
954 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
957 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
958 struct drm_encoder *encoder = &intel_encoder->base;
959 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
960 enum pipe pipe = intel_crtc->pipe;
961 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
962 enum port port = intel_ddi_get_encoder_port(intel_encoder);
963 int type = intel_encoder->type;
966 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
967 temp = TRANS_DDI_FUNC_ENABLE;
968 temp |= TRANS_DDI_SELECT_PORT(port);
970 switch (intel_crtc->bpp) {
972 temp |= TRANS_DDI_BPC_6;
975 temp |= TRANS_DDI_BPC_8;
978 temp |= TRANS_DDI_BPC_10;
981 temp |= TRANS_DDI_BPC_12;
984 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
988 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
989 temp |= TRANS_DDI_PVSYNC;
990 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
991 temp |= TRANS_DDI_PHSYNC;
993 if (cpu_transcoder == TRANSCODER_EDP) {
996 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
999 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1002 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1010 if (type == INTEL_OUTPUT_HDMI) {
1011 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1013 if (intel_hdmi->has_hdmi_sink)
1014 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1016 temp |= TRANS_DDI_MODE_SELECT_DVI;
1018 } else if (type == INTEL_OUTPUT_ANALOG) {
1019 temp |= TRANS_DDI_MODE_SELECT_FDI;
1020 temp |= (intel_crtc->fdi_lanes - 1) << 1;
1022 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1023 type == INTEL_OUTPUT_EDP) {
1024 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1026 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1028 switch (intel_dp->lane_count) {
1030 temp |= TRANS_DDI_PORT_WIDTH_X1;
1033 temp |= TRANS_DDI_PORT_WIDTH_X2;
1036 temp |= TRANS_DDI_PORT_WIDTH_X4;
1039 temp |= TRANS_DDI_PORT_WIDTH_X4;
1040 WARN(1, "Unsupported lane count %d\n",
1041 intel_dp->lane_count);
1045 WARN(1, "Invalid encoder type %d for pipe %d\n",
1046 intel_encoder->type, pipe);
1049 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1052 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1053 enum transcoder cpu_transcoder)
1055 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1056 uint32_t val = I915_READ(reg);
1058 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1059 val |= TRANS_DDI_PORT_NONE;
1060 I915_WRITE(reg, val);
1063 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1065 struct drm_device *dev = intel_connector->base.dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 struct intel_encoder *intel_encoder = intel_connector->encoder;
1068 int type = intel_connector->base.connector_type;
1069 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1071 enum transcoder cpu_transcoder;
1074 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1078 cpu_transcoder = TRANSCODER_EDP;
1080 cpu_transcoder = (enum transcoder)pipe;
1082 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1084 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1085 case TRANS_DDI_MODE_SELECT_HDMI:
1086 case TRANS_DDI_MODE_SELECT_DVI:
1087 return (type == DRM_MODE_CONNECTOR_HDMIA);
1089 case TRANS_DDI_MODE_SELECT_DP_SST:
1090 if (type == DRM_MODE_CONNECTOR_eDP)
1092 case TRANS_DDI_MODE_SELECT_DP_MST:
1093 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1095 case TRANS_DDI_MODE_SELECT_FDI:
1096 return (type == DRM_MODE_CONNECTOR_VGA);
1103 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1106 struct drm_device *dev = encoder->base.dev;
1107 struct drm_i915_private *dev_priv = dev->dev_private;
1108 enum port port = intel_ddi_get_encoder_port(encoder);
1112 tmp = I915_READ(DDI_BUF_CTL(port));
1114 if (!(tmp & DDI_BUF_CTL_ENABLE))
1117 if (port == PORT_A) {
1118 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1120 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1121 case TRANS_DDI_EDP_INPUT_A_ON:
1122 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1125 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1128 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1135 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1136 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1138 if ((tmp & TRANS_DDI_PORT_MASK)
1139 == TRANS_DDI_SELECT_PORT(port)) {
1146 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
1151 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1156 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1160 if (cpu_transcoder == TRANSCODER_EDP) {
1163 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1164 temp &= TRANS_DDI_PORT_MASK;
1166 for (i = PORT_B; i <= PORT_E; i++)
1167 if (temp == TRANS_DDI_SELECT_PORT(i))
1171 ret = I915_READ(PORT_CLK_SEL(port));
1173 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1174 pipe_name(pipe), port_name(port), ret);
1179 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1183 struct intel_crtc *intel_crtc;
1185 for_each_pipe(pipe) {
1187 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1189 if (!intel_crtc->active)
1192 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1195 switch (intel_crtc->ddi_pll_sel) {
1196 case PORT_CLK_SEL_SPLL:
1197 dev_priv->ddi_plls.spll_refcount++;
1199 case PORT_CLK_SEL_WRPLL1:
1200 dev_priv->ddi_plls.wrpll1_refcount++;
1202 case PORT_CLK_SEL_WRPLL2:
1203 dev_priv->ddi_plls.wrpll2_refcount++;
1209 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1211 struct drm_crtc *crtc = &intel_crtc->base;
1212 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1213 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1214 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1215 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1217 if (cpu_transcoder != TRANSCODER_EDP)
1218 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1219 TRANS_CLK_SEL_PORT(port));
1222 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1224 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1225 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1227 if (cpu_transcoder != TRANSCODER_EDP)
1228 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1229 TRANS_CLK_SEL_DISABLED);
1232 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1234 struct drm_encoder *encoder = &intel_encoder->base;
1235 struct drm_crtc *crtc = encoder->crtc;
1236 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1238 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1239 int type = intel_encoder->type;
1241 if (type == INTEL_OUTPUT_EDP) {
1242 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1243 ironlake_edp_panel_vdd_on(intel_dp);
1244 ironlake_edp_panel_on(intel_dp);
1245 ironlake_edp_panel_vdd_off(intel_dp, true);
1248 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1249 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1251 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1252 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1254 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1255 intel_dp_start_link_train(intel_dp);
1256 intel_dp_complete_link_train(intel_dp);
1260 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1262 struct drm_encoder *encoder = &intel_encoder->base;
1263 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1264 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1265 int type = intel_encoder->type;
1269 val = I915_READ(DDI_BUF_CTL(port));
1270 if (val & DDI_BUF_CTL_ENABLE) {
1271 val &= ~DDI_BUF_CTL_ENABLE;
1272 I915_WRITE(DDI_BUF_CTL(port), val);
1276 val = I915_READ(DP_TP_CTL(port));
1277 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1278 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1279 I915_WRITE(DP_TP_CTL(port), val);
1282 intel_wait_ddi_buf_idle(dev_priv, port);
1284 if (type == INTEL_OUTPUT_EDP) {
1285 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1286 ironlake_edp_panel_vdd_on(intel_dp);
1287 ironlake_edp_panel_off(intel_dp);
1290 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1293 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1295 struct drm_encoder *encoder = &intel_encoder->base;
1296 struct drm_device *dev = encoder->dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1299 int type = intel_encoder->type;
1301 if (type == INTEL_OUTPUT_HDMI) {
1302 struct intel_digital_port *intel_dig_port =
1303 enc_to_dig_port(encoder);
1305 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1306 * are ignored so nothing special needs to be done besides
1307 * enabling the port.
1309 I915_WRITE(DDI_BUF_CTL(port),
1310 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
1311 } else if (type == INTEL_OUTPUT_EDP) {
1312 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1314 ironlake_edp_backlight_on(intel_dp);
1318 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1320 struct drm_encoder *encoder = &intel_encoder->base;
1321 int type = intel_encoder->type;
1323 if (type == INTEL_OUTPUT_EDP) {
1324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1326 ironlake_edp_backlight_off(intel_dp);
1330 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1332 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1334 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1337 else if (IS_ULT(dev_priv->dev))
1343 void intel_ddi_pll_init(struct drm_device *dev)
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 uint32_t val = I915_READ(LCPLL_CTL);
1348 /* The LCPLL register should be turned on by the BIOS. For now let's
1349 * just check its state and print errors in case something is wrong.
1350 * Don't even try to turn it on.
1353 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1354 intel_ddi_get_cdclk_freq(dev_priv));
1356 if (val & LCPLL_CD_SOURCE_FCLK)
1357 DRM_ERROR("CDCLK source is not LCPLL\n");
1359 if (val & LCPLL_PLL_DISABLE)
1360 DRM_ERROR("LCPLL is disabled\n");
1363 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1365 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1366 struct intel_dp *intel_dp = &intel_dig_port->dp;
1367 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1368 enum port port = intel_dig_port->port;
1372 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1373 val = I915_READ(DDI_BUF_CTL(port));
1374 if (val & DDI_BUF_CTL_ENABLE) {
1375 val &= ~DDI_BUF_CTL_ENABLE;
1376 I915_WRITE(DDI_BUF_CTL(port), val);
1380 val = I915_READ(DP_TP_CTL(port));
1381 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1382 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1383 I915_WRITE(DP_TP_CTL(port), val);
1384 POSTING_READ(DP_TP_CTL(port));
1387 intel_wait_ddi_buf_idle(dev_priv, port);
1390 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1391 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1392 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1393 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1394 I915_WRITE(DP_TP_CTL(port), val);
1395 POSTING_READ(DP_TP_CTL(port));
1397 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1398 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1399 POSTING_READ(DDI_BUF_CTL(port));
1404 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1406 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1407 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1410 intel_ddi_post_disable(intel_encoder);
1412 val = I915_READ(_FDI_RXA_CTL);
1413 val &= ~FDI_RX_ENABLE;
1414 I915_WRITE(_FDI_RXA_CTL, val);
1416 val = I915_READ(_FDI_RXA_MISC);
1417 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1418 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1419 I915_WRITE(_FDI_RXA_MISC, val);
1421 val = I915_READ(_FDI_RXA_CTL);
1423 I915_WRITE(_FDI_RXA_CTL, val);
1425 val = I915_READ(_FDI_RXA_CTL);
1426 val &= ~FDI_RX_PLL_ENABLE;
1427 I915_WRITE(_FDI_RXA_CTL, val);
1430 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1432 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1433 int type = intel_encoder->type;
1435 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1436 intel_dp_check_link_status(intel_dp);
1439 static void intel_ddi_destroy(struct drm_encoder *encoder)
1441 /* HDMI has nothing special to destroy, so we can go with this. */
1442 intel_dp_encoder_destroy(encoder);
1445 static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1446 const struct drm_display_mode *mode,
1447 struct drm_display_mode *adjusted_mode)
1449 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1450 int type = intel_encoder->type;
1452 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1454 if (type == INTEL_OUTPUT_HDMI)
1455 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1457 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1460 static const struct drm_encoder_funcs intel_ddi_funcs = {
1461 .destroy = intel_ddi_destroy,
1464 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1465 .mode_fixup = intel_ddi_mode_fixup,
1466 .mode_set = intel_ddi_mode_set,
1467 .disable = intel_encoder_noop,
1470 void intel_ddi_init(struct drm_device *dev, enum port port)
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 struct intel_digital_port *intel_dig_port;
1474 struct intel_encoder *intel_encoder;
1475 struct drm_encoder *encoder;
1476 struct intel_connector *hdmi_connector = NULL;
1477 struct intel_connector *dp_connector = NULL;
1479 intel_dig_port = malloc(sizeof(struct intel_digital_port), DRM_MEM_KMS, M_WAITOK | M_ZERO);
1480 if (!intel_dig_port)
1483 dp_connector = malloc(sizeof(struct intel_connector), DRM_MEM_KMS, M_WAITOK | M_ZERO);
1484 if (!dp_connector) {
1485 free(intel_dig_port, DRM_MEM_KMS);
1489 if (port != PORT_A) {
1490 hdmi_connector = malloc(sizeof(struct intel_connector),
1491 DRM_MEM_KMS, M_WAITOK | M_ZERO);
1492 if (!hdmi_connector) {
1493 free(dp_connector, DRM_MEM_KMS);
1494 free(intel_dig_port, DRM_MEM_KMS);
1499 intel_encoder = &intel_dig_port->base;
1500 encoder = &intel_encoder->base;
1502 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1503 DRM_MODE_ENCODER_TMDS);
1504 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1506 intel_encoder->enable = intel_enable_ddi;
1507 intel_encoder->pre_enable = intel_ddi_pre_enable;
1508 intel_encoder->disable = intel_disable_ddi;
1509 intel_encoder->post_disable = intel_ddi_post_disable;
1510 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1512 intel_dig_port->port = port;
1513 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1514 DDI_BUF_PORT_REVERSAL;
1516 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1518 intel_dig_port->hdmi.sdvox_reg = 0;
1519 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1521 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1522 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1523 intel_encoder->cloneable = false;
1524 intel_encoder->hot_plug = intel_ddi_hot_plug;
1527 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1528 intel_dp_init_connector(intel_dig_port, dp_connector);